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Jordan Carlin 2025-05-10 16:55:47 -07:00
parent 2b1569a281
commit 602cc42b03
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188
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-cboz-01.reference_output
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deadbeef # begin_signature
deadbeef
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00000000 # destination 1
00000000
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00000000 # destination 2
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ffffffff # signature The test writes -1 for correct answers and the a positive integer for incorrect copies.
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
0bad0bad
0bad0bad

410
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-csr-permission-s-01.reference_output
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0000000b # Test 5.2.3.6: ecall from going to S mode from M mode
00000002 # S mode write to mstatush with illegal instruction
00000002 # S mode read from mstatush with illegal instruction
00000bad
00000002 # S mode write to menvcfgh with illegal instruction
00000002 # S mode read from menvcfgh with illegal instruction
00000bad
00000002 # S mode write to mseccfgh with illegal instruction
00000002 # S mode read from mseccfgh with illegal instruction
00000bad
00000002 # S mode write to pmpcfg1 with illegal instruction
00000002 # S mode read from pmpcfg1 with illegal instruction
00000bad
00000002 # S mode write to pmpcfg3 with illegal instruction
00000002 # S mode read from pmpcfg3 with illegal instruction
00000bad
00000002 # S mode write to mcycleh with illegal instruction
00000002 # S mode read from mcycleh with illegal instruction
00000bad
00000002 # S mode write to minstreth with illegal instruction
00000002 # S mode read from minstreth with illegal instruction
00000bad
00000002 # S mode write to mhpmcounter3h with illegal instruction
00000002 # S mode read from mhpmcounter3h with illegal instruction
00000bad
00000002 # S mode write to mhpmcounter4h with illegal instruction
00000002 # S mode read from mhpmcounter4h with illegal instruction
00000bad
00000002 # S mode write to mhpmcounter5h with illegal instruction
00000002 # S mode read from mhpmcounter5h with illegal instruction
00000bad
00000002 # S mode write to mhpmcounter6h with illegal instruction
00000002 # S mode read from mhpmcounter6h with illegal instruction
00000bad
00000002 # S mode write to mhpmcounter7h with illegal instruction
00000002 # S mode read from mhpmcounter7h with illegal instruction
00000bad
00000002 # S mode write to mhpmcounter8h with illegal instruction
00000002 # S mode read from mhpmcounter8h with illegal instruction
00000bad
00000002 # S mode write to mhpmcounter9h with illegal instruction
00000002 # S mode read from mhpmcounter9h with illegal instruction
00000bad
00000002 # S mode write to mhpmcounter10h with illegal instruction
00000002 # S mode read from mhpmcounter10h with illegal instruction
00000bad
00000002 # S mode write to mhpmcounter11h with illegal instruction
00000002 # S mode read from mhpmcounter11h with illegal instruction
00000bad
00000002 # S mode write to mhpmcounter12h with illegal instruction
00000002 # S mode read from mhpmcounter12h with illegal instruction
00000bad
00000002 # S mode write to mhpmcounter13h with illegal instruction
00000002 # S mode read from mhpmcounter13h with illegal instruction
00000bad
00000002 # S mode write to mhpmcounter14h with illegal instruction
00000002 # S mode read from mhpmcounter14h with illegal instruction
00000bad
00000002 # S mode write to mhpmcounter15h with illegal instruction
00000002 # S mode read from mhpmcounter15h with illegal instruction
00000bad
00000002 # S mode write to mhpmcounter16h with illegal instruction
00000002 # S mode read from mhpmcounter16h with illegal instruction
00000bad
00000002 # S mode write to mhpmcounter17h with illegal instruction
00000002 # S mode read from mhpmcounter17h with illegal instruction
00000bad
00000002 # S mode write to mhpmcounter18h with illegal instruction
00000002 # S mode read from mhpmcounter18h with illegal instruction
00000bad
00000002 # S mode write to mhpmcounter19h with illegal instruction
00000002 # S mode read from mhpmcounter19h with illegal instruction
00000bad
00000002 # S mode write to mhpmcounter20h with illegal instruction
00000002 # S mode read from mhpmcounter20h with illegal instruction
00000bad
00000002 # S mode write to mhpmcounter21h with illegal instruction
00000002 # S mode read from mhpmcounter21h with illegal instruction
00000bad
00000002 # S mode write to mhpmcounter22h with illegal instruction
00000002 # S mode read from mhpmcounter22h with illegal instruction
00000bad
00000002 # S mode write to mhpmcounter23h with illegal instruction
00000002 # S mode read from mhpmcounter23h with illegal instruction
00000bad
00000002 # S mode write to mhpmcounter24h with illegal instruction
00000002 # S mode read from mhpmcounter24h with illegal instruction
00000bad
00000002 # S mode write to mhpmcounter25h with illegal instruction
00000002 # S mode read from mhpmcounter25h with illegal instruction
00000bad
00000002 # S mode write to mhpmcounter26h with illegal instruction
00000002 # S mode read from mhpmcounter26h with illegal instruction
00000bad
00000002 # S mode write to mhpmcounter27h with illegal instruction
00000002 # S mode read from mhpmcounter27h with illegal instruction
00000bad
00000002 # S mode write to mhpmcounter28h with illegal instruction
00000002 # S mode read from mhpmcounter28h with illegal instruction
00000bad
00000002 # S mode write to mhpmcounter29h with illegal instruction
00000002 # S mode read from mhpmcounter29h with illegal instruction
00000bad
00000002 # S mode write to mhpmcounter30h with illegal instruction
00000002 # S mode read from mhpmcounter30h with illegal instruction
00000bad
00000002 # S mode write to mhpmcounter31h with illegal instruction
00000002 # S mode read from mhpmcounter31h with illegal instruction
00000bad
00000002 # S mode write to mvendorid with illegal instruction
00000002 # S mode read from mvendorid with illegal instruction
00000bad
00000002 # S mode write to marchid with illegal instruction
00000002 # S mode read from marchid with illegal instruction
00000bad
00000002 # S mode write to mimpid with illegal instruction
00000002 # S mode read from mimpid with illegal instruction
00000bad
00000002 # S mode write to mhartid with illegal instruction
00000002 # S mode read from mhartid with illegal instruction
00000bad
00000002 # S mode write to mconfigptr with illegal instruction
00000002 # S mode read from mconfigptr with illegal instruction
00000bad
00000002 # S mode write to mstatus with illegal instruction
00000002 # S mode read from mstatus with illegal instruction
00000bad
00000002 # S mode write to mstatush with illegal instruction
00000002 # S mode read from mstatush with illegal instruction
00000bad
00000002 # S mode write to misa with illegal instruction
00000002 # S mode read from misa with illegal instruction
00000bad
00000002 # S mode write to medeleg with illegal instruction
00000002 # S mode read from medeleg with illegal instruction
00000bad
00000002 # S mode write to mideleg with illegal instruction
00000002 # S mode read from mideleg with illegal instruction
00000bad
00000002 # S mode write to mie with illegal instruction
00000002 # S mode read from mie with illegal instruction
00000bad
00000002 # S mode write to mtvec with illegal instruction
00000002 # S mode read from mtvec with illegal instruction
00000bad
00000002 # S mode write to mcounteren with illegal instruction
00000002 # S mode read from mcounteren with illegal instruction
00000bad
00000002 # S mode write to mscratch with illegal instruction
00000002 # S mode read from mscratch with illegal instruction
00000bad
00000002 # S mode write to mepc with illegal instruction
00000002 # S mode read from mepc with illegal instruction
00000bad
00000002 # S mode write to mcause with illegal instruction
00000002 # S mode read from mcause with illegal instruction
00000bad
00000002 # S mode write to mtval with illegal instruction
00000002 # S mode read from mtval with illegal instruction
00000bad
00000002 # S mode write to mip with illegal instruction
00000002 # S mode read from mip with illegal instruction
00000bad
00000002 # S mode write to menvcfg with illegal instruction
00000002 # S mode read from menvcfg with illegal instruction
00000bad
00000002 # S mode write to menvcfgh with illegal instruction
00000002 # S mode read from menvcfgh with illegal instruction
00000bad
00000002 # S mode write to mseccfg with illegal instruction
00000002 # S mode read from mseccfg with illegal instruction
00000bad
00000002 # S mode write to pmpcfg0 with illegal instruction
00000002 # S mode read from pmpcfg0 with illegal instruction
00000bad
00000002 # S mode write to pmpcfg2 with illegal instruction
00000002 # S mode read from pmpcfg2 with illegal instruction
00000bad
00000002 # S mode write to pmpaddr0 with illegal instruction
00000002 # S mode read from pmpaddr0 with illegal instruction
00000bad
00000002 # S mode write to pmpaddr1 with illegal instruction
00000002 # S mode read from pmpaddr1 with illegal instruction
00000bad
00000002 # S mode write to pmpaddr2 with illegal instruction
00000002 # S mode read from pmpaddr2 with illegal instruction
00000bad
00000002 # S mode write to pmpaddr3 with illegal instruction
00000002 # S mode read from pmpaddr3 with illegal instruction
00000bad
00000002 # S mode write to pmpaddr4 with illegal instruction
00000002 # S mode read from pmpaddr4 with illegal instruction
00000bad
00000002 # S mode write to pmpaddr5 with illegal instruction
00000002 # S mode read from pmpaddr5 with illegal instruction
00000bad
00000002 # S mode write to pmpaddr6 with illegal instruction
00000002 # S mode read from pmpaddr6 with illegal instruction
00000bad
00000002 # S mode write to pmpaddr7 with illegal instruction
00000002 # S mode read from pmpaddr7 with illegal instruction
00000bad
00000002 # S mode write to pmpaddr8 with illegal instruction
00000002 # S mode read from pmpaddr8 with illegal instruction
00000bad
00000002 # S mode write to pmpaddr9 with illegal instruction
00000002 # S mode read from pmpaddr9 with illegal instruction
00000bad
00000002 # S mode write to pmpaddr10 with illegal instruction
00000002 # S mode read from pmpaddr10 with illegal instruction
00000bad
00000002 # S mode write to pmpaddr11 with illegal instruction
00000002 # S mode read from pmpaddr11 with illegal instruction
00000bad
00000002 # S mode write to pmpaddr12 with illegal instruction
00000002 # S mode read from pmpaddr12 with illegal instruction
00000bad
00000002 # S mode write to pmpaddr13 with illegal instruction
00000002 # S mode read from pmpaddr13 with illegal instruction
00000bad
00000002 # S mode write to pmpaddr14 with illegal instruction
00000002 # S mode read from pmpaddr14 with illegal instruction
00000bad
00000002 # S mode write to pmpaddr15 with illegal instruction
00000002 # S mode read from pmpaddr15 with illegal instruction
00000bad
00000002 # S mode write to mcycle with illegal instruction
00000002 # S mode read from mcycle with illegal instruction
00000bad
00000002 # S mode write to minstret with illegal instruction
00000002 # S mode read from minstret with illegal instruction
00000bad
00000002 # S mode write to mhpmcounter3 with illegal instruction
00000002 # S mode read from mhpmcounter3 with illegal instruction
00000bad
00000002 # S mode write to mhpmcounter4 with illegal instruction
00000002 # S mode read from mhpmcounter4 with illegal instruction
00000bad
00000002 # S mode write to mhpmcounter5 with illegal instruction
00000002 # S mode read from mhpmcounter5 with illegal instruction
00000bad
00000002 # S mode write to mhpmcounter6 with illegal instruction
00000002 # S mode read from mhpmcounter6 with illegal instruction
00000bad
00000002 # S mode write to mhpmcounter7 with illegal instruction
00000002 # S mode read from mhpmcounter7 with illegal instruction
00000bad
00000002 # S mode write to mhpmcounter8 with illegal instruction
00000002 # S mode read from mhpmcounter8 with illegal instruction
00000bad
00000002 # S mode write to mhpmcounter9 with illegal instruction
00000002 # S mode read from mhpmcounter9 with illegal instruction
00000bad
00000002 # S mode write to mhpmcounter10 with illegal instruction
00000002 # S mode read from mhpmcounter10 with illegal instruction
00000bad
00000002 # S mode write to mhpmcounter11 with illegal instruction
00000002 # S mode read from mhpmcounter11 with illegal instruction
00000bad
00000002 # S mode write to mhpmcounter12 with illegal instruction
00000002 # S mode read from mhpmcounter12 with illegal instruction
00000bad
00000002 # S mode write to mhpmcounter13 with illegal instruction
00000002 # S mode read from mhpmcounter13 with illegal instruction
00000bad
00000002 # S mode write to mhpmcounter14 with illegal instruction
00000002 # S mode read from mhpmcounter14 with illegal instruction
00000bad
00000002 # S mode write to mhpmcounter15 with illegal instruction
00000002 # S mode read from mhpmcounter15 with illegal instruction
00000bad
00000002 # S mode write to mhpmcounter16 with illegal instruction
00000002 # S mode read from mhpmcounter16 with illegal instruction
00000bad
00000002 # S mode write to mhpmcounter17 with illegal instruction
00000002 # S mode read from mhpmcounter17 with illegal instruction
00000bad
00000002 # S mode write to mhpmcounter18 with illegal instruction
00000002 # S mode read from mhpmcounter18 with illegal instruction
00000bad
00000002 # S mode write to mhpmcounter19 with illegal instruction
00000002 # S mode read from mhpmcounter19 with illegal instruction
00000bad
00000002 # S mode write to mhpmcounter20 with illegal instruction
00000002 # S mode read from mhpmcounter20 with illegal instruction
00000bad
00000002 # S mode write to mhpmcounter21 with illegal instruction
00000002 # S mode read from mhpmcounter21 with illegal instruction
00000bad
00000002 # S mode write to mhpmcounter22 with illegal instruction
00000002 # S mode read from mhpmcounter22 with illegal instruction
00000bad
00000002 # S mode write to mhpmcounter23 with illegal instruction
00000002 # S mode read from mhpmcounter23 with illegal instruction
00000bad
00000002 # S mode write to mhpmcounter24 with illegal instruction
00000002 # S mode read from mhpmcounter24 with illegal instruction
00000bad
00000002 # S mode write to mhpmcounter25 with illegal instruction
00000002 # S mode read from mhpmcounter25 with illegal instruction
00000bad
00000002 # S mode write to mhpmcounter26 with illegal instruction
00000002 # S mode read from mhpmcounter26 with illegal instruction
00000bad
00000002 # S mode write to mhpmcounter27 with illegal instruction
00000002 # S mode read from mhpmcounter27 with illegal instruction
00000bad
00000002 # S mode write to mhpmcounter28 with illegal instruction
00000002 # S mode read from mhpmcounter28 with illegal instruction
00000bad
00000002 # S mode write to mhpmcounter29 with illegal instruction
00000002 # S mode read from mhpmcounter29 with illegal instruction
00000bad
00000002 # S mode write to mhpmcounter30 with illegal instruction
00000002 # S mode read from mhpmcounter30 with illegal instruction
00000bad
00000002 # S mode write to mhpmcounter31 with illegal instruction
00000002 # S mode read from mhpmcounter31 with illegal instruction
00000bad
00000002 # S mode write to mcountinhibit with illegal instruction
00000002 # S mode read from mcountinhibit with illegal instruction
00000bad
00000002 # S mode write to mhpmevent3 with illegal instruction
00000002 # S mode read from mhpmevent3 with illegal instruction
00000bad
00000002 # S mode write to mhpmevent4 with illegal instruction
00000002 # S mode read from mhpmevent4 with illegal instruction
00000bad
00000002 # S mode write to mhpmevent5 with illegal instruction
00000002 # S mode read from mhpmevent5 with illegal instruction
00000bad
00000002 # S mode write to mhpmevent6 with illegal instruction
00000002 # S mode read from mhpmevent6 with illegal instruction
00000bad
00000002 # S mode write to mhpmevent7 with illegal instruction
00000002 # S mode read from mhpmevent7 with illegal instruction
00000bad
00000002 # S mode write to mhpmevent8 with illegal instruction
00000002 # S mode read from mhpmevent8 with illegal instruction
00000bad
00000002 # S mode write to mhpmevent9 with illegal instruction
00000002 # S mode read from mhpmevent9 with illegal instruction
00000bad
00000002 # S mode write to mhpmevent10 with illegal instruction
00000002 # S mode read from mhpmevent10 with illegal instruction
00000bad
00000002 # S mode write to mhpmevent11 with illegal instruction
00000002 # S mode read from mhpmevent11 with illegal instruction
00000bad
00000002 # S mode write to mhpmevent12 with illegal instruction
00000002 # S mode read from mhpmevent12 with illegal instruction
00000bad
00000002 # S mode write to mhpmevent13 with illegal instruction
00000002 # S mode read from mhpmevent13 with illegal instruction
00000bad
00000002 # S mode write to mhpmevent14 with illegal instruction
00000002 # S mode read from mhpmevent14 with illegal instruction
00000bad
00000002 # S mode write to mhpmevent15 with illegal instruction
00000002 # S mode read from mhpmevent15 with illegal instruction
00000bad
00000002 # S mode write to mhpmevent16 with illegal instruction
00000002 # S mode read from mhpmevent16 with illegal instruction
00000bad
00000002 # S mode write to mhpmevent17 with illegal instruction
00000002 # S mode read from mhpmevent17 with illegal instruction
00000bad
00000002 # S mode write to mhpmevent18 with illegal instruction
00000002 # S mode read from mhpmevent18 with illegal instruction
00000bad
00000002 # S mode write to mhpmevent19 with illegal instruction
00000002 # S mode read from mhpmevent19 with illegal instruction
00000bad
00000002 # S mode write to mhpmevent20 with illegal instruction
00000002 # S mode read from mhpmevent20 with illegal instruction
00000bad
00000002 # S mode write to mhpmevent21 with illegal instruction
00000002 # S mode read from mhpmevent21 with illegal instruction
00000bad
00000002 # S mode write to mhpmevent22 with illegal instruction
00000002 # S mode read from mhpmevent22 with illegal instruction
00000bad
00000002 # S mode write to mhpmevent23 with illegal instruction
00000002 # S mode read from mhpmevent23 with illegal instruction
00000bad
00000002 # S mode write to mhpmevent24 with illegal instruction
00000002 # S mode read from mhpmevent24 with illegal instruction
00000bad
00000002 # S mode write to mhpmevent25 with illegal instruction
00000002 # S mode read from mhpmevent25 with illegal instruction
00000bad
00000002 # S mode write to mhpmevent26 with illegal instruction
00000002 # S mode read from mhpmevent26 with illegal instruction
00000bad
00000002 # S mode write to mhpmevent27 with illegal instruction
00000002 # S mode read from mhpmevent27 with illegal instruction
00000bad
00000002 # S mode write to mhpmevent28 with illegal instruction
00000002 # S mode read from mhpmevent28 with illegal instruction
00000bad
00000002 # S mode write to mhpmevent29 with illegal instruction
00000002 # S mode read from mhpmevent29 with illegal instruction
00000bad
00000002 # S mode write to mhpmevent30 with illegal instruction
00000002 # S mode read from mhpmevent30 with illegal instruction
00000bad
00000002 # S mode write to mhpmevent31 with illegal instruction
00000002 # S mode read from mhpmevent31 with illegal instruction
00000bad
00000009 # ecall from terminating tess from S mode

335
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-csr-permission-u-01.reference_output
View file

@ -1,335 +0,0 @@
0000000b # Test 5.2.3.6: ecall from going to U mode from M mode
00000002 # U mode write to sstatus with illegal instruction
00000002 # U mode read from sstatus with illegal instruction
00000bad
00000002 # U mode write to sie with illegal instruction
00000002 # U mode read from sie with illegal instruction
00000bad
00000002 # U mode write to stvec with illegal instruction
00000002 # U mode read from stvec with illegal instruction
00000bad
00000002 # U mode write to scounteren with illegal instruction
00000002 # U mode read from scounteren with illegal instruction
00000bad
00000002 # U mode write to sscratch with illegal instruction
00000002 # U mode read from sscratch with illegal instruction
00000bad
00000002 # U mode write to sepc with illegal instruction
00000002 # U mode read from sepc with illegal instruction
00000bad
00000002 # U mode write to scause with illegal instruction
00000002 # U mode read from scause with illegal instruction
00000bad
00000002 # U mode write to stval with illegal instruction
00000002 # U mode read from stval with illegal instruction
00000bad
00000002 # U mode write to sip with illegal instruction
00000002 # U mode read from sip with illegal instruction
00000bad
00000002 # U mode write to satp with illegal instruction
00000002 # U mode read from satp with illegal instruction
00000bad
00000002 # U mode write to mvendorid with illegal instruction
00000002 # U mode read from mvendorid with illegal instruction
00000bad
00000002 # U mode write to marchid with illegal instruction
00000002 # U mode read from marchid with illegal instruction
00000bad
00000002 # U mode write to mimpid with illegal instruction
00000002 # U mode read from mimpid with illegal instruction
00000bad
00000002 # U mode write to mhartid with illegal instruction
00000002 # U mode read from mhartid with illegal instruction
00000bad
00000002 # S mode write to mconfigptr with illegal instruction
00000002 # S mode read from mconfigptr with illegal instruction
00000bad
00000002 # U mode write to mstatus with illegal instruction
00000002 # U mode read from mstatus with illegal instruction
00000bad
00000002 # U mode write to mstatush with illegal instruction
00000002 # U mode read from mstatush with illegal instruction
00000bad
00000002 # U mode write to misa with illegal instruction
00000002 # U mode read from misa with illegal instruction
00000bad
00000002 # U mode write to medeleg with illegal instruction
00000002 # U mode read from medeleg with illegal instruction
00000bad
00000002 # U mode write to mideleg with illegal instruction
00000002 # U mode read from mideleg with illegal instruction
00000bad
00000002 # U mode write to mie with illegal instruction
00000002 # U mode read from mie with illegal instruction
00000bad
00000002 # U mode write to mtvec with illegal instruction
00000002 # U mode read from mtvec with illegal instruction
00000bad
00000002 # U mode write to mcounteren with illegal instruction
00000002 # U mode read from mcounteren with illegal instruction
00000bad
00000002 # U mode write to mscratch with illegal instruction
00000002 # U mode read from mscratch with illegal instruction
00000bad
00000002 # U mode write to mepc with illegal instruction
00000002 # U mode read from mepc with illegal instruction
00000bad
00000002 # U mode write to mcause with illegal instruction
00000002 # U mode read from mcause with illegal instruction
00000bad
00000002 # U mode write to mtval with illegal instruction
00000002 # U mode read from mtval with illegal instruction
00000bad
00000002 # U mode write to mip with illegal instruction
00000002 # U mode read from mip with illegal instruction
00000bad
00000002 # S mode write to menvcfg with illegal instruction
00000002 # S mode read from menvcfg with illegal instruction
00000bad
00000002 # S mode write to menvcfgh with illegal instruction
00000002 # S mode read from menvcfgh with illegal instruction
00000bad
00000002 # S mode write to mseccfg with illegal instruction
00000002 # S mode read from mseccfg with illegal instruction
00000bad
00000002 # S mode write to senvcfg with illegal instruction
00000002 # S mode read from senvcfg with illegal instruction
00000bad
00000002 # U mode write to pmpcfg0 with illegal instruction
00000002 # U mode read from pmpcfg0 with illegal instruction
00000bad
00000002 # U mode write to pmpcfg2 with illegal instruction
00000002 # U mode read from pmpcfg2 with illegal instruction
00000bad
00000002 # U mode write to pmpaddr0 with illegal instruction
00000002 # U mode read from pmpaddr0 with illegal instruction
00000bad
00000002 # U mode write to pmpaddr1 with illegal instruction
00000002 # U mode read from pmpaddr1 with illegal instruction
00000bad
00000002 # U mode write to pmpaddr2 with illegal instruction
00000002 # U mode read from pmpaddr2 with illegal instruction
00000bad
00000002 # U mode write to pmpaddr3 with illegal instruction
00000002 # U mode read from pmpaddr3 with illegal instruction
00000bad
00000002 # U mode write to pmpaddr4 with illegal instruction
00000002 # U mode read from pmpaddr4 with illegal instruction
00000bad
00000002 # U mode write to pmpaddr5 with illegal instruction
00000002 # U mode read from pmpaddr5 with illegal instruction
00000bad
00000002 # U mode write to pmpaddr6 with illegal instruction
00000002 # U mode read from pmpaddr6 with illegal instruction
00000bad
00000002 # U mode write to pmpaddr7 with illegal instruction
00000002 # U mode read from pmpaddr7 with illegal instruction
00000bad
00000002 # U mode write to pmpaddr8 with illegal instruction
00000002 # U mode read from pmpaddr8 with illegal instruction
00000bad
00000002 # U mode write to pmpaddr9 with illegal instruction
00000002 # U mode read from pmpaddr9 with illegal instruction
00000bad
00000002 # U mode write to pmpaddr10 with illegal instruction
00000002 # U mode read from pmpaddr10 with illegal instruction
00000bad
00000002 # U mode write to pmpaddr11 with illegal instruction
00000002 # U mode read from pmpaddr11 with illegal instruction
00000bad
00000002 # U mode write to pmpaddr12 with illegal instruction
00000002 # U mode read from pmpaddr12 with illegal instruction
00000bad
00000002 # U mode write to pmpaddr13 with illegal instruction
00000002 # U mode read from pmpaddr13 with illegal instruction
00000bad
00000002 # U mode write to pmpaddr14 with illegal instruction
00000002 # U mode read from pmpaddr14 with illegal instruction
00000bad
00000002 # U mode write to pmpaddr15 with illegal instruction
00000002 # U mode read from pmpaddr15 with illegal instruction
00000bad
00000002 # U mode write to mcycle with illegal instruction
00000002 # U mode read from mcycle with illegal instruction
00000bad
00000002 # U mode write to minstret with illegal instruction
00000002 # U mode read from minstret with illegal instruction
00000bad
00000002 # U mode write to mhpmcounter3 with illegal instruction
00000002 # U mode read from mhpmcounter3 with illegal instruction
00000bad
00000002 # U mode write to mhpmcounter4 with illegal instruction
00000002 # U mode read from mhpmcounter4 with illegal instruction
00000bad
00000002 # U mode write to mhpmcounter5 with illegal instruction
00000002 # U mode read from mhpmcounter5 with illegal instruction
00000bad
00000002 # U mode write to mhpmcounter6 with illegal instruction
00000002 # U mode read from mhpmcounter6 with illegal instruction
00000bad
00000002 # U mode write to mhpmcounter7 with illegal instruction
00000002 # U mode read from mhpmcounter7 with illegal instruction
00000bad
00000002 # U mode write to mhpmcounter8 with illegal instruction
00000002 # U mode read from mhpmcounter8 with illegal instruction
00000bad
00000002 # U mode write to mhpmcounter9 with illegal instruction
00000002 # U mode read from mhpmcounter9 with illegal instruction
00000bad
00000002 # U mode write to mhpmcounter10 with illegal instruction
00000002 # U mode read from mhpmcounter10 with illegal instruction
00000bad
00000002 # U mode write to mhpmcounter11 with illegal instruction
00000002 # U mode read from mhpmcounter11 with illegal instruction
00000bad
00000002 # U mode write to mhpmcounter12 with illegal instruction
00000002 # U mode read from mhpmcounter12 with illegal instruction
00000bad
00000002 # U mode write to mhpmcounter13 with illegal instruction
00000002 # U mode read from mhpmcounter13 with illegal instruction
00000bad
00000002 # U mode write to mhpmcounter14 with illegal instruction
00000002 # U mode read from mhpmcounter14 with illegal instruction
00000bad
00000002 # U mode write to mhpmcounter15 with illegal instruction
00000002 # U mode read from mhpmcounter15 with illegal instruction
00000bad
00000002 # U mode write to mhpmcounter16 with illegal instruction
00000002 # U mode read from mhpmcounter16 with illegal instruction
00000bad
00000002 # U mode write to mhpmcounter17 with illegal instruction
00000002 # U mode read from mhpmcounter17 with illegal instruction
00000bad
00000002 # U mode write to mhpmcounter18 with illegal instruction
00000002 # U mode read from mhpmcounter18 with illegal instruction
00000bad
00000002 # U mode write to mhpmcounter19 with illegal instruction
00000002 # U mode read from mhpmcounter19 with illegal instruction
00000bad
00000002 # U mode write to mhpmcounter20 with illegal instruction
00000002 # U mode read from mhpmcounter20 with illegal instruction
00000bad
00000002 # U mode write to mhpmcounter21 with illegal instruction
00000002 # U mode read from mhpmcounter21 with illegal instruction
00000bad
00000002 # U mode write to mhpmcounter22 with illegal instruction
00000002 # U mode read from mhpmcounter22 with illegal instruction
00000bad
00000002 # U mode write to mhpmcounter23 with illegal instruction
00000002 # U mode read from mhpmcounter23 with illegal instruction
00000bad
00000002 # U mode write to mhpmcounter24 with illegal instruction
00000002 # U mode read from mhpmcounter24 with illegal instruction
00000bad
00000002 # U mode write to mhpmcounter25 with illegal instruction
00000002 # U mode read from mhpmcounter25 with illegal instruction
00000bad
00000002 # U mode write to mhpmcounter26 with illegal instruction
00000002 # U mode read from mhpmcounter26 with illegal instruction
00000bad
00000002 # U mode write to mhpmcounter27 with illegal instruction
00000002 # U mode read from mhpmcounter27 with illegal instruction
00000bad
00000002 # U mode write to mhpmcounter28 with illegal instruction
00000002 # U mode read from mhpmcounter28 with illegal instruction
00000bad
00000002 # U mode write to mhpmcounter29 with illegal instruction
00000002 # U mode read from mhpmcounter29 with illegal instruction
00000bad
00000002 # U mode write to mhpmcounter30 with illegal instruction
00000002 # U mode read from mhpmcounter30 with illegal instruction
00000bad
00000002 # U mode write to mhpmcounter31 with illegal instruction
00000002 # U mode read from mhpmcounter31 with illegal instruction
00000bad
00000002 # U mode write to mcountinhibit with illegal instruction
00000002 # U mode read from mcountinhibit with illegal instruction
00000bad
00000002 # U mode write to mhpmevent3 with illegal instruction
00000002 # U mode read from mhpmevent3 with illegal instruction
00000bad
00000002 # U mode write to mhpmevent4 with illegal instruction
00000002 # U mode read from mhpmevent4 with illegal instruction
00000bad
00000002 # U mode write to mhpmevent5 with illegal instruction
00000002 # U mode read from mhpmevent5 with illegal instruction
00000bad
00000002 # U mode write to mhpmevent6 with illegal instruction
00000002 # U mode read from mhpmevent6 with illegal instruction
00000bad
00000002 # U mode write to mhpmevent7 with illegal instruction
00000002 # U mode read from mhpmevent7 with illegal instruction
00000bad
00000002 # U mode write to mhpmevent8 with illegal instruction
00000002 # U mode read from mhpmevent8 with illegal instruction
00000bad
00000002 # U mode write to mhpmevent9 with illegal instruction
00000002 # U mode read from mhpmevent9 with illegal instruction
00000bad
00000002 # U mode write to mhpmevent10 with illegal instruction
00000002 # U mode read from mhpmevent10 with illegal instruction
00000bad
00000002 # U mode write to mhpmevent11 with illegal instruction
00000002 # U mode read from mhpmevent11 with illegal instruction
00000bad
00000002 # U mode write to mhpmevent12 with illegal instruction
00000002 # U mode read from mhpmevent12 with illegal instruction
00000bad
00000002 # U mode write to mhpmevent13 with illegal instruction
00000002 # U mode read from mhpmevent13 with illegal instruction
00000bad
00000002 # U mode write to mhpmevent14 with illegal instruction
00000002 # U mode read from mhpmevent14 with illegal instruction
00000bad
00000002 # U mode write to mhpmevent15 with illegal instruction
00000002 # U mode read from mhpmevent15 with illegal instruction
00000bad
00000002 # U mode write to mhpmevent16 with illegal instruction
00000002 # U mode read from mhpmevent16 with illegal instruction
00000bad
00000002 # U mode write to mhpmevent17 with illegal instruction
00000002 # U mode read from mhpmevent17 with illegal instruction
00000bad
00000002 # U mode write to mhpmevent18 with illegal instruction
00000002 # U mode read from mhpmevent18 with illegal instruction
00000bad
00000002 # U mode write to mhpmevent19 with illegal instruction
00000002 # U mode read from mhpmevent19 with illegal instruction
00000bad
00000002 # U mode write to mhpmevent20 with illegal instruction
00000002 # U mode read from mhpmevent20 with illegal instruction
00000bad
00000002 # U mode write to mhpmevent21 with illegal instruction
00000002 # U mode read from mhpmevent21 with illegal instruction
00000bad
00000002 # U mode write to mhpmevent22 with illegal instruction
00000002 # U mode read from mhpmevent22 with illegal instruction
00000bad
00000002 # U mode write to mhpmevent23 with illegal instruction
00000002 # U mode read from mhpmevent23 with illegal instruction
00000bad
00000002 # U mode write to mhpmevent24 with illegal instruction
00000002 # U mode read from mhpmevent24 with illegal instruction
00000bad
00000002 # U mode write to mhpmevent25 with illegal instruction
00000002 # U mode read from mhpmevent25 with illegal instruction
00000bad
00000002 # U mode write to mhpmevent26 with illegal instruction
00000002 # U mode read from mhpmevent26 with illegal instruction
00000bad
00000002 # U mode write to mhpmevent27 with illegal instruction
00000002 # U mode read from mhpmevent27 with illegal instruction
00000bad
00000002 # U mode write to mhpmevent28 with illegal instruction
00000002 # U mode read from mhpmevent28 with illegal instruction
00000bad
00000002 # U mode write to mhpmevent29 with illegal instruction
00000002 # U mode read from mhpmevent29 with illegal instruction
00000bad
00000002 # U mode write to mhpmevent30 with illegal instruction
00000002 # U mode read from mhpmevent30 with illegal instruction
00000bad
00000002 # U mode write to mhpmevent31 with illegal instruction
00000002 # U mode read from mhpmevent31 with illegal instruction
00000bad
00000008 # ecall from terminating tests in U mode

12
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-minfo-01.reference_output
View file

@ -1,12 +0,0 @@
00000002 # Test 5.2.3.1: write to read-only CSR failed with illegal instruction
00000011 # confirm read-only permissions of mvendorid
00000002 # write to read-only CSR failed with illegal instruction
00000011 # confirm read-only permissions of marchid
00000002 # write to read-only CSR failed with illegal instruction
00000011 # confirm read-only permissions of mimpid
00000002 # write to read-only CSR failed with illegal instruction
00000011 # confirm read-only permissions of mhartid
00000002 # write to read-only CSR failed with illegal instruction
00000011 # confirm read-only permissions of mconfigptr
0000000b # ecall from terminating tests in M mode

2
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-misa-01.reference_output
View file

@ -1,2 +0,0 @@
00000111 # Test 5.3.2.2: successful read of nonzero misa
0000000b # ecall from terminating tests in machine mode

29
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-pmp-01.reference_output
View file

@ -1,29 +0,0 @@
0fffffff
20040000
2004003f
20040080
20040084
200400c0
2004013f
2fffffff
0009001f
0018900c
1f000000
0018900c
200400c0
00000005
00000bad
00600dbb
0000000b
00600d15
00600d02
00600d12
00000007
00600daa
00000007
00000005
00000bad
00000001
00000bad
00000111
00000009

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-satp-invalid-01.reference_output
View file

@ -1,3 +0,0 @@
0000000b # Test *** Number: Ecall from going from M mode to S mode
00000001 # Instruction access fault (was illegal instruction) from turning on virtual memory with invalid satp address
00000009 # ecall from ending tests in S mode.

6
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-status-fp-enabled-01.reference_output
View file

@ -1,6 +0,0 @@
00002000 # read SD = 0, FS = 01
80006000 # read SD = 1, FS = 11
00004000 # read written SD = 1, FS = 10
80006000 # read SD = 1, FS = 11
00000002 # mcause from attempting fmv with status.FS cleared
0000000b # mcause from M mode ecall from test termination

9
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-sret-01.reference_output
View file

@ -1,9 +0,0 @@
0000000b # test 5.3.1.6: mcause for ecall from going to S mode from M mode
00000000 # mtval of ecall (*** defined to be zero for now)
00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0
00000002 # mcause for illegal sret instruction due to status.tsr bit being set.
10200073 # mtval of illegal instruction (illegal instruction's machine code)
00000800 # masked out mstatus.MPP = 01, mstatus.MPIE = 0, and mstatus.MIE = 0
00000009 # mcause from S mode ecall from test termination
00000000 # mtval of ecall (*** defined to be zero for now)
00000800 # masked out mstatus.MPP = 01, mstatus.MPIE = 0, and mstatus.MIE = 0

2
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-cboz-01.S
View file

@ -31,7 +31,7 @@ rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",cbo.zero)
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",cbo.zero)
RVMODEL_IO_WRITE_STR(x31, "# Test Begin\n")

2
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-csr-permission-s-01.S
View file

@ -24,7 +24,7 @@
#include "WALLY-TEST-LIB-32.h"
RVTEST_ISA("RV32I_Zicsr")
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",csr-permission-s)
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;",csr-permission-s)
INIT_TESTS

2
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-csr-permission-u-01.S
View file

@ -24,7 +24,7 @@
#include "WALLY-TEST-LIB-32.h"
RVTEST_ISA("RV32I_Zicsr")
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",csr-permission-u)
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;",csr-permission-u)
INIT_TESTS

2
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-minfo-01.S
View file

@ -24,7 +24,7 @@
#include "WALLY-TEST-LIB-32.h"
RVTEST_ISA("RV32I_Zicsr")
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True; def NO_SAIL=True;",minfo)
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;",minfo)
INIT_TESTS

2
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-misa-01.S
View file

@ -24,7 +24,7 @@
#include "WALLY-TEST-LIB-32.h"
RVTEST_ISA("RV32I_Zicsr")
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",misa)
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;",misa)
INIT_TESTS

2
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-pmp-01.S
View file

@ -24,7 +24,7 @@
#include "WALLY-TEST-LIB-32.h"
RVTEST_ISA("RV32I_Zicsr_Zifencei")
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",pmp)
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;",pmp)
INIT_TESTS

2
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-satp-invalid-01.S
View file

@ -23,7 +23,7 @@
#include "WALLY-TEST-LIB-32.h"
RVTEST_ISA("RV32I_Zicsr")
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True; def TEST_CASE_1=True;def NO_SAIL=True;",satp-invalid)
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True; def TEST_CASE_1=True;",satp-invalid)
INIT_TESTS

2
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-fp-enabled-01.S
View file

@ -24,7 +24,7 @@
#include "WALLY-TEST-LIB-32.h"
RVTEST_ISA("RV32IAF_Zicsr")
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*A.*F.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",status-fp-enabled)
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*A.*F.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;",status-fp-enabled)
INIT_TESTS

2
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-sret-01.S
View file

@ -24,7 +24,7 @@
#include "WALLY-TEST-LIB-32.h"
RVTEST_ISA("RV32I_Zicsr")
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",trap-sret)
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;",trap-sret)
INIT_TESTS

56
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-pmp-01.reference_output
View file

@ -1,56 +0,0 @@
0fffffff # Test 12.3.2.2.1: writeback of value written to PMPADDR0
00000000
20040000 # writeback of value written to PMPADDR1
00000000
2004003f # writeback of value written to PMPADDR2
00000000
20040080 # writeback of value written to PMPADDR3
00000000
20040084 # writeback of value written to PMPADDR4
00000000
200400c0 # writeback of value written to PMPADDR5
00000000
2004013f # writeback of value written to PMPADDR6
00000000
2fffffff # writeback of value written to PMPADDR15
00000000
0009001f # writeback of value written to PMPCFG0
0018900c
00000000 # writeback of value written to PMPCFG2
1f000000
0009001f # old value of PMPCFG0 after failed write to locked out region
0018900c
200400c0 # old value of PMPADDR5 after failed write to locked out region
00000000
00000005 # Test 12.3.2.2.2: read test with access fault to region with L=1, R=0
00000000
00000bad
00000000
00600dbb # read test success from region with L=X=W=R=0
00000000
0000000b # Test 12.3.2.2.3: ecall from going to S mode from M mode
00000000
00600d15 # read test success from RW range (confirming previous write)
00000000
00600d02 # read test success from outside the edge of a read only range
00000000
00600d12 # read test success from outside the other edge of a read only range
00000000
00000007 # write test with access fault in read only range
00000000
00600daa # read success from read only range
00000000
00000007 # write test with access fault in no-access range
00000000
00000005 # read test with access fault in no-access range
00000000
00000bad
00000000
00000001 # execute test with access fault in no-execute range
00000000
00000bad
00000000
00000111 # execute success when X=1
00000000
00000009 # ecall from terminating tests in S mode
00000000

123
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pmp-01.S
View file

@ -1,123 +0,0 @@
///////////////////////////////////////////
//
// WALLY-PMP
//
// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
//
// Created 2021-06-15
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
#include "WALLY-TEST-LIB-64.h"
RVTEST_ISA("RV64I_Zicsr_Zifencei")
RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",pmp)
INIT_TESTS
TRAP_HANDLER m
j run_test_loop // begin test loop/table tests instead of executing inline code.
INIT_TEST_TABLE
TEST_STACK_AND_DATA
# These tests follow the testing plan in Chapter 12 of the riscv-wally textbook
.align 3
test_cases:
# ---------------------------------------------------------------------------------------------
# Test Contents
#
# Here is where the actual tests are held, or rather, what the actual tests do.
# each entry consists of 3 values that will be read in as follows:
#
# '.8byte [x28 Value], [x29 Value], [x30 value]'
# or
# '.8byte [address], [value], [test type]'
#
# The encoding for x30 test type values can be found in the test handler in the framework file
#
# ---------------------------------------------------------------------------------------------
# These tests follow the testing plan in Chapter 12 of the riscv-wally textbook *** what is it called and how do I refer to it?
# =========== test 12.3.2.2 PMPs ===========
# Test 12.3.2.2.1 Config: Write known values and set PMP config according to table 12.4 in the *** riscv book, copied below
# write pmpaddr regs. Each of these should output the value of the pmpaddr after being written.
# | Reg | pmpaddr | pmpcfg | L | A | X | W | R | Comments |
.8byte 0x0, 0x0FFFFFFF, write_pmpaddr_0 # | 0 | 0x0FFFFFFF | 1F | 0 | NAPOT | 0 | 1 | 1 | I/O 00000000-7FFFFFFF RW |
.8byte 0x1, 0x20040000, write_pmpaddr_1 # | 1 | 0x20040000 | 00 | 0 | OFF | 0 | 0 | 0 | |
.8byte 0x2, 0x2004003F, write_pmpaddr_2 # | 2 | 0x2004003F | 09 | 0 | TOR | 0 | 0 | 1 | 80100000-801000FF R |
.8byte 0x3, 0x20040080, write_pmpaddr_3 # | 3 | 0x20040080 | 00 | 0 | OFF | 0 | 0 | 0 | |
.8byte 0x4, 0x20040084, write_pmpaddr_4 # | 4 | 0x20040084 | 0C | 0 | TOR | 1 | 0 | 0 | 80100200-80100210 X |
.8byte 0x5, 0x200400C0, write_pmpaddr_5 # | 5 | 0x200400C0 | 90 | 1 | NA4 | 0 | 0 | 0 | 80100300-80100303 locked out |
.8byte 0x6, 0x2004013F, write_pmpaddr_6 # | 6 | 0x2004013F | 18 | 0 | NAPOT | 0 | 0 | 0 | 80100400-801004FF no access |
# Pmpaddr 7-14 are all zeroed out in this test, so they don't need writes.
.8byte 0xF, 0x2FFFFFFF, write_pmpaddr_15 # | 15 | 0x2FFFFFFF | 1F | 0 | NAPOT | 1 | 1 | 1 | Main mem 80000000-FFFFFFFF RWX|
# write pmpcfg regs with the information in the table above. this should also write the value of these registers to the output.
.8byte 0x0, 0x0018900C0009001F, write_pmpcfg_0 # write pmpcfg0, output 0x0018900C0009001F
.8byte 0x2, 0x1F00000000000000, write_pmpcfg_2 # write pmpcfg2, output 0x1F00000000000000
# write known values to memory where W=0. This should be possible since we're in machine mode.
.8byte 0x80100010, 0x600DAA, write64_test # write to pmpaddr 1-2 range
.8byte 0x80100400, 0x600DBB, write64_test # write to pmpaddr 6 range
# Write executable code to regions where X = 0, 1 in main memory
.8byte 0x80100200, 0x0000806711100393, write64_test # write executable code for "li x7, 0x111; ret" to region with X=1 (PMP4)
.8byte 0x80100020, 0x0000806711100393, write64_test # Write same executable code to region with X=0 (PMP2)
# attempt to write to pmpaddr5 and pmp5cfg after lockout
.8byte 0x0, 0x0018FF0C0009001F, write_pmpcfg_0 # attempt to edit only pmp5cfg (pmpcfg0[47:40]) after lockout.
# instruction ignored, output is 0x0018900C0009001F, NOT 0x0018FF0C0009001F
.8byte 0x5, 0xFFFFFFFF, write_pmpaddr_5 # attempt to edit pmpaddr5 after lockout.
# instruction ignored, output is 0x200400c0, NOT 0xFFFFFFFF
# Test 12.3.2.2.2 Machine mode access
.8byte 0x80100300, 0x0, read64_test # access fault to region with L=1, R=0
.8byte 0x80100400, 0x0, read64_test # successful access to region with L=X=W=R=0
# Test 12.3.2.2.3 System mode access
.8byte 0x0, 0x0, goto_s_mode # go to S mode. 0xb written to output
# test a write followed by a read to each region with R=W=1
.8byte 0x80200000, 0x600D15, write64_test # Write "good value" to RW range (PMP15)
.8byte 0x80200000, 0x600D15, read64_test # confirm write with read
# test a write followed by a read on the edges of a read-only range
.8byte 0x800FFFF8, 0x600D02, write64_test # Write "good value" just below read-only range (PMP2)
.8byte 0x800FFFF8, 0x600D02, read64_test # confirm write with read
.8byte 0x80100100, 0x600D12, write64_test # Write "good value" just above read-only range (PMP2)
.8byte 0x80100100, 0x600D12, read64_test # confirm write with read
# test a read from each read only range verify a write causes an access fault
.8byte 0x80100010, 0xBAD, write64_test # Write fault in read-only range (PMP2)
.8byte 0x80100010, 0x600DAA, read64_test # read correct value out
# test read and write fault on region with no access
.8byte 0x80100208, 0x600D15, write64_test # Write fault on no-access range (PMP6)
.8byte 0x80100208, 0x600D15, read64_test # read fault on no-access range (PMP6)
# test jalr to region with X=0 causes access fault
.8byte 0x80100020, 0xbad, executable_test # execute fault on no-execute range (PMP2)
# test jalr to region with X=1 returns successfully
.8byte 0x80100200, 0x111, executable_test # execute success when X=1
.8byte 0x0, 0x0, terminate_test // terminate tests