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Added CSR permission tests for mconfigptr, menvcfg, mseccfg, etc.

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This commit is contained in:
David Harris 2023-10-15 15:31:03 -07:00
parent b4891d88db
commit 6245748ed7
8 changed files with 86 additions and 20 deletions
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15
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-csr-permission-s-01.reference_output
View file

@ -110,9 +110,15 @@
00000002 # S mode write to mhartid with illegal instruction
00000002 # S mode read from mhartid with illegal instruction
00000bad
00000002 # S mode write to mconfigptr with illegal instruction
00000002 # S mode read from mconfigptr with illegal instruction
00000bad
00000002 # S mode write to mstatus with illegal instruction
00000002 # S mode read from mstatus with illegal instruction
00000bad
00000002 # S mode write to mstatush with illegal instruction
00000002 # S mode read from mstatush with illegal instruction
00000bad
00000002 # S mode write to misa with illegal instruction
00000002 # S mode read from misa with illegal instruction
00000bad
@ -146,6 +152,15 @@
00000002 # S mode write to mip with illegal instruction
00000002 # S mode read from mip with illegal instruction
00000bad
00000002 # S mode write to menvcfg with illegal instruction
00000002 # S mode read from menvcfg with illegal instruction
00000bad
00000002 # S mode write to menvcfgh with illegal instruction
00000002 # S mode read from menvcfgh with illegal instruction
00000bad
00000002 # S mode write to mseccfg with illegal instruction
00000002 # S mode read from mseccfg with illegal instruction
00000bad
00000002 # S mode write to pmpcfg0 with illegal instruction
00000002 # S mode read from pmpcfg0 with illegal instruction
00000bad

18
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-csr-permission-u-01.reference_output
View file

@ -41,9 +41,15 @@
00000002 # U mode write to mhartid with illegal instruction
00000002 # U mode read from mhartid with illegal instruction
00000bad
00000002 # S mode write to mconfigptr with illegal instruction
00000002 # S mode read from mconfigptr with illegal instruction
00000bad
00000002 # U mode write to mstatus with illegal instruction
00000002 # U mode read from mstatus with illegal instruction
00000bad
00000002 # U mode write to mstatush with illegal instruction
00000002 # U mode read from mstatush with illegal instruction
00000bad
00000002 # U mode write to misa with illegal instruction
00000002 # U mode read from misa with illegal instruction
00000bad
@ -77,6 +83,18 @@
00000002 # U mode write to mip with illegal instruction
00000002 # U mode read from mip with illegal instruction
00000bad
00000002 # S mode write to menvcfg with illegal instruction
00000002 # S mode read from menvcfg with illegal instruction
00000bad
00000002 # S mode write to menvcfgh with illegal instruction
00000002 # S mode read from menvcfgh with illegal instruction
00000bad
00000002 # S mode write to mseccfg with illegal instruction
00000002 # S mode read from mseccfg with illegal instruction
00000bad
00000002 # S mode write to senvcfg with illegal instruction
00000002 # S mode read from senvcfg with illegal instruction
00000bad
00000002 # U mode write to pmpcfg0 with illegal instruction
00000002 # U mode read from pmpcfg0 with illegal instruction
00000bad

10
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-csr-permission-s-01.S
View file

@ -83,10 +83,11 @@ WRITE_READ_CSR mvendorid, 0x111
WRITE_READ_CSR marchid, 0x111
WRITE_READ_CSR mimpid, 0x111
WRITE_READ_CSR mhartid, 0x111
# WRITE_READ_CSR mconfigptr, 0x111 # mconfigptr unimplemented in spike as of 31 Jan 22
WRITE_READ_CSR mconfigptr, 0x111
# Machine Trap Setup
WRITE_READ_CSR mstatus, 0x111
WRITE_READ_CSR mstatush, 0x111
WRITE_READ_CSR misa, 0x111
WRITE_READ_CSR medeleg, 0x111
WRITE_READ_CSR mideleg, 0x111
@ -100,12 +101,11 @@ WRITE_READ_CSR mepc, 0x111
WRITE_READ_CSR mcause, 0x111
WRITE_READ_CSR mtval, 0x111
WRITE_READ_CSR mip, 0x111
# WRITE_READ_CSR mtinst, 0x111 # *** these appear not to be implemented in GCC
# WRITE_READ_CSR mtval2, 0x111
# Machine Configuration
# WRITE_READ_CSR menvcfg, 0x111 # *** these appear not to be implemented in GCC
# WRITE_READ_CSR mseccgf, 0x111
WRITE_READ_CSR menvcfg, 0x111
WRITE_READ_CSR menvcfgh, 0x111
WRITE_READ_CSR mseccfg, 0x111
# Machine Memory Protection
WRITE_READ_CSR pmpcfg0, 0x111

11
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-csr-permission-u-01.S
View file

@ -61,10 +61,11 @@ WRITE_READ_CSR mvendorid, 0xAAA
WRITE_READ_CSR marchid, 0xAAA
WRITE_READ_CSR mimpid, 0xAAA
WRITE_READ_CSR mhartid, 0xAAA
# WRITE_READ_CSR mconfigptr, 0xAAA # mconfigptr unimplemented in spike as of 31 Jan 22
WRITE_READ_CSR mconfigptr, 0xAAA # mconfigptr unimplemented in spike as of 31 Jan 22
# Machine Trap Setup
WRITE_READ_CSR mstatus, 0xAAA
WRITE_READ_CSR mstatush, 0xAAA
WRITE_READ_CSR misa, 0xAAA
WRITE_READ_CSR medeleg, 0xAAA
WRITE_READ_CSR mideleg, 0xAAA
@ -78,12 +79,12 @@ WRITE_READ_CSR mepc, 0xAAA
WRITE_READ_CSR mcause, 0xAAA
WRITE_READ_CSR mtval, 0xAAA
WRITE_READ_CSR mip, 0xAAA
# WRITE_READ_CSR mtinst, 0xAAA # *** these appear not to be implemented in GCC
# WRITE_READ_CSR mtval2, 0xAAA
# Machine Configuration
# WRITE_READ_CSR menvcfg, 0xAAA # *** these appear not to be implemented in GCC
# WRITE_READ_CSR mseccgf, 0xAAA
WRITE_READ_CSR menvcfg, 0xAAA
WRITE_READ_CSR menvcfgh, 0xAAA
WRITE_READ_CSR senvcfg, 0xAAA
WRITE_READ_CSR mseccfg, 0xAAA
# Machine Memory Protection
WRITE_READ_CSR pmpcfg0, 0xAAA

18
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-csr-permission-s-01.reference_output
View file

@ -24,6 +24,12 @@
00000000
00000bad
00000000
00000002 # S mode write to mconfigptr with illegal instruction
00000000
00000002 # S mode read from mconfigptr with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mstatus with illegal instruction
00000000
00000002 # S mode read from mstatus with illegal instruction
@ -96,6 +102,18 @@
00000000
00000bad
00000000
00000002 # S mode write to menvcfg with illegal instruction
00000000
00000002 # S mode read from menvcfg with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mseccfg with illegal instruction
00000000
00000002 # S mode read from mseccfg with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to pmpcfg0 with illegal instruction
00000000
00000002 # S mode read from pmpcfg0 with illegal instruction

18
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-csr-permission-u-01.reference_output
View file

@ -84,6 +84,12 @@
00000000
00000bad
00000000
00000002 # S mode write to mconfigptr with illegal instruction
00000000
00000002 # S mode read from mconfigptr with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to mstatus with illegal instruction
00000000
00000002 # U mode read from mstatus with illegal instruction
@ -156,6 +162,18 @@
00000000
00000bad
00000000
00000002 # S mode write to menvcfg with illegal instruction
00000000
00000002 # S mode read from menvcfg with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mseccfg with illegal instruction
00000000
00000002 # S mode read from mseccfg with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to pmpcfg0 with illegal instruction
00000000
00000002 # U mode read from pmpcfg0 with illegal instruction

8
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-csr-permission-s-01.S
View file

@ -45,7 +45,7 @@ WRITE_READ_CSR mvendorid, 0x111
WRITE_READ_CSR marchid, 0x111
WRITE_READ_CSR mimpid, 0x111
WRITE_READ_CSR mhartid, 0x111
# WRITE_READ_CSR mconfigptr, 0x111 # mconfigptr unimplemented in spike as of 31 Jan 22
WRITE_READ_CSR mconfigptr, 0x111 # mconfigptr unimplemented in spike as of 31 Jan 22
# Machine Trap Setup
WRITE_READ_CSR mstatus, 0x111
@ -62,12 +62,10 @@ WRITE_READ_CSR mepc, 0x111
WRITE_READ_CSR mcause, 0x111
WRITE_READ_CSR mtval, 0x111
WRITE_READ_CSR mip, 0x111
# WRITE_READ_CSR mtinst, 0x111 # *** these appear not to be implemented in GCC
# WRITE_READ_CSR mtval2, 0x111
# Machine Configuration
# WRITE_READ_CSR menvcfg, 0x111 # *** these appear not to be implemented in GCC
# WRITE_READ_CSR mseccgf, 0x111
WRITE_READ_CSR menvcfg, 0x111
WRITE_READ_CSR mseccfg, 0x111
# Machine Memory Protection
WRITE_READ_CSR pmpcfg0, 0x111

8
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-csr-permission-u-01.S
View file

@ -61,7 +61,7 @@ WRITE_READ_CSR mvendorid, 0x111
WRITE_READ_CSR marchid, 0x111
WRITE_READ_CSR mimpid, 0x111
WRITE_READ_CSR mhartid, 0x111
# WRITE_READ_CSR mconfigptr, 0x111 # mconfigptr unimplemented in spike as of 31 Jan 22
WRITE_READ_CSR mconfigptr, 0x111 # mconfigptr unimplemented in spike as of 31 Jan 22
# Machine Trap Setup
WRITE_READ_CSR mstatus, 0x111
@ -78,12 +78,10 @@ WRITE_READ_CSR mepc, 0x111
WRITE_READ_CSR mcause, 0x111
WRITE_READ_CSR mtval, 0x111
WRITE_READ_CSR mip, 0x111
# WRITE_READ_CSR mtinst, 0x111 # *** these appear not to be implemented in GCC
# WRITE_READ_CSR mtval2, 0x111
# Machine Configuration
# WRITE_READ_CSR menvcfg, 0x111 # *** these appear not to be implemented in GCC
# WRITE_READ_CSR mseccgf, 0x111
WRITE_READ_CSR menvcfg, 0x111
WRITE_READ_CSR mseccfg, 0x111
# Machine Memory Protection
WRITE_READ_CSR pmpcfg0, 0x111