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Gate more testbench volatile CSRs on supported extensions

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Jordan Carlin 2025-03-19 14:51:17 -07:00
parent 6e8759cc96
commit 629cbf6cea
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1 changed files with 39 additions and 30 deletions
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testbench/testbench.sv
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@ -841,36 +841,46 @@ end
end end
// Volatile CSRs // Volatile CSRs
void'(rvviRefCsrSetVolatile(0, 32'hC00)); // CYCLE // Counter CSRs
void'(rvviRefCsrSetVolatile(0, 32'hB00)); // MCYCLE if (P.ZICNTR_SUPPORTED) begin
void'(rvviRefCsrSetVolatile(0, 32'hC02)); // INSTRET void'(rvviRefCsrSetVolatile(0, 32'hC00)); // CYCLE
void'(rvviRefCsrSetVolatile(0, 32'hB02)); // MINSTRET void'(rvviRefCsrSetVolatile(0, 32'hB00)); // MCYCLE
void'(rvviRefCsrSetVolatile(0, 32'hC01)); // TIME void'(rvviRefCsrSetVolatile(0, 32'hC02)); // INSTRET
if (P.XLEN == 32) begin void'(rvviRefCsrSetVolatile(0, 32'hB02)); // MINSTRET
void'(rvviRefCsrSetVolatile(0, 32'hC80)); // CYCLEH void'(rvviRefCsrSetVolatile(0, 32'hC01)); // TIME
void'(rvviRefCsrSetVolatile(0, 32'hB80)); // MCYCLEH if (P.XLEN == 32) begin
void'(rvviRefCsrSetVolatile(0, 32'hC82)); // INSTRETH void'(rvviRefCsrSetVolatile(0, 32'hC80)); // CYCLEH
void'(rvviRefCsrSetVolatile(0, 32'hB82)); // MINSTRETH void'(rvviRefCsrSetVolatile(0, 32'hB80)); // MCYCLEH
void'(rvviRefCsrSetVolatile(0, 32'hC81)); // TIMEH void'(rvviRefCsrSetVolatile(0, 32'hC82)); // INSTRETH
end void'(rvviRefCsrSetVolatile(0, 32'hB82)); // MINSTRETH
// User HPMCOUNTER3 - HPMCOUNTER31 void'(rvviRefCsrSetVolatile(0, 32'hC81)); // TIMEH
for (iter='hC03; iter<='hC1F; iter++) begin end
void'(rvviRefCsrSetVolatile(0, iter)); // HPMCOUNTERx // HPM counters
if (P.XLEN == 32) if (P.ZIHPM_SUPPORTED) begin
void'(rvviRefCsrSetVolatile(0, iter+128)); // HPMCOUNTERxH // User HPMCOUNTER3 - HPMCOUNTER31
end if (P.U_SUPPORTED) begin
for (iter='hC03; iter<='hC1F; iter++) begin
void'(rvviRefCsrSetVolatile(0, iter)); // HPMCOUNTERx
if (P.XLEN == 32)
void'(rvviRefCsrSetVolatile(0, iter+128)); // HPMCOUNTERxH
end
end
// Machine MHPMCOUNTER3 - MHPMCOUNTER31 // Machine MHPMCOUNTER3 - MHPMCOUNTER31
for (iter='hB03; iter<='hB1F; iter++) begin for (iter='hB03; iter<='hB1F; iter++) begin
void'(rvviRefCsrSetVolatile(0, iter)); // MHPMCOUNTERx void'(rvviRefCsrSetVolatile(0, iter)); // MHPMCOUNTERx
if (P.XLEN == 32) if (P.XLEN == 32)
void'(rvviRefCsrSetVolatile(0, iter+128)); // MHPMCOUNTERxH void'(rvviRefCsrSetVolatile(0, iter+128)); // MHPMCOUNTERxH
end
end
end end
// cannot predict this register due to latency between // cannot predict this register due to latency between
// pending and taken // pending and taken
void'(rvviRefCsrSetVolatile(0, 32'h344)); // MIP void'(rvviRefCsrSetVolatile(0, 32'h344)); // MIP
void'(rvviRefCsrSetVolatile(0, 32'h144)); // SIP if (P.S_SUPPORTED) begin
void'(rvviRefCsrSetVolatile(0, 32'h144)); // SIP
end
// Privileges for PMA are set in the imperas.ic // Privileges for PMA are set in the imperas.ic
// volatile (IO) regions are defined here // volatile (IO) regions are defined here
@ -893,18 +903,17 @@ end
if (P.SPI_SUPPORTED) begin if (P.SPI_SUPPORTED) begin
void'(rvviRefMemorySetVolatile(P.SPI_BASE, (P.SPI_BASE + P.SPI_RANGE))); void'(rvviRefMemorySetVolatile(P.SPI_BASE, (P.SPI_BASE + P.SPI_RANGE)));
end end
void'(rvviRefCsrSetVolatile(0, 32'h104)); // SIE - Temporary!!!!
end end
if (P.ZICSR_SUPPORTED) begin if (P.ZICSR_SUPPORTED) begin
always @(dut.core.priv.priv.csr.csri.MIP_REGW[7]) void'(rvvi.net_push("MTimerInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[7])); always @(dut.core.priv.priv.csr.csri.MIP_REGW[7]) void'(rvvi.net_push("MTimerInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[7]));
always @(dut.core.priv.priv.csr.csri.MIP_REGW[11]) void'(rvvi.net_push("MExternalInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[11])); always @(dut.core.priv.priv.csr.csri.MIP_REGW[11]) void'(rvvi.net_push("MExternalInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[11]));
always @(dut.core.priv.priv.csr.csri.MIP_REGW[9]) void'(rvvi.net_push("SExternalInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[9]));
always @(dut.core.priv.priv.csr.csri.MIP_REGW[3]) void'(rvvi.net_push("MSWInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[3])); always @(dut.core.priv.priv.csr.csri.MIP_REGW[3]) void'(rvvi.net_push("MSWInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[3]));
always @(dut.core.priv.priv.csr.csri.MIP_REGW[1]) void'(rvvi.net_push("SSWInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[1])); if (P.S_SUPPORTED) begin
always @(dut.core.priv.priv.csr.csri.MIP_REGW[5]) void'(rvvi.net_push("STimerInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[5])); always @(dut.core.priv.priv.csr.csri.MIP_REGW[5]) void'(rvvi.net_push("STimerInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[5]));
always @(dut.core.priv.priv.csr.csri.MIP_REGW[9]) void'(rvvi.net_push("SExternalInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[9]));
always @(dut.core.priv.priv.csr.csri.MIP_REGW[1]) void'(rvvi.net_push("SSWInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[1]));
end
end end
final begin final begin