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Code and testbench cleanup
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parent
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commit
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2 changed files with 7 additions and 8 deletions
14
src/cache/cacheway.sv
vendored
14
src/cache/cacheway.sv
vendored
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@ -135,17 +135,17 @@ module cacheway import cvw::*; #(parameter cvw_t P,
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localparam LOGNUMSRAM = $clog2(NUMSRAM);
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for(words = 0; words < NUMSRAM; words++) begin: word
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if (!READ_ONLY_CACHE) begin:wordram
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ram1p1rwbe #(.USE_SRAM(P.USE_SRAM), .DEPTH(NUMLINES), .WIDTH(P.CACHE_SRAMLEN)) CacheDataMem(.clk, .ce(CacheEn), .addr(CacheSetData),
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.dout(ReadDataLine[P.CACHE_SRAMLEN*(words+1)-1:P.CACHE_SRAMLEN*words]),
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.din(LineWriteData[P.CACHE_SRAMLEN*(words+1)-1:P.CACHE_SRAMLEN*words]),
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.we(SelectedWriteWordEn), .bwe(FinalByteMask[SRAMLENINBYTES*(words+1)-1:SRAMLENINBYTES*words]));
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end else begin:wordram // no byte-enable needed for i$.
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if (READ_ONLY_CACHE) begin:wordram // no byte-enable needed for i$.
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ram1p1rwe #(.USE_SRAM(P.USE_SRAM), .DEPTH(NUMLINES), .WIDTH(P.CACHE_SRAMLEN)) CacheDataMem(.clk, .ce(CacheEn), .addr(CacheSetData),
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.dout(ReadDataLine[P.CACHE_SRAMLEN*(words+1)-1:P.CACHE_SRAMLEN*words]),
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.din(LineWriteData[P.CACHE_SRAMLEN*(words+1)-1:P.CACHE_SRAMLEN*words]),
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.we(SelectedWriteWordEn));
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end
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end else begin:wordram // D$ needs byte enables
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ram1p1rwbe #(.USE_SRAM(P.USE_SRAM), .DEPTH(NUMLINES), .WIDTH(P.CACHE_SRAMLEN)) CacheDataMem(.clk, .ce(CacheEn), .addr(CacheSetData),
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.dout(ReadDataLine[P.CACHE_SRAMLEN*(words+1)-1:P.CACHE_SRAMLEN*words]),
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.din(LineWriteData[P.CACHE_SRAMLEN*(words+1)-1:P.CACHE_SRAMLEN*words]),
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.we(SelectedWriteWordEn), .bwe(FinalByteMask[SRAMLENINBYTES*(words+1)-1:SRAMLENINBYTES*words]));
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end
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end
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// AND portion of distributed read multiplexers
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@ -625,7 +625,6 @@ module testbench;
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dut.core.ieu.dp.regf.wd3 == 1)) |
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((InstrM == 32'h6f | InstrM == 32'hfc32a423 | InstrM == 32'hfc32a823) & dut.core.ieu.c.InstrValidM ) |
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((dut.core.lsu.IEUAdrM == ProgramAddrLabelArray["tohost"]) & InstrMName == "SW" );
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//assign DCacheFlushStart = TestComplete;
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end
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DCacheFlushFSM #(P) DCacheFlushFSM(.clk, .start(DCacheFlushStart), .done(DCacheFlushDone));
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