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Update sim-testfloat to fix errors due to bad config element. I am not sure of the reasoning, but the specific path to the testvector was not getting inserted in Questa. This modification also adds features to test individualized tests (.e.g, binary16 only) -- documentation is added in the FPbuild.txt file

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This commit is contained in:
James E. Stine 2023-06-20 17:26:54 -05:00
parent cde2b1f2d2
commit 66643eb78e
4 changed files with 1255 additions and 1251 deletions
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18
sim/FPbuild.txt
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@ -34,18 +34,14 @@ other FP tests given by the great SoftFloat/TestFloat output.
4a.) Each test will test all its vectors - if you want to test a 4a.) Each test will test all its vectors - if you want to test a
subset of the vectors (e.g., only binary16), you should modify the subset of the vectors (e.g., only binary16), you should modify the
cvw/testbench/tests-fp.h and comment out the tests you do not want to testfloat.do in the sim directory. Change the TEST_SIZE="all" to the
test. The best way to do this is to comment out each item out with specific test you want to run. For example, if you want to run only
the // comment option in SV. For example, binary16, you should set this variable to TEST_SIZE="HP".
string f128div[] = '{
// "f128_div_rne.tv",
// "f128_div_rz.tv",
// "f128_div_ru.tv",
// "f128_div_rd.tv",
// "f128_div_rnm.tv"
};
4b.) If you want to turn off the generation of wlf files while running
sim-testfloat-batch, you can modify testfloat.do in the sim
directory. Inside this DO file, modify the WAV file to 0 --> i.e.,
set "quietly set WAV 0;"

3
sim/sim-testfloat-batch
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@ -10,6 +10,3 @@
# sqrt - test square root # sqrt - test square root
# all - test everything # all - test everything
# nowave for 2nd argument supresses wlf files
vsim -c -do "do testfloat.do rv64fpquad $1 $2"

14
sim/testfloat.do
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@ -27,12 +27,16 @@ vlib work
# $num = the added words after the call # $num = the added words after the call
vlog +incdir+../config/$1 +incdir+../config/shared ../src/wally/cvw.sv ../testbench/testbench-fp.sv ../src/fpu/*.sv ../src/fpu/*/*.sv ../src/generic/*.sv ../src/generic/flop/*.sv -suppress 2583,7063,8607,2697 vlog +incdir+../config/$1 +incdir+../config/shared ../src/wally/cvw.sv ../testbench/testbench-fp.sv ../src/fpu/*.sv ../src/fpu/*/*.sv ../src/generic/*.sv ../src/generic/flop/*.sv -suppress 2583,7063,8607,2697
vsim -voptargs=+acc work.testbenchfp -G TEST=$2 # Change TEST_SIZE to only test certain FP width
# values are QP, DP, SP, HP
vsim -voptargs=+acc work.testbenchfp -GTEST=$2 -GTEST_SIZE="all"
# Determine if nowave argument is provided # Set WAV variable to avoid having any output to wave (to limit disk space)
# this removes any output to a wlf or wave window to reduce quietly set WAV 1;
# disk space.
if {($argc > 2) && ($3 eq "nowave")} { # Determine if nowave argument is provided this removes any output to
# a wlf or wave window to reduce disk space.
if {$WAV eq 0} {
puts "No wave output is selected" puts "No wave output is selected"
} else { } else {
puts "wave output is selected" puts "wave output is selected"

55
testbench/testbench-fp.sv
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@ -1,8 +1,9 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// //
// Written: me@KatherineParry.com // Written: me@KatherineParry.com, james.stine@okstate.edu
// Modified: 7/5/2022 // Modified: 7/5/2022
// Modified: 4/2/2023 // Modified: 4/2/2023
// Modified: 6/19/2023
// //
// Purpose: Testbench for Testfloat // Purpose: Testbench for Testfloat
// //
@ -31,6 +32,7 @@ import cvw::*;
module testbenchfp; module testbenchfp;
parameter TEST="none"; parameter TEST="none";
parameter TEST_SIZE="none";
string Tests[]; // list of tests to be run string Tests[]; // list of tests to be run
logic [2:0] OpCtrl[]; // list of op controls logic [2:0] OpCtrl[]; // list of op controls
@ -132,9 +134,12 @@ module testbenchfp;
// div - test division // div - test division
// sqrt - test square root // sqrt - test square root
// all - test all of the above // all - test all of the above
initial begin initial begin
$display("TEST is %s", TEST); $display("\nThe start of simulation...");
if (`Q_SUPPORTED) begin // if Quad percision is supported $display("This simulation for TEST is %s", TEST);
$display("This simulation for TEST is of the operand size of %s", TEST_SIZE);
if (`Q_SUPPORTED & (TEST_SIZE == "QP" | TEST_SIZE == "all")) begin // if Quad percision is supported
if (TEST === "cvtint" | TEST === "all") begin // if testing integer conversion if (TEST === "cvtint" | TEST === "all") begin // if testing integer conversion
// add the 128-bit cvtint tests to the to-be-tested list // add the 128-bit cvtint tests to the to-be-tested list
Tests = {Tests, f128rv32cvtint}; Tests = {Tests, f128rv32cvtint};
@ -279,7 +284,7 @@ module testbenchfp;
end end
end end
end end
if (`D_SUPPORTED) begin // if double precision is supported if (`D_SUPPORTED & (TEST_SIZE == "DP" | TEST_SIZE == "all")) begin // if double precision is supported
if (TEST === "cvtint" | TEST === "all") begin // if integer conversion is being tested if (TEST === "cvtint" | TEST === "all") begin // if integer conversion is being tested
Tests = {Tests, f64rv32cvtint}; Tests = {Tests, f64rv32cvtint};
// add the op-codes for these tests to the op-code list // add the op-codes for these tests to the op-code list
@ -406,7 +411,7 @@ module testbenchfp;
end end
end end
end end
if (`F_SUPPORTED) begin // if single precision being supported if (`F_SUPPORTED & (TEST_SIZE == "SP" | TEST_SIZE == "all")) begin // if single precision being supported
if (TEST === "cvtint"| TEST === "all") begin // if integer conversion is being tested if (TEST === "cvtint"| TEST === "all") begin // if integer conversion is being tested
Tests = {Tests, f32rv32cvtint}; Tests = {Tests, f32rv32cvtint};
// add the op-codes for these tests to the op-code list // add the op-codes for these tests to the op-code list
@ -517,7 +522,7 @@ module testbenchfp;
end end
end end
end end
if (`ZFH_SUPPORTED) begin // if half precision supported if (`ZFH_SUPPORTED & (TEST_SIZE == "HP" | TEST_SIZE == "all")) begin // if half precision supported
if (TEST === "cvtint" | TEST === "all") begin // if in conversions are being tested if (TEST === "cvtint" | TEST === "all") begin // if in conversions are being tested
Tests = {Tests, f16rv32cvtint}; Tests = {Tests, f16rv32cvtint};
// add the op-codes for these tests to the op-code list // add the op-codes for these tests to the op-code list
@ -630,8 +635,15 @@ module testbenchfp;
// Read the first test // Read the first test
initial begin initial begin
//string testname = {`PATH, Tests[TestNum]};
string p = `PATH;
string testname;
string tt0;
tt0 = $psprintf("%s", Tests[TestNum]);
testname = {p, tt0};
// $display("Here you are %s", testname);
$display("\n\nRunning %s vectors ", Tests[TestNum]); $display("\n\nRunning %s vectors ", Tests[TestNum]);
$readmemh({`PATH, Tests[TestNum]}, TestVectors); $readmemh(testname, TestVectors);
// set the test index to 0 // set the test index to 0
TestNum = 0; TestNum = 0;
end end
@ -652,7 +664,7 @@ module testbenchfp;
end end
// extract the inputs (X, Y, Z, SrcA) and the output (Ans, AnsFlg) from the current test vector // extract the inputs (X, Y, Z, SrcA) and the output (Ans, AnsFlg) from the current test vector
readvectors readvectors (.clk, .Fmt(FmtVal), .ModFmt, .TestVector(TestVectors[VectorNum]), readvectors #(P) readvectors (.clk, .Fmt(FmtVal), .ModFmt, .TestVector(TestVectors[VectorNum]),
.VectorNum, .Ans(Ans), .AnsFlg(AnsFlg), .SrcA, .VectorNum, .Ans(Ans), .AnsFlg(AnsFlg), .SrcA,
.Xs, .Ys, .Zs, .Unit(UnitVal), .Xs, .Ys, .Zs, .Unit(UnitVal),
.Xe, .Ye, .Ze, .TestNum, .OpCtrl(OpCtrlVal), .Xe, .Ye, .Ze, .TestNum, .OpCtrl(OpCtrlVal),
@ -664,7 +676,6 @@ module testbenchfp;
.XInf, .YInf, .ZInf, .XExpMax, .XInf, .YInf, .ZInf, .XExpMax,
.X, .Y, .Z, .XPostBox); .X, .Y, .Z, .XPostBox);
/////////////////////////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////////////////////////
// ||||||| ||| ||| ||||||||| // ||||||| ||| ||| |||||||||
@ -697,13 +708,14 @@ module testbenchfp;
.PostProcFlg(Flg), .PostProcRes(FpRes), .FCvtIntRes(IntRes)); .PostProcFlg(Flg), .PostProcRes(FpRes), .FCvtIntRes(IntRes));
if (TEST === "cvtfp" | TEST === "cvtint" | TEST === "all") begin : fcvt if (TEST === "cvtfp" | TEST === "cvtint" | TEST === "all") begin : fcvt
fcvt fcvt (.Xs(Xs), .Xe(Xe), .Xm(Xm), .Int(SrcA), .ToInt(WriteIntVal), fcvt #(P) fcvt (.Xs(Xs), .Xe(Xe), .Xm(Xm), .Int(SrcA), .ToInt(WriteIntVal),
.XZero(XZero), .OpCtrl(OpCtrlVal), .IntZero, .XZero(XZero), .OpCtrl(OpCtrlVal), .IntZero,
.Fmt(ModFmt), .Ce(CvtCalcExpE), .ShiftAmt(CvtShiftAmtE), .ResSubnormUf(CvtResSubnormUfE), .Cs(CvtResSgnE), .LzcIn(CvtLzcInE)); .Fmt(ModFmt), .Ce(CvtCalcExpE), .ShiftAmt(CvtShiftAmtE),
.ResSubnormUf(CvtResSubnormUfE), .Cs(CvtResSgnE), .LzcIn(CvtLzcInE));
end end
if (TEST === "cmp" | TEST === "all") begin: fcmp if (TEST === "cmp" | TEST === "all") begin: fcmp
fcmp fcmp (.Fmt(ModFmt), .OpCtrl(OpCtrlVal), .Xs, .Ys, .Xe, .Ye, fcmp #(P) fcmp (.Fmt(ModFmt), .OpCtrl(OpCtrlVal), .Xs, .Ys, .Xe, .Ye,
.Xm, .Ym, .XZero, .YZero, .CmpIntRes(CmpRes), .Xm, .Ym, .XZero, .YZero, .CmpIntRes(CmpRes),
.XNaN, .YNaN, .XSNaN, .YSNaN, .X, .Y, .CmpNV(CmpFlg[4]), .CmpFpRes(FpCmpRes)); .XNaN, .YNaN, .XSNaN, .YSNaN, .X, .Y, .CmpNV(CmpFlg[4]), .CmpFpRes(FpCmpRes));
end end
@ -824,7 +836,6 @@ always @(posedge clk)
// check results on falling edge of clk // check results on falling edge of clk
always @(negedge clk) begin always @(negedge clk) begin
// check if the NaN value is good. IEEE754-2019 sections 6.3 and 6.2.3 specify: // check if the NaN value is good. IEEE754-2019 sections 6.3 and 6.2.3 specify:
// - the sign of the NaN does not matter for the opperations being tested // - the sign of the NaN does not matter for the opperations being tested
// - when 2 or more NaNs are inputed the NaN that is propigated doesn't matter // - when 2 or more NaNs are inputed the NaN that is propigated doesn't matter
@ -889,16 +900,14 @@ always @(negedge clk) begin
// check if result is correct // check if result is correct
// - wait till the division result is done or one extra cylcle for early termination (to simulate the EM pipline stage) // - wait till the division result is done or one extra cylcle for early termination (to simulate the EM pipline stage)
// if(~((Res === Ans | NaNGood | NaNGood === 1'bx) & (ResFlg === AnsFlg | AnsFlg === 5'bx))&~((FDivBusyE===1'b1)|DivStart)&(UnitVal !== `CVTINTUNIT)&(UnitVal !== `CMPUNIT)) begin ResMatch = (Res === Ans | NaNGood | NaNGood === 1'bx);
assign ResMatch = (Res === Ans | NaNGood | NaNGood === 1'bx); FlagMatch = (ResFlg === AnsFlg | AnsFlg === 5'bx);
assign FlagMatch = (ResFlg === AnsFlg | AnsFlg === 5'bx); divsqrtop = OpCtrlVal == `SQRT_OPCTRL | OpCtrlVal == `DIV_OPCTRL;
assign divsqrtop = OpCtrlVal == `SQRT_OPCTRL | OpCtrlVal == `DIV_OPCTRL;
assign DivDone = OldFDivBusyE & ~FDivBusyE; assign DivDone = OldFDivBusyE & ~FDivBusyE;
//assign divsqrtop = OpCtrl[TestNum] == `SQRT_OPCTRL | OpCtrl[TestNum] == `DIV_OPCTRL; //assign divsqrtop = OpCtrl[TestNum] == `SQRT_OPCTRL | OpCtrl[TestNum] == `DIV_OPCTRL;
assign CheckNow = (DivDone | ~divsqrtop) & (UnitVal !== `CVTINTUNIT)&(UnitVal !== `CMPUNIT); CheckNow = (DivDone | ~divsqrtop) & (UnitVal !== `CVTINTUNIT)&(UnitVal !== `CMPUNIT);
if(~(ResMatch & FlagMatch) & CheckNow) begin if(~(ResMatch & FlagMatch) & CheckNow) begin
// if(~((Res === Ans | NaNGood | NaNGood === 1'bx) & (ResFlg === AnsFlg | AnsFlg === 5'bx))&(DivDone | (TEST != "sqrt" & TEST != "div"))&(UnitVal !== `CVTINTUNIT)&(UnitVal !== `CMPUNIT)) begin
errors += 1; errors += 1;
$display("TestNum %d OpCtrl %d", TestNum, OpCtrl[TestNum]); $display("TestNum %d OpCtrl %d", TestNum, OpCtrl[TestNum]);
$display("Error in %s", Tests[TestNum]); $display("Error in %s", Tests[TestNum]);
@ -931,15 +940,12 @@ always @(negedge clk) begin
end end
if (TestVectors[VectorNum][0] === 1'bx & Tests[TestNum] !== "") begin // if reached the eof if (TestVectors[VectorNum][0] === 1'bx & Tests[TestNum] !== "") begin // if reached the eof
// increment the test // increment the test
TestNum += 1; TestNum += 1;
// clear the vectors // clear the vectors
for(int i=0; i<6133248; i++) TestVectors[i] = {`FLEN*4+8{1'bx}}; for(int i=0; i<6133248; i++) TestVectors[i] = {`FLEN*4+8{1'bx}};
// read next files // read next files
$readmemh({`PATH, Tests[TestNum]}, TestVectors); $readmemh({`PATH, Tests[TestNum]}, TestVectors);
// set the vector index back to 0 // set the vector index back to 0
VectorNum = 0; VectorNum = 0;
// incemet the operation if all the rounding modes have been tested // incemet the operation if all the rounding modes have been tested
@ -985,9 +991,10 @@ module readvectors (
output logic [`FLEN-1:0] X, Y, Z, XPostBox output logic [`FLEN-1:0] X, Y, Z, XPostBox
); );
logic XEn, YEn, ZEn;
`include "parameter-defs.vh" `include "parameter-defs.vh"
localparam Q_LEN = 32'd128;
logic XEn, YEn, ZEn;
// apply test vectors on rising edge of clk // apply test vectors on rising edge of clk
// Format of vectors Inputs(1/2/3)_AnsFlg // Format of vectors Inputs(1/2/3)_AnsFlg