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3 changed files with 4 additions and 4 deletions
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@ -67,7 +67,7 @@ module fdivsqrt import cvw::*; #(parameter cvw_t P) (
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// Integer div/rem signals
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logic BZeroM; // Denominator is zero
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logic [P.INTDIVBLEN-1:0] IntNormShiftM; // Integer normalizatoin shift amount
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logic [P.DIVBLEN-1:0] IntNormShiftM; // Integer normalizatoin shift amount
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logic ALTBM, AsM, BsM, W64M; // Special handling for postprocessor
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logic [P.XLEN-1:0] AM; // Original Numerator for postprocessor
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logic ISpecialCaseE; // Integer div/remainder special cases
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@ -38,7 +38,7 @@ module fdivsqrtpostproc import cvw::*; #(parameter cvw_t P) (
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input logic SqrtM, SpecialCaseM,
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input logic [P.XLEN-1:0] AM, // U/Q(XLEN.0)
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input logic RemOpM, ALTBM, BZeroM, AsM, BsM, W64M,
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input logic [P.INTDIVBLEN-1:0] IntNormShiftM,
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input logic [P.DIVBLEN-1:0] IntNormShiftM,
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output logic [P.DIVb:0] UmM, // U1.DIVb result significand
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output logic WZeroE,
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output logic DivStickyM,
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@ -57,7 +57,7 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) (
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logic [P.NE+1:0] UeE; // Result Exponent (FP only)
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logic [P.DIVb:0] IFX, IFD; // Correctly-sized inputs for iterator, selected from int or fp input
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logic [P.DIVBLEN-1:0] mE, ell; // Leading zeros of inputs
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logic [P.INTDIVBLEN-1:0] IntResultBitsE; // bits in integer result
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logic [P.DIVBLEN-1:0] IntResultBitsE; // bits in integer result
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logic AZeroE, BZeroE; // A or B is Zero for integer division
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logic SignedDivE; // signed division
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logic AsE, BsE; // Signs of integer inputs
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@ -214,7 +214,7 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) (
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fdivsqrtcycles #(P) cyclecalc(.Nf, .IntDivE, .IntResultBitsE, .CyclesE);
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if (P.IDIV_ON_FPU) begin:intpipelineregs
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logic [P.INTDIVBLEN-1:0] IntDivNormShiftE, IntRemNormShiftE, IntNormShiftE;
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logic [P.DIVBLEN-1:0] IntDivNormShiftE, IntRemNormShiftE, IntNormShiftE;
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logic RemOpE;
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/* verilator lint_off WIDTH */
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