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Merge pull request #327 from harshinisrinath1001/main
Fixed the spacing in the fpu module
This commit is contained in:
Ross Thompson
GitHub
commit
7031a7b1ea
13 changed files with 156 additions and 179 deletions
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@ -35,15 +35,15 @@
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module fcmp import cvw::*; #(parameter cvw_t P) (
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module fcmp import cvw::*; #(parameter cvw_t P) (
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input logic [P.FMTBITS-1:0] Fmt, // format of fp number
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input logic [P.FMTBITS-1:0] Fmt, // format of fp number
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input logic [2:0] OpCtrl, // see above table
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input logic [2:0] OpCtrl, // see above table
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input logic Xs, Ys, // input signs
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input logic Xs, Ys, // input signs
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input logic [P.NE-1:0] Xe, Ye, // input exponents
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input logic [P.NE-1:0] Xe, Ye, // input exponents
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input logic [P.NF:0] Xm, Ym, // input mantissa
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input logic [P.NF:0] Xm, Ym, // input mantissa
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input logic XZero, YZero, // is zero
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input logic XZero, YZero, // is zero
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input logic XNaN, YNaN, // is NaN
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input logic XNaN, YNaN, // is NaN
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input logic XSNaN, YSNaN, // is signaling NaN
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input logic XSNaN, YSNaN, // is signaling NaN
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input logic [P.FLEN-1:0] X, Y, // original inputs (before unpacker)
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input logic [P.FLEN-1:0] X, Y, // original inputs (before unpacker)
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output logic CmpNV, // invalid flag
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output logic CmpNV, // invalid flag
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output logic [P.FLEN-1:0] CmpFpRes, // compare floating-point result
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output logic [P.FLEN-1:0] CmpFpRes, // compare floating-point result
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output logic [P.XLEN-1:0] CmpIntRes // compare integer result
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output logic [P.XLEN-1:0] CmpIntRes // compare integer result
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);
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);
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@ -151,5 +151,4 @@ module fcmp import cvw::*; #(parameter cvw_t P) (
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// - inf = inf and -inf = -inf
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// - inf = inf and -inf = -inf
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// - return 0 if comparison with NaN (unordered)
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// - return 0 if comparison with NaN (unordered)
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assign CmpIntRes = {(P.XLEN-1)'(0), (((EQ|BothZero)&OpCtrl[1])|(LT&OpCtrl[0]&~BothZero))&~EitherNaN};
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assign CmpIntRes = {(P.XLEN-1)'(0), (((EQ|BothZero)&OpCtrl[1])|(LT&OpCtrl[0]&~BothZero))&~EitherNaN};
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endmodule
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endmodule
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@ -27,57 +27,57 @@
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////////////////////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////////////////////
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module fctrl import cvw::*; #(parameter cvw_t P) (
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module fctrl import cvw::*; #(parameter cvw_t P) (
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input logic clk,
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input logic clk,
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input logic reset,
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input logic reset,
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// input control signals
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// input control signals
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input logic StallE, StallM, StallW, // stall signals
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input logic StallE, StallM, StallW, // stall signals
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input logic FlushE, FlushM, FlushW, // flush signals
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input logic FlushE, FlushM, FlushW, // flush signals
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input logic IntDivE, // is inteteger division
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input logic IntDivE, // is inteteger division
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input logic [2:0] FRM_REGW, // rounding mode from CSR
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input logic [2:0] FRM_REGW, // rounding mode from CSR
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input logic [1:0] STATUS_FS, // is FPU enabled?
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input logic [1:0] STATUS_FS, // is FPU enabled?
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input logic FDivBusyE, // is the divider busy
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input logic FDivBusyE, // is the divider busy
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// intruction
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// intruction
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input logic [31:0] InstrD, // the full instruction
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input logic [31:0] InstrD, // the full instruction
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input logic [6:0] Funct7D, // bits 31:25 of instruction - may contain percision
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input logic [6:0] Funct7D, // bits 31:25 of instruction - may contain percision
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input logic [6:0] OpD, // bits 6:0 of instruction
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input logic [6:0] OpD, // bits 6:0 of instruction
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input logic [4:0] Rs2D, // bits 24:20 of instruction
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input logic [4:0] Rs2D, // bits 24:20 of instruction
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input logic [2:0] Funct3D, Funct3E, // bits 14:12 of instruction - may contain rounding mode
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input logic [2:0] Funct3D, Funct3E, // bits 14:12 of instruction - may contain rounding mode
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// input mux selections
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// input mux selections
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output logic XEnD, YEnD, ZEnD, // enable inputs
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output logic XEnD, YEnD, ZEnD, // enable inputs
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output logic XEnE, YEnE, ZEnE, // enable inputs
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output logic XEnE, YEnE, ZEnE, // enable inputs
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// opperation mux selections
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// opperation mux selections
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output logic FCvtIntE, FCvtIntW, // convert to integer opperation
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output logic FCvtIntE, FCvtIntW, // convert to integer opperation
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output logic [2:0] FrmM, // FP rounding mode
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output logic [2:0] FrmM, // FP rounding mode
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output logic [P.FMTBITS-1:0] FmtE, FmtM, // FP format
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output logic [P.FMTBITS-1:0] FmtE, FmtM, // FP format
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output logic [2:0] OpCtrlE, OpCtrlM, // Select which opperation to do in each component
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output logic [2:0] OpCtrlE, OpCtrlM, // Select which opperation to do in each component
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output logic FpLoadStoreM, // FP load or store instruction
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output logic FpLoadStoreM, // FP load or store instruction
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output logic [1:0] PostProcSelE, PostProcSelM, // select result in the post processing unit
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output logic [1:0] PostProcSelE, PostProcSelM, // select result in the post processing unit
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output logic [1:0] FResSelE, FResSelM, FResSelW, // Select one of the results that finish in the memory stage
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output logic [1:0] FResSelE, FResSelM, FResSelW, // Select one of the results that finish in the memory stage
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// register control signals
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// register control signals
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output logic FRegWriteE, FRegWriteM, FRegWriteW, // FP register write enable
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output logic FRegWriteE, FRegWriteM, FRegWriteW, // FP register write enable
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output logic FWriteIntE, FWriteIntM, // Write to integer register
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output logic FWriteIntE, FWriteIntM, // Write to integer register
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output logic [4:0] Adr1D, Adr2D, Adr3D, // adresses of each input
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output logic [4:0] Adr1D, Adr2D, Adr3D, // adresses of each input
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output logic [4:0] Adr1E, Adr2E, Adr3E, // adresses of each input
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output logic [4:0] Adr1E, Adr2E, Adr3E, // adresses of each input
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// other control signals
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// other control signals
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output logic IllegalFPUInstrD, // Is the instruction an illegal fpu instruction
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output logic IllegalFPUInstrD, // Is the instruction an illegal fpu instruction
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output logic FDivStartE, IDivStartE // Start division or squareroot
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output logic FDivStartE, IDivStartE // Start division or squareroot
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);
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);
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`define FCTRLW 12
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`define FCTRLW 12
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logic [`FCTRLW-1:0] ControlsD; // control signals
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logic [`FCTRLW-1:0] ControlsD; // control signals
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logic FRegWriteD; // FP register write enable
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logic FRegWriteD; // FP register write enable
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logic FDivStartD; // start division/sqrt
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logic FDivStartD; // start division/sqrt
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logic FWriteIntD; // integer register write enable
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logic FWriteIntD; // integer register write enable
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logic [2:0] OpCtrlD; // Select which opperation to do in each component
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logic [2:0] OpCtrlD; // Select which opperation to do in each component
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logic [1:0] PostProcSelD; // select result in the post processing unit
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logic [1:0] PostProcSelD; // select result in the post processing unit
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logic [1:0] FResSelD; // Select one of the results that finish in the memory stage
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logic [1:0] FResSelD; // Select one of the results that finish in the memory stage
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logic [2:0] FrmD, FrmE; // FP rounding mode
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logic [2:0] FrmD, FrmE; // FP rounding mode
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logic [P.FMTBITS-1:0] FmtD; // FP format
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logic [P.FMTBITS-1:0] FmtD; // FP format
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logic [1:0] Fmt, Fmt2; // format - before possible reduction
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logic [1:0] Fmt, Fmt2; // format - before possible reduction
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logic SupportedFmt; // is the format supported
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logic SupportedFmt; // is the format supported
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logic SupportedFmt2; // is the source format supported for fp -> fp
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logic SupportedFmt2; // is the source format supported for fp -> fp
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logic FCvtIntD, FCvtIntM; // convert to integer opperation
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logic FCvtIntD, FCvtIntM; // convert to integer opperation
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// FPU Instruction Decoder
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// FPU Instruction Decoder
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assign Fmt = Funct7D[1:0];
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assign Fmt = Funct7D[1:0];
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@ -97,7 +97,7 @@ module fctrl import cvw::*; #(parameter cvw_t P) (
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ControlsD = `FCTRLW'b0_0_00_00_000_0_1_0; // for anything other than loads and stores, check for supported format
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ControlsD = `FCTRLW'b0_0_00_00_000_0_1_0; // for anything other than loads and stores, check for supported format
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else begin
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else begin
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ControlsD = `FCTRLW'b0_0_00_00_000_0_1_0; // default: non-implemented instruction
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ControlsD = `FCTRLW'b0_0_00_00_000_0_1_0; // default: non-implemented instruction
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/* verilator lint_off CASEINCOMPLETE */ // default value above has priority so no other default needed
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/* verilator lint_off CASEINCOMPLETE */ // default value above has priority so no other default needed
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case(OpD)
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case(OpD)
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7'b0000111: case(Funct3D)
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7'b0000111: case(Funct3D)
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3'b010: ControlsD = `FCTRLW'b1_0_10_00_0xx_0_0_0; // flw
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3'b010: ControlsD = `FCTRLW'b1_0_10_00_0xx_0_0_0; // flw
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@ -1,4 +1,3 @@
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///////////////////////////////////////////
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///////////////////////////////////////////
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// fcvt.sv
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// fcvt.sv
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//
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//
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@ -96,7 +95,7 @@ module fcvt import cvw::*; #(parameter cvw_t P) (
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// int -> fp : | positive integer | 00000... (if needed) |
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// int -> fp : | positive integer | 00000... (if needed) |
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// fp -> fp : | fraction | 00000... (if needed) |
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// fp -> fp : | fraction | 00000... (if needed) |
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assign LzcInFull = IntToFp ? {TrimInt, {P.CVTLEN-P.XLEN+1{1'b0}}} :
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assign LzcInFull = IntToFp ? {TrimInt, {P.CVTLEN-P.XLEN+1{1'b0}}} :
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{Xm, {P.CVTLEN-P.NF{1'b0}}};
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{Xm, {P.CVTLEN-P.NF{1'b0}}};
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// used as shifter input in postprocessor
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// used as shifter input in postprocessor
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assign LzcIn = LzcInFull[P.CVTLEN-1:0];
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assign LzcIn = LzcInFull[P.CVTLEN-1:0];
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@ -222,5 +221,4 @@ module fcvt import cvw::*; #(parameter cvw_t P) (
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if(Int64) Cs = Int[P.XLEN-1]&Signed;
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if(Int64) Cs = Int[P.XLEN-1]&Signed;
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else Cs = Int[31]&Signed;
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else Cs = Int[31]&Signed;
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else Cs = Xs;
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else Cs = Xs;
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endmodule
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endmodule
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@ -56,7 +56,6 @@ module fhazard(
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// if the needed value is in the writeback stage
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// if the needed value is in the writeback stage
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end else if ((Adr1E == RdW) & FRegWriteW) ForwardXE = 2'b01; // choose FResult64W
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end else if ((Adr1E == RdW) & FRegWriteW) ForwardXE = 2'b01; // choose FResult64W
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// if the needed value is in the memory stage - input 2
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// if the needed value is in the memory stage - input 2
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if ((Adr2E == RdM) & FRegWriteM) begin
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if ((Adr2E == RdM) & FRegWriteM) begin
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// if the result will be FResM (can be taken from the memory stage)
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// if the result will be FResM (can be taken from the memory stage)
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@ -64,7 +63,6 @@ module fhazard(
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// if the needed value is in the writeback stage
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// if the needed value is in the writeback stage
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end else if ((Adr2E == RdW) & FRegWriteW) ForwardYE = 2'b01; // choose FResult64W
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end else if ((Adr2E == RdW) & FRegWriteW) ForwardYE = 2'b01; // choose FResult64W
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// if the needed value is in the memory stage - input 3
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// if the needed value is in the memory stage - input 3
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if ((Adr3E == RdM) & FRegWriteM) begin
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if ((Adr3E == RdM) & FRegWriteM) begin
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// if the result will be FResM (can be taken from the memory stage)
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// if the result will be FResM (can be taken from the memory stage)
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@ -72,5 +70,4 @@ module fhazard(
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// if the needed value is in the writeback stage
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// if the needed value is in the writeback stage
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end else if ((Adr3E == RdW) & FRegWriteW) ForwardZE = 2'b01; // choose FResult64W
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end else if ((Adr3E == RdW) & FRegWriteW) ForwardZE = 2'b01; // choose FResult64W
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end
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end
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endmodule
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endmodule
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181
src/fpu/fpu.sv
181
src/fpu/fpu.sv
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////////////////////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////////////////////
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module fpu import cvw::*; #(parameter cvw_t P) (
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module fpu import cvw::*; #(parameter cvw_t P) (
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input logic clk,
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input logic clk,
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input logic reset,
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input logic reset,
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// Hazards
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// Hazards
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input logic StallE, StallM, StallW, // stall signals (from HZU)
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input logic StallE, StallM, StallW, // stall signals (from HZU)
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input logic FlushE, FlushM, FlushW, // flush signals (from HZU)
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input logic FlushE, FlushM, FlushW, // flush signals (from HZU)
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output logic FPUStallD, // Stall the decode stage (To HZU)
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output logic FPUStallD, // Stall the decode stage (To HZU)
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output logic FDivBusyE, // Is the divide/sqrt unit busy (stall execute stage) (to HZU)
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output logic FDivBusyE, // Is the divide/sqrt unit busy (stall execute stage) (to HZU)
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// CSRs
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// CSRs
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input logic [1:0] STATUS_FS, // Is floating-point enabled? (From privileged unit)
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input logic [1:0] STATUS_FS, // Is floating-point enabled? (From privileged unit)
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input logic [2:0] FRM_REGW, // Rounding mode (from CSR)
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input logic [2:0] FRM_REGW, // Rounding mode (from CSR)
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// Decode stage
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// Decode stage
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input logic [31:0] InstrD, // instruction (from IFU)
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input logic [31:0] InstrD, // instruction (from IFU)
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// Execute stage
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// Execute stage
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input logic [2:0] Funct3E, // Funct fields of instruction specify type of operations
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input logic [2:0] Funct3E, // Funct fields of instruction specify type of operations
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input logic IntDivE, W64E, // Integer division on FPU
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input logic IntDivE, W64E, // Integer division on FPU
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input logic [P.XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // Integer input for convert, move, and int div (from IEU)
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input logic [P.XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // Integer input for convert, move, and int div (from IEU)
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input logic [4:0] RdE, // which FP register to write to (from IEU)
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input logic [4:0] RdE, // which FP register to write to (from IEU)
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output logic FWriteIntE, // integer register write enable (to IEU)
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output logic FWriteIntE, // integer register write enable (to IEU)
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output logic FCvtIntE, // Convert to int (to IEU)
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output logic FCvtIntE, // Convert to int (to IEU)
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// Memory stage
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// Memory stage
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input logic [2:0] Funct3M, // Funct fields of instruction specify type of operations
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input logic [2:0] Funct3M, // Funct fields of instruction specify type of operations
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input logic [4:0] RdM, // which FP register to write to (from IEU)
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input logic [4:0] RdM, // which FP register to write to (from IEU)
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output logic FRegWriteM, // FP register write enable (to privileged unit)
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output logic FRegWriteM, // FP register write enable (to privileged unit)
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output logic FpLoadStoreM, // Fp load instruction? (to LSU)
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output logic FpLoadStoreM, // Fp load instruction? (to LSU)
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output logic [P.FLEN-1:0] FWriteDataM, // Data to be written to memory (to LSU)
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output logic [P.FLEN-1:0] FWriteDataM, // Data to be written to memory (to LSU)
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output logic [P.XLEN-1:0] FIntResM, // data to be written to integer register (to IEU)
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output logic [P.XLEN-1:0] FIntResM, // data to be written to integer register (to IEU)
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output logic IllegalFPUInstrD, // Is the instruction an illegal fpu instruction (to IFU)
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output logic IllegalFPUInstrD, // Is the instruction an illegal fpu instruction (to IFU)
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output logic [4:0] SetFflagsM, // FPU flags (to privileged unit)
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output logic [4:0] SetFflagsM, // FPU flags (to privileged unit)
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// Writeback stage
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// Writeback stage
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input logic [4:0] RdW, // which FP register to write to (from IEU)
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input logic [4:0] RdW, // which FP register to write to (from IEU)
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input logic [P.FLEN-1:0] ReadDataW, // Read data (from LSU)
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input logic [P.FLEN-1:0] ReadDataW, // Read data (from LSU)
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output logic [P.XLEN-1:0] FCvtIntResW, // convert result to to be written to integer register (to IEU)
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output logic [P.XLEN-1:0] FCvtIntResW, // convert result to to be written to integer register (to IEU)
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output logic FCvtIntW, // select FCvtIntRes (to IEU)
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output logic FCvtIntW, // select FCvtIntRes (to IEU)
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output logic [P.XLEN-1:0] FIntDivResultW // Result from integer division (to IEU)
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output logic [P.XLEN-1:0] FIntDivResultW // Result from integer division (to IEU)
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);
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);
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// RISC-V FPU specifics:
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// RISC-V FPU specifics:
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@ -68,86 +68,86 @@ module fpu import cvw::*; #(parameter cvw_t P) (
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// - RISC-V detects underflow after rounding
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// - RISC-V detects underflow after rounding
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// control signals
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// control signals
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logic FRegWriteW; // FP register write enable
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logic FRegWriteW; // FP register write enable
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logic [2:0] FrmM; // FP rounding mode
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logic [2:0] FrmM; // FP rounding mode
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logic [P.FMTBITS-1:0] FmtE, FmtM; // FP precision 0-single 1-double
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logic [P.FMTBITS-1:0] FmtE, FmtM; // FP precision 0-single 1-double
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logic FDivStartE, IDivStartE; // Start division or squareroot
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logic FDivStartE, IDivStartE; // Start division or squareroot
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logic FWriteIntM; // Write to integer register
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logic FWriteIntM; // Write to integer register
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logic [1:0] ForwardXE, ForwardYE, ForwardZE; // forwarding mux control signals
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logic [1:0] ForwardXE, ForwardYE, ForwardZE; // forwarding mux control signals
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logic [2:0] OpCtrlE, OpCtrlM; // Select which opperation to do in each component
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logic [2:0] OpCtrlE, OpCtrlM; // Select which opperation to do in each component
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logic [1:0] FResSelE, FResSelM, FResSelW; // Select one of the results that finish in the memory stage
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logic [1:0] FResSelE, FResSelM, FResSelW; // Select one of the results that finish in the memory stage
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logic [1:0] PostProcSelE, PostProcSelM; // select result in the post processing unit
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logic [1:0] PostProcSelE, PostProcSelM; // select result in the post processing unit
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logic [4:0] Adr1D, Adr2D, Adr3D; // register adresses of each input
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logic [4:0] Adr1D, Adr2D, Adr3D; // register adresses of each input
|
||||||
logic [4:0] Adr1E, Adr2E, Adr3E; // register adresses of each input
|
logic [4:0] Adr1E, Adr2E, Adr3E; // register adresses of each input
|
||||||
logic XEnD, YEnD, ZEnD; // X, Y, Z inputs used for current operation
|
logic XEnD, YEnD, ZEnD; // X, Y, Z inputs used for current operation
|
||||||
logic XEnE, YEnE, ZEnE; // X, Y, Z inputs used for current operation
|
logic XEnE, YEnE, ZEnE; // X, Y, Z inputs used for current operation
|
||||||
logic FRegWriteE; // Write floating-point register
|
logic FRegWriteE; // Write floating-point register
|
||||||
|
|
||||||
// regfile signals
|
// regfile signals
|
||||||
logic [P.FLEN-1:0] FRD1D, FRD2D, FRD3D; // Read Data from FP register - decode stage
|
logic [P.FLEN-1:0] FRD1D, FRD2D, FRD3D; // Read Data from FP register - decode stage
|
||||||
logic [P.FLEN-1:0] FRD1E, FRD2E, FRD3E; // Read Data from FP register - execute stage
|
logic [P.FLEN-1:0] FRD1E, FRD2E, FRD3E; // Read Data from FP register - execute stage
|
||||||
logic [P.FLEN-1:0] XE; // Input 1 to the various units (after forwarding)
|
logic [P.FLEN-1:0] XE; // Input 1 to the various units (after forwarding)
|
||||||
logic [P.XLEN-1:0] IntSrcXE; // Input 1 to the various units (after forwarding)
|
logic [P.XLEN-1:0] IntSrcXE; // Input 1 to the various units (after forwarding)
|
||||||
logic [P.FLEN-1:0] PreYE, YE; // Input 2 to the various units (after forwarding)
|
logic [P.FLEN-1:0] PreYE, YE; // Input 2 to the various units (after forwarding)
|
||||||
logic [P.FLEN-1:0] PreZE, ZE; // Input 3 to the various units (after forwarding)
|
logic [P.FLEN-1:0] PreZE, ZE; // Input 3 to the various units (after forwarding)
|
||||||
|
|
||||||
// unpacking signals
|
// unpacking signals
|
||||||
logic XsE, YsE, ZsE; // input's sign - execute stage
|
logic XsE, YsE, ZsE; // input's sign - execute stage
|
||||||
logic XsM, YsM; // input's sign - memory stage
|
logic XsM, YsM; // input's sign - memory stage
|
||||||
logic [P.NE-1:0] XeE, YeE, ZeE; // input's exponent - execute stage
|
logic [P.NE-1:0] XeE, YeE, ZeE; // input's exponent - execute stage
|
||||||
logic [P.NE-1:0] ZeM; // input's exponent - memory stage
|
logic [P.NE-1:0] ZeM; // input's exponent - memory stage
|
||||||
logic [P.NF:0] XmE, YmE, ZmE; // input's significand - execute stage
|
logic [P.NF:0] XmE, YmE, ZmE; // input's significand - execute stage
|
||||||
logic [P.NF:0] XmM, YmM, ZmM; // input's significand - memory stage
|
logic [P.NF:0] XmM, YmM, ZmM; // input's significand - memory stage
|
||||||
logic XNaNE, YNaNE, ZNaNE; // is the input a NaN - execute stage
|
logic XNaNE, YNaNE, ZNaNE; // is the input a NaN - execute stage
|
||||||
logic XNaNM, YNaNM, ZNaNM; // is the input a NaN - memory stage
|
logic XNaNM, YNaNM, ZNaNM; // is the input a NaN - memory stage
|
||||||
logic XSNaNE, YSNaNE, ZSNaNE; // is the input a signaling NaN - execute stage
|
logic XSNaNE, YSNaNE, ZSNaNE; // is the input a signaling NaN - execute stage
|
||||||
logic XSNaNM, YSNaNM, ZSNaNM; // is the input a signaling NaN - memory stage
|
logic XSNaNM, YSNaNM, ZSNaNM; // is the input a signaling NaN - memory stage
|
||||||
logic XSubnormE; // is the input subnormal
|
logic XSubnormE; // is the input subnormal
|
||||||
logic XZeroE, YZeroE, ZZeroE; // is the input zero - execute stage
|
logic XZeroE, YZeroE, ZZeroE; // is the input zero - execute stage
|
||||||
logic XZeroM, YZeroM; // is the input zero - memory stage
|
logic XZeroM, YZeroM; // is the input zero - memory stage
|
||||||
logic XInfE, YInfE, ZInfE; // is the input infinity - execute stage
|
logic XInfE, YInfE, ZInfE; // is the input infinity - execute stage
|
||||||
logic XInfM, YInfM, ZInfM; // is the input infinity - memory stage
|
logic XInfM, YInfM, ZInfM; // is the input infinity - memory stage
|
||||||
logic XExpMaxE; // is the exponent all ones (max value)
|
logic XExpMaxE; // is the exponent all ones (max value)
|
||||||
logic [P.FLEN-1:0] XPostBoxE; // X after fixing bad NaN box. Needed for 1-input operations
|
logic [P.FLEN-1:0] XPostBoxE; // X after fixing bad NaN box. Needed for 1-input operations
|
||||||
|
|
||||||
// Fma Signals
|
// Fma Signals
|
||||||
logic FmaAddSubE; // Multiply by 1.0 when adding or subtracting
|
logic FmaAddSubE; // Multiply by 1.0 when adding or subtracting
|
||||||
logic [1:0] FmaZSelE; // Select Z = Y when adding or subtracting, 0 when multiplying
|
logic [1:0] FmaZSelE; // Select Z = Y when adding or subtracting, 0 when multiplying
|
||||||
logic [3*P.NF+3:0] SmE, SmM; // Sum significand
|
logic [3*P.NF+3:0] SmE, SmM; // Sum significand
|
||||||
logic FmaAStickyE, FmaAStickyM; // FMA addend sticky bit output
|
logic FmaAStickyE, FmaAStickyM; // FMA addend sticky bit output
|
||||||
logic [P.NE+1:0] SeE,SeM; // Sum exponent
|
logic [P.NE+1:0] SeE,SeM; // Sum exponent
|
||||||
logic InvAE, InvAM; // Invert addend
|
logic InvAE, InvAM; // Invert addend
|
||||||
logic AsE, AsM; // Addend sign
|
logic AsE, AsM; // Addend sign
|
||||||
logic PsE, PsM; // Product sign
|
logic PsE, PsM; // Product sign
|
||||||
logic SsE, SsM; // Sum sign
|
logic SsE, SsM; // Sum sign
|
||||||
logic [$clog2(3*P.NF+5)-1:0] SCntE, SCntM; // LZA sum leading zero count
|
logic [$clog2(3*P.NF+5)-1:0] SCntE, SCntM; // LZA sum leading zero count
|
||||||
|
|
||||||
// Cvt Signals
|
// Cvt Signals
|
||||||
logic [P.NE:0] CeE, CeM; // convert intermediate expoent
|
logic [P.NE:0] CeE, CeM; // convert intermediate expoent
|
||||||
logic [P.LOGCVTLEN-1:0] CvtShiftAmtE, CvtShiftAmtM; // how much to shift by
|
logic [P.LOGCVTLEN-1:0] CvtShiftAmtE, CvtShiftAmtM; // how much to shift by
|
||||||
logic CvtResSubnormUfE, CvtResSubnormUfM; // does the result underflow or is subnormal
|
logic CvtResSubnormUfE, CvtResSubnormUfM; // does the result underflow or is subnormal
|
||||||
logic CsE, CsM; // convert result sign
|
logic CsE, CsM; // convert result sign
|
||||||
logic IntZeroE, IntZeroM; // is the integer zero?
|
logic IntZeroE, IntZeroM; // is the integer zero?
|
||||||
logic [P.CVTLEN-1:0] CvtLzcInE, CvtLzcInM; // input to the Leading Zero Counter (priority encoder)
|
logic [P.CVTLEN-1:0] CvtLzcInE, CvtLzcInM; // input to the Leading Zero Counter (priority encoder)
|
||||||
logic [P.XLEN-1:0] FCvtIntResM; // fcvt integer result (for IEU)
|
logic [P.XLEN-1:0] FCvtIntResM; // fcvt integer result (for IEU)
|
||||||
|
|
||||||
// divide signals
|
// divide signals
|
||||||
logic [P.DIVb:0] QmM; // fdivsqrt signifcand
|
logic [P.DIVb:0] QmM; // fdivsqrt signifcand
|
||||||
logic [P.NE+1:0] QeM; // fdivsqrt exponent
|
logic [P.NE+1:0] QeM; // fdivsqrt exponent
|
||||||
logic DivStickyM; // fdivsqrt sticky bit
|
logic DivStickyM; // fdivsqrt sticky bit
|
||||||
logic FDivDoneE, IFDivStartE; // fdivsqrt control signals
|
logic FDivDoneE, IFDivStartE; // fdivsqrt control signals
|
||||||
logic [P.XLEN-1:0] FIntDivResultM; // fdivsqrt integer division result (for IEU)
|
logic [P.XLEN-1:0] FIntDivResultM; // fdivsqrt integer division result (for IEU)
|
||||||
|
|
||||||
// result and flag signals
|
// result and flag signals
|
||||||
logic [P.XLEN-1:0] ClassResE; // classify result
|
logic [P.XLEN-1:0] ClassResE; // classify result
|
||||||
logic [P.FLEN-1:0] CmpFpResE; // compare result to FPU (min/max)
|
logic [P.FLEN-1:0] CmpFpResE; // compare result to FPU (min/max)
|
||||||
logic [P.XLEN-1:0] CmpIntResE; // compare result to IEU (eq/lt/le)
|
logic [P.XLEN-1:0] CmpIntResE; // compare result to IEU (eq/lt/le)
|
||||||
logic CmpNVE; // compare invalid flag (Not Valid)
|
logic CmpNVE; // compare invalid flag (Not Valid)
|
||||||
logic [P.FLEN-1:0] SgnResE; // sign injection result
|
logic [P.FLEN-1:0] SgnResE; // sign injection result
|
||||||
logic [P.XLEN-1:0] FIntResE; // FPU to IEU E-stage result (classify, compare, move)
|
logic [P.XLEN-1:0] FIntResE; // FPU to IEU E-stage result (classify, compare, move)
|
||||||
logic [P.FLEN-1:0] PostProcResM; // Postprocessor output
|
logic [P.FLEN-1:0] PostProcResM; // Postprocessor output
|
||||||
logic [4:0] PostProcFlgM; // Postprocessor flags
|
logic [4:0] PostProcFlgM; // Postprocessor flags
|
||||||
logic PreNVE, PreNVM; // selected flag that is ready in the memory stage
|
logic PreNVE, PreNVM; // selected flag that is ready in the memory stage
|
||||||
logic [P.FLEN-1:0] FpResM, FpResW; // FPU preliminary result
|
logic [P.FLEN-1:0] FpResM, FpResW; // FPU preliminary result
|
||||||
logic [P.FLEN-1:0] PreFpResE, PreFpResM; // selected result that is ready in the memory stage
|
logic [P.FLEN-1:0] PreFpResE, PreFpResM; // selected result that is ready in the memory stage
|
||||||
logic [P.FLEN-1:0] FResultW; // final FP result being written to the FP register
|
logic [P.FLEN-1:0] FResultW; // final FP result being written to the FP register
|
||||||
|
|
@ -156,9 +156,9 @@ module fpu import cvw::*; #(parameter cvw_t P) (
|
||||||
logic [P.FLEN-1:0] AlignedSrcAE; // align SrcA from IEU to the floating point format for fmv
|
logic [P.FLEN-1:0] AlignedSrcAE; // align SrcA from IEU to the floating point format for fmv
|
||||||
logic [P.FLEN-1:0] BoxedZeroE; // Zero value for Z for multiplication, with NaN boxing if needed
|
logic [P.FLEN-1:0] BoxedZeroE; // Zero value for Z for multiplication, with NaN boxing if needed
|
||||||
logic [P.FLEN-1:0] BoxedOneE; // One value for Z for multiplication, with NaN boxing if needed
|
logic [P.FLEN-1:0] BoxedOneE; // One value for Z for multiplication, with NaN boxing if needed
|
||||||
logic StallUnpackedM; // Stall unpacker outputs during multicycle fdivsqrt
|
logic StallUnpackedM; // Stall unpacker outputs during multicycle fdivsqrt
|
||||||
logic [P.FLEN-1:0] SgnExtXE; // Sign-extended X input for move to integer
|
logic [P.FLEN-1:0] SgnExtXE; // Sign-extended X input for move to integer
|
||||||
logic mvsgn; // sign bit for extending move
|
logic mvsgn; // sign bit for extending move
|
||||||
|
|
||||||
//////////////////////////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////////////////////////
|
||||||
// Decode Stage: fctrl decoder, read register file
|
// Decode Stage: fctrl decoder, read register file
|
||||||
|
|
@ -205,15 +205,15 @@ module fpu import cvw::*; #(parameter cvw_t P) (
|
||||||
mux2 #(P.FLEN) fonemux ({{P.FLEN-P.LEN1{1'b1}}, 2'b0, {P.NE1-1{1'b1}}, (P.NF1)'(0)}, {2'b0, {P.NE-1{1'b1}}, (P.NF)'(0)}, FmtE, BoxedOneE); // NaN boxing zeroes
|
mux2 #(P.FLEN) fonemux ({{P.FLEN-P.LEN1{1'b1}}, 2'b0, {P.NE1-1{1'b1}}, (P.NF1)'(0)}, {2'b0, {P.NE-1{1'b1}}, (P.NF)'(0)}, FmtE, BoxedOneE); // NaN boxing zeroes
|
||||||
else if(P.FPSIZES == 3 | P.FPSIZES == 4)
|
else if(P.FPSIZES == 3 | P.FPSIZES == 4)
|
||||||
mux4 #(P.FLEN) fonemux ({{P.FLEN-P.S_LEN{1'b1}}, 2'b0, {P.S_NE-1{1'b1}}, (P.S_NF)'(0)},
|
mux4 #(P.FLEN) fonemux ({{P.FLEN-P.S_LEN{1'b1}}, 2'b0, {P.S_NE-1{1'b1}}, (P.S_NF)'(0)},
|
||||||
{{P.FLEN-P.D_LEN{1'b1}}, 2'b0, {P.D_NE-1{1'b1}}, (P.D_NF)'(0)},
|
{{P.FLEN-P.D_LEN{1'b1}}, 2'b0, {P.D_NE-1{1'b1}}, (P.D_NF)'(0)},
|
||||||
{{P.FLEN-P.H_LEN{1'b1}}, 2'b0, {P.H_NE-1{1'b1}}, (P.H_NF)'(0)},
|
{{P.FLEN-P.H_LEN{1'b1}}, 2'b0, {P.H_NE-1{1'b1}}, (P.H_NF)'(0)},
|
||||||
{2'b0, {P.NE-1{1'b1}}, (P.NF)'(0)}, FmtE, BoxedOneE); // NaN boxing zeroes
|
{2'b0, {P.NE-1{1'b1}}, (P.NF)'(0)}, FmtE, BoxedOneE); // NaN boxing zeroes
|
||||||
assign FmaAddSubE = OpCtrlE[2]&OpCtrlE[1]&(FResSelE==2'b01)&(PostProcSelE==2'b10);
|
assign FmaAddSubE = OpCtrlE[2]&OpCtrlE[1]&(FResSelE==2'b01)&(PostProcSelE==2'b10);
|
||||||
mux2 #(P.FLEN) fyaddmux (PreYE, BoxedOneE, FmaAddSubE, YE); // Force Y to be 1 for add/subtract
|
mux2 #(P.FLEN) fyaddmux (PreYE, BoxedOneE, FmaAddSubE, YE); // Force Y to be 1 for add/subtract
|
||||||
|
|
||||||
// Select NAN-boxed value of Z = 0.0 in proper format for FMA for multiply X*Y+Z
|
// Select NAN-boxed value of Z = 0.0 in proper format for FMA for multiply X*Y+Z
|
||||||
// For add and subtract, Z comes from second source operand
|
// For add and subtract, Z comes from second source operand
|
||||||
if(P.FPSIZES == 1) assign BoxedZeroE = 0;
|
if(P.FPSIZES == 1) assign BoxedZeroE = 0;
|
||||||
else if(P.FPSIZES == 2)
|
else if(P.FPSIZES == 2)
|
||||||
mux2 #(P.FLEN) fmulzeromux ({{P.FLEN-P.LEN1{1'b1}}, {P.LEN1{1'b0}}}, (P.FLEN)'(0), FmtE, BoxedZeroE); // NaN boxing zeroes
|
mux2 #(P.FLEN) fmulzeromux ({{P.FLEN-P.LEN1{1'b1}}, {P.LEN1{1'b0}}}, (P.FLEN)'(0), FmtE, BoxedZeroE); // NaN boxing zeroes
|
||||||
else if(P.FPSIZES == 3 | P.FPSIZES == 4)
|
else if(P.FPSIZES == 3 | P.FPSIZES == 4)
|
||||||
|
|
@ -262,7 +262,6 @@ module fpu import cvw::*; #(parameter cvw_t P) (
|
||||||
.ToInt(FWriteIntE), .XZero(XZeroE), .Fmt(FmtE), .Ce(CeE), .ShiftAmt(CvtShiftAmtE),
|
.ToInt(FWriteIntE), .XZero(XZeroE), .Fmt(FmtE), .Ce(CeE), .ShiftAmt(CvtShiftAmtE),
|
||||||
.ResSubnormUf(CvtResSubnormUfE), .Cs(CsE), .IntZero(IntZeroE), .LzcIn(CvtLzcInE));
|
.ResSubnormUf(CvtResSubnormUfE), .Cs(CsE), .IntZero(IntZeroE), .LzcIn(CvtLzcInE));
|
||||||
|
|
||||||
|
|
||||||
// NaN Box SrcA to convert integer to requested FP size
|
// NaN Box SrcA to convert integer to requested FP size
|
||||||
if(P.FPSIZES == 1) assign AlignedSrcAE = {{P.FLEN-P.XLEN{1'b1}}, ForwardedSrcAE};
|
if(P.FPSIZES == 1) assign AlignedSrcAE = {{P.FLEN-P.XLEN{1'b1}}, ForwardedSrcAE};
|
||||||
else if(P.FPSIZES == 2)
|
else if(P.FPSIZES == 2)
|
||||||
|
|
@ -334,7 +333,7 @@ module fpu import cvw::*; #(parameter cvw_t P) (
|
||||||
.PostProcSel(PostProcSelM), .PostProcRes(PostProcResM), .PostProcFlg(PostProcFlgM), .FCvtIntRes(FCvtIntResM));
|
.PostProcSel(PostProcSelM), .PostProcRes(PostProcResM), .PostProcFlg(PostProcFlgM), .FCvtIntRes(FCvtIntResM));
|
||||||
|
|
||||||
// FPU flag selection - to privileged
|
// FPU flag selection - to privileged
|
||||||
mux2 #(5) FPUFlgMux({PreNVM&~FResSelM[1], 4'b0}, PostProcFlgM, ~FResSelM[1]&FResSelM[0], SetFflagsM);
|
mux2 #(5) FPUFlgMux({PreNVM&~FResSelM[1], 4'b0}, PostProcFlgM, ~FResSelM[1]&FResSelM[0], SetFflagsM);
|
||||||
mux2 #(P.FLEN) FPUResMux(PreFpResM, PostProcResM, FResSelM[0], FpResM);
|
mux2 #(P.FLEN) FPUResMux(PreFpResM, PostProcResM, FResSelM[0], FpResM);
|
||||||
|
|
||||||
// M/W pipe registers
|
// M/W pipe registers
|
||||||
|
|
|
||||||
|
|
@ -30,8 +30,8 @@ module fregfile #(parameter FLEN) (
|
||||||
input logic clk, reset,
|
input logic clk, reset,
|
||||||
input logic we4, // write enable
|
input logic we4, // write enable
|
||||||
input logic [4:0] a1, a2, a3, a4, // adresses
|
input logic [4:0] a1, a2, a3, a4, // adresses
|
||||||
input logic [FLEN-1:0] wd4, // write data
|
input logic [FLEN-1:0] wd4, // write data
|
||||||
output logic [FLEN-1:0] rd1, rd2, rd3 // read data
|
output logic [FLEN-1:0] rd1, rd2, rd3 // read data
|
||||||
);
|
);
|
||||||
|
|
||||||
logic [FLEN-1:0] rf[31:0];
|
logic [FLEN-1:0] rf[31:0];
|
||||||
|
|
@ -51,4 +51,3 @@ module fregfile #(parameter FLEN) (
|
||||||
assign #2 rd3 = rf[a3];
|
assign #2 rd3 = rf[a3];
|
||||||
|
|
||||||
endmodule // regfile
|
endmodule // regfile
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -27,10 +27,10 @@
|
||||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
module fsgninj import cvw::*; #(parameter cvw_t P) (
|
module fsgninj import cvw::*; #(parameter cvw_t P) (
|
||||||
input logic Xs, Ys, // X and Y sign bits
|
input logic Xs, Ys, // X and Y sign bits
|
||||||
input logic [P.FLEN-1:0] X, // X
|
input logic [P.FLEN-1:0] X, // X
|
||||||
input logic [P.FMTBITS-1:0] Fmt, // format
|
input logic [P.FMTBITS-1:0] Fmt, // format
|
||||||
input logic [1:0] OpCtrl, // operation control
|
input logic [1:0] OpCtrl, // operation control
|
||||||
output logic [P.FLEN-1:0] SgnRes // result
|
output logic [P.FLEN-1:0] SgnRes // result
|
||||||
);
|
);
|
||||||
|
|
||||||
|
|
@ -73,5 +73,4 @@ module fsgninj import cvw::*; #(parameter cvw_t P) (
|
||||||
endcase
|
endcase
|
||||||
assign SgnRes = {SgnBits[3], X[P.Q_LEN-2:P.D_LEN], SgnBits[2], X[P.D_LEN-2:P.S_LEN], SgnBits[1], X[P.S_LEN-2:P.H_LEN], SgnBits[0], X[P.H_LEN-2:0]};
|
assign SgnRes = {SgnBits[3], X[P.Q_LEN-2:P.D_LEN], SgnBits[2], X[P.D_LEN-2:P.S_LEN], SgnBits[1], X[P.S_LEN-2:P.H_LEN], SgnBits[0], X[P.H_LEN-2:0]};
|
||||||
end
|
end
|
||||||
|
|
||||||
endmodule
|
endmodule
|
||||||
|
|
|
||||||
|
|
@ -28,24 +28,24 @@
|
||||||
|
|
||||||
module unpackinput import cvw::*; #(parameter cvw_t P) (
|
module unpackinput import cvw::*; #(parameter cvw_t P) (
|
||||||
input logic [P.FLEN-1:0] In, // inputs from register file
|
input logic [P.FLEN-1:0] In, // inputs from register file
|
||||||
input logic En, // enable the input
|
input logic En, // enable the input
|
||||||
input logic [P.FMTBITS-1:0] Fmt, // format signal 00 - single 01 - double 11 - quad 10 - half
|
input logic [P.FMTBITS-1:0] Fmt, // format signal 00 - single 01 - double 11 - quad 10 - half
|
||||||
output logic Sgn, // sign bits of the number
|
output logic Sgn, // sign bits of the number
|
||||||
output logic [P.NE-1:0] Exp, // exponent of the number (converted to largest supported precision)
|
output logic [P.NE-1:0] Exp, // exponent of the number (converted to largest supported precision)
|
||||||
output logic [P.NF:0] Man, // mantissa of the number (converted to largest supported precision)
|
output logic [P.NF:0] Man, // mantissa of the number (converted to largest supported precision)
|
||||||
output logic NaN, // is the number a NaN
|
output logic NaN, // is the number a NaN
|
||||||
output logic SNaN, // is the number a signaling NaN
|
output logic SNaN, // is the number a signaling NaN
|
||||||
output logic Zero, // is the number zero
|
output logic Zero, // is the number zero
|
||||||
output logic Inf, // is the number infinity
|
output logic Inf, // is the number infinity
|
||||||
output logic ExpNonZero, // is the exponent not zero
|
output logic ExpNonZero, // is the exponent not zero
|
||||||
output logic FracZero, // is the fraction zero
|
output logic FracZero, // is the fraction zero
|
||||||
output logic ExpMax, // does In have the maximum exponent (NaN or Inf)
|
output logic ExpMax, // does In have the maximum exponent (NaN or Inf)
|
||||||
output logic Subnorm, // is the number subnormal
|
output logic Subnorm, // is the number subnormal
|
||||||
output logic [P.FLEN-1:0] PostBox // Number reboxed correctly as a NaN
|
output logic [P.FLEN-1:0] PostBox // Number reboxed correctly as a NaN
|
||||||
);
|
);
|
||||||
|
|
||||||
logic [P.NF-1:0] Frac; // Fraction of XYZ
|
logic [P.NF-1:0] Frac; // Fraction of XYZ
|
||||||
logic BadNaNBox; // incorrectly NaN Boxed
|
logic BadNaNBox; // incorrectly NaN Boxed
|
||||||
|
|
||||||
if (P.FPSIZES == 1) begin // if there is only one floating point format supported
|
if (P.FPSIZES == 1) begin // if there is only one floating point format supported
|
||||||
assign BadNaNBox = 0;
|
assign BadNaNBox = 0;
|
||||||
|
|
@ -107,7 +107,6 @@ module unpackinput import cvw::*; #(parameter cvw_t P) (
|
||||||
// is the exponent all 1's
|
// is the exponent all 1's
|
||||||
assign ExpMax = Fmt ? &In[P.FLEN-2:P.NF] : &In[P.LEN1-2:P.NF1];
|
assign ExpMax = Fmt ? &In[P.FLEN-2:P.NF] : &In[P.LEN1-2:P.NF1];
|
||||||
|
|
||||||
|
|
||||||
end else if (P.FPSIZES == 3) begin // three floating point precsions supported
|
end else if (P.FPSIZES == 3) begin // three floating point precsions supported
|
||||||
|
|
||||||
// largest format | larger format | smallest format
|
// largest format | larger format | smallest format
|
||||||
|
|
@ -246,7 +245,6 @@ module unpackinput import cvw::*; #(parameter cvw_t P) (
|
||||||
2'b00: Sgn = In[P.S_LEN-1];
|
2'b00: Sgn = In[P.S_LEN-1];
|
||||||
2'b10: Sgn = In[P.H_LEN-1];
|
2'b10: Sgn = In[P.H_LEN-1];
|
||||||
endcase
|
endcase
|
||||||
|
|
||||||
|
|
||||||
// extract the fraction
|
// extract the fraction
|
||||||
always_comb
|
always_comb
|
||||||
|
|
@ -266,7 +264,6 @@ module unpackinput import cvw::*; #(parameter cvw_t P) (
|
||||||
2'b10: ExpNonZero = |In[P.H_LEN-2:P.H_NF];
|
2'b10: ExpNonZero = |In[P.H_LEN-2:P.H_NF];
|
||||||
endcase
|
endcase
|
||||||
|
|
||||||
|
|
||||||
// example double to single conversion:
|
// example double to single conversion:
|
||||||
// 1023 = 0011 1111 1111
|
// 1023 = 0011 1111 1111
|
||||||
// 127 = 0000 0111 1111 (subtract this)
|
// 127 = 0000 0111 1111 (subtract this)
|
||||||
|
|
@ -284,8 +281,7 @@ module unpackinput import cvw::*; #(parameter cvw_t P) (
|
||||||
2'b00: Exp = {In[P.S_LEN-2], {P.Q_NE-P.S_NE{~In[P.S_LEN-2]}}, In[P.S_LEN-3:P.S_NF+1], In[P.S_NF]|~ExpNonZero};
|
2'b00: Exp = {In[P.S_LEN-2], {P.Q_NE-P.S_NE{~In[P.S_LEN-2]}}, In[P.S_LEN-3:P.S_NF+1], In[P.S_NF]|~ExpNonZero};
|
||||||
2'b10: Exp = {In[P.H_LEN-2], {P.Q_NE-P.H_NE{~In[P.H_LEN-2]}}, In[P.H_LEN-3:P.H_NF+1], In[P.H_NF]|~ExpNonZero};
|
2'b10: Exp = {In[P.H_LEN-2], {P.Q_NE-P.H_NE{~In[P.H_LEN-2]}}, In[P.H_LEN-3:P.H_NF+1], In[P.H_NF]|~ExpNonZero};
|
||||||
endcase
|
endcase
|
||||||
|
|
||||||
|
|
||||||
// is the exponent all 1's
|
// is the exponent all 1's
|
||||||
always_comb
|
always_comb
|
||||||
case (Fmt)
|
case (Fmt)
|
||||||
|
|
|
||||||
|
|
@ -33,5 +33,3 @@ module adder #(parameter WIDTH=8) (
|
||||||
|
|
||||||
assign y = a + b;
|
assign y = a + b;
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -36,5 +36,3 @@ module counter #(parameter WIDTH=8) (
|
||||||
assign qnext = q + 1;
|
assign qnext = q + 1;
|
||||||
flopenr #(WIDTH) cntrflop(clk, reset, en, qnext, q);
|
flopenr #(WIDTH) cntrflop(clk, reset, en, qnext, q);
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -32,4 +32,3 @@ module neg #(parameter WIDTH = 8) (
|
||||||
|
|
||||||
assign y = ~a + 1;
|
assign y = ~a + 1;
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -48,5 +48,3 @@ module or_rows #(parameter ROWS = 8, COLS=2) (
|
||||||
/* verilator lint_on UNOPTFLAT */
|
/* verilator lint_on UNOPTFLAT */
|
||||||
end
|
end
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -48,6 +48,3 @@ module prioritythermometer #(parameter N = 8) (
|
||||||
end
|
end
|
||||||
/* verilator lint_on UNOPTFLAT */
|
/* verilator lint_on UNOPTFLAT */
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
|
||||||
Loading…
Add table
Add a link
Reference in a new issue