mirror of
https://github.com/openhwgroup/cvw.git
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Merge branch 'rvvi'
This commit is contained in:
Rose Thompson
commit
7223b15134
37 changed files with 1809 additions and 20 deletions
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@ -44,6 +44,21 @@ module fpgaTop
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inout SDCCmd,
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input SDCCD,
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/*
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* Ethernet: 100BASE-T MII
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*/
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output phy_ref_clk,
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input phy_rx_clk,
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input [3:0] phy_rxd,
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input phy_rx_dv,
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input phy_rx_er,
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input phy_tx_clk,
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output [3:0] phy_txd,
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output phy_tx_en,
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input phy_col, // nc
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input phy_crs, // nc
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output phy_reset_n,
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inout [15:0] ddr3_dq,
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inout [1:0] ddr3_dqs_n,
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inout [1:0] ddr3_dqs_p,
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@ -428,7 +443,8 @@ module fpgaTop
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wire mmcm_locked;
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wire [11:0] device_temp;
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wire mmcm1_locked;
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(* mark_debug = "true" *) logic RVVIStall;
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assign GPIOIN = {28'b0, GPI};
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assign GPO = GPIOOUT[4:0];
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@ -446,6 +462,7 @@ module fpgaTop
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xlnx_mmcm xln_mmcm(.clk_out1(clk167),
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.clk_out2(clk200),
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.clk_out3(CPUCLK),
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.clk_out4(phy_ref_clk),
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.reset(1'b0),
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.locked(mmcm1_locked),
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.clk_in1(default_100mhz_clk));
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@ -496,7 +513,7 @@ module fpgaTop
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.HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
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.HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0),
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.GPIOIN, .GPIOOUT, .GPIOEN,
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.UARTSin, .UARTSout, .SDCIntr);
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.UARTSin, .UARTSout, .SDCIntr, .ExternalStall(RVVIStall));
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// ahb lite to axi bridge
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@ -1096,7 +1113,144 @@ module fpgaTop
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.init_calib_complete(c0_init_calib_complete),
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.device_temp(device_temp));
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(* mark_debug = "true" *) logic IlaTrigger;
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if(P.RVVI_SYNTH_SUPPORTED) begin : rvvi_synth
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localparam MAX_CSRS = 3;
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localparam TOTAL_CSRS = 36;
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// pipeline controlls
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logic StallE, StallM, StallW, FlushE, FlushM, FlushW;
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// required
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logic [P.XLEN-1:0] PCM;
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logic InstrValidM;
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logic [31:0] InstrRawD;
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logic [63:0] Mcycle, Minstret;
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logic TrapM;
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logic [1:0] PrivilegeModeW;
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// registers gpr and fpr
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logic GPRWen, FPRWen;
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logic [4:0] GPRAddr, FPRAddr;
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logic [P.XLEN-1:0] GPRValue, FPRValue;
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logic [P.XLEN-1:0] CSRArray [TOTAL_CSRS-1:0];
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logic valid;
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logic [187+(3*P.XLEN) + MAX_CSRS*(P.XLEN+12)-1:0] rvvi;
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assign StallE = fpgaTop.wallypipelinedsoc.core.StallE;
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assign StallM = fpgaTop.wallypipelinedsoc.core.StallM;
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assign StallW = fpgaTop.wallypipelinedsoc.core.StallW;
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assign FlushE = fpgaTop.wallypipelinedsoc.core.FlushE;
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assign FlushM = fpgaTop.wallypipelinedsoc.core.FlushM;
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assign FlushW = fpgaTop.wallypipelinedsoc.core.FlushW;
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assign InstrValidM = fpgaTop.wallypipelinedsoc.core.ieu.InstrValidM;
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assign InstrRawD = fpgaTop.wallypipelinedsoc.core.ifu.InstrRawD;
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assign PCM = fpgaTop.wallypipelinedsoc.core.ifu.PCM;
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assign Mcycle = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[0];
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assign Minstret = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2];
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assign TrapM = fpgaTop.wallypipelinedsoc.core.TrapM;
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assign PrivilegeModeW = fpgaTop.wallypipelinedsoc.core.priv.priv.privmode.PrivilegeModeW;
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assign GPRAddr = fpgaTop.wallypipelinedsoc.core.ieu.dp.regf.a3;
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assign GPRWen = fpgaTop.wallypipelinedsoc.core.ieu.dp.regf.we3;
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assign GPRValue = fpgaTop.wallypipelinedsoc.core.ieu.dp.regf.wd3;
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assign FPRAddr = fpgaTop.wallypipelinedsoc.core.fpu.fpu.fregfile.a4;
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assign FPRWen = fpgaTop.wallypipelinedsoc.core.fpu.fpu.fregfile.we4;
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assign FPRValue = fpgaTop.wallypipelinedsoc.core.fpu.fpu.fregfile.wd4;
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assign CSRArray[0] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MSTATUS_REGW; // 12'h300
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assign CSRArray[1] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MSTATUSH_REGW; // 12'h310
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assign CSRArray[2] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MTVEC_REGW; // 12'h305
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assign CSRArray[3] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MEPC_REGW; // 12'h341
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assign CSRArray[4] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MCOUNTEREN_REGW; // 12'h306
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assign CSRArray[5] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MCOUNTINHIBIT_REGW; // 12'h320
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assign CSRArray[6] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MEDELEG_REGW; // 12'h302
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assign CSRArray[7] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MIDELEG_REGW; // 12'h303
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assign CSRArray[8] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MIP_REGW; // 12'h344
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assign CSRArray[9] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MIE_REGW; // 12'h304
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assign CSRArray[10] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MISA_REGW; // 12'h301
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assign CSRArray[11] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MENVCFG_REGW; // 12'h30A
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assign CSRArray[12] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MHARTID_REGW; // 12'hF14
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assign CSRArray[13] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MSCRATCH_REGW; // 12'h340
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assign CSRArray[14] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MCAUSE_REGW; // 12'h342
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assign CSRArray[15] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MTVAL_REGW; // 12'h343
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assign CSRArray[16] = 0; // 12'hF11
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assign CSRArray[17] = 0; // 12'hF12
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assign CSRArray[18] = {{P.XLEN-12{1'b0}}, 12'h100}; //P.XLEN'h100; // 12'hF13
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assign CSRArray[19] = 0; // 12'hF15
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assign CSRArray[20] = 0; // 12'h34A
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// supervisor CSRs
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assign CSRArray[21] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.SSTATUS_REGW; // 12'h100
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assign CSRArray[22] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MIE_REGW & 12'h222; // 12'h104
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assign CSRArray[23] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.STVEC_REGW; // 12'h105
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assign CSRArray[24] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.SEPC_REGW; // 12'h141
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assign CSRArray[25] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.SCOUNTEREN_REGW; // 12'h106
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assign CSRArray[26] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.SENVCFG_REGW; // 12'h10A
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assign CSRArray[27] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.SATP_REGW; // 12'h180
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assign CSRArray[28] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.SSCRATCH_REGW; // 12'h140
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assign CSRArray[29] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.STVAL_REGW; // 12'h143
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assign CSRArray[30] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.SCAUSE_REGW; // 12'h142
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assign CSRArray[31] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MIP_REGW & 12'h222 & fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MIDELEG_REGW; // 12'h144
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assign CSRArray[32] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW; // 12'h14D
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// user CSRs
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assign CSRArray[33] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csru.csru.FFLAGS_REGW; // 12'h001
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assign CSRArray[34] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csru.csru.FRM_REGW; // 12'h002
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assign CSRArray[35] = {fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csru.csru.FRM_REGW, fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csru.csru.FFLAGS_REGW}; // 12'h003
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rvvisynth #(P, MAX_CSRS) rvvisynth(.clk(CPUCLK), .reset(bus_struct_reset), .StallE, .StallM, .StallW, .FlushE, .FlushM, .FlushW,
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.PCM, .InstrValidM, .InstrRawD, .Mcycle, .Minstret, .TrapM,
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.PrivilegeModeW, .GPRWen, .FPRWen, .GPRAddr, .FPRAddr, .GPRValue, .FPRValue, .CSRArray,
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.valid, .rvvi);
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// axi 4 write data channel
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logic [31:0] RvviAxiWdata;
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logic [3:0] RvviAxiWstrb;
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logic RvviAxiWlast;
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logic RvviAxiWvalid;
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logic RvviAxiWready;
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logic [31:0] RvviAxiRdata;
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logic [3:0] RvviAxiRstrb;
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logic RvviAxiRlast;
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logic RvviAxiRvalid;
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logic tx_error_underflow, tx_fifo_overflow, tx_fifo_bad_frame, tx_fifo_good_frame, rx_error_bad_frame;
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logic rx_error_bad_fcs, rx_fifo_overflow, rx_fifo_bad_frame, rx_fifo_good_frame;
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packetizer #(P, MAX_CSRS) packetizer(.rvvi, .valid, .m_axi_aclk(CPUCLK), .m_axi_aresetn(~bus_struct_reset), .RVVIStall,
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.RvviAxiWdata, .RvviAxiWstrb, .RvviAxiWlast, .RvviAxiWvalid, .RvviAxiWready);
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eth_mac_mii_fifo #(.TARGET("XILINX"), .CLOCK_INPUT_STYLE("BUFG"), .AXIS_DATA_WIDTH(32), .TX_FIFO_DEPTH(1024)) ethernet(.rst(bus_struct_reset), .logic_clk(CPUCLK), .logic_rst(bus_struct_reset),
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.tx_axis_tdata(RvviAxiWdata), .tx_axis_tkeep(RvviAxiWstrb), .tx_axis_tvalid(RvviAxiWvalid), .tx_axis_tready(RvviAxiWready),
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.tx_axis_tlast(RvviAxiWlast), .tx_axis_tuser('0), .rx_axis_tdata(RvviAxiRdata),
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.rx_axis_tkeep(RvviAxiRstrb), .rx_axis_tvalid(RvviAxiRvalid), .rx_axis_tready(1'b1),
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.rx_axis_tlast(RvviAxiRlast), .rx_axis_tuser(),
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.mii_rx_clk(phy_rx_clk),
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.mii_rxd(phy_rxd),
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.mii_rx_dv(phy_rx_dv),
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.mii_rx_er(phy_rx_er),
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.mii_tx_clk(phy_tx_clk),
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.mii_txd(phy_txd),
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.mii_tx_en(phy_tx_en),
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.mii_tx_er(),
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// status
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.tx_error_underflow, .tx_fifo_overflow, .tx_fifo_bad_frame, .tx_fifo_good_frame, .rx_error_bad_frame,
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.rx_error_bad_fcs, .rx_fifo_overflow, .rx_fifo_bad_frame, .rx_fifo_good_frame,
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.cfg_ifg(8'd12), .cfg_tx_enable(1'b1), .cfg_rx_enable(1'b1)
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);
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triggergen triggergen(.clk(CPUCLK), .reset(bus_struct_reset), .RvviAxiRdata,
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.RvviAxiRstrb, .RvviAxiRlast, .RvviAxiRvalid, .IlaTrigger);
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end else begin // if (P.RVVI_SYNTH_SUPPORTED)
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assign IlaTrigger = '0;
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assign RVVIStall = '0;
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end
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//assign phy_reset_n = ~bus_struct_reset;
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assign phy_reset_n = ~1'b0;
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endmodule
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