github-mirrors/cvw
1
0
Fork 0
mirror of https://github.com/openhwgroup/cvw.git synced 2025-04-23 13:27:16 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions 2

Minor tweaks

Browse source
This commit is contained in:
David Harris 2021-02-02 19:44:37 -05:00
parent 429f48e766
commit 756352f129
2 changed files with 4 additions and 4 deletions
Download patch file Download diff file Expand all files Collapse all files

2
wally-pipelined/src/ieu/datapath.sv
View file

@ -77,10 +77,10 @@ module datapath (
logic [`XLEN-1:0] ALUResultW;
logic [`XLEN-1:0] ResultW;
// Decode stage
assign Rs1D = InstrD[19:15];
assign Rs2D = InstrD[24:20];
assign RdD = InstrD[11:7];
regfile regf(clk, reset, RegWriteW, Rs1D, Rs2D, RdW, ResultW, RD1D, RD2D);
extend ext(.InstrD(InstrD[31:7]), .*);

6
wally-pipelined/src/privileged/csrm.sv
View file

@ -101,9 +101,9 @@ module csrm #(parameter
assign WriteMEPCM = MTrapM | (CSRMWriteM && (CSRAdrM == MEPC));
assign WriteMCAUSEM = MTrapM | (CSRMWriteM && (CSRAdrM == MCAUSE));
assign WriteMTVALM = MTrapM | (CSRMWriteM && (CSRAdrM == MTVAL));
assign WritePMPCFG0M = MTrapM | (CSRMWriteM && (CSRAdrM == PMPCFG0));
assign WritePMPCFG2M = MTrapM | (CSRMWriteM && (CSRAdrM == PMPCFG2));
assign WritePMPADDR0M = MTrapM | (CSRMWriteM && (CSRAdrM == PMPADDR0));
assign WritePMPCFG0M = (CSRMWriteM && (CSRAdrM == PMPCFG0));
assign WritePMPCFG2M = (CSRMWriteM && (CSRAdrM == PMPCFG2));
assign WritePMPADDR0M = (CSRMWriteM && (CSRAdrM == PMPADDR0));
assign WriteMCOUNTERENM = CSRMWriteM && (CSRAdrM == MCOUNTEREN);
assign WriteMCOUNTINHIBITM = CSRMWriteM && (CSRAdrM == MCOUNTINHIBIT);