mirror of
https://github.com/openhwgroup/cvw.git
synced 2025-04-23 13:27:16 -04:00
Updates to fpga top level.
This commit is contained in:
Rose Thompson
parent
26cd22c388
commit
7693c5d4e2
1 changed files with 125 additions and 125 deletions
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@ -62,12 +62,12 @@ module fpgaTop
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);
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wire CPUCLK;
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(* mark_debug = "true" *) wire c0_ddr4_ui_clk_sync_rst;
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(* mark_debug = "true" *) wire bus_struct_reset;
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(* mark_debug = "true" *) wire peripheral_reset;
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(* mark_debug = "true" *) wire interconnect_aresetn;
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(* mark_debug = "true" *) wire peripheral_aresetn;
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(* mark_debug = "true" *) wire mb_reset;
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wire c0_ddr4_ui_clk_sync_rst;
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wire bus_struct_reset;
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wire peripheral_reset;
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wire interconnect_aresetn;
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wire peripheral_aresetn;
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wire mb_reset;
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wire HCLKOpen;
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wire HRESETnOpen;
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@ -175,48 +175,48 @@ module fpgaTop
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// Crossbar to Bus ------------------------------------------------
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(* mark_debug = "true" *)wire s00_axi_aclk;
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(* mark_debug = "true" *)wire s00_axi_aresetn;
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(* mark_debug = "true" *)wire [3:0] s00_axi_awid;
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(* mark_debug = "true" *)wire [31:0]s00_axi_awaddr;
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(* mark_debug = "true" *)wire [7:0]s00_axi_awlen;
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(* mark_debug = "true" *)wire [2:0]s00_axi_awsize;
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(* mark_debug = "true" *)wire [1:0]s00_axi_awburst;
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(* mark_debug = "true" *)wire [0:0]s00_axi_awlock;
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(* mark_debug = "true" *)wire [3:0]s00_axi_awcache;
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(* mark_debug = "true" *)wire [2:0]s00_axi_awprot;
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(* mark_debug = "true" *)wire [3:0]s00_axi_awregion;
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(* mark_debug = "true" *)wire [3:0]s00_axi_awqos;
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(* mark_debug = "true" *) wire s00_axi_awvalid;
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(* mark_debug = "true" *) wire s00_axi_awready;
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(* mark_debug = "true" *)wire [63:0]s00_axi_wdata;
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(* mark_debug = "true" *)wire [7:0]s00_axi_wstrb;
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(* mark_debug = "true" *)wire s00_axi_wlast;
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(* mark_debug = "true" *)wire s00_axi_wvalid;
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(* mark_debug = "true" *)wire s00_axi_wready;
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(* mark_debug = "true" *)wire [1:0]s00_axi_bresp;
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(* mark_debug = "true" *)wire s00_axi_bvalid;
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(* mark_debug = "true" *)wire s00_axi_bready;
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wire s00_axi_aclk;
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wire s00_axi_aresetn;
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wire [3:0] s00_axi_awid;
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wire [31:0]s00_axi_awaddr;
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wire [7:0]s00_axi_awlen;
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wire [2:0]s00_axi_awsize;
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wire [1:0]s00_axi_awburst;
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wire [0:0]s00_axi_awlock;
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wire [3:0]s00_axi_awcache;
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wire [2:0]s00_axi_awprot;
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wire [3:0]s00_axi_awregion;
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wire [3:0]s00_axi_awqos;
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wire s00_axi_awvalid;
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wire s00_axi_awready;
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wire [63:0]s00_axi_wdata;
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wire [7:0]s00_axi_wstrb;
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wire s00_axi_wlast;
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wire s00_axi_wvalid;
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wire s00_axi_wready;
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wire [1:0]s00_axi_bresp;
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wire s00_axi_bvalid;
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wire s00_axi_bready;
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wire [3:0] s00_axi_arid;
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(* mark_debug = "true" *)wire [31:0]s00_axi_araddr;
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(* mark_debug = "true" *)wire [7:0]s00_axi_arlen;
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(* mark_debug = "true" *)wire [2:0]s00_axi_arsize;
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(* mark_debug = "true" *)wire [1:0]s00_axi_arburst;
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(* mark_debug = "true" *)wire [0:0]s00_axi_arlock;
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(* mark_debug = "true" *)wire [3:0]s00_axi_arcache;
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(* mark_debug = "true" *)wire [2:0]s00_axi_arprot;
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(* mark_debug = "true" *)wire [3:0]s00_axi_arregion;
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(* mark_debug = "true" *)wire [3:0]s00_axi_arqos;
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(* mark_debug = "true" *)wire s00_axi_arvalid;
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(* mark_debug = "true" *)wire s00_axi_arready;
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(* mark_debug = "true" *)wire [63:0]s00_axi_rdata;
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(* mark_debug = "true" *)wire [1:0]s00_axi_rresp;
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(* mark_debug = "true" *)wire s00_axi_rlast;
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(* mark_debug = "true" *)wire s00_axi_rvalid;
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(* mark_debug = "true" *)wire s00_axi_rready;
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wire [31:0]s00_axi_araddr;
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wire [7:0]s00_axi_arlen;
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wire [2:0]s00_axi_arsize;
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wire [1:0]s00_axi_arburst;
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wire [0:0]s00_axi_arlock;
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wire [3:0]s00_axi_arcache;
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wire [2:0]s00_axi_arprot;
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wire [3:0]s00_axi_arregion;
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wire [3:0]s00_axi_arqos;
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wire s00_axi_arvalid;
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wire s00_axi_arready;
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wire [63:0]s00_axi_rdata;
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wire [1:0]s00_axi_rresp;
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wire s00_axi_rlast;
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wire s00_axi_rvalid;
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wire s00_axi_rready;
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(* mark_debug = "true" *)wire [3:0] s00_axi_bid;
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(* mark_debug = "true" *)wire [3:0] s00_axi_rid;
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wire [3:0] s00_axi_bid;
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wire [3:0] s00_axi_rid;
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// 64to32 dwidth converter input interface-------------------------
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wire s01_axi_aclk;
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@ -231,8 +231,8 @@ module fpgaTop
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wire [2:0]s01_axi_awprot;
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wire [3:0]s01_axi_awregion;
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wire [3:0]s01_axi_awqos; // qos signals need to be 0 for SDC
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(* mark_debug = "true" *) wire s01_axi_awvalid;
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(* mark_debug = "true" *) wire s01_axi_awready;
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wire s01_axi_awvalid;
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wire s01_axi_awready;
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wire [63:0]s01_axi_wdata;
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wire [7:0]s01_axi_wstrb;
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wire s01_axi_wlast;
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@ -269,8 +269,8 @@ module fpgaTop
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wire [2:0]axi4in_axi_awprot;
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wire [3:0]axi4in_axi_awregion;
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wire [3:0]axi4in_axi_awqos;
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(* mark_debug = "true" *) wire axi4in_axi_awvalid;
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(* mark_debug = "true" *) wire axi4in_axi_awready;
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wire axi4in_axi_awvalid;
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wire axi4in_axi_awready;
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wire [31:0]axi4in_axi_wdata;
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wire [3:0]axi4in_axi_wstrb;
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wire axi4in_axi_wlast;
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@ -297,30 +297,30 @@ module fpgaTop
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wire axi4in_axi_rready;
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// AXI4 to AXI4-Lite Protocol converter output
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(* mark_debug = "true" *) wire [31:0]SDCin_axi_awaddr;
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(* mark_debug = "true" *) wire [2:0]SDCin_axi_awprot;
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(* mark_debug = "true" *) wire SDCin_axi_awvalid;
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(* mark_debug = "true" *) wire SDCin_axi_awready;
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(* mark_debug = "true" *) wire [31:0]SDCin_axi_wdata;
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(* mark_debug = "true" *) wire [3:0]SDCin_axi_wstrb;
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(* mark_debug = "true" *) wire SDCin_axi_wvalid;
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(* mark_debug = "true" *) wire SDCin_axi_wready;
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(* mark_debug = "true" *) wire [1:0]SDCin_axi_bresp;
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(* mark_debug = "true" *) wire SDCin_axi_bvalid;
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(* mark_debug = "true" *) wire SDCin_axi_bready;
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(* mark_debug = "true" *) wire [31:0]SDCin_axi_araddr;
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(* mark_debug = "true" *) wire [2:0]SDCin_axi_arprot;
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(* mark_debug = "true" *) wire SDCin_axi_arvalid;
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(* mark_debug = "true" *) wire SDCin_axi_arready;
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(* mark_debug = "true" *) wire [31:0]SDCin_axi_rdata;
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(* mark_debug = "true" *) wire [1:0]SDCin_axi_rresp;
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(* mark_debug = "true" *) wire SDCin_axi_rvalid;
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(* mark_debug = "true" *) wire SDCin_axi_rready;
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wire [31:0]SDCin_axi_awaddr;
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wire [2:0]SDCin_axi_awprot;
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wire SDCin_axi_awvalid;
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wire SDCin_axi_awready;
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wire [31:0]SDCin_axi_wdata;
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wire [3:0]SDCin_axi_wstrb;
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wire SDCin_axi_wvalid;
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wire SDCin_axi_wready;
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wire [1:0]SDCin_axi_bresp;
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wire SDCin_axi_bvalid;
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wire SDCin_axi_bready;
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wire [31:0]SDCin_axi_araddr;
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wire [2:0]SDCin_axi_arprot;
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wire SDCin_axi_arvalid;
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wire SDCin_axi_arready;
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wire [31:0]SDCin_axi_rdata;
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wire [1:0]SDCin_axi_rresp;
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wire SDCin_axi_rvalid;
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wire SDCin_axi_rready;
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// ----------------------------------------------------------------
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// 32to64 dwidth converter input interface -----------------------
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(* mark_debug = "true" *) wire [31:0]SDCout_axi_awaddr;
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(* mark_debug = "true" *) wire [7:0]SDCout_axi_awlen;
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wire [31:0]SDCout_axi_awaddr;
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wire [7:0]SDCout_axi_awlen;
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wire [2:0]SDCout_axi_awsize;
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wire [1:0]SDCout_axi_awburst;
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wire [0:0]SDCout_axi_awlock;
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@ -328,16 +328,16 @@ module fpgaTop
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wire [2:0]SDCout_axi_awprot;
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wire [3:0]SDCout_axi_awregion;
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wire [3:0]SDCout_axi_awqos;
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(* mark_debug = "true" *) wire SDCout_axi_awvalid;
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(* mark_debug = "true" *) wire SDCout_axi_awready;
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(* mark_debug = "true" *) wire [31:0]SDCout_axi_wdata;
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wire SDCout_axi_awvalid;
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wire SDCout_axi_awready;
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wire [31:0]SDCout_axi_wdata;
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wire [3:0]SDCout_axi_wstrb;
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(* mark_debug = "true" *) wire SDCout_axi_wlast;
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(* mark_debug = "true" *) wire SDCout_axi_wvalid;
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(* mark_debug = "true" *)wire SDCout_axi_wready;
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(* mark_debug = "true" *) wire [1:0]SDCout_axi_bresp;
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(* mark_debug = "true" *) wire SDCout_axi_bvalid;
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(* mark_debug = "true" *) wire SDCout_axi_bready;
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wire SDCout_axi_wlast;
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wire SDCout_axi_wvalid;
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wire SDCout_axi_wready;
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wire [1:0]SDCout_axi_bresp;
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wire SDCout_axi_bvalid;
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wire SDCout_axi_bready;
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wire [31:0]SDCout_axi_araddr;
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wire [7:0]SDCout_axi_arlen;
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wire [2:0]SDCout_axi_arsize;
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@ -356,45 +356,45 @@ module fpgaTop
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wire SDCout_axi_rready;
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// Output Interface
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(* mark_debug = "true" *) wire [3:0]m01_axi_awid;
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(* mark_debug = "true" *) wire [31:0]m01_axi_awaddr;
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(* mark_debug = "true" *) wire [7:0]m01_axi_awlen;
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(* mark_debug = "true" *) wire [2:0]m01_axi_awsize;
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(* mark_debug = "true" *) wire [1:0]m01_axi_awburst;
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(* mark_debug = "true" *) wire [0:0]m01_axi_awlock;
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(* mark_debug = "true" *) wire [3:0]m01_axi_awcache;
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(* mark_debug = "true" *) wire [2:0]m01_axi_awprot;
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(* mark_debug = "true" *) wire [3:0]m01_axi_awregion;
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(* mark_debug = "true" *) wire [3:0]m01_axi_awqos;
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(* mark_debug = "true" *) wire m01_axi_awvalid;
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(* mark_debug = "true" *) wire m01_axi_awready;
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(* mark_debug = "true" *) wire [63:0]m01_axi_wdata;
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(* mark_debug = "true" *) wire [7:0]m01_axi_wstrb;
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(* mark_debug = "true" *) wire m01_axi_wlast;
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(* mark_debug = "true" *) wire m01_axi_wvalid;
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(* mark_debug = "true" *) wire m01_axi_wready;
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(* mark_debug = "true" *) wire [3:0] m01_axi_bid;
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(* mark_debug = "true" *) wire [1:0]m01_axi_bresp;
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(* mark_debug = "true" *) wire m01_axi_bvalid;
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(* mark_debug = "true" *) wire m01_axi_bready;
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(* mark_debug = "true" *) wire [3:0] m01_axi_arid;
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(* mark_debug = "true" *) wire [31:0]m01_axi_araddr;
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(* mark_debug = "true" *) wire [7:0]m01_axi_arlen;
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(* mark_debug = "true" *) wire [2:0]m01_axi_arsize;
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(* mark_debug = "true" *) wire [1:0]m01_axi_arburst;
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(* mark_debug = "true" *) wire [0:0]m01_axi_arlock;
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(* mark_debug = "true" *) wire [3:0]m01_axi_arcache;
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(* mark_debug = "true" *) wire [2:0]m01_axi_arprot;
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(* mark_debug = "true" *) wire [3:0]m01_axi_arregion;
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(* mark_debug = "true" *) wire [3:0]m01_axi_arqos;
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(* mark_debug = "true" *) wire m01_axi_arvalid;
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(* mark_debug = "true" *) wire m01_axi_arready;
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(* mark_debug = "true" *) wire [3:0] m01_axi_rid;
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(* mark_debug = "true" *) wire [63:0]m01_axi_rdata;
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(* mark_debug = "true" *) wire [1:0]m01_axi_rresp;
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(* mark_debug = "true" *) wire m01_axi_rlast;
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(* mark_debug = "true" *) wire m01_axi_rvalid;
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(* mark_debug = "true" *) wire m01_axi_rready;
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wire [3:0]m01_axi_awid;
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wire [31:0]m01_axi_awaddr;
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wire [7:0]m01_axi_awlen;
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wire [2:0]m01_axi_awsize;
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wire [1:0]m01_axi_awburst;
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wire [0:0]m01_axi_awlock;
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wire [3:0]m01_axi_awcache;
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wire [2:0]m01_axi_awprot;
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wire [3:0]m01_axi_awregion;
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wire [3:0]m01_axi_awqos;
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wire m01_axi_awvalid;
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wire m01_axi_awready;
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wire [63:0]m01_axi_wdata;
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wire [7:0]m01_axi_wstrb;
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wire m01_axi_wlast;
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wire m01_axi_wvalid;
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wire m01_axi_wready;
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wire [3:0] m01_axi_bid;
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wire [1:0]m01_axi_bresp;
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wire m01_axi_bvalid;
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wire m01_axi_bready;
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wire [3:0] m01_axi_arid;
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wire [31:0]m01_axi_araddr;
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wire [7:0]m01_axi_arlen;
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wire [2:0]m01_axi_arsize;
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wire [1:0]m01_axi_arburst;
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wire [0:0]m01_axi_arlock;
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wire [3:0]m01_axi_arcache;
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wire [2:0]m01_axi_arprot;
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wire [3:0]m01_axi_arregion;
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wire [3:0]m01_axi_arqos;
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wire m01_axi_arvalid;
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wire m01_axi_arready;
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wire [3:0] m01_axi_rid;
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wire [63:0]m01_axi_rdata;
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wire [1:0]m01_axi_rresp;
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wire m01_axi_rlast;
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wire m01_axi_rvalid;
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wire m01_axi_rready;
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// Old SDC input
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// wire [3:0] SDCDatIn;
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@ -405,7 +405,7 @@ module fpgaTop
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wire sd_cmd_reg_t;
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// SD Card Interrupt signal
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(* mark_debug = "true" *) wire SDCIntr;
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wire SDCIntr;
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// New SDC Data IOBUF connections
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wire [3:0] sd_dat_i;
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@ -413,10 +413,10 @@ module fpgaTop
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wire sd_dat_reg_t;
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(* mark_debug = "true" *) wire c0_init_calib_complete;
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wire c0_init_calib_complete;
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wire dbg_clk;
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wire [511 : 0] dbg_bus;
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(* mark_debug = "true" *) wire ui_clk_sync_rst;
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wire ui_clk_sync_rst;
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wire CLK208;
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wire clk167;
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@ -425,9 +425,9 @@ module fpgaTop
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wire app_sr_active;
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wire app_ref_ack;
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wire app_zq_ack;
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(* mark_debug = "true" *) wire mmcm_locked;
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wire mmcm_locked;
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wire [11:0] device_temp;
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(* mark_debug = "true" *) wire mmcm1_locked;
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wire mmcm1_locked;
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assign GPIOIN = {28'b0, GPI};
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@ -474,7 +474,7 @@ module fpgaTop
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// reset controller XILINX IP
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xlnx_proc_sys_reset xlnx_proc_sys_reset_0
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(.slowest_sync_clk(CPUCLK),
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.ext_reset_in(c0_ddr4_ui_clk_sync_rst),
|
||||
.ext_reset_in(1'b0),
|
||||
.aux_reset_in(south_reset),
|
||||
.mb_debug_sys_rst(1'b0),
|
||||
.dcm_locked(c0_init_calib_complete),
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue