mirror of
https://github.com/openhwgroup/cvw.git
synced 2025-04-20 03:47:20 -04:00
csh script corrections
This commit is contained in:
parent
d876b76911
commit
79870cc910
1 changed files with 3 additions and 3 deletions
|
@ -25,11 +25,11 @@ extend LD_LIBRARY_PATH $RISCV/lib64
|
|||
extend PATH $RISCV/bin
|
||||
|
||||
# Activate riscv-python Virtual Environment
|
||||
source "$RISCV"/riscv-python/bin/activate
|
||||
source "$RISCV"/riscv-python/bin/activate.csh
|
||||
|
||||
# environment variables needed for RISCV-DV
|
||||
setenv RISCV_GCC $(which riscv64-unknown-elf-gcc) # Copy this as it is
|
||||
setenv RISCV_OBJCOPY $(which riscv64-unknown-elf-objcopy) # Copy this as it is
|
||||
setenv RISCV_GCC `which riscv64-unknown-elf-gcc` # Copy this as it is
|
||||
setenv RISCV_OBJCOPY `which riscv64-unknown-elf-objcopy` # Copy this as it is
|
||||
setenv SPIKE_PATH $RISCV/bin # Change this for your path to riscv-isa-sim (spike)
|
||||
|
||||
# Verilator needs a larger stack to simulate CORE-V Wally
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue