Renamed BTB misprediction to BTA.

src/ifu/bpred/bpred.sv

@@ -64,7 +64,7 @@ module bpred (
   output logic             BPWrongE,              // Prediction is wrong
   output logic             BPWrongM,              // Prediction is wrong
   output logic             BPDirPredWrongM,           // Prediction direction is wrong
-  output logic             BTBPredPCWrongM,           // Prediction target wrong
+  output logic             BTAWrongM,           // Prediction target wrong
   output logic             RASPredPCWrongM,           // RAS prediction is wrong
   output logic             IClassWrongM // Class prediction is wrong
   );
@@ -215,10 +215,10 @@ module bpred (
     flopenrc #(`XLEN) RASTargetEReg(clk, reset, FlushE, ~StallE, RASPCD, RASPCE);
     flopenrc #(3) BPPredWrongRegM(clk, reset, FlushM, ~StallM, 
 				  {BPDirPredWrongE, BTBPredPCWrongE, RASPredPCWrongE},
-				  {BPDirPredWrongM, BTBPredPCWrongM, RASPredPCWrongM});
+				  {BPDirPredWrongM, BTAWrongM, RASPredPCWrongM});
     
   end else begin
-    assign {BTBPredPCWrongM, RASPredPCWrongM} = '0;
+    assign {BTAWrongM, RASPredPCWrongM} = '0;
   end
 
   // **** Fix me

src/ifu/ifu.sv

@@ -66,7 +66,7 @@ module ifu (
   // branch predictor
   output logic [3:0] 		InstrClassM,                              // The valid instruction class. 1-hot encoded as jalr, ret, jr (not ret), j, br
   output logic 				BPDirPredWrongM,                          // Prediction direction is wrong
-  output logic 				BTBPredPCWrongM,                          // Prediction target wrong
+  output logic 				BTAWrongM,                          // Prediction target wrong
   output logic 				RASPredPCWrongM,                          // RAS prediction is wrong
   output logic 				IClassWrongM,                             // Class prediction is wrong
   output logic 			    ICacheStallF,                             // I$ busy with multicycle operation
@@ -331,12 +331,12 @@ module ifu (
                 .BranchD, .BranchE, .JumpD, .JumpE,
                 .InstrD, .PCNextF, .PCPlus2or4F, .PC1NextF, .PCE, .PCM, .PCSrcE, .IEUAdrE, .IEUAdrM, .PCF, .NextValidPCE,
                 .PCD, .PCLinkE, .InstrClassM, .BPWrongE, .PostSpillInstrRawF, .BPWrongM,
-                .BPDirPredWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .IClassWrongM);
+                .BPDirPredWrongM, .BTAWrongM, .RASPredPCWrongM, .IClassWrongM);
 
   end else begin : bpred
     mux2 #(`XLEN) pcmux1(.d0(PCPlus2or4F), .d1(IEUAdrE), .s(PCSrcE), .y(PC1NextF));    
     assign BPWrongE = PCSrcE;
-    assign {InstrClassM, BPDirPredWrongM, BTBPredPCWrongM, RASPredPCWrongM, IClassWrongM} = '0;
+    assign {InstrClassM, BPDirPredWrongM, BTAWrongM, RASPredPCWrongM, IClassWrongM} = '0;
     assign NextValidPCE = PCE;
   end      
 

src/privileged/csr.sv

@@ -62,7 +62,7 @@ module csr #(parameter
   input  logic             ICacheStallF,
   input  logic             DCacheStallM,
   input  logic             BPDirPredWrongM,
-  input  logic             BTBPredPCWrongM,
+  input  logic             BTAWrongM,
   input  logic             RASPredPCWrongM,
   input  logic             IClassWrongM,
   input  logic             BPWrongM,                              // branch predictor is wrong
@@ -266,7 +266,7 @@ module csr #(parameter
   if (`ZICOUNTERS_SUPPORTED) begin:counters
     csrc  counters(.clk, .reset, .StallE, .StallM, .FlushM,
       .InstrValidNotFlushedM, .LoadStallD, .StoreStallD, .CSRWriteM, .CSRMWriteM,
-      .BPDirPredWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .IClassWrongM, .BPWrongM,
+      .BPDirPredWrongM, .BTAWrongM, .RASPredPCWrongM, .IClassWrongM, .BPWrongM,
       .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .sfencevmaM,
       .InterruptM, .ExceptionM, .FenceM, .ICacheStallF, .DCacheStallM, .DivBusyE, .FDivBusyE,
       .CSRAdrM, .PrivilegeModeW, .CSRWriteValM,

src/privileged/csrc.sv

@@ -46,7 +46,7 @@ module csrc #(parameter
   input  logic 	            InstrValidNotFlushedM, LoadStallD, StoreStallD, 
   input  logic              CSRMWriteM, CSRWriteM,
   input  logic 	            BPDirPredWrongM,
-  input  logic 	            BTBPredPCWrongM,
+  input  logic 	            BTAWrongM,
   input  logic 	            RASPredPCWrongM,
   input  logic 	            IClassWrongM,
   input  logic              BPWrongM,                              // branch predictor is wrong
@@ -99,7 +99,7 @@ module csrc #(parameter
     assign CounterEvent[5] = InstrClassM[2] & InstrValidNotFlushedM;                    // return instructions
 	assign CounterEvent[6] = BPWrongM & InstrValidNotFlushedM;                     // branch predictor wrong
     assign CounterEvent[7] = BPDirPredWrongM & InstrValidNotFlushedM;                   // Branch predictor wrong direction
-    assign CounterEvent[8] = BTBPredPCWrongM & InstrValidNotFlushedM;                   // branch predictor wrong target
+    assign CounterEvent[8] = BTAWrongM & InstrValidNotFlushedM;                   // branch predictor wrong target
     assign CounterEvent[9] = RASPredPCWrongM & InstrValidNotFlushedM;                   // return address stack wrong address
     assign CounterEvent[10] = IClassWrongM & InstrValidNotFlushedM;       // instruction class predictor wrong
     assign CounterEvent[11] = LoadStallM & InstrValidNotFlushedM;                       // Load Stalls. don't want to suppress on flush as this only happens if flushed.

src/privileged/privileged.sv

@@ -50,7 +50,7 @@ module privileged (
   input  logic             ICacheStallF,                              // I cache stalled
   input  logic             DCacheStallM,                              // D cache stalled
   input  logic 		       BPDirPredWrongM,                           // branch predictor guessed wrong direction
-  input  logic 		       BTBPredPCWrongM,                           // branch predictor guessed wrong target
+  input  logic 		       BTAWrongM,                           // branch predictor guessed wrong target
   input  logic 		       RASPredPCWrongM,                           // return adddress stack guessed wrong target
   input  logic 		       IClassWrongM,                              // branch predictor guessed wrong instruction class
   input  logic             BPWrongM,                                  // branch predictor is wrong
@@ -130,7 +130,7 @@ module privileged (
     .CSRReadM, .CSRWriteM, .TrapM, .mretM, .sretM, .wfiM, .IntPendingM, .InterruptM,
     .MTimerInt, .MExtInt, .SExtInt, .MSwInt,
     .MTIME_CLINT, .InstrValidM, .FRegWriteM, .LoadStallD, .StoreStallD,
-    .BPDirPredWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPWrongM,
+    .BPDirPredWrongM, .BTAWrongM, .RASPredPCWrongM, .BPWrongM,
     .sfencevmaM, .ExceptionM, .FenceM, .ICacheStallF, .DCacheStallM, .DivBusyE, .FDivBusyE,
     .IClassWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess,
     .NextPrivilegeModeM, .PrivilegeModeW, .CauseM, .SelHPTW,

src/wally/wallypipelinedcore.sv

@@ -142,7 +142,7 @@ module wallypipelinedcore (
   
   logic                          BPWrongE, BPWrongM;
   logic                          BPDirPredWrongM;
-  logic                          BTBPredPCWrongM;
+  logic                          BTAWrongM;
   logic                          RASPredPCWrongM;
   logic                          IClassWrongM;
   logic [3:0]                    InstrClassM;
@@ -178,7 +178,7 @@ module wallypipelinedcore (
     // Mem
     .CommittedF, .UnalignedPCNextF, .InvalidateICacheM, .CSRWriteFenceM,
     .InstrD, .InstrM, .PCM, .InstrClassM, .BPDirPredWrongM,
-    .BTBPredPCWrongM, .RASPredPCWrongM, .IClassWrongM,
+    .BTAWrongM, .RASPredPCWrongM, .IClassWrongM,
     // Faults out
     .IllegalBaseInstrD, .IllegalFPUInstrD, .InstrPageFaultF, .IllegalIEUFPUInstrD, .InstrMisalignedFaultM,
     // mmu management
@@ -291,7 +291,7 @@ module wallypipelinedcore (
       .RetM, .TrapM, .sfencevmaM, .FenceM, .DCacheStallM, .ICacheStallF,
       .InstrValidM, .CommittedM, .CommittedF,
       .FRegWriteM, .LoadStallD, .StoreStallD,
-      .BPDirPredWrongM, .BTBPredPCWrongM, .BPWrongM,
+      .BPDirPredWrongM, .BTAWrongM, .BPWrongM,
       .RASPredPCWrongM, .IClassWrongM, .DivBusyE, .FDivBusyE,
       .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .PrivilegedM,
       .InstrPageFaultF, .LoadPageFaultM, .StoreAmoPageFaultM,