Merge pull request #1456 from davidharrishmc/dev

Temporarily return G=0 so riscof can build PMP ACTs

config/rv32gc/config.vh

@@ -139,7 +139,7 @@ localparam logic IDIV_ON_FPU = 0;
 localparam PMP_ENTRIES = 32'd16;
 // grain size should be a full cache line to avoid problems with accesses within a cache line
 // that span grain boundaries but are handled without a spill
-localparam PMP_G = 32'd4; // 64 bytes for 512-bit cache line
+localparam PMP_G = 32'd0; // 64 bytes for 512-bit cache line
 
 // Address space
 localparam logic [63:0] RESET_VECTOR = 64'h80000000;

config/rv32gc/imperas.ic

@@ -45,7 +45,7 @@
 
 # PMP Configuration
 --override cpu/PMP_registers=16
---override cpu/PMP_grain=4   # 64-byte grains to match cache line width
+--override cpu/PMP_grain=0   # 64-byte grains to match cache line width
 --override cpu/PMP_decompose=T  # unaligned accesses are decomposed into separate aligned accesses
 --override cpu/PMP_undefined=T # access to unimplemented PMP registers cause illegal instruction exception
 

config/rv64gc/config.vh

@@ -140,7 +140,7 @@ localparam PMP_ENTRIES = 32'd16;
 
 // grain size should be a full cache line to avoid problems with accesses within a cache line
 // that span grain boundaries but are handled without a spill
-localparam PMP_G = 32'd4;  //e.g. 4 for 64-byte grains (512-bit cache lines)
+localparam PMP_G = 32'd0;  //e.g. 4 for 64-byte grains (512-bit cache lines)
 
 // Address space
 localparam logic [63:0] RESET_VECTOR = 64'h0000000080000000;

config/rv64gc/imperas.ic

@@ -48,7 +48,7 @@
 
 # PMP Configuration
 --override cpu/PMP_registers=16
---override cpu/PMP_grain=4   # 64-byte grains to match cache line width
+--override cpu/PMP_grain=0   # 64-byte grains to match cache line width
 --override cpu/PMP_decompose=T  # unaligned accesses are decomposed into separate aligned accesses
 --override cpu/PMP_undefined=T # access to unimplemented PMP registers cause illegal instruction exception
 

testbench/common/riscvassertions.sv

@@ -22,9 +22,9 @@
 module riscvassertions import cvw::*; #(parameter cvw_t P);
   initial begin
     assert (P.PMP_ENTRIES == 0 | P.PMP_ENTRIES==16 | P.PMP_ENTRIES==64) else $fatal(1, "Illegal number of PMP entries: PMP_ENTRIES must be 0, 16, or 64");
-    assert (P.PMP_G > 0 | P.XLEN == 32 | P.PMP_ENTRIES == 0) else $fatal(1, "RV64 requires PMP_G at least 1 to avoid checking for 8-byte accesses to 4-byte region");
+//    assert (P.PMP_G > 0 | P.XLEN == 32 | P.PMP_ENTRIES == 0) else $fatal(1, "RV64 requires PMP_G at least 1 to avoid checking for 8-byte accesses to 4-byte region");
-    assert ((P.PMP_G >= $clog2(P.DCACHE_LINELENINBITS/8)-2) | !P.ZICCLSM_SUPPORTED | P.PMP_ENTRIES == 0) else $fatal(1, "Systems that support misaligned data with PMP must have grain size of at least one cache line so accesses that span grains will also cause spills");
+//    assert ((P.PMP_G >= $clog2(P.DCACHE_LINELENINBITS/8)-2) | !P.ZICCLSM_SUPPORTED | P.PMP_ENTRIES == 0) else $fatal(1, "Systems that support misaligned data with PMP must have grain size of at least one cache line so accesses that span grains will also cause spills");
-    assert ((P.PMP_G >= $clog2(P.ICACHE_LINELENINBITS/8)-2) | !P.ZCA_SUPPORTED | (P.PMP_ENTRIES == 0) | !P.ICACHE_SUPPORTED) else $fatal(1, "Systems that support compressed instructions with PMP must have grain size of at least one cache line so fetches that span grains will also cause spills");
+//    assert ((P.PMP_G >= $clog2(P.ICACHE_LINELENINBITS/8)-2) | !P.ZCA_SUPPORTED | (P.PMP_ENTRIES == 0) | !P.ICACHE_SUPPORTED) else $fatal(1, "Systems that support compressed instructions with PMP must have grain size of at least one cache line so fetches that span grains will also cause spills");
     assert (P.PMP_G < P.PA_BITS-2 | P.PMP_ENTRIES == 0) else $fatal(1, "PMP granularity must be less than the number of physical address bits");
     assert (P.IDIV_BITSPERCYCLE == 1 | P.IDIV_BITSPERCYCLE==2 | P.IDIV_BITSPERCYCLE==4) else $fatal(1, "Illegal number of divider bits/cycle: IDIV_BITSPERCYCLE must be 1, 2, or 4");
     assert (P.F_SUPPORTED | !P.D_SUPPORTED) else $fatal(1, "Can't support double fp (D) without supporting float (F)");

testbench/testbench.sv

@@ -918,14 +918,12 @@ end
   end
 
   if (P.ZICSR_SUPPORTED) begin
-    always @(dut.core.priv.priv.csr.csri.MIP_REGW[7])   void'(rvvi.net_push("MTimerInterrupt",    dut.core.priv.priv.csr.csri.MIP_REGW[7]));
+    always @(dut.core.priv.priv.trap.ValidIntsM[7])   void'(rvvi.net_push("MTimerInterrupt",    dut.core.priv.priv.trap.ValidIntsM[7]));
-    always @(dut.core.priv.priv.csr.csri.MIP_REGW[11])  void'(rvvi.net_push("MExternalInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[11]));
+    always @(dut.core.priv.priv.trap.ValidIntsM[11])  void'(rvvi.net_push("MExternalInterrupt", dut.core.priv.priv.trap.ValidIntsM[11]));
-    always @(dut.core.priv.priv.csr.csri.MIP_REGW[3])   void'(rvvi.net_push("MSWInterrupt",       dut.core.priv.priv.csr.csri.MIP_REGW[3]));
+    always @(dut.core.priv.priv.trap.ValidIntsM[3])   void'(rvvi.net_push("MSWInterrupt",       dut.core.priv.priv.trap.ValidIntsM[3]));
-    if (P.S_SUPPORTED) begin
+    always @(dut.core.priv.priv.trap.ValidIntsM[5])   void'(rvvi.net_push("STimerInterrupt",    dut.core.priv.priv.trap.ValidIntsM[5]));
-      always @(dut.core.priv.priv.csr.csri.MIP_REGW[5])   void'(rvvi.net_push("STimerInterrupt",    dut.core.priv.priv.csr.csri.MIP_REGW[5]));
+    always @(dut.core.priv.priv.trap.ValidIntsM[9])   void'(rvvi.net_push("SExternalInterrupt", dut.core.priv.priv.trap.ValidIntsM[9]));
-      always @(dut.core.priv.priv.csr.csri.MIP_REGW[9])   void'(rvvi.net_push("SExternalInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[9]));
+    always @(dut.core.priv.priv.trap.ValidIntsM[1])   void'(rvvi.net_push("SSWInterrupt",       dut.core.priv.priv.trap.ValidIntsM[1])); 
-      always @(dut.core.priv.priv.csr.csri.MIP_REGW[1])   void'(rvvi.net_push("SSWInterrupt",       dut.core.priv.priv.csr.csri.MIP_REGW[1]));
-    end
   end
 
   final begin

tests/riscof/sail_cSim/rv32gc.json

@@ -10,7 +10,7 @@
   },
   "memory": {
     "pmp": {
-      "grain": 4,
+      "grain": 0,
       "count": 16
     },
     "misaligned": {

tests/riscof/sail_cSim/rv64gc.json

@@ -10,7 +10,7 @@
   },
   "memory": {
     "pmp": {
-      "grain": 4,
+      "grain": 0,
       "count": 16
     },
     "misaligned": {

tests/riscof/spike/spike_rv32gc_isa.yaml

@@ -28,7 +28,7 @@ hart0:
               - Unchanged
   PMP:
     implemented: True
-    pmp-grain: 4
+    pmp-grain: 0
     pmp-count: 16
-    pmp-writable: 12
+    pmp-writable: 16
 

tests/riscof/spike/spike_rv64gc_isa.yaml

@@ -30,6 +30,6 @@ hart0:
               - Unchanged
   PMP:
     implemented: True
-    pmp-grain: 4
+    pmp-grain: 0
     pmp-count: 16
-    pmp-writable: 12
+    pmp-writable: 16