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Merge pull request #1331 from jordancarlin/riscv-arch-test-bump
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Update riscv-arch-test and add sv32 tests to fcov
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David Harris 2025-03-29 07:28:16 -07:00 • committed by GitHub
commit 85cc264341
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3 changed files with 17 additions and 2 deletions
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2
addins/riscv-arch-test

@ -1 +1 @@
Subproject commit 3baa17a888cd6b5a8ca78ada757783ae0c061b3a
Subproject commit 4812bdf0690c5ca0d9e2aba7e406cfa1f82b6a30

10
bin/regression-wally
View file

@ -319,7 +319,7 @@ def addTestsByDir(testDir, config, sim, coverStr, configs, lockstepMode=0, breke
sim_logdir = f"{regressionDir}/{sim}/logs/"
cmdPrefix = f"wsim --sim {sim} {coverStr} {'--lockstep' if lockstepMode else ''} {config}"
# fcov/ccov only runs on WALLY-COV-ALL.elf files; other lockstep runs on all files
fileStart = "WALLY-COV-ALL" if "cvw-arch-verif/tests" in testDir and "priv" not in testDir else ""
fileStart = "WALLY-COV-ALL" if "cvw-arch-verif/tests" in testDir and "priv" not in testDir else "ref" if "riscv-arch-test" in testDir else ""
fileEnd = ".elf"
if lockstepMode:
gs = "Mismatches : 0"
@ -438,11 +438,19 @@ def selectTests(args, sims, coverStr):
addTestsByDir(f"{archVerifDir}/tests/lockstep/rv64/", "rv64gc", coveragesim, coverStr, configs)
addTestsByDir(f"{archVerifDir}/tests/lockstep/priv/rv64/", "rv64gc", coveragesim, coverStr, configs)
addTestsByDir(WALLY+"/tests/coverage/", "rv64gc", coveragesim, coverStr, configs)
# Extra tests from riscv-arch-test that should be run as part of the functional coverage suite
addTestsByDir(f"{WALLY}/tests/riscof/work/riscv-arch-test/rv32i_m/vm_sv32", "rv32gc", coveragesim, coverStr, configs)
addTestsByDir(f"{WALLY}/tests/riscof/work/riscv-arch-test/rv32i_m/pmp32", "rv32gc", coveragesim, coverStr, configs)
addTestsByDir(f"{WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/pmp64", "rv64gc", coveragesim, coverStr, configs)
elif args.fcov: # run tests in lockstep in functional coverage mode
addTestsByDir(f"{archVerifDir}/tests/lockstep/rv32/", "rv32gc", coveragesim, coverStr, configs, lockstepMode=1)
addTestsByDir(f"{archVerifDir}/tests/lockstep/rv64/", "rv64gc", coveragesim, coverStr, configs, lockstepMode=1)
addTestsByDir(f"{archVerifDir}/tests/lockstep/priv/rv32/", "rv32gc", coveragesim, coverStr, configs, lockstepMode=1)
addTestsByDir(f"{archVerifDir}/tests/lockstep/priv/rv64/", "rv64gc", coveragesim, coverStr, configs, lockstepMode=1)
# Extra tests from riscv-arch-test that should be run as part of the functional coverage suite
addTestsByDir(f"{WALLY}/tests/riscof/work/riscv-arch-test/rv32i_m/vm_sv32", "rv32gc", coveragesim, coverStr, configs, lockstepMode=1)
# addTestsByDir(f"{WALLY}/tests/riscof/work/riscv-arch-test/rv32i_m/pmp32", "rv32gc", coveragesim, coverStr, configs, lockstepMode=1) TODO: Add when working in lockstep
# addTestsByDir(f"{WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/pmp64", "rv64gc", coveragesim, coverStr, configs, lockstepMode=1) TODO: Add when working in lockstep
elif args.breker:
addTestsByDir(WALLY+"/tests/breker/work", "breker", "questa", coverStr, configs, brekerMode=1)
elif not args.testfloat:

7
testbench/tests.vh
View file

@ -253,6 +253,9 @@ string arch32vm_sv32[] = '{
"rv32i_m/vm_sv32/src/vm_U_Bit_set_U_mode.S",
"rv32i_m/vm_sv32/src/vm_U_Bit_unset_S_mode.S",
"rv32i_m/vm_sv32/src/vm_U_Bit_unset_U_mode.S",
"rv32i_m/vm_sv32/src/vm_VA_all_ones_S_mode.S",
"rv32i_m/vm_sv32/src/vm_global_pte_S_mode.S",
"rv32i_m/vm_sv32/src/vm_global_pte_U_mode.S",
"rv32i_m/vm_sv32/src/vm_invalid_pte_S_mode.S",
"rv32i_m/vm_sv32/src/vm_invalid_pte_U_mode.S",
"rv32i_m/vm_sv32/src/vm_misaligned_S_mode.S",
@ -261,6 +264,9 @@ string arch32vm_sv32[] = '{
"rv32i_m/vm_sv32/src/vm_mprv_U_mode.S",
"rv32i_m/vm_sv32/src/vm_mprv_U_set_sum_set_S_mode.S",
"rv32i_m/vm_sv32/src/vm_mprv_U_set_sum_unset_S_mode.S",
"rv32i_m/vm_sv32/src/vm_mprv_bare_mode.S",
// "rv32i_m/vm_sv32/src/vm_mstatus_sbe_set_S_mode.S", TODO: Reenable when Sail big endian support is merged
// "rv32i_m/vm_sv32/src/vm_mstatus_sbe_set_sum_set_S_mode.S",
"rv32i_m/vm_sv32/src/vm_mxr_S_mode.S",
"rv32i_m/vm_sv32/src/vm_mxr_U_mode.S",
"rv32i_m/vm_sv32/src/vm_nleaf_pte_level0_S_mode.S",
@ -270,6 +276,7 @@ string arch32vm_sv32[] = '{
"rv32i_m/vm_sv32/src/vm_reserved_rwx_pte_S_mode.S",
"rv32i_m/vm_sv32/src/vm_reserved_rwx_pte_U_mode.S",
"rv32i_m/vm_sv32/src/vm_sum_set_S_mode.S",
"rv32i_m/vm_sv32/src/vm_sum_set_U_Bit_unset_S_mode.S",
"rv32i_m/vm_sv32/src/vm_sum_unset_S_mode.S"
};