mirror of
https://github.com/openhwgroup/cvw.git
synced 2025-04-22 12:57:23 -04:00
Deleted remaining old configs except fpga as I still need to create the parameterized version.
This commit is contained in:
Ross Thompson
parent
75b5c23edd
commit
87fb9a3e16
6 changed files with 0 additions and 938 deletions
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@ -1,156 +0,0 @@
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//////////////////////////////////////////
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// wally-config.vh
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//
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// Written: David_Harris@hmc.edu 4 January 2021
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// Modified:
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//
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// Purpose: Specify which features are configured
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// Macros to determine which modes are supported based on MISA
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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||||
// may obtain a copy of the License at
|
||||
//
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||||
// https://solderpad.org/licenses/SHL-2.1/
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||||
//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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||||
// either express or implied. See the License for the specific language governing permissions
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||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
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// include shared configuration
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`include "wally-shared.vh"
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`define FPGA 0
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`define QEMU 0
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// RV32 or RV64: XLEN = 32 or 64
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`define XLEN 32
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// IEEE 754 compliance
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`define IEEE754 0
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// E
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`define MISA (32'h00000010)
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`define ZICSR_SUPPORTED 0
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`define ZIFENCEI_SUPPORTED 0
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`define COUNTERS 0
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`define ZICOUNTERS_SUPPORTED 0
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`define ZFH_SUPPORTED 0
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`define SSTC_SUPPORTED 0
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// LSU microarchitectural Features
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`define BUS_SUPPORTED 1
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`define DCACHE_SUPPORTED 0
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`define ICACHE_SUPPORTED 0
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`define VIRTMEM_SUPPORTED 0
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`define VECTORED_INTERRUPTS_SUPPORTED 0
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`define BIGENDIAN_SUPPORTED 0
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// TLB configuration. Entries should be a power of 2
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`define ITLB_ENTRIES 0
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`define DTLB_ENTRIES 0
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// Cache configuration. Sizes should be a power of two
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// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
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`define DCACHE_NUMWAYS 4
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`define DCACHE_WAYSIZEINBYTES 4096
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`define DCACHE_LINELENINBITS 512
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`define ICACHE_NUMWAYS 4
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`define ICACHE_WAYSIZEINBYTES 4096
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`define ICACHE_LINELENINBITS 512
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// Integer Divider Configuration
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// IDIV_BITSPERCYCLE must be 1, 2, or 4
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`define IDIV_BITSPERCYCLE 1
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`define IDIV_ON_FPU 0
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// Legal number of PMP entries are 0, 16, or 64
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`define PMP_ENTRIES 0
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// Address space
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`define RESET_VECTOR 32'h80000000
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// WFI Timeout Wait
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`define WFI_TIMEOUT_BIT 16
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// Peripheral Addresses
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// Peripheral memory space extends from BASE to BASE+RANGE
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// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
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`define DTIM_SUPPORTED 1'b0
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`define DTIM_BASE 34'h80000000
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`define DTIM_RANGE 34'h007FFFFF
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`define IROM_SUPPORTED 1'b0
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`define IROM_BASE 34'h80000000
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`define IROM_RANGE 34'h007FFFFF
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`define BOOTROM_SUPPORTED 1'b1
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`define BOOTROM_BASE 34'h00001000
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`define BOOTROM_RANGE 34'h00000FFF
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`define UNCORE_RAM_SUPPORTED 1'b1
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`define UNCORE_RAM_BASE 34'h80000000
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`define UNCORE_RAM_RANGE 34'h07FFFFFF
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`define EXT_MEM_SUPPORTED 1'b0
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`define EXT_MEM_BASE 34'h80000000
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`define EXT_MEM_RANGE 34'h07FFFFFF
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`define CLINT_SUPPORTED 1'b0
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`define CLINT_BASE 34'h02000000
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`define CLINT_RANGE 34'h0000FFFF
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`define GPIO_SUPPORTED 1'b0
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`define GPIO_BASE 34'h10060000
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`define GPIO_RANGE 34'h000000FF
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`define UART_SUPPORTED 1'b0
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`define UART_BASE 34'h10000000
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`define UART_RANGE 34'h00000007
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`define PLIC_SUPPORTED 1'b0
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`define PLIC_BASE 34'h0C000000
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`define PLIC_RANGE 34'h03FFFFFF
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`define SDC_SUPPORTED 1'b0
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`define SDC_BASE 34'h00012100
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`define SDC_RANGE 34'h0000001F
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// Bus Interface width
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`define AHBW 32
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// Test modes
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// Tie GPIO outputs back to inputs
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`define GPIO_LOOPBACK_TEST 1
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// Hardware configuration
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`define UART_PRESCALE 1
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// Interrupt configuration
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`define PLIC_NUM_SRC 10
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// comment out the following if >=32 sources
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`define PLIC_NUM_SRC_LT_32
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`define PLIC_GPIO_ID 3
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`define PLIC_UART_ID 10
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`define BPRED_SUPPORTED 0
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`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
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`define BPRED_SIZE 10
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`define BPRED_NUM_LHR 6
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`define BTB_SIZE 10
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`define SVADU_SUPPORTED 0
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`define ZMMUL_SUPPORTED 0
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// FPU division architecture
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`define RADIX 32'h4
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`define DIVCOPIES 32'h4
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// bit manipulation
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`define ZBA_SUPPORTED 0
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`define ZBB_SUPPORTED 0
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`define ZBC_SUPPORTED 0
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`define ZBS_SUPPORTED 0
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// Memory synthesis configuration
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`define USE_SRAM 0
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@ -1,155 +0,0 @@
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//////////////////////////////////////////
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// wally-config.vh
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//
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// Written: David_Harris@hmc.edu 4 January 2021
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// Modified:
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//
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||||
// Purpose: Specify which features are configured
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||||
// Macros to determine which modes are supported based on MISA
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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||||
//
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||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
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// include shared configuration
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`include "wally-shared.vh"
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`define FPGA 0
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`define QEMU 0
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// RV32 or RV64: XLEN = 32 or 64
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`define XLEN 32
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// IEEE 754 compliance
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`define IEEE754 0
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`define MISA (32'h00000104 | 1 << 20 | 1 << 18 | 1 << 12 | 1 << 0 | 1 <<3 | 1 << 5)
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`define ZICSR_SUPPORTED 1
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`define ZIFENCEI_SUPPORTED 1
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`define COUNTERS 32
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`define ZICOUNTERS_SUPPORTED 1
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`define ZFH_SUPPORTED 0
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`define SSTC_SUPPORTED 1
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// LSU microarchitectural Features
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`define BUS_SUPPORTED 1
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`define DCACHE_SUPPORTED 1
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`define ICACHE_SUPPORTED 1
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`define VIRTMEM_SUPPORTED 1
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`define VECTORED_INTERRUPTS_SUPPORTED 1
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`define BIGENDIAN_SUPPORTED 1
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// TLB configuration. Entries should be a power of 2
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`define ITLB_ENTRIES 32
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`define DTLB_ENTRIES 32
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// Cache configuration. Sizes should be a power of two
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// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
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`define DCACHE_NUMWAYS 4
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`define DCACHE_WAYSIZEINBYTES 4096
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`define DCACHE_LINELENINBITS 512
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`define ICACHE_NUMWAYS 4
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`define ICACHE_WAYSIZEINBYTES 4096
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`define ICACHE_LINELENINBITS 512
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// Integer Divider Configuration
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// IDIV_BITSPERCYCLE must be 1, 2, or 4
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`define IDIV_BITSPERCYCLE 4
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`define IDIV_ON_FPU 1
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// Legal number of PMP entries are 0, 16, or 64
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`define PMP_ENTRIES 16
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// Address space
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`define RESET_VECTOR 32'h80000000
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// WFI Timeout Wait
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`define WFI_TIMEOUT_BIT 16
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// Peripheral Addresses
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// Peripheral memory space extends from BASE to BASE+RANGE
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// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
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`define DTIM_SUPPORTED 1'b0
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`define DTIM_BASE 34'h80000000
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`define DTIM_RANGE 34'h007FFFFF
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`define IROM_SUPPORTED 1'b0
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`define IROM_BASE 34'h80000000
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`define IROM_RANGE 34'h007FFFFF
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`define BOOTROM_SUPPORTED 1'b1
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`define BOOTROM_BASE 34'h00001000
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`define BOOTROM_RANGE 34'h00000FFF
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`define UNCORE_RAM_SUPPORTED 1'b1
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`define UNCORE_RAM_BASE 34'h80000000
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`define UNCORE_RAM_RANGE 34'h07FFFFFF
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`define EXT_MEM_SUPPORTED 1'b0
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`define EXT_MEM_BASE 34'h80000000
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`define EXT_MEM_RANGE 34'h07FFFFFF
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`define CLINT_SUPPORTED 1'b1
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`define CLINT_BASE 34'h02000000
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`define CLINT_RANGE 34'h0000FFFF
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`define GPIO_SUPPORTED 1'b1
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`define GPIO_BASE 34'h10060000
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`define GPIO_RANGE 34'h000000FF
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`define UART_SUPPORTED 1'b1
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`define UART_BASE 34'h10000000
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`define UART_RANGE 34'h00000007
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`define PLIC_SUPPORTED 1'b1
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`define PLIC_BASE 34'h0C000000
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`define PLIC_RANGE 34'h03FFFFFF
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`define SDC_SUPPORTED 1'b0
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`define SDC_BASE 34'h00012100
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`define SDC_RANGE 34'h0000001F
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// Bus Interface width
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`define AHBW 32
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// Test modes
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// Tie GPIO outputs back to inputs
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`define GPIO_LOOPBACK_TEST 1
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// Hardware configuration
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`define UART_PRESCALE 1
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// Interrupt configuration
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`define PLIC_NUM_SRC 10
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// comment out the following if >=32 sources
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`define PLIC_NUM_SRC_LT_32
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`define PLIC_GPIO_ID 3
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`define PLIC_UART_ID 10
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`define BPRED_SUPPORTED 1
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`define BPRED_TYPE "BP_GSHARE" // "BP_LOCAL_REPAIR" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
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`define BPRED_SIZE 16
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`define BPRED_NUM_LHR 8
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`define BTB_SIZE 10
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`define SVADU_SUPPORTED 1
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`define ZMMUL_SUPPORTED 0
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// FPU division architecture
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`define RADIX 32'h4
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`define DIVCOPIES 32'h4
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// bit manipulation
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`define ZBA_SUPPORTED 1
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`define ZBB_SUPPORTED 1
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`define ZBC_SUPPORTED 1
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`define ZBS_SUPPORTED 1
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// Memory synthesis configuration
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`define USE_SRAM 0
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@ -1,156 +0,0 @@
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//////////////////////////////////////////
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// wally-config.vh
|
||||
//
|
||||
// Written: David_Harris@hmc.edu 4 January 2021
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: Specify which features are configured
|
||||
// Macros to determine which modes are supported based on MISA
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
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// include shared configuration
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`include "wally-shared.vh"
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`define FPGA 0
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`define QEMU 0
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|
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// RV32 or RV64: XLEN = 32 or 64
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`define XLEN 32
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|
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// IEEE 754 compliance
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`define IEEE754 0
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|
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// I
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`define MISA (32'h00000104)
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`define ZICSR_SUPPORTED 0
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`define ZIFENCEI_SUPPORTED 0
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`define COUNTERS 32
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`define ZICOUNTERS_SUPPORTED 0
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`define ZFH_SUPPORTED 0
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`define SSTC_SUPPORTED 0
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// LSU microarchitectural Features
|
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`define BUS_SUPPORTED 0
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`define DCACHE_SUPPORTED 0
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`define ICACHE_SUPPORTED 0
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`define VIRTMEM_SUPPORTED 0
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`define VECTORED_INTERRUPTS_SUPPORTED 1
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`define BIGENDIAN_SUPPORTED 0
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||||
|
||||
// TLB configuration. Entries should be a power of 2
|
||||
`define ITLB_ENTRIES 32
|
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`define DTLB_ENTRIES 32
|
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|
||||
// Cache configuration. Sizes should be a power of two
|
||||
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
|
||||
`define DCACHE_NUMWAYS 4
|
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`define DCACHE_WAYSIZEINBYTES 4096
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`define DCACHE_LINELENINBITS 512
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`define ICACHE_NUMWAYS 4
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`define ICACHE_WAYSIZEINBYTES 4096
|
||||
`define ICACHE_LINELENINBITS 512
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||||
|
||||
// Integer Divider Configuration
|
||||
// IDIV_BITSPERCYCLE must be 1, 2, or 4
|
||||
`define IDIV_BITSPERCYCLE 4
|
||||
`define IDIV_ON_FPU 0
|
||||
|
||||
// Legal number of PMP entries are 0, 16, or 64
|
||||
`define PMP_ENTRIES 0
|
||||
|
||||
// Address space
|
||||
`define RESET_VECTOR 32'h80000000
|
||||
|
||||
// WFI Timeout Wait
|
||||
`define WFI_TIMEOUT_BIT 16
|
||||
|
||||
// Peripheral Addresses
|
||||
// Peripheral memory space extends from BASE to BASE+RANGE
|
||||
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
|
||||
`define DTIM_SUPPORTED 1'b1
|
||||
`define DTIM_BASE 34'h80000000
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||||
`define DTIM_RANGE 34'h007FFFFF
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||||
`define IROM_SUPPORTED 1'b1
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||||
`define IROM_BASE 34'h80000000
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`define IROM_RANGE 34'h007FFFFF
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||||
`define BOOTROM_SUPPORTED 1'b0
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||||
`define BOOTROM_BASE 34'h00001000
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||||
`define BOOTROM_RANGE 34'h00000FFF
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||||
`define UNCORE_RAM_SUPPORTED 1'b0
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||||
`define UNCORE_RAM_BASE 34'h80000000
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||||
`define UNCORE_RAM_RANGE 34'h07FFFFFF
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||||
`define EXT_MEM_SUPPORTED 1'b0
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||||
`define EXT_MEM_BASE 34'h80000000
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||||
`define EXT_MEM_RANGE 34'h07FFFFFF
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||||
`define CLINT_SUPPORTED 1'b0
|
||||
`define CLINT_BASE 34'h02000000
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||||
`define CLINT_RANGE 34'h0000FFFF
|
||||
`define GPIO_SUPPORTED 1'b0
|
||||
`define GPIO_BASE 34'h10060000
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||||
`define GPIO_RANGE 34'h000000FF
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||||
`define UART_SUPPORTED 1'b0
|
||||
`define UART_BASE 34'h10000000
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||||
`define UART_RANGE 34'h00000007
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||||
`define PLIC_SUPPORTED 1'b0
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`define PLIC_BASE 34'h0C000000
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||||
`define PLIC_RANGE 34'h03FFFFFF
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||||
`define SDC_SUPPORTED 1'b0
|
||||
`define SDC_BASE 34'h00012100
|
||||
`define SDC_RANGE 34'h0000001F
|
||||
|
||||
// Bus Interface width
|
||||
`define AHBW 32
|
||||
|
||||
// Test modes
|
||||
|
||||
// Tie GPIO outputs back to inputs
|
||||
`define GPIO_LOOPBACK_TEST 1
|
||||
|
||||
// Hardware configuration
|
||||
`define UART_PRESCALE 1
|
||||
|
||||
// Interrupt configuration
|
||||
`define PLIC_NUM_SRC 10
|
||||
// comment out the following if >=32 sources
|
||||
`define PLIC_NUM_SRC_LT_32
|
||||
`define PLIC_GPIO_ID 3
|
||||
`define PLIC_UART_ID 10
|
||||
|
||||
`define BPRED_SUPPORTED 0
|
||||
`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
|
||||
`define BPRED_SIZE 10
|
||||
`define BPRED_NUM_LHR 6
|
||||
`define BTB_SIZE 10
|
||||
|
||||
`define SVADU_SUPPORTED 0
|
||||
`define ZMMUL_SUPPORTED 0
|
||||
|
||||
// FPU division architecture
|
||||
`define RADIX 32'h4
|
||||
`define DIVCOPIES 32'h4
|
||||
|
||||
// bit manipulation
|
||||
`define ZBA_SUPPORTED 0
|
||||
`define ZBB_SUPPORTED 0
|
||||
`define ZBC_SUPPORTED 0
|
||||
`define ZBS_SUPPORTED 0
|
||||
|
||||
// Memory synthesis configuration
|
||||
`define USE_SRAM 0
|
||||
|
|
@ -1,155 +0,0 @@
|
|||
//////////////////////////////////////////
|
||||
// wally-config.vh
|
||||
//
|
||||
// Written: David_Harris@hmc.edu 4 January 2021
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: Specify which features are configured
|
||||
// Macros to determine which modes are supported based on MISA
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// include shared configuration
|
||||
`include "wally-shared.vh"
|
||||
|
||||
`define FPGA 0
|
||||
`define QEMU 0
|
||||
|
||||
// RV32 or RV64: XLEN = 32 or 64
|
||||
`define XLEN 32
|
||||
|
||||
// IEEE 754 compliance
|
||||
`define IEEE754 0
|
||||
|
||||
`define MISA (32'h00000104 | 1 << 20 | 1 << 18 | 1 << 12)
|
||||
`define ZICSR_SUPPORTED 1
|
||||
`define ZIFENCEI_SUPPORTED 1
|
||||
`define COUNTERS 32
|
||||
`define ZICOUNTERS_SUPPORTED 1
|
||||
`define ZFH_SUPPORTED 0
|
||||
`define SSTC_SUPPORTED 0
|
||||
|
||||
// LSU microarchitectural Features
|
||||
`define BUS_SUPPORTED 1
|
||||
`define DCACHE_SUPPORTED 0
|
||||
`define ICACHE_SUPPORTED 0
|
||||
`define VIRTMEM_SUPPORTED 0
|
||||
`define VECTORED_INTERRUPTS_SUPPORTED 1
|
||||
`define BIGENDIAN_SUPPORTED 0
|
||||
|
||||
// TLB configuration. Entries should be a power of 2
|
||||
`define ITLB_ENTRIES 0
|
||||
`define DTLB_ENTRIES 0
|
||||
|
||||
// Cache configuration. Sizes should be a power of two
|
||||
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
|
||||
`define DCACHE_NUMWAYS 4
|
||||
`define DCACHE_WAYSIZEINBYTES 4096
|
||||
`define DCACHE_LINELENINBITS 512
|
||||
`define ICACHE_NUMWAYS 4
|
||||
`define ICACHE_WAYSIZEINBYTES 4096
|
||||
`define ICACHE_LINELENINBITS 512
|
||||
|
||||
// Integer Divider Configuration
|
||||
// IDIV_BITSPERCYCLE must be 1, 2, or 4
|
||||
`define IDIV_BITSPERCYCLE 2
|
||||
`define IDIV_ON_FPU 0
|
||||
|
||||
// Legal number of PMP entries are 0, 16, or 64
|
||||
`define PMP_ENTRIES 0
|
||||
|
||||
// Address space
|
||||
`define RESET_VECTOR 32'h80000000
|
||||
|
||||
// WFI Timeout Wait
|
||||
`define WFI_TIMEOUT_BIT 16
|
||||
|
||||
// Peripheral Addresses
|
||||
// Peripheral memory space extends from BASE to BASE+RANGE
|
||||
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
|
||||
`define DTIM_SUPPORTED 1'b1
|
||||
`define DTIM_BASE 34'h80000000
|
||||
`define DTIM_RANGE 34'h007FFFFF
|
||||
`define IROM_SUPPORTED 1'b1
|
||||
`define IROM_BASE 34'h80000000
|
||||
`define IROM_RANGE 34'h007FFFFF
|
||||
`define BOOTROM_SUPPORTED 1'b0
|
||||
`define BOOTROM_BASE 34'h00001000
|
||||
`define BOOTROM_RANGE 34'h00000FFF
|
||||
`define UNCORE_RAM_SUPPORTED 1'b0
|
||||
`define UNCORE_RAM_BASE 34'h80000000
|
||||
`define UNCORE_RAM_RANGE 34'h07FFFFFF
|
||||
`define EXT_MEM_SUPPORTED 1'b0
|
||||
`define EXT_MEM_BASE 34'h80000000
|
||||
`define EXT_MEM_RANGE 34'h07FFFFFF
|
||||
`define CLINT_SUPPORTED 1'b1
|
||||
`define CLINT_BASE 34'h02000000
|
||||
`define CLINT_RANGE 34'h0000FFFF
|
||||
`define GPIO_SUPPORTED 1'b1
|
||||
`define GPIO_BASE 34'h10060000
|
||||
`define GPIO_RANGE 34'h000000FF
|
||||
`define UART_SUPPORTED 1'b1
|
||||
`define UART_BASE 34'h10000000
|
||||
`define UART_RANGE 34'h00000007
|
||||
`define PLIC_SUPPORTED 1'b1
|
||||
`define PLIC_BASE 34'h0C000000
|
||||
`define PLIC_RANGE 34'h03FFFFFF
|
||||
`define SDC_SUPPORTED 1'b0
|
||||
`define SDC_BASE 34'h00012100
|
||||
`define SDC_RANGE 34'h0000001F
|
||||
|
||||
// Bus Interface width
|
||||
`define AHBW 32
|
||||
|
||||
// Test modes
|
||||
|
||||
// Tie GPIO outputs back to inputs
|
||||
`define GPIO_LOOPBACK_TEST 1
|
||||
|
||||
// Hardware configuration
|
||||
`define UART_PRESCALE 1
|
||||
|
||||
// Interrupt configuration
|
||||
`define PLIC_NUM_SRC 10
|
||||
// comment out the following if >=32 sources
|
||||
`define PLIC_NUM_SRC_LT_32
|
||||
`define PLIC_GPIO_ID 3
|
||||
`define PLIC_UART_ID 10
|
||||
|
||||
`define BPRED_SUPPORTED 0
|
||||
`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
|
||||
`define BPRED_SIZE 10
|
||||
`define BPRED_NUM_LHR 6
|
||||
`define BTB_SIZE 10
|
||||
|
||||
`define SVADU_SUPPORTED 0
|
||||
`define ZMMUL_SUPPORTED 0
|
||||
|
||||
// FPU division architecture
|
||||
`define RADIX 32'h4
|
||||
`define DIVCOPIES 32'h4
|
||||
|
||||
// bit manipulation
|
||||
`define ZBA_SUPPORTED 0
|
||||
`define ZBB_SUPPORTED 0
|
||||
`define ZBC_SUPPORTED 0
|
||||
`define ZBS_SUPPORTED 0
|
||||
|
||||
// Memory synthesis configuration
|
||||
`define USE_SRAM 0
|
||||
|
|
@ -1,158 +0,0 @@
|
|||
//////////////////////////////////////////
|
||||
// wally-config.vh
|
||||
//
|
||||
// Written: David_Harris@hmc.edu 4 January 2021
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: Specify which features are configured
|
||||
// Macros to determine which modes are supported based on MISA
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// include shared configuration
|
||||
`include "wally-shared.vh"
|
||||
|
||||
`define FPGA 0
|
||||
`define QEMU 0
|
||||
|
||||
// RV32 or RV64: XLEN = 32 or 64
|
||||
`define XLEN 64
|
||||
|
||||
// IEEE 754 compliance
|
||||
`define IEEE754 0
|
||||
|
||||
// MISA RISC-V configuration per specification
|
||||
`define MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0 )
|
||||
`define ZICSR_SUPPORTED 1
|
||||
`define ZIFENCEI_SUPPORTED 1
|
||||
`define COUNTERS 32
|
||||
`define ZICOUNTERS_SUPPORTED 1
|
||||
`define ZFH_SUPPORTED 1
|
||||
`define SSTC_SUPPORTED 0
|
||||
|
||||
// LSU microarchitectural Features
|
||||
`define BUS_SUPPORTED 1
|
||||
`define DCACHE_SUPPORTED 1
|
||||
`define ICACHE_SUPPORTED 1
|
||||
`define VIRTMEM_SUPPORTED 1
|
||||
`define VECTORED_INTERRUPTS_SUPPORTED 1
|
||||
`define BIGENDIAN_SUPPORTED 1
|
||||
|
||||
// TLB configuration. Entries should be a power of 2
|
||||
`define ITLB_ENTRIES 32
|
||||
`define DTLB_ENTRIES 32
|
||||
|
||||
// Cache configuration. Sizes should be a power of two
|
||||
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
|
||||
`define DCACHE_NUMWAYS 4
|
||||
`define DCACHE_WAYSIZEINBYTES 4096
|
||||
`define DCACHE_LINELENINBITS 512
|
||||
`define ICACHE_NUMWAYS 4
|
||||
`define ICACHE_WAYSIZEINBYTES 4096
|
||||
`define ICACHE_LINELENINBITS 512
|
||||
|
||||
// Integer Divider Configuration
|
||||
// IDIV_BITSPERCYCLE must be 1, 2, or 4
|
||||
`define IDIV_BITSPERCYCLE 4
|
||||
`define IDIV_ON_FPU 1
|
||||
|
||||
// Legal number of PMP entries are 0, 16, or 64
|
||||
`define PMP_ENTRIES 16
|
||||
|
||||
// Address space
|
||||
`define RESET_VECTOR 64'h0000000080000000
|
||||
|
||||
// Bus Interface width
|
||||
`define AHBW 64
|
||||
|
||||
// WFI Timeout Wait
|
||||
`define WFI_TIMEOUT_BIT 16
|
||||
|
||||
// Peripheral Physiccal Addresses
|
||||
// Peripheral memory space extends from BASE to BASE+RANGE
|
||||
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
|
||||
|
||||
// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
|
||||
`define DTIM_SUPPORTED 1'b0
|
||||
`define DTIM_BASE 56'h80000000
|
||||
`define DTIM_RANGE 56'h007FFFFF
|
||||
`define IROM_SUPPORTED 1'b0
|
||||
`define IROM_BASE 56'h80000000
|
||||
`define IROM_RANGE 56'h007FFFFF
|
||||
`define BOOTROM_SUPPORTED 1'b1
|
||||
`define BOOTROM_BASE 56'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
|
||||
`define BOOTROM_RANGE 56'h00000FFF
|
||||
`define UNCORE_RAM_SUPPORTED 1'b1
|
||||
`define UNCORE_RAM_BASE 56'h80000000
|
||||
`define UNCORE_RAM_RANGE 56'h7FFFFFFF
|
||||
`define EXT_MEM_SUPPORTED 1'b0
|
||||
`define EXT_MEM_BASE 56'h80000000
|
||||
`define EXT_MEM_RANGE 56'h07FFFFFF
|
||||
`define CLINT_SUPPORTED 1'b1
|
||||
`define CLINT_BASE 56'h02000000
|
||||
`define CLINT_RANGE 56'h0000FFFF
|
||||
`define GPIO_SUPPORTED 1'b1
|
||||
`define GPIO_BASE 56'h10060000
|
||||
`define GPIO_RANGE 56'h000000FF
|
||||
`define UART_SUPPORTED 1'b1
|
||||
`define UART_BASE 56'h10000000
|
||||
`define UART_RANGE 56'h00000007
|
||||
`define PLIC_SUPPORTED 1'b1
|
||||
`define PLIC_BASE 56'h0C000000
|
||||
`define PLIC_RANGE 56'h03FFFFFF
|
||||
`define SDC_SUPPORTED 1'b0
|
||||
`define SDC_BASE 56'h00012100
|
||||
`define SDC_RANGE 56'h0000001F
|
||||
|
||||
// Test modes
|
||||
|
||||
// Tie GPIO outputs back to inputs
|
||||
`define GPIO_LOOPBACK_TEST 1
|
||||
|
||||
// Hardware configuration
|
||||
`define UART_PRESCALE 1
|
||||
|
||||
// Interrupt configuration
|
||||
`define PLIC_NUM_SRC 10
|
||||
// comment out the following if >=32 sources
|
||||
`define PLIC_NUM_SRC_LT_32
|
||||
`define PLIC_GPIO_ID 3
|
||||
`define PLIC_UART_ID 10
|
||||
|
||||
`define BPRED_SUPPORTED 1
|
||||
`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
|
||||
`define BPRED_SIZE 10
|
||||
`define BPRED_NUM_LHR 6
|
||||
`define BTB_SIZE 10
|
||||
|
||||
`define SVADU_SUPPORTED 0
|
||||
`define ZMMUL_SUPPORTED 0
|
||||
|
||||
// FPU division architecture
|
||||
`define RADIX 32'h4
|
||||
`define DIVCOPIES 32'h4
|
||||
|
||||
// bit manipulation
|
||||
`define ZBA_SUPPORTED 0
|
||||
`define ZBB_SUPPORTED 0
|
||||
`define ZBC_SUPPORTED 0
|
||||
`define ZBS_SUPPORTED 0
|
||||
|
||||
// Memory synthesis configuration
|
||||
`define USE_SRAM 0
|
||||
|
|
@ -1,158 +0,0 @@
|
|||
//////////////////////////////////////////
|
||||
// wally-config.vh
|
||||
//
|
||||
// Written: David_Harris@hmc.edu 4 January 2021
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: Specify which features are configured
|
||||
// Macros to determine which modes are supported based on MISA
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// include shared configuration
|
||||
`include "wally-shared.vh"
|
||||
|
||||
`define FPGA 0
|
||||
`define QEMU 0
|
||||
|
||||
// RV32 or RV64: XLEN = 32 or 64
|
||||
`define XLEN 64
|
||||
|
||||
// IEEE 754 compliance
|
||||
`define IEEE754 0
|
||||
|
||||
// MISA RISC-V configuration per specification
|
||||
`define MISA (32'h00000104)
|
||||
`define ZICSR_SUPPORTED 0
|
||||
`define ZIFENCEI_SUPPORTED 0
|
||||
`define COUNTERS 32
|
||||
`define ZICOUNTERS_SUPPORTED 0
|
||||
`define ZFH_SUPPORTED 0
|
||||
`define SSTC_SUPPORTED 0
|
||||
|
||||
// LSU microarchitectural Features
|
||||
`define BUS_SUPPORTED 0
|
||||
`define DCACHE_SUPPORTED 0
|
||||
`define ICACHE_SUPPORTED 0
|
||||
`define VIRTMEM_SUPPORTED 0
|
||||
`define VECTORED_INTERRUPTS_SUPPORTED 1
|
||||
`define BIGENDIAN_SUPPORTED 0
|
||||
|
||||
// TLB configuration. Entries should be a power of 2
|
||||
`define ITLB_ENTRIES 0
|
||||
`define DTLB_ENTRIES 0
|
||||
|
||||
// Cache configuration. Sizes should be a power of two
|
||||
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
|
||||
`define DCACHE_NUMWAYS 4
|
||||
`define DCACHE_WAYSIZEINBYTES 4096
|
||||
`define DCACHE_LINELENINBITS 512
|
||||
`define ICACHE_NUMWAYS 4
|
||||
`define ICACHE_WAYSIZEINBYTES 4096
|
||||
`define ICACHE_LINELENINBITS 512
|
||||
|
||||
// Integer Divider Configuration
|
||||
// IDIV_BITSPERCYCLE must be 1, 2, or 4
|
||||
`define IDIV_BITSPERCYCLE 4
|
||||
`define IDIV_ON_FPU 0
|
||||
|
||||
// Legal number of PMP entries are 0, 16, or 64
|
||||
`define PMP_ENTRIES 0
|
||||
|
||||
// Address space
|
||||
`define RESET_VECTOR 64'h0000000080000000
|
||||
|
||||
// Bus Interface width
|
||||
`define AHBW (`XLEN)
|
||||
|
||||
// WFI Timeout Wait
|
||||
`define WFI_TIMEOUT_BIT 16
|
||||
|
||||
// Peripheral Physiccal Addresses
|
||||
// Peripheral memory space extends from BASE to BASE+RANGE
|
||||
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
|
||||
|
||||
// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
|
||||
`define DTIM_SUPPORTED 1'b1
|
||||
`define DTIM_BASE 56'h80000000
|
||||
`define DTIM_RANGE 56'h007FFFFF
|
||||
`define IROM_SUPPORTED 1'b1
|
||||
`define IROM_BASE 56'h80000000
|
||||
`define IROM_RANGE 56'h007FFFFF
|
||||
`define BOOTROM_SUPPORTED 1'b0
|
||||
`define BOOTROM_BASE 56'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
|
||||
`define BOOTROM_RANGE 56'h00000FFF
|
||||
`define UNCORE_RAM_SUPPORTED 1'b0
|
||||
`define UNCORE_RAM_BASE 56'h80000000
|
||||
`define UNCORE_RAM_RANGE 56'h7FFFFFFF
|
||||
`define EXT_MEM_SUPPORTED 1'b0
|
||||
`define EXT_MEM_BASE 56'h80000000
|
||||
`define EXT_MEM_RANGE 56'h07FFFFFF
|
||||
`define CLINT_SUPPORTED 1'b0
|
||||
`define CLINT_BASE 56'h02000000
|
||||
`define CLINT_RANGE 56'h0000FFFF
|
||||
`define GPIO_SUPPORTED 1'b0
|
||||
`define GPIO_BASE 56'h10060000
|
||||
`define GPIO_RANGE 56'h000000FF
|
||||
`define UART_SUPPORTED 1'b0
|
||||
`define UART_BASE 56'h10000000
|
||||
`define UART_RANGE 56'h00000007
|
||||
`define PLIC_SUPPORTED 1'b0
|
||||
`define PLIC_BASE 56'h0C000000
|
||||
`define PLIC_RANGE 56'h03FFFFFF
|
||||
`define SDC_SUPPORTED 1'b0
|
||||
`define SDC_BASE 56'h00012100
|
||||
`define SDC_RANGE 56'h0000001F
|
||||
|
||||
// Test modes
|
||||
|
||||
// Tie GPIO outputs back to inputs
|
||||
`define GPIO_LOOPBACK_TEST 1
|
||||
|
||||
// Hardware configuration
|
||||
`define UART_PRESCALE 1
|
||||
|
||||
// Interrupt configuration
|
||||
`define PLIC_NUM_SRC 10
|
||||
// comment out the following if >=32 sources
|
||||
`define PLIC_NUM_SRC_LT_32
|
||||
`define PLIC_GPIO_ID 3
|
||||
`define PLIC_UART_ID 10
|
||||
|
||||
`define BPRED_SUPPORTED 0
|
||||
`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
|
||||
`define BPRED_SIZE 10
|
||||
`define BPRED_NUM_LHR 6
|
||||
`define BTB_SIZE 10
|
||||
|
||||
`define SVADU_SUPPORTED 0
|
||||
`define ZMMUL_SUPPORTED 0
|
||||
|
||||
// FPU division architecture
|
||||
`define RADIX 32'h4
|
||||
`define DIVCOPIES 32'h4
|
||||
|
||||
// bit manipulation
|
||||
`define ZBA_SUPPORTED 0
|
||||
`define ZBB_SUPPORTED 0
|
||||
`define ZBC_SUPPORTED 0
|
||||
`define ZBS_SUPPORTED 0
|
||||
|
||||
// Memory synthesis configuration
|
||||
`define USE_SRAM 0
|
||||
Loading…
Add table
Add a link
Reference in a new issue