mirror of
https://github.com/openhwgroup/cvw.git
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
This commit is contained in:
David Harris
commit
89ee6c778e
7 changed files with 178 additions and 132 deletions
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@ -17,15 +17,15 @@ endgroup
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connect_debug_port u_ila_0/clk [get_nets [list xlnx_ddr4_c0/inst/u_ddr4_infrastructure/addn_ui_clkout1 ]]
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set_property port_width 64 [get_debug_ports u_ila_0/probe0]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
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connect_debug_port u_ila_0/probe0 [get_nets [list {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[0]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[1]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[2]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[3]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[4]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[5]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[6]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[7]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[8]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[9]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[10]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[11]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[12]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[13]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[14]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[15]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[16]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[17]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[18]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[19]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[20]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[21]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[22]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[23]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[24]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[25]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[26]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[27]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[28]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[29]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[30]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[31]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[32]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[33]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[34]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[35]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[36]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[37]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[38]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[39]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[40]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[41]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[42]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[43]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[44]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[45]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[46]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[47]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[48]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[49]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[50]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[51]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[52]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[53]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[54]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[55]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[56]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[57]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[58]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[59]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[60]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[61]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[62]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[63]} ]]
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connect_debug_port u_ila_0/probe0 [get_nets [list {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[0]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[1]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[2]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[3]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[4]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[5]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[6]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[7]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[8]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[9]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[10]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[11]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[12]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[13]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[14]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[15]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[16]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[17]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[18]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[19]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[20]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[21]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[22]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[23]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[24]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[25]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[26]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[27]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[28]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[29]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[30]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[31]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[32]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[33]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[34]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[35]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[36]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[37]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[38]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[39]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[40]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[41]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[42]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[43]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[44]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[45]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[46]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[47]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[48]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[49]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[50]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[51]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[52]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[53]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[54]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[55]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[56]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[57]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[58]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[59]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[60]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[61]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[62]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[63]} ]]
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create_debug_port u_ila_0 probe
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set_property port_width 64 [get_debug_ports u_ila_0/probe1]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
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connect_debug_port u_ila_0/probe1 [get_nets [list {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[0]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[1]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[2]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[3]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[4]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[5]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[6]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[7]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[8]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[9]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[10]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[11]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[12]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[13]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[14]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[15]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[16]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[17]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[18]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[19]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[20]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[21]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[22]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[23]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[24]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[25]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[26]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[27]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[28]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[29]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[30]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[31]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[32]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[33]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[34]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[35]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[36]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[37]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[38]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[39]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[40]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[41]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[42]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[43]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[44]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[45]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[46]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[47]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[48]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[49]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[50]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[51]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[52]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[53]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[54]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[55]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[56]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[57]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[58]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[59]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[60]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[61]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[62]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[63]} ]]
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connect_debug_port u_ila_0/probe1 [get_nets [list {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[0]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[1]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[2]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[3]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[4]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[5]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[6]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[7]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[8]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[9]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[10]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[11]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[12]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[13]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[14]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[15]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[16]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[17]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[18]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[19]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[20]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[21]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[22]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[23]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[24]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[25]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[26]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[27]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[28]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[29]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[30]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[31]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[32]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[33]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[34]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[35]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[36]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[37]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[38]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[39]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[40]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[41]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[42]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[43]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[44]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[45]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[46]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[47]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[48]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[49]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[50]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[51]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[52]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[53]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[54]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[55]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[56]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[57]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[58]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[59]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[60]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[61]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[62]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[63]} ]]
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create_debug_port u_ila_0 probe
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set_property port_width 32 [get_debug_ports u_ila_0/probe2]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
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connect_debug_port u_ila_0/probe2 [get_nets [list {wallypipelinedsoc/hart/lsu/LsuBusAdr[0]} {wallypipelinedsoc/hart/lsu/LsuBusAdr[1]} {wallypipelinedsoc/hart/lsu/LsuBusAdr[2]} {wallypipelinedsoc/hart/lsu/LsuBusAdr[3]} {wallypipelinedsoc/hart/lsu/LsuBusAdr[4]} {wallypipelinedsoc/hart/lsu/LsuBusAdr[5]} {wallypipelinedsoc/hart/lsu/LsuBusAdr[6]} {wallypipelinedsoc/hart/lsu/LsuBusAdr[7]} {wallypipelinedsoc/hart/lsu/LsuBusAdr[8]} {wallypipelinedsoc/hart/lsu/LsuBusAdr[9]} {wallypipelinedsoc/hart/lsu/LsuBusAdr[10]} {wallypipelinedsoc/hart/lsu/LsuBusAdr[11]} {wallypipelinedsoc/hart/lsu/LsuBusAdr[12]} {wallypipelinedsoc/hart/lsu/LsuBusAdr[13]} {wallypipelinedsoc/hart/lsu/LsuBusAdr[14]} {wallypipelinedsoc/hart/lsu/LsuBusAdr[15]} {wallypipelinedsoc/hart/lsu/LsuBusAdr[16]} {wallypipelinedsoc/hart/lsu/LsuBusAdr[17]} {wallypipelinedsoc/hart/lsu/LsuBusAdr[18]} {wallypipelinedsoc/hart/lsu/LsuBusAdr[19]} {wallypipelinedsoc/hart/lsu/LsuBusAdr[20]} {wallypipelinedsoc/hart/lsu/LsuBusAdr[21]} {wallypipelinedsoc/hart/lsu/LsuBusAdr[22]} {wallypipelinedsoc/hart/lsu/LsuBusAdr[23]} {wallypipelinedsoc/hart/lsu/LsuBusAdr[24]} {wallypipelinedsoc/hart/lsu/LsuBusAdr[25]} {wallypipelinedsoc/hart/lsu/LsuBusAdr[26]} {wallypipelinedsoc/hart/lsu/LsuBusAdr[27]} {wallypipelinedsoc/hart/lsu/LsuBusAdr[28]} {wallypipelinedsoc/hart/lsu/LsuBusAdr[29]} {wallypipelinedsoc/hart/lsu/LsuBusAdr[30]} {wallypipelinedsoc/hart/lsu/LsuBusAdr[31]} ]]
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connect_debug_port u_ila_0/probe2 [get_nets [list {wallypipelinedsoc/hart/lsu/LSUBusAdr[0]} {wallypipelinedsoc/hart/lsu/LSUBusAdr[1]} {wallypipelinedsoc/hart/lsu/LSUBusAdr[2]} {wallypipelinedsoc/hart/lsu/LSUBusAdr[3]} {wallypipelinedsoc/hart/lsu/LSUBusAdr[4]} {wallypipelinedsoc/hart/lsu/LSUBusAdr[5]} {wallypipelinedsoc/hart/lsu/LSUBusAdr[6]} {wallypipelinedsoc/hart/lsu/LSUBusAdr[7]} {wallypipelinedsoc/hart/lsu/LSUBusAdr[8]} {wallypipelinedsoc/hart/lsu/LSUBusAdr[9]} {wallypipelinedsoc/hart/lsu/LSUBusAdr[10]} {wallypipelinedsoc/hart/lsu/LSUBusAdr[11]} {wallypipelinedsoc/hart/lsu/LSUBusAdr[12]} {wallypipelinedsoc/hart/lsu/LSUBusAdr[13]} {wallypipelinedsoc/hart/lsu/LSUBusAdr[14]} {wallypipelinedsoc/hart/lsu/LSUBusAdr[15]} {wallypipelinedsoc/hart/lsu/LSUBusAdr[16]} {wallypipelinedsoc/hart/lsu/LSUBusAdr[17]} {wallypipelinedsoc/hart/lsu/LSUBusAdr[18]} {wallypipelinedsoc/hart/lsu/LSUBusAdr[19]} {wallypipelinedsoc/hart/lsu/LSUBusAdr[20]} {wallypipelinedsoc/hart/lsu/LSUBusAdr[21]} {wallypipelinedsoc/hart/lsu/LSUBusAdr[22]} {wallypipelinedsoc/hart/lsu/LSUBusAdr[23]} {wallypipelinedsoc/hart/lsu/LSUBusAdr[24]} {wallypipelinedsoc/hart/lsu/LSUBusAdr[25]} {wallypipelinedsoc/hart/lsu/LSUBusAdr[26]} {wallypipelinedsoc/hart/lsu/LSUBusAdr[27]} {wallypipelinedsoc/hart/lsu/LSUBusAdr[28]} {wallypipelinedsoc/hart/lsu/LSUBusAdr[29]} {wallypipelinedsoc/hart/lsu/LSUBusAdr[30]} {wallypipelinedsoc/hart/lsu/LSUBusAdr[31]} ]]
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create_debug_port u_ila_0 probe
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set_property port_width 6 [get_debug_ports u_ila_0/probe3]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
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@ -142,19 +142,19 @@ connect_debug_port u_ila_0/probe30 [get_nets [list {wallypipelinedsoc/uncore/sdc
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create_debug_port u_ila_0 probe
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set_property port_width 2 [get_debug_ports u_ila_0/probe31]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31]
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connect_debug_port u_ila_0/probe31 [get_nets [list {wallypipelinedsoc/hart/lsu/LsuBusSize[0]} {wallypipelinedsoc/hart/lsu/LsuBusSize[1]} ]]
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connect_debug_port u_ila_0/probe31 [get_nets [list {wallypipelinedsoc/hart/lsu/LSUBusSize[0]} {wallypipelinedsoc/hart/lsu/LSUBusSize[1]} ]]
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create_debug_port u_ila_0 probe
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set_property port_width 1 [get_debug_ports u_ila_0/probe32]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32]
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connect_debug_port u_ila_0/probe32 [get_nets [list wallypipelinedsoc/hart/lsu/LsuBusAck ]]
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connect_debug_port u_ila_0/probe32 [get_nets [list wallypipelinedsoc/hart/lsu/LSUBusAck ]]
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create_debug_port u_ila_0 probe
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set_property port_width 1 [get_debug_ports u_ila_0/probe33]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33]
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connect_debug_port u_ila_0/probe33 [get_nets [list wallypipelinedsoc/hart/lsu/LsuBusRead ]]
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connect_debug_port u_ila_0/probe33 [get_nets [list wallypipelinedsoc/hart/lsu/LSUBusRead ]]
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create_debug_port u_ila_0 probe
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set_property port_width 1 [get_debug_ports u_ila_0/probe34]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34]
|
||||
connect_debug_port u_ila_0/probe34 [get_nets [list wallypipelinedsoc/hart/lsu/LsuBusWrite ]]
|
||||
connect_debug_port u_ila_0/probe34 [get_nets [list wallypipelinedsoc/hart/lsu/LSUBusWrite ]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe35]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35]
|
||||
|
|
@ -340,7 +340,7 @@ connect_debug_port u_ila_0/probe77 [get_nets [list wallypipelinedsoc/hart/hzu/St
|
|||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe78]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe78]
|
||||
connect_debug_port u_ila_0/probe78 [get_nets [list wallypipelinedsoc/hart/hzu/MulDivStallD ]]
|
||||
connect_debug_port u_ila_0/probe78 [get_nets [list wallypipelinedsoc/hart/hzu/MDUStallD ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe79]
|
||||
|
|
@ -355,7 +355,7 @@ connect_debug_port u_ila_0/probe80 [get_nets [list wallypipelinedsoc/hart/hzu/LS
|
|||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe81]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe81]
|
||||
connect_debug_port u_ila_0/probe81 [get_nets [list wallypipelinedsoc/hart/hzu/IfuStallF ]]
|
||||
connect_debug_port u_ila_0/probe81 [get_nets [list wallypipelinedsoc/hart/hzu/IFUStallF ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe82]
|
||||
|
|
@ -452,22 +452,22 @@ connect_debug_port u_ila_0/probe99 [get_nets [list {wallypipelinedsoc/hart/ifu/i
|
|||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 64 [get_debug_ports u_ila_0/probe100]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe100]
|
||||
connect_debug_port u_ila_0/probe100 [get_nets [list {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[0]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[1]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[2]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[3]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[4]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[5]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[6]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[7]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[8]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[9]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[10]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[11]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[12]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[13]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[14]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[15]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[16]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[17]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[18]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[19]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[20]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[21]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[22]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[23]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[24]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[25]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[26]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[27]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[28]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[29]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[30]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[31]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[32]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[33]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[34]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[35]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[36]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[37]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[38]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[39]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[40]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[41]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[42]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[43]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[44]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[45]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[46]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[47]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[48]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[49]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[50]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[51]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[52]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[53]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[54]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[55]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[56]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[57]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[58]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[59]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[60]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[61]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[62]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[63]}]]
|
||||
connect_debug_port u_ila_0/probe100 [get_nets [list {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[0]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[1]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[2]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[3]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[4]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[5]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[6]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[7]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[8]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[9]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[10]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[11]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[12]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[13]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[14]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[15]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[16]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[17]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[18]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[19]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[20]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[21]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[22]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[23]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[24]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[25]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[26]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[27]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[28]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[29]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[30]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[31]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[32]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[33]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[34]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[35]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[36]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[37]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[38]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[39]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[40]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[41]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[42]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[43]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[44]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[45]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[46]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[47]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[48]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[49]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[50]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[51]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[52]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[53]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[54]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[55]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[56]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[57]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[58]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[59]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[60]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[61]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[62]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[63]}]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe101]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe101]
|
||||
connect_debug_port u_ila_0/probe101 [get_nets [list wallypipelinedsoc/hart/ifu/IfuBusAck ]]
|
||||
connect_debug_port u_ila_0/probe101 [get_nets [list wallypipelinedsoc/hart/ifu/IFUBusAck ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 32 [get_debug_ports u_ila_0/probe102]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe102]
|
||||
connect_debug_port u_ila_0/probe102 [get_nets [list {wallypipelinedsoc/hart/ifu/IfuBusAdr[0]} {wallypipelinedsoc/hart/ifu/IfuBusAdr[1]} {wallypipelinedsoc/hart/ifu/IfuBusAdr[2]} {wallypipelinedsoc/hart/ifu/IfuBusAdr[3]} {wallypipelinedsoc/hart/ifu/IfuBusAdr[4]} {wallypipelinedsoc/hart/ifu/IfuBusAdr[5]} {wallypipelinedsoc/hart/ifu/IfuBusAdr[6]} {wallypipelinedsoc/hart/ifu/IfuBusAdr[7]} {wallypipelinedsoc/hart/ifu/IfuBusAdr[8]} {wallypipelinedsoc/hart/ifu/IfuBusAdr[9]} {wallypipelinedsoc/hart/ifu/IfuBusAdr[10]} {wallypipelinedsoc/hart/ifu/IfuBusAdr[11]} {wallypipelinedsoc/hart/ifu/IfuBusAdr[12]} {wallypipelinedsoc/hart/ifu/IfuBusAdr[13]} {wallypipelinedsoc/hart/ifu/IfuBusAdr[14]} {wallypipelinedsoc/hart/ifu/IfuBusAdr[15]} {wallypipelinedsoc/hart/ifu/IfuBusAdr[16]} {wallypipelinedsoc/hart/ifu/IfuBusAdr[17]} {wallypipelinedsoc/hart/ifu/IfuBusAdr[18]} {wallypipelinedsoc/hart/ifu/IfuBusAdr[19]} {wallypipelinedsoc/hart/ifu/IfuBusAdr[20]} {wallypipelinedsoc/hart/ifu/IfuBusAdr[21]} {wallypipelinedsoc/hart/ifu/IfuBusAdr[22]} {wallypipelinedsoc/hart/ifu/IfuBusAdr[23]} {wallypipelinedsoc/hart/ifu/IfuBusAdr[24]} {wallypipelinedsoc/hart/ifu/IfuBusAdr[25]} {wallypipelinedsoc/hart/ifu/IfuBusAdr[26]} {wallypipelinedsoc/hart/ifu/IfuBusAdr[27]} {wallypipelinedsoc/hart/ifu/IfuBusAdr[28]} {wallypipelinedsoc/hart/ifu/IfuBusAdr[29]} {wallypipelinedsoc/hart/ifu/IfuBusAdr[30]} {wallypipelinedsoc/hart/ifu/IfuBusAdr[31]}]]
|
||||
connect_debug_port u_ila_0/probe102 [get_nets [list {wallypipelinedsoc/hart/ifu/IFUBusAdr[0]} {wallypipelinedsoc/hart/ifu/IFUBusAdr[1]} {wallypipelinedsoc/hart/ifu/IFUBusAdr[2]} {wallypipelinedsoc/hart/ifu/IFUBusAdr[3]} {wallypipelinedsoc/hart/ifu/IFUBusAdr[4]} {wallypipelinedsoc/hart/ifu/IFUBusAdr[5]} {wallypipelinedsoc/hart/ifu/IFUBusAdr[6]} {wallypipelinedsoc/hart/ifu/IFUBusAdr[7]} {wallypipelinedsoc/hart/ifu/IFUBusAdr[8]} {wallypipelinedsoc/hart/ifu/IFUBusAdr[9]} {wallypipelinedsoc/hart/ifu/IFUBusAdr[10]} {wallypipelinedsoc/hart/ifu/IFUBusAdr[11]} {wallypipelinedsoc/hart/ifu/IFUBusAdr[12]} {wallypipelinedsoc/hart/ifu/IFUBusAdr[13]} {wallypipelinedsoc/hart/ifu/IFUBusAdr[14]} {wallypipelinedsoc/hart/ifu/IFUBusAdr[15]} {wallypipelinedsoc/hart/ifu/IFUBusAdr[16]} {wallypipelinedsoc/hart/ifu/IFUBusAdr[17]} {wallypipelinedsoc/hart/ifu/IFUBusAdr[18]} {wallypipelinedsoc/hart/ifu/IFUBusAdr[19]} {wallypipelinedsoc/hart/ifu/IFUBusAdr[20]} {wallypipelinedsoc/hart/ifu/IFUBusAdr[21]} {wallypipelinedsoc/hart/ifu/IFUBusAdr[22]} {wallypipelinedsoc/hart/ifu/IFUBusAdr[23]} {wallypipelinedsoc/hart/ifu/IFUBusAdr[24]} {wallypipelinedsoc/hart/ifu/IFUBusAdr[25]} {wallypipelinedsoc/hart/ifu/IFUBusAdr[26]} {wallypipelinedsoc/hart/ifu/IFUBusAdr[27]} {wallypipelinedsoc/hart/ifu/IFUBusAdr[28]} {wallypipelinedsoc/hart/ifu/IFUBusAdr[29]} {wallypipelinedsoc/hart/ifu/IFUBusAdr[30]} {wallypipelinedsoc/hart/ifu/IFUBusAdr[31]}]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe103]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe103]
|
||||
connect_debug_port u_ila_0/probe103 [get_nets [list wallypipelinedsoc/hart/ifu/IfuBusRead ]]
|
||||
connect_debug_port u_ila_0/probe103 [get_nets [list wallypipelinedsoc/hart/ifu/IFUBusRead ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 64 [get_debug_ports u_ila_0/probe104]
|
||||
|
|
|
|||
37
fpga/generator/dcache-miss-evict-dirty-deadlock.tsm
Normal file
37
fpga/generator/dcache-miss-evict-dirty-deadlock.tsm
Normal file
|
|
@ -0,0 +1,37 @@
|
|||
##################################################
|
||||
#
|
||||
# For info on creating trigger state machines:
|
||||
# 1) In the main Vivado menu bar, select
|
||||
# Window > Language Templates
|
||||
# 2) In the Templates window, select
|
||||
# Debug > Trigger State Machine
|
||||
# 3) Refer to the entry 'Info' for an overview
|
||||
# of the trigger state machine language.
|
||||
#
|
||||
# More information can be found in this document:
|
||||
#
|
||||
# Vivado Design Suite User Guide: Programming
|
||||
# and Debugging (UG908)
|
||||
#
|
||||
##################################################
|
||||
state state_reset:
|
||||
if(wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState == 32'h00000003) then
|
||||
reset_counter $counter0;
|
||||
goto state_begin_count;
|
||||
#goto state_trigger;
|
||||
else
|
||||
goto state_reset;
|
||||
endif
|
||||
|
||||
state state_begin_count:
|
||||
if($counter0 == 16'h0164) then
|
||||
goto state_trigger;
|
||||
elseif(wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState == 32'h00000003) then
|
||||
increment_counter $counter0;
|
||||
goto state_begin_count;
|
||||
else
|
||||
goto state_reset;
|
||||
endif
|
||||
|
||||
state state_trigger:
|
||||
trigger;
|
||||
36
fpga/generator/trigger.tsm
Normal file
36
fpga/generator/trigger.tsm
Normal file
|
|
@ -0,0 +1,36 @@
|
|||
##################################################
|
||||
#
|
||||
# For info on creating trigger state machines:
|
||||
# 1) In the main Vivado menu bar, select
|
||||
# Window > Language Templates
|
||||
# 2) In the Templates window, select
|
||||
# Debug > Trigger State Machine
|
||||
# 3) Refer to the entry 'Info' for an overview
|
||||
# of the trigger state machine language.
|
||||
#
|
||||
# More information can be found in this document:
|
||||
#
|
||||
# Vivado Design Suite User Guide: Programming
|
||||
# and Debugging (UG908)
|
||||
#
|
||||
##################################################
|
||||
state state_reset:
|
||||
if(wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState == 32'h00000015) then
|
||||
reset_counter $counter0;
|
||||
goto state_begin_count;
|
||||
else
|
||||
goto state_reset;
|
||||
endif
|
||||
|
||||
state state_begin_count:
|
||||
if($counter0 == 16'h0064) then
|
||||
goto state_trigger;
|
||||
elseif(wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState == 32'h00000015) then
|
||||
increment_counter $counter0;
|
||||
goto state_begin_count;
|
||||
else
|
||||
goto state_reset;
|
||||
endif
|
||||
|
||||
state state_trigger:
|
||||
trigger;
|
||||
|
|
@ -13,9 +13,7 @@ add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/Ret
|
|||
add wave -noupdate -group HDU -expand -group hazards -color Pink /testbench/dut/hart/hzu/TrapM
|
||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD
|
||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/StoreStallD
|
||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/IfuStallF
|
||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LSUStall
|
||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD
|
||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/DivBusyE
|
||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/priv/trap/ExceptionM
|
||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/priv/trap/InstrMisalignedFaultM
|
||||
|
|
@ -173,22 +171,15 @@ add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcBE
|
|||
add wave -noupdate -group icache -color Gold /testbench/dut/hart/ifu/icache/icache/cachefsm/CurrState
|
||||
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/icache/ReadDataWord
|
||||
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/icache/SelAdr
|
||||
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/icache/LsuAdrE
|
||||
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/icache/LsuPAdrM
|
||||
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/icache/RAdr
|
||||
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/icache/PreLsuPAdrM
|
||||
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/icache/CacheHit
|
||||
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/icache/CacheStall
|
||||
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/icache/ReadDataLineSets
|
||||
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/IfuBusAdr
|
||||
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/IfuBusHRDATA
|
||||
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/IfuBusAck
|
||||
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/icache/CacheMemWriteData
|
||||
add wave -noupdate -group icache /testbench/dut/hart/ifu/SpillSupport/SpillDataLine0
|
||||
add wave -noupdate -group AHB -color Gold /testbench/dut/hart/ebu/BusState
|
||||
add wave -noupdate -group AHB /testbench/dut/hart/ebu/NextBusState
|
||||
add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/AtomicMaskedM
|
||||
add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/LsuBusSize
|
||||
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HCLK
|
||||
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HRESETn
|
||||
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HRDATA
|
||||
|
|
@ -214,11 +205,10 @@ add wave -noupdate -expand -group lsu -color Gold /testbench/dut/hart/lsu/MEM_VI
|
|||
add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/SelHPTW
|
||||
add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/InterlockStall
|
||||
add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/LSUStall
|
||||
add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/LsuBusAdr
|
||||
add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/ReadDataM
|
||||
add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/WriteDataM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/hart/lsu/dcache/dcache/cachefsm/CurrState
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/FinalWriteData
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/SRAMLineWriteEnableM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/SRAMWordWriteEnableM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/SRAMWayWriteEnable
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/SRAMWordEnable
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/SelAdr
|
||||
|
|
@ -231,75 +221,73 @@ add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush
|
|||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/hart/lsu/dcache/dcache/VictimTag
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/hart/lsu/dcache/dcache/CacheBusAdr
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/hart/lsu/WordCount
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/hart/lsu/dcache/dcache/CacheableM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/hart/lsu/dcache/dcache/FlushAdr
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/hart/lsu/dcache/dcache/FlushAdrQ
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/hart/lsu/dcache/dcache/FlushWay
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/CacheMemWriteData
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/WayHit
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/IgnoreRequest
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/SetValid}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/SetDirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/DirtyBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/ValidBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/DirtyBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/ValidBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/SetDirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/WriteWordEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/SetValid}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/SetDirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/DirtyBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/ValidBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/SetValid}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/SetDirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/ClearDirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/VDWriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/DirtyBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/ValidBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/dcache/SetValid
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/dcache/ClearValid
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/dcache/SetDirty
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/dcache/ClearDirty
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/SetValid}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/SetDirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/DirtyBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/ValidBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/DirtyBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/ValidBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/SetDirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/WriteWordEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/SetValid}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/SetDirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/DirtyBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/ValidBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/SetValid}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/SetDirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/ClearDirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/VDWriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/DirtyBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/ValidBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/dcache/SetValid
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/dcache/ClearValid
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/dcache/SetDirty
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/dcache/ClearDirty
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/dcache/RAdr
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/WayHit}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/Valid}
|
||||
|
|
@ -323,23 +311,20 @@ add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testb
|
|||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/dcache/VictimWay
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/dcache/VictimDirtyWay
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/dcache/VictimDirty
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/RW
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/LsuAdrE
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/IEUAdrM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/LsuPAdrM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/CacheableM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/FlushCache
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/FinalWriteData
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/ReadDataWord
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/CacheStall
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/RW
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/IEUAdrM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/FlushCache
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/FinalWriteData
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/ReadDataWord
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/CacheStall
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/dcache/WayHit
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/dcache/CacheHit
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/WordCount
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/dcache/CacheBusAdr
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/dcache/CacheFetchLine
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/dcache/CacheWriteLine
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/dcache/CacheBusAck
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/dcache/CacheMemWriteData
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/dcache/CacheBusAdr
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/dcache/CacheFetchLine
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/dcache/CacheWriteLine
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/dcache/CacheBusAck
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/dcache/CacheMemWriteData
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation
|
||||
|
|
@ -476,7 +461,6 @@ add wave -noupdate /testbench/dut/hart/ifu/PCSrcE
|
|||
add wave -noupdate /testbench/dut/hart/ieu/c/BranchTakenE
|
||||
add wave -noupdate /testbench/dut/hart/ieu/c/BranchE
|
||||
add wave -noupdate /testbench/dut/hart/ifu/PCLinkE
|
||||
add wave -noupdate /testbench/dut/hart/lsu/LsuBusSize
|
||||
add wave -noupdate /testbench/dut/hart/ifu/PCF
|
||||
add wave -noupdate /testbench/dut/uncore/uart/uart/u/LSR
|
||||
add wave -noupdate /testbench/dut/uncore/uart/uart/u/DLM
|
||||
|
|
@ -486,22 +470,13 @@ add wave -noupdate /testbench/dut/hart/ifu/BPPredWrongM
|
|||
add wave -noupdate /testbench/dut/hart/ifu/InvalidateICacheM
|
||||
add wave -noupdate -expand -group ifu /testbench/dut/hart/ifu/PCF
|
||||
add wave -noupdate -expand -group ifu /testbench/dut/hart/ifu/PostSpillInstrRawF
|
||||
add wave -noupdate -expand -group ifu /testbench/dut/hart/ifu/IfuStallF
|
||||
add wave -noupdate -expand -group ifu -expand -group {Bus FSM} -color Gold /testbench/dut/hart/ifu/busfsm/BusCurrState
|
||||
add wave -noupdate -expand -group ifu -expand -group {Bus FSM} /testbench/dut/hart/ifu/BusStall
|
||||
add wave -noupdate -expand -group ifu -expand -group {Bus FSM} -color Orange /testbench/dut/hart/ifu/IfuBusRead
|
||||
add wave -noupdate -expand -group ifu -expand -group {Bus FSM} /testbench/dut/hart/ifu/IfuBusAdr
|
||||
add wave -noupdate -expand -group ifu -expand -group {Bus FSM} -color Orange /testbench/dut/hart/ifu/IfuBusAck
|
||||
add wave -noupdate -expand -group ifu -expand -group {Bus FSM} /testbench/dut/hart/ifu/IfuBusHRDATA
|
||||
add wave -noupdate -expand -group ifu -expand -group Spills /testbench/dut/hart/ifu/SpillSupport/Spill
|
||||
add wave -noupdate -expand -group ifu -expand -group Spills -color Gold /testbench/dut/hart/ifu/SpillSupport/CurrState
|
||||
add wave -noupdate /testbench/dut/hart/lsu/LsuBusAdr
|
||||
add wave -noupdate /testbench/dut/hart/lsu/LsuBusWrite
|
||||
add wave -noupdate /testbench/dut/hart/lsu/LsuBusHWDATA
|
||||
add wave -noupdate /testbench/dut/hart/lsu/LsuBusAck
|
||||
add wave -noupdate /testbench/dut/hart/lsu/dcache/dcache/VictimTag
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 6} {5187387 ns} 1} {{Cursor 5} {5144964 ns} 0}
|
||||
WaveRestoreCursors {{Cursor 6} {5187387 ns} 1} {{Cursor 5} {88705641 ns} 0}
|
||||
quietly wave cursor active 2
|
||||
configure wave -namecolwidth 250
|
||||
configure wave -valuecolwidth 314
|
||||
|
|
@ -517,4 +492,4 @@ configure wave -griddelta 40
|
|||
configure wave -timeline 0
|
||||
configure wave -timelineunits ns
|
||||
update
|
||||
WaveRestoreZoom {5144901 ns} {5145101 ns}
|
||||
WaveRestoreZoom {88705577 ns} {88705705 ns}
|
||||
|
|
|
|||
|
|
@ -33,15 +33,14 @@
|
|||
|
||||
module interlockfsm
|
||||
(input logic clk,
|
||||
input logic reset,
|
||||
input logic AnyCPUReqM,
|
||||
input logic ITLBMissF,
|
||||
input logic ITLBWriteF,
|
||||
input logic DTLBMissM,
|
||||
input logic DTLBWriteM,
|
||||
input logic ExceptionM,
|
||||
input logic PendingInterruptM,
|
||||
input logic DCacheStall,
|
||||
input logic reset,
|
||||
input logic AnyCPUReqM,
|
||||
input logic ITLBMissF,
|
||||
input logic ITLBWriteF,
|
||||
input logic DTLBMissM,
|
||||
input logic DTLBWriteM,
|
||||
input logic TrapM,
|
||||
input logic DCacheStall,
|
||||
|
||||
output logic InterlockStall,
|
||||
output logic SelReplayCPURequest,
|
||||
|
|
@ -111,8 +110,8 @@ module interlockfsm
|
|||
assign SelReplayCPURequest = (InterlockNextState == STATE_T0_REPLAY);
|
||||
assign SelHPTW = (InterlockCurrState == STATE_T3_DTLB_MISS) | (InterlockCurrState == STATE_T4_ITLB_MISS) |
|
||||
(InterlockCurrState == STATE_T5_ITLB_MISS) | (InterlockCurrState == STATE_T7_DITLB_MISS);
|
||||
assign IgnoreRequest = (InterlockCurrState == STATE_T0_READY & (ITLBMissF | DTLBMissM | ExceptionM | PendingInterruptM)) |
|
||||
assign IgnoreRequest = (InterlockCurrState == STATE_T0_READY & (ITLBMissF | DTLBMissM | TrapM)) |
|
||||
((InterlockCurrState == STATE_T0_REPLAY)
|
||||
& (ExceptionM | PendingInterruptM));
|
||||
& (TrapM));
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -44,8 +44,7 @@ module lsu
|
|||
input logic [2:0] Funct3M,
|
||||
input logic [6:0] Funct7M,
|
||||
input logic [1:0] AtomicM,
|
||||
input logic ExceptionM,
|
||||
input logic PendingInterruptM,
|
||||
input logic TrapM,
|
||||
input logic FlushDCacheM,
|
||||
output logic CommittedM,
|
||||
output logic SquashSCW,
|
||||
|
|
@ -136,13 +135,13 @@ module lsu
|
|||
assign AnyCPUReqM = (|MemRWM) | (|AtomicM);
|
||||
|
||||
interlockfsm interlockfsm (.clk, .reset, .AnyCPUReqM, .ITLBMissF, .ITLBWriteF,
|
||||
.DTLBMissM, .DTLBWriteM, .ExceptionM, .PendingInterruptM, .DCacheStall,
|
||||
.DTLBMissM, .DTLBWriteM, .TrapM, .DCacheStall,
|
||||
.InterlockStall, .SelReplayCPURequest, .SelHPTW,
|
||||
.IgnoreRequest);
|
||||
|
||||
hptw hptw(.clk, .reset, .SATP_REGW, .PCF, .IEUAdrM,
|
||||
.ITLBMissF(ITLBMissF & ~PendingInterruptM),
|
||||
.DTLBMissM(DTLBMissM & ~PendingInterruptM),
|
||||
.ITLBMissF(ITLBMissF & ~TrapM),
|
||||
.DTLBMissM(DTLBMissM & ~TrapM),
|
||||
.MemRWM, .PTE, .PageType, .ITLBWriteF, .DTLBWriteM,
|
||||
.HPTWReadPTE(ReadDataM),
|
||||
.DCacheStall, .HPTWAdr, .HPTWRead, .HPTWSize, .AnyCPUReqM);
|
||||
|
|
|
|||
|
|
@ -244,7 +244,7 @@ module wallypipelinedhart (
|
|||
.FlushW,
|
||||
// CPU interface
|
||||
.MemRWM, .Funct3M, .Funct7M(InstrM[31:25]),
|
||||
.AtomicM, .ExceptionM, .PendingInterruptM,
|
||||
.AtomicM, .TrapM,
|
||||
.CommittedM, .DCacheMiss, .DCacheAccess,
|
||||
.SquashSCW,
|
||||
//.DataMisalignedM(DataMisalignedM),
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue