Initial rv32imc lockstep and fcov config files

config/rv32imc/coverage.svh

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+// coverage.svh
+// David_Harris@hmc.edu 7 September 2024
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+
+// This file is needed in the config subdirectory for each config supporting coverage.
+// It defines which extensions are enabled for that config.
+
+// Define XLEN, used in covergroups
+`define XLEN32
+
+// Define relevant addresses
+`define ACCESS_FAULT_ADDRESS 32'h0000
+`define CLINT_BASE 64'h02000000
+
+// Unprivileged extensions
+`define I_COVERAGE
+`define M_COVERAGE
+`define ZCA_COVERAGE
+`define ZICSR_COVERAGE
+// TODO: Should include ZIFENCEI when that is added to cvw-arch-verif
+
+// Privileged extensions
+`define ZICSRM_COVERAGE
+`define ZICSRS_COVERAGE
+`define ZICSRU_COVERAGE
+`define EXCEPTIONSM_COVERAGE
+`define EXCEPTIONSS_COVERAGE
+`define EXCEPTIONSU_COVERAGE
+`define EXCEPTIONSZC_COVERAGE
+`define ZICNTRU_COVERAGE
+`define ZICNTRS_COVERAGE
+`define ZICNTRM_COVERAGE
+`define INTERRUPTSU_COVERAGE
+`define INTERRUPTSM_COVERAGE
+`define INTERRUPTSS_COVERAGE

config/rv32imc/imperas.ic

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+# imperas.ic
+# Initialization file for ImperasDV lock step simulation
+# David_Harris@hmc.edu 15 August 2024
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+
+#--mpdconsole
+#--gdbconsole
+#--showoverrides
+#--showcommands
+
+# Core settings
+--variant RV32IMC
+--override cpu/priv_version=1.12
+--override cpu/user_version=20191213
+# arch
+--override cpu/mimpid=0x100
+--override cpu/mvendorid=0x602
+--override cpu/marchid=0x24
+--override refRoot/cpu/tvec_align=64
+# --override refRoot/cpu/envcfg_mask=1   # dh 1/26/24 this should be deleted when ImperasDV is updated to allow envcfg.FIOM to be written
+
+# No virtual memory
+--override cpu/Sv_modes=1
+
+--override cpu/tval_ii_code=T
+
+# mstatus.FS read-only 0
+--override cpu/mstatus_FS_zero=T
+
+# Little endian only
+--override cpu/endianFixed=T
+
+# For code coverage, don't produce pseudoinstructions
+--override no_pseudo_inst=T
+
+# Show "c." with compressed instructions
+--override show_c_prefix=T
+
+# mcause and scause only have 4 lsbs of code and 1 msb of interrupt flag
+--override cpu/ecode_mask=0x8000000F  # for RV32
+# --override cpu/ecode_mask=0x800000000000000F # for RV64
+
+# Debug mode not yet supported
+--override cpu/debug_mode=none
+
+--override cpu/Smepmp_version=none
+--override cpu/Smmpm=none
+#--override cpu/Zicfilp=F
+--override cpu/trigger_num=0 # disable CSRs 7a0-7a8
+
+--override cpu/reset_address=0x80000000
+
+--override cpu/unaligned=F  # Zicclsm (should be true)
+--override cpu/wfi_is_nop=T
+--override cpu/misa_Extensions_mask=0x0 # MISA not writable
+
+# Enable SVADU hardware update of A/D bits when menvcfg.ADUE=1
+#--override cpu/updatePTEA=F
+#--override cpu/updatePTED=F
+
+--override cpu/PMP_registers=0
+--override cpu/PMP_undefined=T
+
+# PMA Settings
+# 'r': read access allowed
+# 'w': write access allowed
+# 'x': execute access allowed
+# 'a': aligned access required
+# 'A': atomic instructions NOT allowed (actually USER1 privilege needed)
+# 'P': push/pop instructions NOT allowed (actually USER2 privilege needed)
+# '1': 1-byte accesses allowed
+# '2': 2-byte accesses allowed
+# '4': 4-byte accesses allowed
+# '8': 8-byte accesses allowed
+# '-', space: ignored (use for input string formatting).
+#
+# SVxx Memory 0x0000000000 0x7FFFFFFFFF
+#
+--callcommand refRoot/cpu/setPMA -lo 0x0000000000 -hi 0xFFFFFFFFFFFFFFFFFF -attributes " ---a-- ---- " # All memory inaccessible unless defined otherwise
+--callcommand refRoot/cpu/setPMA -lo 0x0000000000 -hi 0x7FFFFFFFFF -attributes " ---a-- ---- " # INITIAL
+--callcommand refRoot/cpu/setPMA -lo 0x0000001000 -hi 0x0000001FFF -attributes " r-x-A- 1248 " # BOOTROM
+--callcommand refRoot/cpu/setPMA -lo 0x0000012100 -hi 0x000001211F -attributes " rw-aA- --48 " # SDC
+--callcommand refRoot/cpu/setPMA -lo 0x0002000000 -hi 0x000200FFFF -attributes " rw-aA- 1248 " # CLINT
+--callcommand refRoot/cpu/setPMA -lo 0x000C000000 -hi 0x000FFFFFFF -attributes " rw-aA- --4- " # PLIC
+--callcommand refRoot/cpu/setPMA -lo 0x0010000000 -hi 0x0010000007 -attributes " rw-aA- 1--- " # UART0
+--callcommand refRoot/cpu/setPMA -lo 0x0010060000 -hi 0x00100600FF -attributes " rw-aA- --4- " # GPIO
+--callcommand refRoot/cpu/setPMA -lo 0x0010040000 -hi 0x0010040FFF -attributes " rw-aA- --4- " # SPI
+--callcommand refRoot/cpu/setPMA -lo 0x0080000000 -hi 0x008FFFFFFF -attributes " rwx--- 1248 " # UNCORE_RAM
+
+# Enable the Imperas instruction coverage
+#-extlib    refRoot/cpu/cv=imperas.com/intercept/riscvInstructionCoverage/1.0
+#-override  refRoot/cpu/cv/cover=basic
+#-override  refRoot/cpu/cv/extensions=RV32I
+
+# Store simulator output to logfile
+--output imperas.log