mirror of
https://github.com/openhwgroup/cvw.git
synced 2025-04-23 05:17:20 -04:00
added support for new version of riscof and arch tests, now supports tests that can be compiled for both rv32 and rv64
This commit is contained in:
Daniel Torres
parent
9421b77613
commit
8dcb794bbb
4 changed files with 178 additions and 177 deletions
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@ -1057,176 +1057,176 @@ string imperas32f[] = '{
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string arch64d[] = '{
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`RISCVARCHTEST,
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"rv64i_m/D/src/d_fadd_b10-01.S",
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"rv64i_m/D/src/d_fadd_b1-01.S",
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"rv64i_m/D/src/d_fadd_b11-01.S",
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"rv64i_m/D/src/d_fadd_b12-01.S",
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"rv64i_m/D/src/d_fadd_b13-01.S",
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"rv64i_m/D/src/d_fadd_b2-01.S",
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"rv64i_m/D/src/d_fadd_b3-01.S",
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"rv64i_m/D/src/d_fadd_b4-01.S",
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"rv64i_m/D/src/d_fadd_b5-01.S",
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"rv64i_m/D/src/d_fadd_b7-01.S",
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"rv64i_m/D/src/d_fadd_b8-01.S",
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"rv64i_m/D/src/d_fclass_b1-01.S",
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"rv64i_m/D/src/d_fcvt.d.l_b25-01.S",
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"rv64i_m/D/src/d_fcvt.d.l_b26-01.S",
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"rv64i_m/D/src/d_fcvt.d.lu_b25-01.S",
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"rv64i_m/D/src/d_fcvt.d.lu_b26-01.S",
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"rv64i_m/D/src/d_fcvt.d.s_b1-01.S",
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"rv64i_m/D/src/d_fcvt.d.s_b22-01.S",
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"rv64i_m/D/src/d_fcvt.d.s_b23-01.S",
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"rv64i_m/D/src/d_fcvt.d.s_b24-01.S",
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"rv64i_m/D/src/d_fcvt.d.s_b27-01.S",
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"rv64i_m/D/src/d_fcvt.d.s_b28-01.S",
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"rv64i_m/D/src/d_fcvt.d.s_b29-01.S",
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"rv64i_m/D/src/d_fcvt.d.w_b25-01.S",
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"rv64i_m/D/src/d_fcvt.d.w_b26-01.S",
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"rv64i_m/D/src/d_fcvt.d.wu_b25-01.S",
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"rv64i_m/D/src/d_fcvt.d.wu_b26-01.S",
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"rv64i_m/D/src/d_fcvt.l.d_b1-01.S",
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"rv64i_m/D/src/d_fcvt.l.d_b22-01.S",
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"rv64i_m/D/src/d_fcvt.l.d_b23-01.S",
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"rv64i_m/D/src/d_fcvt.l.d_b24-01.S",
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"rv64i_m/D/src/d_fcvt.l.d_b27-01.S",
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"rv64i_m/D/src/d_fcvt.l.d_b28-01.S",
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"rv64i_m/D/src/d_fcvt.l.d_b29-01.S",
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"rv64i_m/D/src/d_fcvt.lu.d_b1-01.S",
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"rv64i_m/D/src/d_fcvt.lu.d_b22-01.S",
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"rv64i_m/D/src/d_fcvt.lu.d_b23-01.S",
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"rv64i_m/D/src/d_fcvt.lu.d_b24-01.S",
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"rv64i_m/D/src/d_fcvt.lu.d_b27-01.S",
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"rv64i_m/D/src/d_fcvt.lu.d_b28-01.S",
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"rv64i_m/D/src/d_fcvt.lu.d_b29-01.S",
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"rv64i_m/D/src/d_fcvt.s.d_b1-01.S",
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"rv64i_m/D/src/d_fcvt.s.d_b22-01.S",
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"rv64i_m/D/src/d_fcvt.s.d_b23-01.S",
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"rv64i_m/D/src/d_fcvt.s.d_b24-01.S",
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"rv64i_m/D/src/d_fcvt.s.d_b27-01.S",
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"rv64i_m/D/src/d_fcvt.s.d_b28-01.S",
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"rv64i_m/D/src/d_fcvt.s.d_b29-01.S",
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"rv64i_m/D/src/d_fcvt.w.d_b1-01.S",
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"rv64i_m/D/src/d_fcvt.w.d_b22-01.S",
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"rv64i_m/D/src/d_fcvt.w.d_b23-01.S",
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"rv64i_m/D/src/d_fcvt.w.d_b24-01.S",
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"rv64i_m/D/src/d_fcvt.w.d_b27-01.S",
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"rv64i_m/D/src/d_fcvt.w.d_b28-01.S",
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"rv64i_m/D/src/d_fcvt.w.d_b29-01.S",
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"rv64i_m/D/src/d_fcvt.wu.d_b1-01.S",
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"rv64i_m/D/src/d_fcvt.wu.d_b22-01.S",
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"rv64i_m/D/src/d_fcvt.wu.d_b23-01.S",
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"rv64i_m/D/src/d_fcvt.wu.d_b24-01.S",
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"rv64i_m/D/src/d_fcvt.wu.d_b27-01.S",
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"rv64i_m/D/src/d_fcvt.wu.d_b28-01.S",
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"rv64i_m/D/src/d_fcvt.wu.d_b29-01.S",
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"rv64i_m/D/src/d_fdiv_b1-01.S",
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"rv64i_m/D/src/d_fdiv_b20-01.S",
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"rv64i_m/D/src/d_fdiv_b2-01.S",
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"rv64i_m/D/src/d_fdiv_b21-01.S",
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"rv64i_m/D/src/d_fdiv_b3-01.S",
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"rv64i_m/D/src/d_fdiv_b4-01.S",
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"rv64i_m/D/src/d_fdiv_b5-01.S",
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"rv64i_m/D/src/d_fdiv_b6-01.S",
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"rv64i_m/D/src/d_fdiv_b7-01.S",
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"rv64i_m/D/src/d_fdiv_b8-01.S",
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"rv64i_m/D/src/d_fdiv_b9-01.S",
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"rv64i_m/D/src/d_feq_b1-01.S",
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"rv64i_m/D/src/d_feq_b19-01.S",
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"rv64i_m/D/src/d_fle_b1-01.S",
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"rv64i_m/D/src/d_fle_b19-01.S",
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"rv64i_m/D/src/d_flt_b1-01.S",
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"rv64i_m/D/src/d_flt_b19-01.S",
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"rv64i_m/D/src/d_fld-align-01.S",
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"rv64i_m/D/src/d_fsd-align-01.S",
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"rv64i_m/D/src/d_fmadd_b14-01.S",
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"rv64i_m/D/src/d_fmadd_b16-01.S",
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"rv64i_m/D/src/d_fmadd_b17-01.S",
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"rv64i_m/D/src/d_fmadd_b18-01.S",
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"rv64i_m/D/src/d_fmadd_b2-01.S",
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"rv64i_m/D/src/d_fmadd_b3-01.S",
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"rv64i_m/D/src/d_fmadd_b4-01.S",
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"rv64i_m/D/src/d_fmadd_b5-01.S",
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"rv64i_m/D/src/d_fmadd_b6-01.S",
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"rv64i_m/D/src/d_fmadd_b7-01.S",
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"rv64i_m/D/src/d_fmadd_b8-01.S",
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"rv64i_m/D/src/d_fmax_b1-01.S",
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"rv64i_m/D/src/d_fmax_b19-01.S",
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"rv64i_m/D/src/d_fmin_b1-01.S",
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"rv64i_m/D/src/d_fmin_b19-01.S",
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"rv64i_m/D/src/d_fmsub_b14-01.S",
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"rv64i_m/D/src/d_fmsub_b16-01.S",
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"rv64i_m/D/src/d_fmsub_b17-01.S",
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"rv64i_m/D/src/d_fmsub_b18-01.S",
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"rv64i_m/D/src/d_fmsub_b2-01.S",
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"rv64i_m/D/src/d_fmsub_b3-01.S",
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"rv64i_m/D/src/d_fmsub_b4-01.S",
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"rv64i_m/D/src/d_fmsub_b5-01.S",
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"rv64i_m/D/src/d_fmsub_b6-01.S",
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"rv64i_m/D/src/d_fmsub_b7-01.S",
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"rv64i_m/D/src/d_fmsub_b8-01.S",
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"rv64i_m/D/src/d_fmul_b1-01.S",
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"rv64i_m/D/src/d_fmul_b2-01.S",
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"rv64i_m/D/src/d_fmul_b3-01.S",
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"rv64i_m/D/src/d_fmul_b4-01.S",
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"rv64i_m/D/src/d_fmul_b5-01.S",
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"rv64i_m/D/src/d_fmul_b6-01.S",
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"rv64i_m/D/src/d_fmul_b7-01.S",
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"rv64i_m/D/src/d_fmul_b8-01.S",
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"rv64i_m/D/src/d_fmul_b9-01.S",
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"rv64i_m/D/src/d_fmv.d.x_b25-01.S",
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"rv64i_m/D/src/d_fmv.d.x_b26-01.S",
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"rv64i_m/D/src/d_fmv.x.d_b1-01.S",
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"rv64i_m/D/src/d_fmv.x.d_b22-01.S",
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"rv64i_m/D/src/d_fmv.x.d_b23-01.S",
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"rv64i_m/D/src/d_fmv.x.d_b24-01.S",
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"rv64i_m/D/src/d_fmv.x.d_b27-01.S",
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"rv64i_m/D/src/d_fmv.x.d_b28-01.S",
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"rv64i_m/D/src/d_fmv.x.d_b29-01.S",
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"rv64i_m/D/src/d_fnmadd_b14-01.S",
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"rv64i_m/D/src/d_fnmadd_b16-01.S",
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"rv64i_m/D/src/d_fnmadd_b17-01.S",
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"rv64i_m/D/src/d_fnmadd_b18-01.S",
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"rv64i_m/D/src/d_fnmadd_b2-01.S",
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"rv64i_m/D/src/d_fnmadd_b3-01.S",
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"rv64i_m/D/src/d_fnmadd_b4-01.S",
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"rv64i_m/D/src/d_fnmadd_b5-01.S",
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"rv64i_m/D/src/d_fnmadd_b6-01.S",
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"rv64i_m/D/src/d_fnmadd_b7-01.S",
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"rv64i_m/D/src/d_fnmadd_b8-01.S",
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"rv64i_m/D/src/d_fnmsub_b14-01.S",
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"rv64i_m/D/src/d_fnmsub_b16-01.S",
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"rv64i_m/D/src/d_fnmsub_b17-01.S",
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"rv64i_m/D/src/d_fnmsub_b18-01.S",
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"rv64i_m/D/src/d_fnmsub_b2-01.S",
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"rv64i_m/D/src/d_fnmsub_b3-01.S",
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"rv64i_m/D/src/d_fnmsub_b4-01.S",
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"rv64i_m/D/src/d_fnmsub_b5-01.S",
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"rv64i_m/D/src/d_fnmsub_b6-01.S",
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"rv64i_m/D/src/d_fnmsub_b7-01.S",
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"rv64i_m/D/src/d_fnmsub_b8-01.S",
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"rv64i_m/D/src/d_fsgnj_b1-01.S",
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"rv64i_m/D/src/d_fsgnjn_b1-01.S",
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"rv64i_m/D/src/d_fsgnjx_b1-01.S",
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// "rv64i_m/D/src/d_fsqrt_b1-01.S",
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// "rv64i_m/D/src/d_fsqrt_b20-01.S",
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// "rv64i_m/D/src/d_fsqrt_b2-01.S",
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// "rv64i_m/D/src/d_fsqrt_b3-01.S",
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// "rv64i_m/D/src/d_fsqrt_b4-01.S",
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// "rv64i_m/D/src/d_fsqrt_b5-01.S",
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// "rv64i_m/D/src/d_fsqrt_b7-01.S",
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// "rv64i_m/D/src/d_fsqrt_b8-01.S",
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// "rv64i_m/D/src/d_fsqrt_b9-01.S",
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"rv64i_m/D/src/d_fsub_b10-01.S",
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"rv64i_m/D/src/d_fsub_b1-01.S",
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"rv64i_m/D/src/d_fsub_b11-01.S",
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"rv64i_m/D/src/d_fsub_b12-01.S",
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"rv64i_m/D/src/d_fsub_b13-01.S",
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"rv64i_m/D/src/d_fsub_b2-01.S",
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"rv64i_m/D/src/d_fsub_b3-01.S",
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"rv64i_m/D/src/d_fsub_b4-01.S",
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"rv64i_m/D/src/d_fsub_b5-01.S",
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"rv64i_m/D/src/d_fsub_b7-01.S",
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"rv64i_m/D/src/d_fsub_b8-01.S"
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"rv64i_m/D/src/fadd.d_b10-01.S",
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"rv64i_m/D/src/fadd.d_b1-01.S",
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"rv64i_m/D/src/fadd.d_b11-01.S",
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"rv64i_m/D/src/fadd.d_b12-01.S",
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"rv64i_m/D/src/fadd.d_b13-01.S",
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"rv64i_m/D/src/fadd.d_b2-01.S",
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"rv64i_m/D/src/fadd.d_b3-01.S",
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"rv64i_m/D/src/fadd.d_b4-01.S",
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"rv64i_m/D/src/fadd.d_b5-01.S",
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"rv64i_m/D/src/fadd.d_b7-01.S",
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"rv64i_m/D/src/fadd.d_b8-01.S",
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"rv64i_m/D/src/fclass.d_b1-01.S",
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"rv64i_m/D/src/fcvt.d.l_b25-01.S",
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"rv64i_m/D/src/fcvt.d.l_b26-01.S",
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"rv64i_m/D/src/fcvt.d.lu_b25-01.S",
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"rv64i_m/D/src/fcvt.d.lu_b26-01.S",
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"rv64i_m/D/src/fcvt.d.s_b1-01.S",
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"rv64i_m/D/src/fcvt.d.s_b22-01.S",
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"rv64i_m/D/src/fcvt.d.s_b23-01.S",
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"rv64i_m/D/src/fcvt.d.s_b24-01.S",
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"rv64i_m/D/src/fcvt.d.s_b27-01.S",
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"rv64i_m/D/src/fcvt.d.s_b28-01.S",
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"rv64i_m/D/src/fcvt.d.s_b29-01.S",
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"rv64i_m/D/src/fcvt.d.w_b25-01.S",
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"rv64i_m/D/src/fcvt.d.w_b26-01.S",
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"rv64i_m/D/src/fcvt.d.wu_b25-01.S",
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"rv64i_m/D/src/fcvt.d.wu_b26-01.S",
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"rv64i_m/D/src/fcvt.l.d_b1-01.S",
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"rv64i_m/D/src/fcvt.l.d_b22-01.S",
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"rv64i_m/D/src/fcvt.l.d_b23-01.S",
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"rv64i_m/D/src/fcvt.l.d_b24-01.S",
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"rv64i_m/D/src/fcvt.l.d_b27-01.S",
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"rv64i_m/D/src/fcvt.l.d_b28-01.S",
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"rv64i_m/D/src/fcvt.l.d_b29-01.S",
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"rv64i_m/D/src/fcvt.lu.d_b1-01.S",
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"rv64i_m/D/src/fcvt.lu.d_b22-01.S",
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"rv64i_m/D/src/fcvt.lu.d_b23-01.S",
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"rv64i_m/D/src/fcvt.lu.d_b24-01.S",
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"rv64i_m/D/src/fcvt.lu.d_b27-01.S",
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"rv64i_m/D/src/fcvt.lu.d_b28-01.S",
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"rv64i_m/D/src/fcvt.lu.d_b29-01.S",
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"rv64i_m/D/src/fcvt.s.d_b1-01.S",
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"rv64i_m/D/src/fcvt.s.d_b22-01.S",
|
||||
"rv64i_m/D/src/fcvt.s.d_b23-01.S",
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||||
"rv64i_m/D/src/fcvt.s.d_b24-01.S",
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"rv64i_m/D/src/fcvt.s.d_b27-01.S",
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"rv64i_m/D/src/fcvt.s.d_b28-01.S",
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"rv64i_m/D/src/fcvt.s.d_b29-01.S",
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"rv64i_m/D/src/fcvt.w.d_b1-01.S",
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"rv64i_m/D/src/fcvt.w.d_b22-01.S",
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"rv64i_m/D/src/fcvt.w.d_b23-01.S",
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"rv64i_m/D/src/fcvt.w.d_b24-01.S",
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"rv64i_m/D/src/fcvt.w.d_b27-01.S",
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"rv64i_m/D/src/fcvt.w.d_b28-01.S",
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"rv64i_m/D/src/fcvt.w.d_b29-01.S",
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"rv64i_m/D/src/fcvt.wu.d_b1-01.S",
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"rv64i_m/D/src/fcvt.wu.d_b22-01.S",
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"rv64i_m/D/src/fcvt.wu.d_b23-01.S",
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"rv64i_m/D/src/fcvt.wu.d_b24-01.S",
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"rv64i_m/D/src/fcvt.wu.d_b27-01.S",
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"rv64i_m/D/src/fcvt.wu.d_b28-01.S",
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"rv64i_m/D/src/fcvt.wu.d_b29-01.S",
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"rv64i_m/D/src/fdiv.d_b1-01.S",
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"rv64i_m/D/src/fdiv.d_b20-01.S",
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"rv64i_m/D/src/fdiv.d_b2-01.S",
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"rv64i_m/D/src/fdiv.d_b21-01.S",
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"rv64i_m/D/src/fdiv.d_b3-01.S",
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"rv64i_m/D/src/fdiv.d_b4-01.S",
|
||||
"rv64i_m/D/src/fdiv.d_b5-01.S",
|
||||
"rv64i_m/D/src/fdiv.d_b6-01.S",
|
||||
"rv64i_m/D/src/fdiv.d_b7-01.S",
|
||||
"rv64i_m/D/src/fdiv.d_b8-01.S",
|
||||
"rv64i_m/D/src/fdiv.d_b9-01.S",
|
||||
"rv64i_m/D/src/feq.d_b1-01.S",
|
||||
"rv64i_m/D/src/feq.d_b19-01.S",
|
||||
"rv64i_m/D/src/fle.d_b1-01.S",
|
||||
"rv64i_m/D/src/fle.d_b19-01.S",
|
||||
"rv64i_m/D/src/flt.d_b1-01.S",
|
||||
"rv64i_m/D/src/flt.d_b19-01.S",
|
||||
// "rv64i_m/D/src/fld-align-01.S", //missing right now from top of tree, should be returned when it comes back
|
||||
// "rv64i_m/D/src/fsd-align-01.S", //https://github.com/riscv-non-isa/riscv-arch-test/issues/266
|
||||
"rv64i_m/D/src/fmadd.d_b14-01.S",
|
||||
"rv64i_m/D/src/fmadd.d_b16-01.S",
|
||||
"rv64i_m/D/src/fmadd.d_b17-01.S",
|
||||
"rv64i_m/D/src/fmadd.d_b18-01.S",
|
||||
"rv64i_m/D/src/fmadd.d_b2-01.S",
|
||||
"rv64i_m/D/src/fmadd.d_b3-01.S",
|
||||
"rv64i_m/D/src/fmadd.d_b4-01.S",
|
||||
"rv64i_m/D/src/fmadd.d_b5-01.S",
|
||||
"rv64i_m/D/src/fmadd.d_b6-01.S",
|
||||
"rv64i_m/D/src/fmadd.d_b7-01.S",
|
||||
"rv64i_m/D/src/fmadd.d_b8-01.S",
|
||||
"rv64i_m/D/src/fmax.d_b1-01.S",
|
||||
"rv64i_m/D/src/fmax.d_b19-01.S",
|
||||
"rv64i_m/D/src/fmin.d_b1-01.S",
|
||||
"rv64i_m/D/src/fmin.d_b19-01.S",
|
||||
"rv64i_m/D/src/fmsub.d_b14-01.S",
|
||||
"rv64i_m/D/src/fmsub.d_b16-01.S",
|
||||
"rv64i_m/D/src/fmsub.d_b17-01.S",
|
||||
"rv64i_m/D/src/fmsub.d_b18-01.S",
|
||||
"rv64i_m/D/src/fmsub.d_b2-01.S",
|
||||
"rv64i_m/D/src/fmsub.d_b3-01.S",
|
||||
"rv64i_m/D/src/fmsub.d_b4-01.S",
|
||||
"rv64i_m/D/src/fmsub.d_b5-01.S",
|
||||
"rv64i_m/D/src/fmsub.d_b6-01.S",
|
||||
"rv64i_m/D/src/fmsub.d_b7-01.S",
|
||||
"rv64i_m/D/src/fmsub.d_b8-01.S",
|
||||
"rv64i_m/D/src/fmul.d_b1-01.S",
|
||||
"rv64i_m/D/src/fmul.d_b2-01.S",
|
||||
"rv64i_m/D/src/fmul.d_b3-01.S",
|
||||
"rv64i_m/D/src/fmul.d_b4-01.S",
|
||||
"rv64i_m/D/src/fmul.d_b5-01.S",
|
||||
"rv64i_m/D/src/fmul.d_b6-01.S",
|
||||
"rv64i_m/D/src/fmul.d_b7-01.S",
|
||||
"rv64i_m/D/src/fmul.d_b8-01.S",
|
||||
"rv64i_m/D/src/fmul.d_b9-01.S",
|
||||
"rv64i_m/D/src/fmv.d.x_b25-01.S",
|
||||
"rv64i_m/D/src/fmv.d.x_b26-01.S",
|
||||
"rv64i_m/D/src/fmv.x.d_b1-01.S",
|
||||
"rv64i_m/D/src/fmv.x.d_b22-01.S",
|
||||
"rv64i_m/D/src/fmv.x.d_b23-01.S",
|
||||
"rv64i_m/D/src/fmv.x.d_b24-01.S",
|
||||
"rv64i_m/D/src/fmv.x.d_b27-01.S",
|
||||
"rv64i_m/D/src/fmv.x.d_b28-01.S",
|
||||
"rv64i_m/D/src/fmv.x.d_b29-01.S",
|
||||
"rv64i_m/D/src/fnmadd.d_b14-01.S",
|
||||
"rv64i_m/D/src/fnmadd.d_b16-01.S",
|
||||
"rv64i_m/D/src/fnmadd.d_b17-01.S",
|
||||
"rv64i_m/D/src/fnmadd.d_b18-01.S",
|
||||
"rv64i_m/D/src/fnmadd.d_b2-01.S",
|
||||
"rv64i_m/D/src/fnmadd.d_b3-01.S",
|
||||
"rv64i_m/D/src/fnmadd.d_b4-01.S",
|
||||
"rv64i_m/D/src/fnmadd.d_b5-01.S",
|
||||
"rv64i_m/D/src/fnmadd.d_b6-01.S",
|
||||
"rv64i_m/D/src/fnmadd.d_b7-01.S",
|
||||
"rv64i_m/D/src/fnmadd.d_b8-01.S",
|
||||
"rv64i_m/D/src/fnmsub.d_b14-01.S",
|
||||
"rv64i_m/D/src/fnmsub.d_b16-01.S",
|
||||
"rv64i_m/D/src/fnmsub.d_b17-01.S",
|
||||
"rv64i_m/D/src/fnmsub.d_b18-01.S",
|
||||
"rv64i_m/D/src/fnmsub.d_b2-01.S",
|
||||
"rv64i_m/D/src/fnmsub.d_b3-01.S",
|
||||
"rv64i_m/D/src/fnmsub.d_b4-01.S",
|
||||
"rv64i_m/D/src/fnmsub.d_b5-01.S",
|
||||
"rv64i_m/D/src/fnmsub.d_b6-01.S",
|
||||
"rv64i_m/D/src/fnmsub.d_b7-01.S",
|
||||
"rv64i_m/D/src/fnmsub.d_b8-01.S",
|
||||
"rv64i_m/D/src/fsgnj.d_b1-01.S",
|
||||
"rv64i_m/D/src/fsgnjn.d_b1-01.S",
|
||||
"rv64i_m/D/src/fsgnjx.d_b1-01.S",
|
||||
// "rv64i_m/D/src/fsqrt.d_b1-01.S",
|
||||
// "rv64i_m/D/src/fsqrt.d_b20-01.S",
|
||||
// "rv64i_m/D/src/fsqrt.d_b2-01.S",
|
||||
// "rv64i_m/D/src/fsqrt.d_b3-01.S",
|
||||
// "rv64i_m/D/src/fsqrt.d_b4-01.S",
|
||||
// "rv64i_m/D/src/fsqrt.d_b5-01.S",
|
||||
// "rv64i_m/D/src/fsqrt.d_b7-01.S",
|
||||
// "rv64i_m/D/src/fsqrt.d_b8-01.S",
|
||||
// "rv64i_m/D/src/fsqrt.d_b9-01.S",
|
||||
"rv64i_m/D/src/fssub.d_b10-01.S",
|
||||
"rv64i_m/D/src/fssub.d_b1-01.S",
|
||||
"rv64i_m/D/src/fssub.d_b11-01.S",
|
||||
"rv64i_m/D/src/fssub.d_b12-01.S",
|
||||
"rv64i_m/D/src/fssub.d_b13-01.S",
|
||||
"rv64i_m/D/src/fssub.d_b2-01.S",
|
||||
"rv64i_m/D/src/fssub.d_b3-01.S",
|
||||
"rv64i_m/D/src/fssub.d_b4-01.S",
|
||||
"rv64i_m/D/src/fssub.d_b5-01.S",
|
||||
"rv64i_m/D/src/fssub.d_b7-01.S",
|
||||
"rv64i_m/D/src/fssub.d_b8-01.S"
|
||||
};
|
||||
|
||||
string arch32priv[] = '{
|
||||
|
|
@ -1310,7 +1310,7 @@ string imperas32f[] = '{
|
|||
"rv32i_m/F/src/fle_b19-01.S",
|
||||
"rv32i_m/F/src/flt_b1-01.S",
|
||||
"rv32i_m/F/src/flt_b19-01.S",
|
||||
"rv32i_m/F/src/flw-align-01.S",
|
||||
// "rv32i_m/F/src/flw-align-01.S",
|
||||
"rv32i_m/F/src/fmadd_b1-01.S",
|
||||
"rv32i_m/F/src/fmadd_b14-01.S",
|
||||
// "rv32i_m/F/src/fmadd_b15-01.S",
|
||||
|
|
@ -1407,8 +1407,8 @@ string imperas32f[] = '{
|
|||
"rv32i_m/F/src/fsub_b4-01.S",
|
||||
"rv32i_m/F/src/fsub_b5-01.S",
|
||||
"rv32i_m/F/src/fsub_b7-01.S",
|
||||
"rv32i_m/F/src/fsub_b8-01.S",
|
||||
"rv32i_m/F/src/fsw-align-01.S"
|
||||
"rv32i_m/F/src/fsub_b8-01.S"
|
||||
// "rv32i_m/F/src/fsw-align-01.S"
|
||||
};
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -26,10 +26,11 @@ fsd_fld_tempfix:
|
|||
build_arch: fsd_fld_tempfix
|
||||
riscof run --work-dir=$(work_dir) --config=config$(XLEN).ini --suite=$(arch_dir)/riscv-test-suite/ --env=$(arch_dir)/riscv-test-suite/env --no-browser
|
||||
rm -rf $(arch_workdir)/rv$(XLEN)i_m
|
||||
mv -f $(work_dir)/rv$(XLEN)i_m $(arch_workdir)/
|
||||
rsync -a $(work_dir)/rv32i_m/ $(arch_workdir)/rv$(XLEN)i_m/ || echo "error suppressed"
|
||||
rsync -a $(work_dir)/rv64i_m/ $(arch_workdir)/rv$(XLEN)i_m/ || echo "error suppressed"
|
||||
|
||||
build_wally:
|
||||
riscof --verbose debug run --work-dir=$(work_dir) --config=config$(XLEN).ini --suite=$(wally_dir)/riscv-test-suite/ --env=$(wally_dir)/riscv-test-suite/env --no-browser --no-dut-run
|
||||
riscof --verbose debug run --work-dir=$(work_dir) --config=config$(XLEN).ini --suite=$(wally_dir)/riscv-test-suite/ --env=$(wally_dir)/riscv-test-suite/env --no-browser --no-dut-run 2>&1 | tee log.txt
|
||||
rm -rf $(wally_workdir)/rv$(XLEN)i_m
|
||||
mv -f $(work_dir)/rv$(XLEN)i_m $(wally_workdir)/
|
||||
|
||||
|
|
|
|||
|
|
@ -94,7 +94,7 @@ class sail_cSim(pluginTemplate):
|
|||
|
||||
execute = "@cd "+testentry['work_dir']+";"
|
||||
|
||||
cmd = self.compile_cmd.format(testentry['isa'].lower(), self.xlen) + ' ' + test + ' -o ' + elf
|
||||
cmd = self.compile_cmd.format(testentry['isa'].lower().replace('zicsr', ' ', 1), self.xlen) + ' ' + test + ' -o ' + elf
|
||||
compile_cmd = cmd + ' -D' + " -D".join(testentry['macros'])
|
||||
execute+=compile_cmd+";"
|
||||
|
||||
|
|
|
|||
|
|
@ -151,7 +151,7 @@ class spike(pluginTemplate):
|
|||
|
||||
# substitute all variables in the compile command that we created in the initialize
|
||||
# function
|
||||
cmd = self.compile_cmd.format(testentry['isa'].lower(), self.xlen, test, elf, compile_macros)
|
||||
cmd = self.compile_cmd.format(testentry['isa'].lower().replace('zicsr', ' ', 2), self.xlen, test, elf, compile_macros)
|
||||
|
||||
# if the user wants to disable running the tests and only compile the tests, then
|
||||
# the "else" clause is executed below assigning the sim command to simple no action
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue