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Moved fpu to temporary location to fix compile and cleaned up interface formatting

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This commit is contained in:
David Harris 2021-02-01 23:44:41 -05:00
parent f143518b23
commit 92bf1674b4
105 changed files with 182 additions and 36242 deletions
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2
wally-pipelined/src/dmem/dmem.sv
View file

@ -28,6 +28,8 @@
`include "wally-config.vh"
module dmem (
input logic clk, reset,
//
input logic [1:0] MemRWM,
output logic [1:0] MemRWdcuoutM,
output logic DataMisalignedM,

25
wally-pipelined/src/ebu/subwordread.sv
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@ -26,17 +26,16 @@
`include "wally-config.vh"
module subwordread (
// input logic [1:0] MemRWM,
// from AHB Interface
input logic [`XLEN-1:0] HRDATA,
input logic [31:0] HADDR,
input logic UnsignedLoadM,
input logic [2:0] HSIZE,
// to ifu/dmems
output logic [`XLEN-1:0] HRDATAMasked
// input logic [`XLEN-1:0] HWDATA,
// output logic [`XLEN-1:0] HWDATA
);
logic [7:0] ByteM; // *** declare locally to generate as either 4 or 8 bits
logic [7:0] ByteM;
logic [15:0] HalfwordM;
generate
@ -75,12 +74,12 @@ module subwordread (
always_comb
case({UnsignedLoadM, HSIZE[1:0]})
3'b000: HRDATAMasked = {{56{ByteM[7]}}, ByteM}; // lb
3'b001: HRDATAMasked = {{48{HalfwordM[15]}}, HalfwordM[15:0]}; // lh
3'b001: HRDATAMasked = {{48{HalfwordM[15]}}, HalfwordM[15:0]}; // lh
3'b010: HRDATAMasked = {{32{WordM[31]}}, WordM[31:0]}; // lw
3'b011: HRDATAMasked = HRDATA; // ld
3'b100: HRDATAMasked = {56'b0, ByteM[7:0]}; // lbu
3'b101: HRDATAMasked = {48'b0, HalfwordM[15:0]}; // lhu
3'b110: HRDATAMasked = {32'b0, WordM[31:0]}; // lwu
3'b011: HRDATAMasked = HRDATA; // ld
3'b100: HRDATAMasked = {56'b0, ByteM[7:0]}; // lbu
3'b101: HRDATAMasked = {48'b0, HalfwordM[15:0]}; // lhu
3'b110: HRDATAMasked = {32'b0, WordM[31:0]}; // lwu
default: HRDATAMasked = HRDATA; // Shouldn't happen
endcase
end else begin // 32-bit
@ -104,10 +103,10 @@ module subwordread (
always_comb
case({UnsignedLoadM, HSIZE[1:0]})
3'b000: HRDATAMasked = {{24{ByteM[7]}}, ByteM}; // lb
3'b001: HRDATAMasked = {{16{HalfwordM[15]}}, HalfwordM[15:0]}; // lh
3'b010: HRDATAMasked = HRDATA; // lw
3'b100: HRDATAMasked = {24'b0, ByteM[7:0]}; // lbu
3'b101: HRDATAMasked = {16'b0, HalfwordM[15:0]}; // lhu
3'b001: HRDATAMasked = {{16{HalfwordM[15]}}, HalfwordM[15:0]}; // lh
3'b010: HRDATAMasked = HRDATA; // lw
3'b100: HRDATAMasked = {24'b0, ByteM[7:0]}; // lbu
3'b101: HRDATAMasked = {16'b0, HalfwordM[15:0]}; // lhu
default: HRDATAMasked = HRDATA;
endcase
end

312
wally-pipelined/src/fpucmp/fpcomp.sv
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@ -1,312 +0,0 @@
//
// File name : fpcomp.v
// Title : Floating-Point Comparator
// project : FPU
// Library : fpcomp
// Author(s) : James E. Stine
// Purpose : definition of main unit to floating-point comparator
// notes :
//
// Copyright Oklahoma State University
//
// Floating Point Comparator (Algorithm)
//
// 1.) Performs sign-extension if the inputs are 32-bit integers.
// 2.) Perform a magnitude comparison on the lower 63 bits of the inputs
// 3.) Check for special cases (+0=-0, unordered, and infinite values)
// and correct for sign bits
//
// This module takes 64-bits inputs op1 and op2, VSS, and VDD
// signals, and a 2-bit signal Sel that indicates the type of
// operands being compared as indicated below.
// Sel Description
// 00 double precision numbers
// 01 single precision numbers
// 10 half precision numbers
// 11 (unused)
//
// The comparator produces a 2-bit signal FCC, which
// indicates the result of the comparison:
//
// fcc decscription
// 00 A = B
// 01 A < B
// 10 A > B
// 11 A and B are unordered (i.e., A or B is NaN)
//
// It also produces an invalid operation flag, which is one
// if either of the input operands is a signaling NaN per 754
module fpcomp (Invalid, FCC, op1, op2, Sel);
input logic [63:0] op1;
input logic [63:0] op2;
input logic [1:0] Sel;
output logic Invalid; // Invalid Operation
output logic [1:0] FCC; // Condition Codes
supply1 VDD;
supply0 VSS;
logic LT; // magnitude op1 < magnitude op2
logic EQ; // magnitude op1 = magnitude op2
// Perform magnitude comparison between the 63 least signficant bits
// of the input operands. Only LT and EQ are returned, since GT can
// be determined from these values.
magcompare64b magcomp2 (LT, EQ, {~op1[63], op1[62:0]}, {~op2[63], op2[62:0]});
// Determine final values based on output of magnitude comparison,
// sign bits, and special case testing.
exception_cmp exc1 (Invalid, FCC, op1, op2, LT, EQ, Sel);
endmodule // fpcomp
module magcompare2b (LT, GT, A, B);
input logic [1:0] A;
input logic [1:0] B;
output logic LT;
output logic GT;
// Determine if A < B using a minimized sum-of-products expression
assign LT = ~A[1]&B[1] | ~A[1]&~A[0]&B[0] | ~A[0]&B[1]&B[0];
// Determine if A > B using a minimized sum-of-products expression
assign GT = A[1]&~B[1] | A[1]&A[0]&~B[0] | A[0]&~B[1]&~B[0];
endmodule // magcompare2b
// 2-bit magnitude comparator
// This module compares two 2-bit values A and B. LT is '1' if A < B
// and GT is '1'if A > B. LT and GT are both '0' if A = B. However,
// this version actually incorporates don't cares into the equation to
// simplify the optimization
module magcompare2c (LT, GT, A, B);
input logic [1:0] A;
input logic [1:0] B;
output logic LT;
output logic GT;
assign LT = B[1] | (!A[1]&B[0]);
assign GT = A[1] | (!B[1]&A[0]);
endmodule // magcompare2b
// This module compares two 64-bit values A and B. LT is '1' if A < B
// and EQ is '1'if A = B. LT and GT are both '0' if A > B.
// This structure was modified so
// that it only does a strict magnitdude comparison, and only
// returns flags for less than (LT) and eqaual to (EQ). It uses a tree
// of 63 2-bit magnitude comparators, followed by one OR gates.
//
// J. E. Stine and M. J. Schulte, "A combined two's complement and
// floating-point comparator," 2005 IEEE International Symposium on
// Circuits and Systems, Kobe, 2005, pp. 89-92 Vol. 1.
// doi: 10.1109/ISCAS.2005.1464531
module magcompare64b (LT, EQ, A, B);
input logic [63:0] A;
input logic [63:0] B;
logic [31:0] s;
logic [31:0] t;
logic [15:0] u;
logic [15:0] v;
logic [7:0] w;
logic [7:0] x;
logic [3:0] y;
logic [3:0] z;
logic [1:0] a;
logic [1:0] b;
logic GT;
output logic LT;
output logic EQ;
magcompare2b mag1(s[0], t[0], A[1:0], B[1:0]);
magcompare2b mag2(s[1], t[1], A[3:2], B[3:2]);
magcompare2b mag3(s[2], t[2], A[5:4], B[5:4]);
magcompare2b mag4(s[3], t[3], A[7:6], B[7:6]);
magcompare2b mag5(s[4], t[4], A[9:8], B[9:8]);
magcompare2b mag6(s[5], t[5], A[11:10], B[11:10]);
magcompare2b mag7(s[6], t[6], A[13:12], B[13:12]);
magcompare2b mag8(s[7], t[7], A[15:14], B[15:14]);
magcompare2b mag9(s[8], t[8], A[17:16], B[17:16]);
magcompare2b magA(s[9], t[9], A[19:18], B[19:18]);
magcompare2b magB(s[10], t[10], A[21:20], B[21:20]);
magcompare2b magC(s[11], t[11], A[23:22], B[23:22]);
magcompare2b magD(s[12], t[12], A[25:24], B[25:24]);
magcompare2b magE(s[13], t[13], A[27:26], B[27:26]);
magcompare2b magF(s[14], t[14], A[29:28], B[29:28]);
magcompare2b mag10(s[15], t[15], A[31:30], B[31:30]);
magcompare2b mag11(s[16], t[16], A[33:32], B[33:32]);
magcompare2b mag12(s[17], t[17], A[35:34], B[35:34]);
magcompare2b mag13(s[18], t[18], A[37:36], B[37:36]);
magcompare2b mag14(s[19], t[19], A[39:38], B[39:38]);
magcompare2b mag15(s[20], t[20], A[41:40], B[41:40]);
magcompare2b mag16(s[21], t[21], A[43:42], B[43:42]);
magcompare2b mag17(s[22], t[22], A[45:44], B[45:44]);
magcompare2b mag18(s[23], t[23], A[47:46], B[47:46]);
magcompare2b mag19(s[24], t[24], A[49:48], B[49:48]);
magcompare2b mag1A(s[25], t[25], A[51:50], B[51:50]);
magcompare2b mag1B(s[26], t[26], A[53:52], B[53:52]);
magcompare2b mag1C(s[27], t[27], A[55:54], B[55:54]);
magcompare2b mag1D(s[28], t[28], A[57:56], B[57:56]);
magcompare2b mag1E(s[29], t[29], A[59:58], B[59:58]);
magcompare2b mag1F(s[30], t[30], A[61:60], B[61:60]);
magcompare2b mag20(s[31], t[31], A[63:62], B[63:62]);
magcompare2c mag21(u[0], v[0], t[1:0], s[1:0]);
magcompare2c mag22(u[1], v[1], t[3:2], s[3:2]);
magcompare2c mag23(u[2], v[2], t[5:4], s[5:4]);
magcompare2c mag24(u[3], v[3], t[7:6], s[7:6]);
magcompare2c mag25(u[4], v[4], t[9:8], s[9:8]);
magcompare2c mag26(u[5], v[5], t[11:10], s[11:10]);
magcompare2c mag27(u[6], v[6], t[13:12], s[13:12]);
magcompare2c mag28(u[7], v[7], t[15:14], s[15:14]);
magcompare2c mag29(u[8], v[8], t[17:16], s[17:16]);
magcompare2c mag2A(u[9], v[9], t[19:18], s[19:18]);
magcompare2c mag2B(u[10], v[10], t[21:20], s[21:20]);
magcompare2c mag2C(u[11], v[11], t[23:22], s[23:22]);
magcompare2c mag2D(u[12], v[12], t[25:24], s[25:24]);
magcompare2c mag2E(u[13], v[13], t[27:26], s[27:26]);
magcompare2c mag2F(u[14], v[14], t[29:28], s[29:28]);
magcompare2c mag30(u[15], v[15], t[31:30], s[31:30]);
magcompare2c mag31(w[0], x[0], v[1:0], u[1:0]);
magcompare2c mag32(w[1], x[1], v[3:2], u[3:2]);
magcompare2c mag33(w[2], x[2], v[5:4], u[5:4]);
magcompare2c mag34(w[3], x[3], v[7:6], u[7:6]);
magcompare2c mag35(w[4], x[4], v[9:8], u[9:8]);
magcompare2c mag36(w[5], x[5], v[11:10], u[11:10]);
magcompare2c mag37(w[6], x[6], v[13:12], u[13:12]);
magcompare2c mag38(w[7], x[7], v[15:14], u[15:14]);
magcompare2c mag39(y[0], z[0], x[1:0], w[1:0]);
magcompare2c mag3A(y[1], z[1], x[3:2], w[3:2]);
magcompare2c mag3B(y[2], z[2], x[5:4], w[5:4]);
magcompare2c mag3C(y[3], z[3], x[7:6], w[7:6]);
magcompare2c mag3D(a[0], b[0], z[1:0], y[1:0]);
magcompare2c mag3E(a[1], b[1], z[3:2], y[3:2]);
magcompare2c mag3F(LT, GT, b[1:0], a[1:0]);
assign EQ = ~(LT | GT);
endmodule // magcompare64b
// This module takes 64-bits inputs A and B, two magnitude comparison
// flags LT_mag and EQ_mag, and a 2-bit signal Sel that indicates the type of
// operands being compared as indicated below.
// Sel Description
// 00 double precision numbers
// 01 single precision numbers
// 10 half precision numbers
// 11 bfloat precision numbers
//
// The comparator produces a 2-bit signal fcc, which
// indicates the result of the comparison as follows:
// fcc decscription
// 00 A = B
// 01 A < B
// 10 A > B
// 11 A and B are unordered (i.e., A or B is NaN)
// It also produces a invalid operation flag, which is one
// if either of the input operands is a signaling NaN.
module exception_cmp (invalid, fcc, A, B, LT_mag, EQ_mag, Sel);
input logic [63:0] A;
input logic [63:0] B;
input logic LT_mag;
input logic EQ_mag;
input logic [1:0] Sel;
output logic invalid;
output logic [1:0] fcc;
logic dp;
logic sp;
logic hp;
logic Azero;
logic Bzero;
logic ANaN;
logic BNaN;
logic ASNaN;
logic BSNaN;
logic UO;
logic GT;
logic LT;
logic EQ;
logic [62:0] sixtythreezeros = 63'h0;
// dp is one if the comparison is being performed on a 64-bit
// sp is one if the comparison is being performed on a 32-bit
// hp is one if the comparison is being performed on a 16-bit
assign dp = !Sel[1]&!Sel[0];
assign sp = !Sel[1]&Sel[0];
assign hp = Sel[1]&!Sel[0];
// Test if A or B is NaN.
assign ANaN = (A[62]&A[61]&A[60]&A[59]&A[58]) &
((sp&A[57]&A[56]&A[55]&(A[54]|A[53])) |
(dp&A[57]&A[56]&A[55]&A[54]&A[53]&A[52]&(A[51]|A[50])) |
(hp&(A[57]|A[56])));
assign BNaN = (B[62]&B[61]&B[60]&B[59]&B[58]) &
((sp&B[57]&B[56]&B[55]&(B[54]|B[53])) |
(dp&B[57]&B[56]&B[55]&B[54]&B[53]&B[52]&(B[51]|B[50])) |
(hp&(B[57]|B[56])));
// Values are unordered if ((A is NaN) OR (B is NaN)) AND (a floating
// point comparison is being performed.
assign UO = (ANaN | BNaN);
// Test if A or B is a signaling NaN.
assign ASNaN = ANaN & (sp&~A[53] | dp&~A[50] | hp&~A[56]);
assign BSNaN = BNaN & (sp&~B[53] | dp&~B[50] | hp&~B[56]);
// If either A or B is a signaling NaN the "Invalid Operation"
// exception flag is set to one; otherwise it is zero.
assign invalid = (ASNaN | BSNaN);
// Test if A is +0 or -0 when viewed as a floating point number (i.e,
// the 63 least siginficant bits of A are zero).
// Depending on how this synthesizes, it may work better to replace
// this with assign Azero = ~(A[62] | A[61] | ... | A[0])
assign Azero = (A[62:0] == sixtythreezeros);
assign Bzero = (B[62:0] == sixtythreezeros);
// A and B are equal if (their magnitudes are equal) AND ((their signs are
// equal) or (their magnitudes are zero AND they are floating point
// numbers)). Also, A and B are not equal if they are unordered.
assign EQ = (EQ_mag | (Azero&Bzero)) & (~UO);
// A is less than B if (A is negative and B is posiive) OR
// (A and B are positive and the magnitude of A is less than
// the magnitude of B) or (A and B are negative integers and
// the magnitude of A is less than the magnitude of B) or
// (A and B are negative floating point numbers and
// the magnitude of A is greater than the magnitude of B).
// Also, A is not less than B if A and B are equal or unordered.
assign LT = ((~LT_mag & A[63] & B[63]) |
(LT_mag & ~(A[63] & B[63])))&~EQ&~UO;
// A is greater than B when LT, EQ, and UO are are false.
assign GT = ~(LT | EQ | UO);
// Note: it may be possible to optimize the setting of fcc
// a little more, but it is probably not worth the effort.
// Set the bits of fcc based on LT, GT, EQ, and UO
assign fcc[0] = LT | UO;
assign fcc[1] = GT | UO;
endmodule // exception_cmp

60
wally-pipelined/src/fpucmp/test_f16.do
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@ -1,60 +0,0 @@
# Copyright 1991-2016 Mentor Graphics Corporation
#
# Modification by Oklahoma State University
# Use with Testbench
# James Stine, 2008
# Go Cowboys!!!!!!
#
# All Rights Reserved.
#
# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION
# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
# Use this run.do file to run this example.
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
# do run.do
# or, to run from a shell, type the following at the shell prompt:
# vsim -do run.do -c
# (omit the "-c" to see the GUI while running from the shell)
onbreak {resume}
# create library
if [file exists work] {
vdel -all
}
vlib work
# compile source files
vlog "fpcomp.sv" "test_f16.sv"
# start and run simulation
vsim -voptargs=+acc work.tb
view wave
#vcd file test.vcd
#vcd add -r /tb/dut/*
-- display input and output signals as hexidecimal values
# Diplays All Signals recursively
add wave -hex -r /tb/*
-- Set Wave Output Items
TreeUpdate [SetDefaultTree]
WaveRestoreZoom {0 ps} {75 ns}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
-- Run the Simulation
-- 42,133 vectors,
run 591300ns
quit

68
wally-pipelined/src/fpucmp/test_f16.sv
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@ -1,68 +0,0 @@
`timescale 1ns/1ps
module tb ();
logic [63:0] op1;
logic [63:0] op2;
logic [1:0] Sel;
logic Invalid;
logic [1:0] FCC;
logic clk;
logic [3:0] yexpected;
logic reset;
logic [63:0] vectornum, errors; // bookkeeping variables
logic [139:0] testvectors[50000:0]; // array of testvectors
logic [7:0] flags_expected;
integer handle3;
integer desc3;
// instantiate device under test
fpcomp dut (Invalid, FCC, op1, op2, Sel);
always
begin
clk = 1; #5; clk = 0; #5;
end
initial
begin
handle3 = $fopen("test_f16.out");
desc3 = handle3;
$readmemh("./cmp_f16.tv", testvectors);
vectornum = 0; errors = 0;
reset = 1; #27; reset = 0;
end
always @(posedge clk)
begin
desc3 = handle3;
#0 Sel = 2'b10;
#1; {op1, op2, yexpected, flags_expected} = testvectors[vectornum];
end
// check results on falling edge of clk
always @(negedge clk)
if (~reset)
begin // skip during reset
if (FCC !== yexpected[3:0])
begin
errors = errors + 1;
$display("Error %4d: inputs = %h %h", errors, op1, op2);
$display(" outputs = %h (%h expected)", FCC, yexpected[3:0]);
end
$fdisplay(desc3, "%h_%h_%b_%b", op1, op2, FCC, Invalid);
vectornum = vectornum + 1;
if (testvectors[vectornum] === 140'hx)
begin
$display("%d tests completed with %d errors",
vectornum, errors);
$finish;
end
end // if (~reset)
endmodule // tb

60
wally-pipelined/src/fpucmp/test_f32.do
View file

@ -1,60 +0,0 @@
# Copyright 1991-2016 Mentor Graphics Corporation
#
# Modification by Oklahoma State University
# Use with Testbench
# James Stine, 2008
# Go Cowboys!!!!!!
#
# All Rights Reserved.
#
# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION
# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
# Use this run.do file to run this example.
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
# do run.do
# or, to run from a shell, type the following at the shell prompt:
# vsim -do run.do -c
# (omit the "-c" to see the GUI while running from the shell)
onbreak {resume}
# create library
if [file exists work] {
vdel -all
}
vlib work
# compile source files
vlog "fpcomp.sv" "test_f32.sv"
# start and run simulation
vsim -voptargs=+acc work.tb
view wave
#vcd file test.vcd
#vcd add -r /tb/dut/*
-- display input and output signals as hexidecimal values
# Diplays All Signals recursively
add wave -hex -r /tb/*
-- Set Wave Output Items
TreeUpdate [SetDefaultTree]
WaveRestoreZoom {0 ps} {75 ns}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
-- Run the Simulation
-- 39,337 vectors,
run 540000ns
quit

68
wally-pipelined/src/fpucmp/test_f32.sv
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@ -1,68 +0,0 @@
`timescale 1ns/1ps
module tb ();
logic [63:0] op1;
logic [63:0] op2;
logic [1:0] Sel;
logic Invalid;
logic [1:0] FCC;
logic clk;
logic [3:0] yexpected;
logic reset;
logic [63:0] vectornum, errors; // bookkeeping variables
logic [139:0] testvectors[50000:0]; // array of testvectors
logic [7:0] flags_expected;
integer handle3;
integer desc3;
// instantiate device under test
fpcomp dut (Invalid, FCC, op1, op2, Sel);
always
begin
clk = 1; #5; clk = 0; #5;
end
initial
begin
handle3 = $fopen("test_f32.out");
desc3 = handle3;
$readmemh("./cmp_f32.tv", testvectors);
vectornum = 0; errors = 0;
reset = 1; #27; reset = 0;
end
always @(posedge clk)
begin
desc3 = handle3;
#0 Sel = 2'b01;
#1; {op1, op2, yexpected, flags_expected} = testvectors[vectornum];
end
// check results on falling edge of clk
always @(negedge clk)
if (~reset)
begin // skip during reset
if (FCC !== yexpected[3:0])
begin
errors = errors + 1;
$display("Error %4d: inputs = %h %h", errors, op1, op2);
$display(" outputs = %h (%h expected)", FCC, yexpected[3:0]);
end
$fdisplay(desc3, "%h_%h_%b_%b", op1, op2, FCC, Invalid);
vectornum = vectornum + 1;
if (testvectors[vectornum] === 140'hx)
begin
$display("%d tests completed with %d errors",
vectornum, errors);
$finish;
end
end // if (~reset)
endmodule // tb

60
wally-pipelined/src/fpucmp/test_f64.do
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@ -1,60 +0,0 @@
# Copyright 1991-2016 Mentor Graphics Corporation
#
# Modification by Oklahoma State University
# Use with Testbench
# James Stine, 2008
# Go Cowboys!!!!!!
#
# All Rights Reserved.
#
# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION
# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
# Use this run.do file to run this example.
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
# do run.do
# or, to run from a shell, type the following at the shell prompt:
# vsim -do run.do -c
# (omit the "-c" to see the GUI while running from the shell)
onbreak {resume}
# create library
if [file exists work] {
vdel -all
}
vlib work
# compile source files
vlog "fpcomp.sv" "test_f64.sv"
# start and run simulation
vsim -voptargs=+acc work.tb
view wave
#vcd file test.vcd
#vcd add -r /tb/dut/*
-- display input and output signals as hexidecimal values
# Diplays All Signals recursively
add wave -hex -r /tb/*
-- Set Wave Output Items
TreeUpdate [SetDefaultTree]
WaveRestoreZoom {0 ps} {75 ns}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
-- Run the Simulation
-- 39,052 vectors, 390,565ns
run 545000ns
quit

68
wally-pipelined/src/fpucmp/test_f64.sv
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@ -1,68 +0,0 @@
`timescale 1ns/1ps
module tb ();
logic [63:0] op1;
logic [63:0] op2;
logic [1:0] Sel;
logic Invalid;
logic [1:0] FCC;
logic clk;
logic [3:0] yexpected;
logic reset;
logic [63:0] vectornum, errors; // bookkeeping variables
logic [139:0] testvectors[50000:0]; // array of testvectors
logic [7:0] flags_expected;
integer handle3;
integer desc3;
// instantiate device under test
fpcomp dut (Invalid, FCC, op1, op2, Sel);
always
begin
clk = 1; #5; clk = 0; #5;
end
initial
begin
handle3 = $fopen("test_f64.out");
desc3 = handle3;
$readmemh("./cmp_f64.tv", testvectors);
vectornum = 0; errors = 0;
reset = 1; #27; reset = 0;
end
always @(posedge clk)
begin
desc3 = handle3;
#0 Sel = 2'b00;
#1; {op1, op2, yexpected, flags_expected} = testvectors[vectornum];
end
// check results on falling edge of clk
always @(negedge clk)
if (~reset)
begin // skip during reset
if (FCC !== yexpected[3:0])
begin
errors = errors + 1;
$display("Error %4d: inputs = %h %h", errors, op1, op2);
$display(" outputs = %h (%h expected)", FCC, yexpected[3:0]);
end
$fdisplay(desc3, "%h_%h_%b_%b", op1, op2, FCC, Invalid);
vectornum = vectornum + 1;
if (testvectors[vectornum] === 140'hx)
begin
$display("%d tests completed with %d errors",
vectornum, errors);
$finish;
end
end // if (~reset)
endmodule // tb

60
wally-pipelined/src/fpucmp/test_vector.do
View file

@ -1,60 +0,0 @@
# Copyright 1991-2016 Mentor Graphics Corporation
#
# Modification by Oklahoma State University
# Use with Testbench
# James Stine, 2008
# Go Cowboys!!!!!!
#
# All Rights Reserved.
#
# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION
# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
# Use this run.do file to run this example.
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
# do run.do
# or, to run from a shell, type the following at the shell prompt:
# vsim -do run.do -c
# (omit the "-c" to see the GUI while running from the shell)
onbreak {resume}
# create library
if [file exists work] {
vdel -all
}
vlib work
# compile source files
vlog "fpcomp.sv" "test_vector.sv"
# start and run simulation
vsim -voptargs=+acc work.tb
view wave
#vcd file test.vcd
#vcd add -r /tb/dut/*
-- display input and output signals as hexidecimal values
# Diplays All Signals recursively
add wave -hex -r /tb/*
-- Set Wave Output Items
TreeUpdate [SetDefaultTree]
WaveRestoreZoom {0 ps} {75 ns}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
-- Run the Simulation
-- 39,052 vectors, 390,565ns
run 100ns
quit

74
wally-pipelined/src/fpucmp/test_vector.sv
View file

@ -1,74 +0,0 @@
`timescale 1ns/1ps
module tb ();
logic [63:0] op1;
logic [63:0] op2;
logic [1:0] Sel;
logic Invalid;
logic [1:0] FCC;
logic clk;
logic [3:0] yexpected;
logic reset;
logic [63:0] vectornum, errors; // bookkeeping variables
logic [139:0] testvectors[50000:0]; // array of testvectors
logic [7:0] flags_expected;
integer handle3;
integer desc3;
// instantiate device under test
fpcomp dut (Invalid, FCC, op1, op2, Sel);
always
begin
clk = 1; #5; clk = 0; #5;
end
initial
begin
handle3 = $fopen("test_vector.out");
desc3 = handle3;
$readmemh("./test_vector.tv", testvectors);
vectornum = 0; errors = 0;
reset = 1; #27; reset = 0;
end
always @(posedge clk)
begin
desc3 = handle3;
#0 Sel = 2'b10;
#1; {op1, op2, yexpected, flags_expected} = testvectors[vectornum];
end
// check results on falling edge of clk
always @(negedge clk)
if (~reset)
begin // skip during reset
if (testvectors[vectornum] === 140'bx)
begin
$display("%d tests completed with %d errors",
vectornum, errors);
$finish;
end
if (FCC !== yexpected[3:0])
begin
errors = errors + 1;
$display("Error %4d: inputs = %h %h", errors, op1, op2);
$display(" outputs = %h (%h expected)", FCC, yexpected[3:0]);
end
$fdisplay(desc3, "%h_%h_%b_%b", op1, op2, FCC, Invalid);
vectornum = vectornum + 1;
if (testvectors[vectornum] === 140'hx)
begin
$display("%d tests completed with %d errors",
vectornum, errors);
$finish;
end
end // if (~reset)
endmodule // tb

1
wally-pipelined/src/fpucmp/test_vector.tv
View file

@ -1 +0,0 @@
B0B1FFF7FFFFFFFE_7FFC000000000000_3_10

620
wally-pipelined/src/fpudivsqrt/bk128.v
View file

@ -1,620 +0,0 @@
// Brent-Kung Carry-save Prefix Adder
module bk128 (cout, sum, a, b, cin);
input [127:0] a, b;
input cin;
output [127:0] sum;
output cout;
wire [128:0] p,g,t;
wire [127:0] c;
// pre-computation
assign p={a^b,1'b0};
assign g={a&b, cin};
assign t[1]=p[1];
assign t[2]=p[2];
assign t[3]=p[3]^g[2];
assign t[4]=p[4];
assign t[5]=p[5]^g[4];
assign t[6]=p[6];
assign t[7]=p[7]^g[6];
assign t[8]=p[8];
assign t[9]=p[9]^g[8];
assign t[10]=p[10];
assign t[11]=p[11]^g[10];
assign t[12]=p[12];
assign t[13]=p[13]^g[12];
assign t[14]=p[14];
assign t[15]=p[15]^g[14];
assign t[16]=p[16];
assign t[17]=p[17]^g[16];
assign t[18]=p[18];
assign t[19]=p[19]^g[18];
assign t[20]=p[20];
assign t[21]=p[21]^g[20];
assign t[22]=p[22];
assign t[23]=p[23]^g[22];
assign t[24]=p[24];
assign t[25]=p[25]^g[24];
assign t[26]=p[26];
assign t[27]=p[27]^g[26];
assign t[28]=p[28];
assign t[29]=p[29]^g[28];
assign t[30]=p[30];
assign t[31]=p[31]^g[30];
assign t[32]=p[32];
assign t[33]=p[33]^g[32];
assign t[34]=p[34];
assign t[35]=p[35]^g[34];
assign t[36]=p[36];
assign t[37]=p[37]^g[36];
assign t[38]=p[38];
assign t[39]=p[39]^g[38];
assign t[40]=p[40];
assign t[41]=p[41]^g[40];
assign t[42]=p[42];
assign t[43]=p[43]^g[42];
assign t[44]=p[44];
assign t[45]=p[45]^g[44];
assign t[46]=p[46];
assign t[47]=p[47]^g[46];
assign t[48]=p[48];
assign t[49]=p[49]^g[48];
assign t[50]=p[50];
assign t[51]=p[51]^g[50];
assign t[52]=p[52];
assign t[53]=p[53]^g[52];
assign t[54]=p[54];
assign t[55]=p[55]^g[54];
assign t[56]=p[56];
assign t[57]=p[57]^g[56];
assign t[58]=p[58];
assign t[59]=p[59]^g[58];
assign t[60]=p[60];
assign t[61]=p[61]^g[60];
assign t[62]=p[62];
assign t[63]=p[63]^g[62];
assign t[64]=p[64];
assign t[65]=p[65]^g[64];
assign t[66]=p[66];
assign t[67]=p[67]^g[66];
assign t[68]=p[68];
assign t[69]=p[69]^g[68];
assign t[70]=p[70];
assign t[71]=p[71]^g[70];
assign t[72]=p[72];
assign t[73]=p[73]^g[72];
assign t[74]=p[74];
assign t[75]=p[75]^g[74];
assign t[76]=p[76];
assign t[77]=p[77]^g[76];
assign t[78]=p[78];
assign t[79]=p[79]^g[78];
assign t[80]=p[80];
assign t[81]=p[81]^g[80];
assign t[82]=p[82];
assign t[83]=p[83]^g[82];
assign t[84]=p[84];
assign t[85]=p[85]^g[84];
assign t[86]=p[86];
assign t[87]=p[87]^g[86];
assign t[88]=p[88];
assign t[89]=p[89]^g[88];
assign t[90]=p[90];
assign t[91]=p[91]^g[90];
assign t[92]=p[92];
assign t[93]=p[93]^g[92];
assign t[94]=p[94];
assign t[95]=p[95]^g[94];
assign t[96]=p[96];
assign t[97]=p[97]^g[96];
assign t[98]=p[98];
assign t[99]=p[99]^g[98];
assign t[100]=p[100];
assign t[101]=p[101]^g[100];
assign t[102]=p[102];
assign t[103]=p[103]^g[102];
assign t[104]=p[104];
assign t[105]=p[105]^g[104];
assign t[106]=p[106];
assign t[107]=p[107]^g[106];
assign t[108]=p[108];
assign t[109]=p[109]^g[108];
assign t[110]=p[110];
assign t[111]=p[111]^g[110];
assign t[112]=p[112];
assign t[113]=p[113]^g[112];
assign t[114]=p[114];
assign t[115]=p[115]^g[114];
assign t[116]=p[116];
assign t[117]=p[117]^g[116];
assign t[118]=p[118];
assign t[119]=p[119]^g[118];
assign t[120]=p[120];
assign t[121]=p[121]^g[120];
assign t[122]=p[122];
assign t[123]=p[123]^g[122];
assign t[124]=p[124];
assign t[125]=p[125]^g[124];
assign t[126]=p[126];
assign t[127]=p[127]^g[126];
assign t[128]=p[128];
// prefix tree
brent_kung_cs prefix_tree(c, p[127:0], g[127:0]);
// post-computation
assign sum=p[128:1]^c;
assign cout=g[128]|(p[128]&c[127]);
endmodule
module brent_kung_cs (c, p, g);
input [127:0] p;
input [127:0] g;
output [128:1] c;
// parallel-prefix, Brent-Kung
// Stage 1: Generates G/P pairs that span 1 bits
grey b_1_0 (G_1_0, {g[1],g[0]}, p[1]);
black b_3_2 (G_3_2, P_3_2, {g[3],g[2]}, {p[3],p[2]});
black b_5_4 (G_5_4, P_5_4, {g[5],g[4]}, {p[5],p[4]});
black b_7_6 (G_7_6, P_7_6, {g[7],g[6]}, {p[7],p[6]});
black b_9_8 (G_9_8, P_9_8, {g[9],g[8]}, {p[9],p[8]});
black b_11_10 (G_11_10, P_11_10, {g[11],g[10]}, {p[11],p[10]});
black b_13_12 (G_13_12, P_13_12, {g[13],g[12]}, {p[13],p[12]});
black b_15_14 (G_15_14, P_15_14, {g[15],g[14]}, {p[15],p[14]});
black b_17_16 (G_17_16, P_17_16, {g[17],g[16]}, {p[17],p[16]});
black b_19_18 (G_19_18, P_19_18, {g[19],g[18]}, {p[19],p[18]});
black b_21_20 (G_21_20, P_21_20, {g[21],g[20]}, {p[21],p[20]});
black b_23_22 (G_23_22, P_23_22, {g[23],g[22]}, {p[23],p[22]});
black b_25_24 (G_25_24, P_25_24, {g[25],g[24]}, {p[25],p[24]});
black b_27_26 (G_27_26, P_27_26, {g[27],g[26]}, {p[27],p[26]});
black b_29_28 (G_29_28, P_29_28, {g[29],g[28]}, {p[29],p[28]});
black b_31_30 (G_31_30, P_31_30, {g[31],g[30]}, {p[31],p[30]});
black b_33_32 (G_33_32, P_33_32, {g[33],g[32]}, {p[33],p[32]});
black b_35_34 (G_35_34, P_35_34, {g[35],g[34]}, {p[35],p[34]});
black b_37_36 (G_37_36, P_37_36, {g[37],g[36]}, {p[37],p[36]});
black b_39_38 (G_39_38, P_39_38, {g[39],g[38]}, {p[39],p[38]});
black b_41_40 (G_41_40, P_41_40, {g[41],g[40]}, {p[41],p[40]});
black b_43_42 (G_43_42, P_43_42, {g[43],g[42]}, {p[43],p[42]});
black b_45_44 (G_45_44, P_45_44, {g[45],g[44]}, {p[45],p[44]});
black b_47_46 (G_47_46, P_47_46, {g[47],g[46]}, {p[47],p[46]});
black b_49_48 (G_49_48, P_49_48, {g[49],g[48]}, {p[49],p[48]});
black b_51_50 (G_51_50, P_51_50, {g[51],g[50]}, {p[51],p[50]});
black b_53_52 (G_53_52, P_53_52, {g[53],g[52]}, {p[53],p[52]});
black b_55_54 (G_55_54, P_55_54, {g[55],g[54]}, {p[55],p[54]});
black b_57_56 (G_57_56, P_57_56, {g[57],g[56]}, {p[57],p[56]});
black b_59_58 (G_59_58, P_59_58, {g[59],g[58]}, {p[59],p[58]});
black b_61_60 (G_61_60, P_61_60, {g[61],g[60]}, {p[61],p[60]});
black b_63_62 (G_63_62, P_63_62, {g[63],g[62]}, {p[63],p[62]});
black b_65_64 (G_65_64, P_65_64, {g[65],g[64]}, {p[65],p[64]});
black b_67_66 (G_67_66, P_67_66, {g[67],g[66]}, {p[67],p[66]});
black b_69_68 (G_69_68, P_69_68, {g[69],g[68]}, {p[69],p[68]});
black b_71_70 (G_71_70, P_71_70, {g[71],g[70]}, {p[71],p[70]});
black b_73_72 (G_73_72, P_73_72, {g[73],g[72]}, {p[73],p[72]});
black b_75_74 (G_75_74, P_75_74, {g[75],g[74]}, {p[75],p[74]});
black b_77_76 (G_77_76, P_77_76, {g[77],g[76]}, {p[77],p[76]});
black b_79_78 (G_79_78, P_79_78, {g[79],g[78]}, {p[79],p[78]});
black b_81_80 (G_81_80, P_81_80, {g[81],g[80]}, {p[81],p[80]});
black b_83_82 (G_83_82, P_83_82, {g[83],g[82]}, {p[83],p[82]});
black b_85_84 (G_85_84, P_85_84, {g[85],g[84]}, {p[85],p[84]});
black b_87_86 (G_87_86, P_87_86, {g[87],g[86]}, {p[87],p[86]});
black b_89_88 (G_89_88, P_89_88, {g[89],g[88]}, {p[89],p[88]});
black b_91_90 (G_91_90, P_91_90, {g[91],g[90]}, {p[91],p[90]});
black b_93_92 (G_93_92, P_93_92, {g[93],g[92]}, {p[93],p[92]});
black b_95_94 (G_95_94, P_95_94, {g[95],g[94]}, {p[95],p[94]});
black b_97_96 (G_97_96, P_97_96, {g[97],g[96]}, {p[97],p[96]});
black b_99_98 (G_99_98, P_99_98, {g[99],g[98]}, {p[99],p[98]});
black b_101_100 (G_101_100, P_101_100, {g[101],g[100]}, {p[101],p[100]});
black b_103_102 (G_103_102, P_103_102, {g[103],g[102]}, {p[103],p[102]});
black b_105_104 (G_105_104, P_105_104, {g[105],g[104]}, {p[105],p[104]});
black b_107_106 (G_107_106, P_107_106, {g[107],g[106]}, {p[107],p[106]});
black b_109_108 (G_109_108, P_109_108, {g[109],g[108]}, {p[109],p[108]});
black b_111_110 (G_111_110, P_111_110, {g[111],g[110]}, {p[111],p[110]});
black b_113_112 (G_113_112, P_113_112, {g[113],g[112]}, {p[113],p[112]});
black b_115_114 (G_115_114, P_115_114, {g[115],g[114]}, {p[115],p[114]});
black b_117_116 (G_117_116, P_117_116, {g[117],g[116]}, {p[117],p[116]});
black b_119_118 (G_119_118, P_119_118, {g[119],g[118]}, {p[119],p[118]});
black b_121_120 (G_121_120, P_121_120, {g[121],g[120]}, {p[121],p[120]});
black b_123_122 (G_123_122, P_123_122, {g[123],g[122]}, {p[123],p[122]});
black b_125_124 (G_125_124, P_125_124, {g[125],g[124]}, {p[125],p[124]});
black b_127_126 (G_127_126, P_127_126, {g[127],g[126]}, {p[127],p[126]});
// Stage 2: Generates G/P pairs that span 2 bits
grey g_3_0 (G_3_0, {G_3_2,G_1_0}, P_3_2);
black b_7_4 (G_7_4, P_7_4, {G_7_6,G_5_4}, {P_7_6,P_5_4});
black b_11_8 (G_11_8, P_11_8, {G_11_10,G_9_8}, {P_11_10,P_9_8});
black b_15_12 (G_15_12, P_15_12, {G_15_14,G_13_12}, {P_15_14,P_13_12});
black b_19_16 (G_19_16, P_19_16, {G_19_18,G_17_16}, {P_19_18,P_17_16});
black b_23_20 (G_23_20, P_23_20, {G_23_22,G_21_20}, {P_23_22,P_21_20});
black b_27_24 (G_27_24, P_27_24, {G_27_26,G_25_24}, {P_27_26,P_25_24});
black b_31_28 (G_31_28, P_31_28, {G_31_30,G_29_28}, {P_31_30,P_29_28});
black b_35_32 (G_35_32, P_35_32, {G_35_34,G_33_32}, {P_35_34,P_33_32});
black b_39_36 (G_39_36, P_39_36, {G_39_38,G_37_36}, {P_39_38,P_37_36});
black b_43_40 (G_43_40, P_43_40, {G_43_42,G_41_40}, {P_43_42,P_41_40});
black b_47_44 (G_47_44, P_47_44, {G_47_46,G_45_44}, {P_47_46,P_45_44});
black b_51_48 (G_51_48, P_51_48, {G_51_50,G_49_48}, {P_51_50,P_49_48});
black b_55_52 (G_55_52, P_55_52, {G_55_54,G_53_52}, {P_55_54,P_53_52});
black b_59_56 (G_59_56, P_59_56, {G_59_58,G_57_56}, {P_59_58,P_57_56});
black b_63_60 (G_63_60, P_63_60, {G_63_62,G_61_60}, {P_63_62,P_61_60});
black b_67_64 (G_67_64, P_67_64, {G_67_66,G_65_64}, {P_67_66,P_65_64});
black b_71_68 (G_71_68, P_71_68, {G_71_70,G_69_68}, {P_71_70,P_69_68});
black b_75_72 (G_75_72, P_75_72, {G_75_74,G_73_72}, {P_75_74,P_73_72});
black b_79_76 (G_79_76, P_79_76, {G_79_78,G_77_76}, {P_79_78,P_77_76});
black b_83_80 (G_83_80, P_83_80, {G_83_82,G_81_80}, {P_83_82,P_81_80});
black b_87_84 (G_87_84, P_87_84, {G_87_86,G_85_84}, {P_87_86,P_85_84});
black b_91_88 (G_91_88, P_91_88, {G_91_90,G_89_88}, {P_91_90,P_89_88});
black b_95_92 (G_95_92, P_95_92, {G_95_94,G_93_92}, {P_95_94,P_93_92});
black b_99_96 (G_99_96, P_99_96, {G_99_98,G_97_96}, {P_99_98,P_97_96});
black b_103_100 (G_103_100, P_103_100, {G_103_102,G_101_100}, {P_103_102,P_101_100});
black b_107_104 (G_107_104, P_107_104, {G_107_106,G_105_104}, {P_107_106,P_105_104});
black b_111_108 (G_111_108, P_111_108, {G_111_110,G_109_108}, {P_111_110,P_109_108});
black b_115_112 (G_115_112, P_115_112, {G_115_114,G_113_112}, {P_115_114,P_113_112});
black b_119_116 (G_119_116, P_119_116, {G_119_118,G_117_116}, {P_119_118,P_117_116});
black b_123_120 (G_123_120, P_123_120, {G_123_122,G_121_120}, {P_123_122,P_121_120});
black b_127_124 (G_127_124, P_127_124, {G_127_126,G_125_124}, {P_127_126,P_125_124});
// Stage 3: Generates G/P pairs that span 4 bits
grey g_7_0 (G_7_0, {G_7_4,G_3_0}, P_7_4);
black b_15_8 (G_15_8, P_15_8, {G_15_12,G_11_8}, {P_15_12,P_11_8});
black b_23_16 (G_23_16, P_23_16, {G_23_20,G_19_16}, {P_23_20,P_19_16});
black b_31_24 (G_31_24, P_31_24, {G_31_28,G_27_24}, {P_31_28,P_27_24});
black b_39_32 (G_39_32, P_39_32, {G_39_36,G_35_32}, {P_39_36,P_35_32});
black b_47_40 (G_47_40, P_47_40, {G_47_44,G_43_40}, {P_47_44,P_43_40});
black b_55_48 (G_55_48, P_55_48, {G_55_52,G_51_48}, {P_55_52,P_51_48});
black b_63_56 (G_63_56, P_63_56, {G_63_60,G_59_56}, {P_63_60,P_59_56});
black b_71_64 (G_71_64, P_71_64, {G_71_68,G_67_64}, {P_71_68,P_67_64});
black b_79_72 (G_79_72, P_79_72, {G_79_76,G_75_72}, {P_79_76,P_75_72});
black b_87_80 (G_87_80, P_87_80, {G_87_84,G_83_80}, {P_87_84,P_83_80});
black b_95_88 (G_95_88, P_95_88, {G_95_92,G_91_88}, {P_95_92,P_91_88});
black b_103_96 (G_103_96, P_103_96, {G_103_100,G_99_96}, {P_103_100,P_99_96});
black b_111_104 (G_111_104, P_111_104, {G_111_108,G_107_104}, {P_111_108,P_107_104});
black b_119_112 (G_119_112, P_119_112, {G_119_116,G_115_112}, {P_119_116,P_115_112});
black b_127_120 (G_127_120, P_127_120, {G_127_124,G_123_120}, {P_127_124,P_123_120});
// Stage 4: Generates G/P pairs that span 8 bits
grey g_15_0 (G_15_0, {G_15_8,G_7_0}, P_15_8);
black b_31_16 (G_31_16, P_31_16, {G_31_24,G_23_16}, {P_31_24,P_23_16});
black b_47_32 (G_47_32, P_47_32, {G_47_40,G_39_32}, {P_47_40,P_39_32});
black b_63_48 (G_63_48, P_63_48, {G_63_56,G_55_48}, {P_63_56,P_55_48});
black b_79_64 (G_79_64, P_79_64, {G_79_72,G_71_64}, {P_79_72,P_71_64});
black b_95_80 (G_95_80, P_95_80, {G_95_88,G_87_80}, {P_95_88,P_87_80});
black b_111_96 (G_111_96, P_111_96, {G_111_104,G_103_96}, {P_111_104,P_103_96});
black b_127_112 (G_127_112, P_127_112, {G_127_120,G_119_112}, {P_127_120,P_119_112});
// Stage 5: Generates G/P pairs that span 16 bits
grey g_31_0 (G_31_0, {G_31_16,G_15_0}, P_31_16);
black b_63_32 (G_63_32, P_63_32, {G_63_48,G_47_32}, {P_63_48,P_47_32});
black b_95_64 (G_95_64, P_95_64, {G_95_80,G_79_64}, {P_95_80,P_79_64});
black b_127_96 (G_127_96, P_127_96, {G_127_112,G_111_96}, {P_127_112,P_111_96});
// Stage 6: Generates G/P pairs that span 32 bits
grey g_63_0 (G_63_0, {G_63_32,G_31_0}, P_63_32);
black b_127_64 (G_127_64, P_127_64, {G_127_96,G_95_64}, {P_127_96,P_95_64});
// Stage 7: Generates G/P pairs that span 64 bits
grey g_127_0 (G_127_0, {G_127_64,G_63_0}, P_127_64);
// Stage 8: Generates G/P pairs that span 32 bits
grey g_95_0 (G_95_0, {G_95_64,G_63_0}, P_95_64);
// Stage 9: Generates G/P pairs that span 16 bits
grey g_47_0 (G_47_0, {G_47_32,G_31_0}, P_47_32);
grey g_79_0 (G_79_0, {G_79_64,G_63_0}, P_79_64);
grey g_111_0 (G_111_0, {G_111_96,G_95_0}, P_111_96);
// Stage 10: Generates G/P pairs that span 8 bits
grey g_23_0 (G_23_0, {G_23_16,G_15_0}, P_23_16);
grey g_39_0 (G_39_0, {G_39_32,G_31_0}, P_39_32);
grey g_55_0 (G_55_0, {G_55_48,G_47_0}, P_55_48);
grey g_71_0 (G_71_0, {G_71_64,G_63_0}, P_71_64);
grey g_87_0 (G_87_0, {G_87_80,G_79_0}, P_87_80);
grey g_103_0 (G_103_0, {G_103_96,G_95_0}, P_103_96);
grey g_119_0 (G_119_0, {G_119_112,G_111_0}, P_119_112);
// Stage 11: Generates G/P pairs that span 4 bits
grey g_11_0 (G_11_0, {G_11_8,G_7_0}, P_11_8);
grey g_19_0 (G_19_0, {G_19_16,G_15_0}, P_19_16);
grey g_27_0 (G_27_0, {G_27_24,G_23_0}, P_27_24);
grey g_35_0 (G_35_0, {G_35_32,G_31_0}, P_35_32);
grey g_43_0 (G_43_0, {G_43_40,G_39_0}, P_43_40);
grey g_51_0 (G_51_0, {G_51_48,G_47_0}, P_51_48);
grey g_59_0 (G_59_0, {G_59_56,G_55_0}, P_59_56);
grey g_67_0 (G_67_0, {G_67_64,G_63_0}, P_67_64);
grey g_75_0 (G_75_0, {G_75_72,G_71_0}, P_75_72);
grey g_83_0 (G_83_0, {G_83_80,G_79_0}, P_83_80);
grey g_91_0 (G_91_0, {G_91_88,G_87_0}, P_91_88);
grey g_99_0 (G_99_0, {G_99_96,G_95_0}, P_99_96);
grey g_107_0 (G_107_0, {G_107_104,G_103_0}, P_107_104);
grey g_115_0 (G_115_0, {G_115_112,G_111_0}, P_115_112);
grey g_123_0 (G_123_0, {G_123_120,G_119_0}, P_123_120);
// Stage 12: Generates G/P pairs that span 2 bits
grey g_5_0 (G_5_0, {G_5_4,G_3_0}, P_5_4);
grey g_9_0 (G_9_0, {G_9_8,G_7_0}, P_9_8);
grey g_13_0 (G_13_0, {G_13_12,G_11_0}, P_13_12);
grey g_17_0 (G_17_0, {G_17_16,G_15_0}, P_17_16);
grey g_21_0 (G_21_0, {G_21_20,G_19_0}, P_21_20);
grey g_25_0 (G_25_0, {G_25_24,G_23_0}, P_25_24);
grey g_29_0 (G_29_0, {G_29_28,G_27_0}, P_29_28);
grey g_33_0 (G_33_0, {G_33_32,G_31_0}, P_33_32);
grey g_37_0 (G_37_0, {G_37_36,G_35_0}, P_37_36);
grey g_41_0 (G_41_0, {G_41_40,G_39_0}, P_41_40);
grey g_45_0 (G_45_0, {G_45_44,G_43_0}, P_45_44);
grey g_49_0 (G_49_0, {G_49_48,G_47_0}, P_49_48);
grey g_53_0 (G_53_0, {G_53_52,G_51_0}, P_53_52);
grey g_57_0 (G_57_0, {G_57_56,G_55_0}, P_57_56);
grey g_61_0 (G_61_0, {G_61_60,G_59_0}, P_61_60);
grey g_65_0 (G_65_0, {G_65_64,G_63_0}, P_65_64);
grey g_69_0 (G_69_0, {G_69_68,G_67_0}, P_69_68);
grey g_73_0 (G_73_0, {G_73_72,G_71_0}, P_73_72);
grey g_77_0 (G_77_0, {G_77_76,G_75_0}, P_77_76);
grey g_81_0 (G_81_0, {G_81_80,G_79_0}, P_81_80);
grey g_85_0 (G_85_0, {G_85_84,G_83_0}, P_85_84);
grey g_89_0 (G_89_0, {G_89_88,G_87_0}, P_89_88);
grey g_93_0 (G_93_0, {G_93_92,G_91_0}, P_93_92);
grey g_97_0 (G_97_0, {G_97_96,G_95_0}, P_97_96);
grey g_101_0 (G_101_0, {G_101_100,G_99_0}, P_101_100);
grey g_105_0 (G_105_0, {G_105_104,G_103_0}, P_105_104);
grey g_109_0 (G_109_0, {G_109_108,G_107_0}, P_109_108);
grey g_113_0 (G_113_0, {G_113_112,G_111_0}, P_113_112);
grey g_117_0 (G_117_0, {G_117_116,G_115_0}, P_117_116);
grey g_121_0 (G_121_0, {G_121_120,G_119_0}, P_121_120);
grey g_125_0 (G_125_0, {G_125_124,G_123_0}, P_125_124);
// Last grey cell stage
grey g_2_0 (G_2_0, {g[2],G_1_0}, p[2]);
grey g_4_0 (G_4_0, {g[4],G_3_0}, p[4]);
grey g_6_0 (G_6_0, {g[6],G_5_0}, p[6]);
grey g_8_0 (G_8_0, {g[8],G_7_0}, p[8]);
grey g_10_0 (G_10_0, {g[10],G_9_0}, p[10]);
grey g_12_0 (G_12_0, {g[12],G_11_0}, p[12]);
grey g_14_0 (G_14_0, {g[14],G_13_0}, p[14]);
grey g_16_0 (G_16_0, {g[16],G_15_0}, p[16]);
grey g_18_0 (G_18_0, {g[18],G_17_0}, p[18]);
grey g_20_0 (G_20_0, {g[20],G_19_0}, p[20]);
grey g_22_0 (G_22_0, {g[22],G_21_0}, p[22]);
grey g_24_0 (G_24_0, {g[24],G_23_0}, p[24]);
grey g_26_0 (G_26_0, {g[26],G_25_0}, p[26]);
grey g_28_0 (G_28_0, {g[28],G_27_0}, p[28]);
grey g_30_0 (G_30_0, {g[30],G_29_0}, p[30]);
grey g_32_0 (G_32_0, {g[32],G_31_0}, p[32]);
grey g_34_0 (G_34_0, {g[34],G_33_0}, p[34]);
grey g_36_0 (G_36_0, {g[36],G_35_0}, p[36]);
grey g_38_0 (G_38_0, {g[38],G_37_0}, p[38]);
grey g_40_0 (G_40_0, {g[40],G_39_0}, p[40]);
grey g_42_0 (G_42_0, {g[42],G_41_0}, p[42]);
grey g_44_0 (G_44_0, {g[44],G_43_0}, p[44]);
grey g_46_0 (G_46_0, {g[46],G_45_0}, p[46]);
grey g_48_0 (G_48_0, {g[48],G_47_0}, p[48]);
grey g_50_0 (G_50_0, {g[50],G_49_0}, p[50]);
grey g_52_0 (G_52_0, {g[52],G_51_0}, p[52]);
grey g_54_0 (G_54_0, {g[54],G_53_0}, p[54]);
grey g_56_0 (G_56_0, {g[56],G_55_0}, p[56]);
grey g_58_0 (G_58_0, {g[58],G_57_0}, p[58]);
grey g_60_0 (G_60_0, {g[60],G_59_0}, p[60]);
grey g_62_0 (G_62_0, {g[62],G_61_0}, p[62]);
grey g_64_0 (G_64_0, {g[64],G_63_0}, p[64]);
grey g_66_0 (G_66_0, {g[66],G_65_0}, p[66]);
grey g_68_0 (G_68_0, {g[68],G_67_0}, p[68]);
grey g_70_0 (G_70_0, {g[70],G_69_0}, p[70]);
grey g_72_0 (G_72_0, {g[72],G_71_0}, p[72]);
grey g_74_0 (G_74_0, {g[74],G_73_0}, p[74]);
grey g_76_0 (G_76_0, {g[76],G_75_0}, p[76]);
grey g_78_0 (G_78_0, {g[78],G_77_0}, p[78]);
grey g_80_0 (G_80_0, {g[80],G_79_0}, p[80]);
grey g_82_0 (G_82_0, {g[82],G_81_0}, p[82]);
grey g_84_0 (G_84_0, {g[84],G_83_0}, p[84]);
grey g_86_0 (G_86_0, {g[86],G_85_0}, p[86]);
grey g_88_0 (G_88_0, {g[88],G_87_0}, p[88]);
grey g_90_0 (G_90_0, {g[90],G_89_0}, p[90]);
grey g_92_0 (G_92_0, {g[92],G_91_0}, p[92]);
grey g_94_0 (G_94_0, {g[94],G_93_0}, p[94]);
grey g_96_0 (G_96_0, {g[96],G_95_0}, p[96]);
grey g_98_0 (G_98_0, {g[98],G_97_0}, p[98]);
grey g_100_0 (G_100_0, {g[100],G_99_0}, p[100]);
grey g_102_0 (G_102_0, {g[102],G_101_0}, p[102]);
grey g_104_0 (G_104_0, {g[104],G_103_0}, p[104]);
grey g_106_0 (G_106_0, {g[106],G_105_0}, p[106]);
grey g_108_0 (G_108_0, {g[108],G_107_0}, p[108]);
grey g_110_0 (G_110_0, {g[110],G_109_0}, p[110]);
grey g_112_0 (G_112_0, {g[112],G_111_0}, p[112]);
grey g_114_0 (G_114_0, {g[114],G_113_0}, p[114]);
grey g_116_0 (G_116_0, {g[116],G_115_0}, p[116]);
grey g_118_0 (G_118_0, {g[118],G_117_0}, p[118]);
grey g_120_0 (G_120_0, {g[120],G_119_0}, p[120]);
grey g_122_0 (G_122_0, {g[122],G_121_0}, p[122]);
grey g_124_0 (G_124_0, {g[124],G_123_0}, p[124]);
grey g_126_0 (G_126_0, {g[126],G_125_0}, p[126]);
// Final Stage: Apply c_k+1=G_k_0
assign c[1]=g[0];
assign c[2]=G_1_0;
assign c[3]=G_2_0;
assign c[4]=G_3_0;
assign c[5]=G_4_0;
assign c[6]=G_5_0;
assign c[7]=G_6_0;
assign c[8]=G_7_0;
assign c[9]=G_8_0;
assign c[10]=G_9_0;
assign c[11]=G_10_0;
assign c[12]=G_11_0;
assign c[13]=G_12_0;
assign c[14]=G_13_0;
assign c[15]=G_14_0;
assign c[16]=G_15_0;
assign c[17]=G_16_0;
assign c[18]=G_17_0;
assign c[19]=G_18_0;
assign c[20]=G_19_0;
assign c[21]=G_20_0;
assign c[22]=G_21_0;
assign c[23]=G_22_0;
assign c[24]=G_23_0;
assign c[25]=G_24_0;
assign c[26]=G_25_0;
assign c[27]=G_26_0;
assign c[28]=G_27_0;
assign c[29]=G_28_0;
assign c[30]=G_29_0;
assign c[31]=G_30_0;
assign c[32]=G_31_0;
assign c[33]=G_32_0;
assign c[34]=G_33_0;
assign c[35]=G_34_0;
assign c[36]=G_35_0;
assign c[37]=G_36_0;
assign c[38]=G_37_0;
assign c[39]=G_38_0;
assign c[40]=G_39_0;
assign c[41]=G_40_0;
assign c[42]=G_41_0;
assign c[43]=G_42_0;
assign c[44]=G_43_0;
assign c[45]=G_44_0;
assign c[46]=G_45_0;
assign c[47]=G_46_0;
assign c[48]=G_47_0;
assign c[49]=G_48_0;
assign c[50]=G_49_0;
assign c[51]=G_50_0;
assign c[52]=G_51_0;
assign c[53]=G_52_0;
assign c[54]=G_53_0;
assign c[55]=G_54_0;
assign c[56]=G_55_0;
assign c[57]=G_56_0;
assign c[58]=G_57_0;
assign c[59]=G_58_0;
assign c[60]=G_59_0;
assign c[61]=G_60_0;
assign c[62]=G_61_0;
assign c[63]=G_62_0;
assign c[64]=G_63_0;
assign c[65]=G_64_0;
assign c[66]=G_65_0;
assign c[67]=G_66_0;
assign c[68]=G_67_0;
assign c[69]=G_68_0;
assign c[70]=G_69_0;
assign c[71]=G_70_0;
assign c[72]=G_71_0;
assign c[73]=G_72_0;
assign c[74]=G_73_0;
assign c[75]=G_74_0;
assign c[76]=G_75_0;
assign c[77]=G_76_0;
assign c[78]=G_77_0;
assign c[79]=G_78_0;
assign c[80]=G_79_0;
assign c[81]=G_80_0;
assign c[82]=G_81_0;
assign c[83]=G_82_0;
assign c[84]=G_83_0;
assign c[85]=G_84_0;
assign c[86]=G_85_0;
assign c[87]=G_86_0;
assign c[88]=G_87_0;
assign c[89]=G_88_0;
assign c[90]=G_89_0;
assign c[91]=G_90_0;
assign c[92]=G_91_0;
assign c[93]=G_92_0;
assign c[94]=G_93_0;
assign c[95]=G_94_0;
assign c[96]=G_95_0;
assign c[97]=G_96_0;
assign c[98]=G_97_0;
assign c[99]=G_98_0;
assign c[100]=G_99_0;
assign c[101]=G_100_0;
assign c[102]=G_101_0;
assign c[103]=G_102_0;
assign c[104]=G_103_0;
assign c[105]=G_104_0;
assign c[106]=G_105_0;
assign c[107]=G_106_0;
assign c[108]=G_107_0;
assign c[109]=G_108_0;
assign c[110]=G_109_0;
assign c[111]=G_110_0;
assign c[112]=G_111_0;
assign c[113]=G_112_0;
assign c[114]=G_113_0;
assign c[115]=G_114_0;
assign c[116]=G_115_0;
assign c[117]=G_116_0;
assign c[118]=G_117_0;
assign c[119]=G_118_0;
assign c[120]=G_119_0;
assign c[121]=G_120_0;
assign c[122]=G_121_0;
assign c[123]=G_122_0;
assign c[124]=G_123_0;
assign c[125]=G_124_0;
assign c[126]=G_125_0;
assign c[127]=G_126_0;
assign c[128]=G_127_0;
endmodule // brent_kung_cs
// Black cell
module black(gout, pout, gin, pin);
input [1:0] gin, pin;
output gout, pout;
assign pout=pin[1]&pin[0];
assign gout=gin[1]|(pin[1]&gin[0]);
endmodule // black
// Grey cell
module grey(gout, gin, pin);
input[1:0] gin;
input pin;
output gout;
assign gout=gin[1]|(pin&gin[0]);
endmodule // grey

120
wally-pipelined/src/fpudivsqrt/bk13.v
View file

@ -1,120 +0,0 @@
// Brent-Kung Carry-save Prefix Adder
module exp_add (cout, sum, a, b, cin);
input [12:0] a, b;
input cin;
output [12:0] sum;
output cout;
wire [13:0] p,g,t;
wire [12:0] c;
// pre-computation
assign p={a^b,1'b0};
assign g={a&b, cin};
assign t[1]=p[1];
assign t[2]=p[2];
assign t[3]=p[3]^g[2];
assign t[4]=p[4];
assign t[5]=p[5]^g[4];
assign t[6]=p[6];
assign t[7]=p[7]^g[6];
assign t[8]=p[8];
assign t[9]=p[9]^g[8];
assign t[10]=p[10];
assign t[11]=p[11]^g[10];
assign t[12]=p[12];
assign t[13]=p[13];
// prefix tree
brent_kung_cs prefix_tree(c, p[12:0], g[12:0]);
// post-computation
assign sum=p[13:1]^c;
assign cout=g[13]|(p[13]&c[12]);
endmodule
module brent_kung_cs (c, p, g);
input [12:0] p;
input [12:0] g;
output [13:1] c;
// parallel-prefix, Brent-Kung
// Stage 1: Generates G/P pairs that span 1 bits
grey b_1_0 (G_1_0, {g[1],g[0]}, p[1]);
black b_3_2 (G_3_2, P_3_2, {g[3],g[2]}, {p[3],p[2]});
black b_5_4 (G_5_4, P_5_4, {g[5],g[4]}, {p[5],p[4]});
black b_7_6 (G_7_6, P_7_6, {g[7],g[6]}, {p[7],p[6]});
black b_9_8 (G_9_8, P_9_8, {g[9],g[8]}, {p[9],p[8]});
black b_11_10 (G_11_10, P_11_10, {g[11],g[10]}, {p[11],p[10]});
black b_13_12 (G_13_12, P_13_12, {g[13],g[12]}, {p[13],p[12]});
// Stage 2: Generates G/P pairs that span 2 bits
grey g_3_0 (G_3_0, {G_3_2,G_1_0}, P_3_2);
black b_7_4 (G_7_4, P_7_4, {G_7_6,G_5_4}, {P_7_6,P_5_4});
black b_11_8 (G_11_8, P_11_8, {G_11_10,G_9_8}, {P_11_10,P_9_8});
// Stage 3: Generates G/P pairs that span 4 bits
grey g_7_0 (G_7_0, {G_7_4,G_3_0}, P_7_4);
// Stage 4: Generates G/P pairs that span 8 bits
// Stage 5: Generates G/P pairs that span 4 bits
grey g_11_0 (G_11_0, {G_11_8,G_7_0}, P_11_8);
// Stage 6: Generates G/P pairs that span 2 bits
grey g_5_0 (G_5_0, {G_5_4,G_3_0}, P_5_4);
grey g_9_0 (G_9_0, {G_9_8,G_7_0}, P_9_8);
// Last grey cell stage
grey g_2_0 (G_2_0, {g[2],G_1_0}, p[2]);
grey g_4_0 (G_4_0, {g[4],G_3_0}, p[4]);
grey g_6_0 (G_6_0, {g[6],G_5_0}, p[6]);
grey g_8_0 (G_8_0, {g[8],G_7_0}, p[8]);
grey g_10_0 (G_10_0, {g[10],G_9_0}, p[10]);
grey g_12_0 (G_12_0, {g[12],G_11_0}, p[12]);
// Final Stage: Apply c_k+1=G_k_0
assign c[1]=g[0];
assign c[2]=G_1_0;
assign c[3]=G_2_0;
assign c[4]=G_3_0;
assign c[5]=G_4_0;
assign c[6]=G_5_0;
assign c[7]=G_6_0;
assign c[8]=G_7_0;
assign c[9]=G_8_0;
assign c[10]=G_9_0;
assign c[11]=G_10_0;
assign c[12]=G_11_0;
assign c[13]=G_12_0;
endmodule
// Black cell
module black(gout, pout, gin, pin);
input [1:0] gin, pin;
output gout, pout;
assign pout=pin[1]&pin[0];
assign gout=gin[1]|(pin[1]&gin[0]);
endmodule
// Grey cell
module grey(gout, gin, pin);
input[1:0] gin;
input pin;
output gout;
assign gout=gin[1]|(pin&gin[0]);
endmodule

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// Brent-Kung Prefix Adder
module add (cout, sum, a, b, cin);
input [13:0] a, b;
input cin;
output [13:0] sum;
output cout;
wire [14:0] p,g;
wire [13:0] c;
// pre-computation
assign p={a^b,1'b0};
assign g={a&b, cin};
// prefix tree
brent_kung prefix_tree(c, p[13:0], g[13:0]);
// post-computation
assign sum=p[14:1]^c;
assign cout=g[14]|(p[14]&c[13]);
endmodule
module brent_kung (c, p, g);
input [13:0] p;
input [13:0] g;
output [14:1] c;
// parallel-prefix, Brent-Kung
// Stage 1: Generates G/P pairs that span 1 bits
grey b_1_0 (G_1_0, {g[1],g[0]}, p[1]);
black b_3_2 (G_3_2, P_3_2, {g[3],g[2]}, {p[3],p[2]});
black b_5_4 (G_5_4, P_5_4, {g[5],g[4]}, {p[5],p[4]});
black b_7_6 (G_7_6, P_7_6, {g[7],g[6]}, {p[7],p[6]});
black b_9_8 (G_9_8, P_9_8, {g[9],g[8]}, {p[9],p[8]});
black b_11_10 (G_11_10, P_11_10, {g[11],g[10]}, {p[11],p[10]});
black b_13_12 (G_13_12, P_13_12, {g[13],g[12]}, {p[13],p[12]});
// Stage 2: Generates G/P pairs that span 2 bits
grey g_3_0 (G_3_0, {G_3_2,G_1_0}, P_3_2);
black b_7_4 (G_7_4, P_7_4, {G_7_6,G_5_4}, {P_7_6,P_5_4});
black b_11_8 (G_11_8, P_11_8, {G_11_10,G_9_8}, {P_11_10,P_9_8});
// Stage 3: Generates G/P pairs that span 4 bits
grey g_7_0 (G_7_0, {G_7_4,G_3_0}, P_7_4);
// Stage 4: Generates G/P pairs that span 8 bits
// Stage 5: Generates G/P pairs that span 4 bits
grey g_11_0 (G_11_0, {G_11_8,G_7_0}, P_11_8);
// Stage 6: Generates G/P pairs that span 2 bits
grey g_5_0 (G_5_0, {G_5_4,G_3_0}, P_5_4);
grey g_9_0 (G_9_0, {G_9_8,G_7_0}, P_9_8);
grey g_13_0 (G_13_0, {G_13_12,G_11_0}, P_13_12);
// Last grey cell stage
grey g_2_0 (G_2_0, {g[2],G_1_0}, p[2]);
grey g_4_0 (G_4_0, {g[4],G_3_0}, p[4]);
grey g_6_0 (G_6_0, {g[6],G_5_0}, p[6]);
grey g_8_0 (G_8_0, {g[8],G_7_0}, p[8]);
grey g_10_0 (G_10_0, {g[10],G_9_0}, p[10]);
grey g_12_0 (G_12_0, {g[12],G_11_0}, p[12]);
// Final Stage: Apply c_k+1=G_k_0
assign c[1]=g[0];
assign c[2]=G_1_0;
assign c[3]=G_2_0;
assign c[4]=G_3_0;
assign c[5]=G_4_0;
assign c[6]=G_5_0;
assign c[7]=G_6_0;
assign c[8]=G_7_0;
assign c[9]=G_8_0;
assign c[10]=G_9_0;
assign c[11]=G_10_0;
assign c[12]=G_11_0;
assign c[13]=G_12_0;
assign c[14]=G_13_0;
endmodule
// Black cell
module black(gout, pout, gin, pin);
input [1:0] gin, pin;
output gout, pout;
assign pout=pin[1]&pin[0];
assign gout=gin[1]|(pin[1]&gin[0]);
endmodule
// Grey cell
module grey(gout, gin, pin);
input[1:0] gin;
input pin;
output gout;
assign gout=gin[1]|(pin&gin[0]);
endmodule

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wally-pipelined/src/fpudivsqrt/bk15.v
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// Kogge-Stone Prefix Adder
module bk15 (cout, sum, a, b, cin);
input [14:0] a, b;
input cin;
output [14:0] sum;
output cout;
wire [15:0] p,g;
wire [15:1] h,c;
// pre-computation
assign p={a|b,1'b1};
assign g={a&b, cin};
// prefix tree
kogge_stone prefix_tree(h, c, p[14:0], g[14:0]);
// post-computation
assign h[15]=g[15]|c[15];
assign sum=p[15:1]^h|g[15:1]&c;
assign cout=p[15]&h[15];
endmodule // bk15
module kogge_stone (h, c, p, g);
input [14:0] p;
input [14:0] g;
output [15:1] h;
output [15:1] c;
// parallel-prefix, Kogge-Stone
// Stage 1: Generates G/P pairs that span 1 bits
rgry g_1_0 (H_1_0, {g[1],g[0]});
rblk b_2_1 (H_2_1, I_2_1, {g[2],g[1]}, {p[1],p[0]});
rblk b_3_2 (H_3_2, I_3_2, {g[3],g[2]}, {p[2],p[1]});
rblk b_4_3 (H_4_3, I_4_3, {g[4],g[3]}, {p[3],p[2]});
rblk b_5_4 (H_5_4, I_5_4, {g[5],g[4]}, {p[4],p[3]});
rblk b_6_5 (H_6_5, I_6_5, {g[6],g[5]}, {p[5],p[4]});
rblk b_7_6 (H_7_6, I_7_6, {g[7],g[6]}, {p[6],p[5]});
rblk b_8_7 (H_8_7, I_8_7, {g[8],g[7]}, {p[7],p[6]});
rblk b_9_8 (H_9_8, I_9_8, {g[9],g[8]}, {p[8],p[7]});
rblk b_10_9 (H_10_9, I_10_9, {g[10],g[9]}, {p[9],p[8]});
rblk b_11_10 (H_11_10, I_11_10, {g[11],g[10]}, {p[10],p[9]});
rblk b_12_11 (H_12_11, I_12_11, {g[12],g[11]}, {p[11],p[10]});
rblk b_13_12 (H_13_12, I_13_12, {g[13],g[12]}, {p[12],p[11]});
rblk b_14_13 (H_14_13, I_14_13, {g[14],g[13]}, {p[13],p[12]});
// Stage 2: Generates G/P pairs that span 2 bits
grey g_2_0 (H_2_0, {H_2_1,g[0]}, I_2_1);
grey g_3_0 (H_3_0, {H_3_2,H_1_0}, I_3_2);
black b_4_1 (H_4_1, I_4_1, {H_4_3,H_2_1}, {I_4_3,I_2_1});
black b_5_2 (H_5_2, I_5_2, {H_5_4,H_3_2}, {I_5_4,I_3_2});
black b_6_3 (H_6_3, I_6_3, {H_6_5,H_4_3}, {I_6_5,I_4_3});
black b_7_4 (H_7_4, I_7_4, {H_7_6,H_5_4}, {I_7_6,I_5_4});
black b_8_5 (H_8_5, I_8_5, {H_8_7,H_6_5}, {I_8_7,I_6_5});
black b_9_6 (H_9_6, I_9_6, {H_9_8,H_7_6}, {I_9_8,I_7_6});
black b_10_7 (H_10_7, I_10_7, {H_10_9,H_8_7}, {I_10_9,I_8_7});
black b_11_8 (H_11_8, I_11_8, {H_11_10,H_9_8}, {I_11_10,I_9_8});
black b_12_9 (H_12_9, I_12_9, {H_12_11,H_10_9}, {I_12_11,I_10_9});
black b_13_10 (H_13_10, I_13_10, {H_13_12,H_11_10}, {I_13_12,I_11_10});
black b_14_11 (H_14_11, I_14_11, {H_14_13,H_12_11}, {I_14_13,I_12_11});
// Stage 3: Generates G/P pairs that span 4 bits
grey g_4_0 (H_4_0, {H_4_1,g[0]}, I_4_1);
grey g_5_0 (H_5_0, {H_5_2,H_1_0}, I_5_2);
grey g_6_0 (H_6_0, {H_6_3,H_2_0}, I_6_3);
grey g_7_0 (H_7_0, {H_7_4,H_3_0}, I_7_4);
black b_8_1 (H_8_1, I_8_1, {H_8_5,H_4_1}, {I_8_5,I_4_1});
black b_9_2 (H_9_2, I_9_2, {H_9_6,H_5_2}, {I_9_6,I_5_2});
black b_10_3 (H_10_3, I_10_3, {H_10_7,H_6_3}, {I_10_7,I_6_3});
black b_11_4 (H_11_4, I_11_4, {H_11_8,H_7_4}, {I_11_8,I_7_4});
black b_12_5 (H_12_5, I_12_5, {H_12_9,H_8_5}, {I_12_9,I_8_5});
black b_13_6 (H_13_6, I_13_6, {H_13_10,H_9_6}, {I_13_10,I_9_6});
black b_14_7 (H_14_7, I_14_7, {H_14_11,H_10_7}, {I_14_11,I_10_7});
// Stage 4: Generates G/P pairs that span 8 bits
grey g_8_0 (H_8_0, {H_8_1,g[0]}, I_8_1);
grey g_9_0 (H_9_0, {H_9_2,H_1_0}, I_9_2);
grey g_10_0 (H_10_0, {H_10_3,H_2_0}, I_10_3);
grey g_11_0 (H_11_0, {H_11_4,H_3_0}, I_11_4);
grey g_12_0 (H_12_0, {H_12_5,H_4_0}, I_12_5);
grey g_13_0 (H_13_0, {H_13_6,H_5_0}, I_13_6);
grey g_14_0 (H_14_0, {H_14_7,H_6_0}, I_14_7);
// Final Stage: Apply c_k+1=p_k&H_k_0
assign c[1]=g[0];
assign h[1]=H_1_0; assign c[2]=p[1]&H_1_0;
assign h[2]=H_2_0; assign c[3]=p[2]&H_2_0;
assign h[3]=H_3_0; assign c[4]=p[3]&H_3_0;
assign h[4]=H_4_0; assign c[5]=p[4]&H_4_0;
assign h[5]=H_5_0; assign c[6]=p[5]&H_5_0;
assign h[6]=H_6_0; assign c[7]=p[6]&H_6_0;
assign h[7]=H_7_0; assign c[8]=p[7]&H_7_0;
assign h[8]=H_8_0; assign c[9]=p[8]&H_8_0;
assign h[9]=H_9_0; assign c[10]=p[9]&H_9_0;
assign h[10]=H_10_0; assign c[11]=p[10]&H_10_0;
assign h[11]=H_11_0; assign c[12]=p[11]&H_11_0;
assign h[12]=H_12_0; assign c[13]=p[12]&H_12_0;
assign h[13]=H_13_0; assign c[14]=p[13]&H_13_0;
assign h[14]=H_14_0; assign c[15]=p[14]&H_14_0;
endmodule // kogge_stone
// Black cell
module black(gout, pout, gin, pin);
input [1:0] gin, pin;
output gout, pout;
assign pout=pin[1]&pin[0];
assign gout=gin[1]|(pin[1]&gin[0]);
endmodule // black
// Grey cell
module grey(gout, gin, pin);
input[1:0] gin;
input pin;
output gout;
assign gout=gin[1]|(pin&gin[0]);
endmodule // grey
// reduced Black cell
module rblk(hout, iout, gin, pin);
input [1:0] gin, pin;
output hout, iout;
assign iout=pin[1]&pin[0];
assign hout=gin[1]|gin[0];
endmodule // rblk
// reduced Grey cell
module rgry(hout, gin);
input[1:0] gin;
output hout;
assign hout=gin[1]|gin[0];
endmodule // rgry

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wally-pipelined/src/fpudivsqrt/convert_inputs.v
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// This module takes as inputs two operands (op1 and op2)
// and the result precision (P). Based on the operation and precision,
// it conditionally converts single precision values to double
// precision values and modifies the sign of op1.
// The converted operands are Float1 and Float2.
module convert_inputs(Float1, Float2b, op1, op2, op_type, P);
input [63:0] op1; // 1st input operand (A)
input [63:0] op2; // 2nd input operand (B)
input P; // Result Precision (0 for double, 1 for single)
input op_type; // Operation
output [63:0] Float1; // Converted 1st input operand
output [63:0] Float2b; // Converted 2nd input operand
wire [63:0] Float2;
wire Zexp1; // One if the exponent of op1 is zero
wire Zexp2; // One if the exponent of op2 is zero
wire Oexp1; // One if the exponent of op1 is all ones
wire Oexp2; // One if the exponent of op2 is all ones
// Test if the input exponent is zero, because if it is then the
// exponent of the converted number should be zero.
assign Zexp1 = ~(op1[62] | op1[61] | op1[60] | op1[59] |
op1[58] | op1[57] | op1[56] | op1[55]);
assign Zexp2 = ~(op2[62] | op2[61] | op2[60] | op2[59] |
op2[58] | op2[57] | op2[56] | op2[55]);
assign Oexp1 = (op1[62] & op1[61] & op1[60] & op1[59] &
op1[58] & op1[57] & op1[56] & op1[55]);
assign Oexp2 = (op2[62] & op2[61] & op2[60] & op2[59] &
op2[58] & op2[57] & op2[56] &op2[55]);
// Conditionally convert op1. Lower 29 bits are zero for single precision.
assign Float1[62:29] = P ? {op1[62], {3{(~op1[62]&~Zexp1)|Oexp1}}, op1[61:32]}
: op1[62:29];
assign Float1[28:0] = op1[28:0] & {29{~P}};
// Conditionally convert op2. Lower 29 bits are zero for single precision.
assign Float2[62:29] = P ? {op2[62], {3{(~op2[62]&~Zexp2)|Oexp2}}, op2[61:32]}
: op2[62:29];
assign Float2[28:0] = op2[28:0] & {29{~P}};
// Set the sign of Float1 based on its original sign
assign Float1[63] = op1[63];
assign Float2[63] = op2[63];
// For sqrt, assign Float2 same as Float1 for simplicity
assign Float2b = op_type ? Float1 : Float2;
endmodule // convert_inputs

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wally-pipelined/src/fpudivsqrt/divconvDP.sv
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`timescale 1ps/1ps
module divconv (q1, qm1, qp1, q0, qm0, qp0,
rega_out, regb_out, regc_out, regd_out,
regr_out, d, n,
sel_muxa, sel_muxb, sel_muxr,
reset, clk,
load_rega, load_regb, load_regc, load_regd,
load_regr, load_regs, P, op_type, exp_odd);
input logic [52:0] d, n;
input logic [2:0] sel_muxa, sel_muxb;
input logic sel_muxr;
input logic load_rega, load_regb, load_regc, load_regd;
input logic load_regr, load_regs;
input logic P;
input logic op_type;
input logic exp_odd;
input logic reset;
input logic clk;
output logic [63:0] q1, qp1, qm1;
output logic [63:0] q0, qp0, qm0;
output logic [63:0] rega_out, regb_out, regc_out, regd_out;
output logic [127:0] regr_out;
supply1 vdd;
supply0 vss;
logic [63:0] muxa_out, muxb_out;
logic [10:0] ia_div, ia_sqrt;
logic [63:0] ia_out;
logic [127:0] mul_out;
logic [63:0] q_out1, qm_out1, qp_out1;
logic [63:0] q_out0, qm_out0, qp_out0;
logic [63:0] mcand, mplier, mcand_q;
logic [63:0] twocmp_out;
logic [64:0] three;
logic [127:0] Carry, Carry2;
logic [127:0] Sum, Sum2;
logic [127:0] constant, constant2;
logic [63:0] q_const, qp_const, qm_const;
logic [63:0] d2, n2;
logic [11:0] d3;
// Check if exponent is odd for sqrt
// If exp_odd=1 and sqrt, then M/2 and use ia_addr=0 as IA
assign d2 = (exp_odd&op_type) ? {vss,d,10'h0} : {d,11'h0};
assign n2 = op_type ? d2 : {n,11'h0};
// IA div/sqrt
sbtm ia1 (d[52:41], ia_div);
sbtm2 ia2 (d2[63:52], ia_sqrt);
assign ia_out = op_type ? {ia_sqrt, {53{1'b0}}} : {ia_div, {53{1'b0}}};
// Choose IA or iteration
mux6 #(64) mx1 (d2, ia_out, rega_out, regc_out, regd_out, regb_out, sel_muxb, muxb_out);
mux5 #(64) mx2 (regc_out, n2, ia_out, regb_out, regd_out, sel_muxa, muxa_out);
// Deal with remainder if [0.5, 1) instead of [1, 2)
mux2 #(128) mx3a ({~n, {75{1'b1}}}, {{1'b1}, ~n, {74{1'b1}}}, q1[63], constant2);
// Select Mcand, Remainder/Q''
mux2 #(128) mx3 (128'h0, constant2, sel_muxr, constant);
// Select mcand - remainder should always choose q1 [1,2) because
// adjustment of N in the from XX.FFFFFFF
mux2 #(64) mx4 (q0, q1, q1[63], mcand_q);
mux2 #(64) mx5 (muxb_out, mcand_q, sel_muxr&op_type, mplier);
mux2 #(64) mx6 (muxa_out, mcand_q, sel_muxr, mcand);
// TDM multiplier (carry/save)
multiplier mult1 (mcand, mplier, Sum, Carry);
// Q*D - N (reversed but changed in rounder.v to account for sign reversal)
csa #(128) csa1 (Sum, Carry, constant, Sum2, Carry2);
// Add ulp for subtraction in remainder
mux2 #(1) mx7 (1'b0, 1'b1, sel_muxr, muxr_out);
// Constant for Q''
mux2 #(64) mx8 ({64'h0000_0000_0000_0200}, {64'h0000_0040_0000_0000}, P, q_const);
mux2 #(64) mx9 ({64'h0000_0000_0000_0A00}, {64'h0000_0140_0000_0000}, P, qp_const);
mux2 #(64) mxA ({64'hFFFF_FFFF_FFFF_F9FF}, {64'hFFFF_FF3F_FFFF_FFFF}, P, qm_const);
// CPA (from CSA)/Remainder addition/subtraction
ldf128 cpa1 (cout1, mul_out, Sum2, Carry2, muxr_out);
// Assuming [1,2) - q1
ldf64 cpa2 (cout2, q_out1, regb_out, q_const, 1'b0);
ldf64 cpa3 (cout3, qp_out1, regb_out, qp_const, 1'b0);
ldf64 cpa4 (cout4, qm_out1, regb_out, qm_const, 1'b1);
// Assuming [0.5,1) - q0
ldf64 cpa5 (cout5, q_out0, {regb_out[62:0], vss}, q_const, 1'b0);
ldf64 cpa6 (cout6, qp_out0, {regb_out[62:0], vss}, qp_const, 1'b0);
ldf64 cpa7 (cout7, qm_out0, {regb_out[62:0], vss}, qm_const, 1'b1);
// One's complement instead of two's complement (for hw efficiency)
assign three = {~mul_out[126], mul_out[126], ~mul_out[125:63]};
mux2 #(64) mxTC (~mul_out[126:63], three[64:1], op_type, twocmp_out);
// regs
flopenr #(64) regc (clk, reset, load_regc, twocmp_out, regc_out);
flopenr #(64) regb (clk, reset, load_regb, mul_out[126:63], regb_out);
flopenr #(64) rega (clk, reset, load_rega, mul_out[126:63], rega_out);
flopenr #(64) regd (clk, reset, load_regd, mul_out[126:63], regd_out);
flopenr #(128) regr (clk, reset, load_regr, mul_out, regr_out);
// Assuming [1,2)
flopenr #(64) rege (clk, reset, load_regs, {q_out1[63:39], (q_out1[38:10] & {29{~P}}), 10'h0}, q1);
flopenr #(64) regf (clk, reset, load_regs, {qm_out1[63:39], (qm_out1[38:10] & {29{~P}}), 10'h0}, qm1);
flopenr #(64) regg (clk, reset, load_regs, {qp_out1[63:39], (qp_out1[38:10] & {29{~P}}), 10'h0}, qp1);
// Assuming [0,1)
flopenr #(64) regh (clk, reset, load_regs, {q_out0[63:39], (q_out0[38:10] & {29{~P}}), 10'h0}, q0);
flopenr #(64) regj (clk, reset, load_regs, {qm_out0[63:39], (qm_out0[38:10] & {29{~P}}), 10'h0}, qm0);
flopenr #(64) regk (clk, reset, load_regs, {qp_out0[63:39], (qp_out0[38:10] & {29{~P}}), 10'h0}, qp0);
endmodule // divconv
module adder #(parameter WIDTH=8)
(input logic [WIDTH-1:0] a, b,
output logic [WIDTH-1:0] y);
assign y = a + b;
endmodule // adder
module flopenr #(parameter WIDTH = 8)
(input logic clk, reset, en,
input logic [WIDTH-1:0] d,
output logic [WIDTH-1:0] q);
always_ff @(posedge clk, posedge reset)
if (reset) q <= #10 0;
else if (en) q <= #10 d;
endmodule // flopenr
module flopr #(parameter WIDTH = 8)
(input logic clk, reset,
input logic [WIDTH-1:0] d,
output logic [WIDTH-1:0] q);
always_ff @(posedge clk, posedge reset)
if (reset) q <= #10 0;
else q <= #10 d;
endmodule // flopr
module flopenrc #(parameter WIDTH = 8)
(input logic clk, reset, en, clear,
input logic [WIDTH-1:0] d,
output logic [WIDTH-1:0] q);
always_ff @(posedge clk, posedge reset)
if (reset) q <= #10 0;
else if (en)
if (clear) q <= #10 0;
else q <= #10 d;
endmodule // flopenrc
module floprc #(parameter WIDTH = 8)
(input logic clk, reset, clear,
input logic [WIDTH-1:0] d,
output logic [WIDTH-1:0] q);
always_ff @(posedge clk, posedge reset)
if (reset) q <= #10 0;
else
if (clear) q <= #10 0;
else q <= #10 d;
endmodule // floprc
module mux2 #(parameter WIDTH = 8)
(input logic [WIDTH-1:0] d0, d1,
input logic s,
output logic [WIDTH-1:0] y);
assign y = s ? d1 : d0;
endmodule // mux2
module mux3 #(parameter WIDTH = 8)
(input logic [WIDTH-1:0] d0, d1, d2,
input logic [1:0] s,
output logic [WIDTH-1:0] y);
assign y = s[1] ? d2 : (s[0] ? d1 : d0);
endmodule // mux3
module mux4 #(parameter WIDTH = 8)
(input logic [WIDTH-1:0] d0, d1, d2, d3,
input logic [1:0] s,
output logic [WIDTH-1:0] y);
assign y = s[1] ? (s[0] ? d3 : d2) : (s[0] ? d1 : d0);
endmodule // mux4
module mux5 #(parameter WIDTH = 8)
(input logic [WIDTH-1:0] d0, d1, d2, d3, d4,
input logic [2:0] s,
output logic [WIDTH-1:0] y);
always_comb
casez (s)
3'b000 : y = d0;
3'b001 : y = d1;
3'b010 : y = d2;
3'b011 : y = d3;
3'b1?? : y = d4;
endcase // casez (s)
endmodule // mux5
module mux6 #(parameter WIDTH = 8)
(input logic [WIDTH-1:0] d0, d1, d2, d3, d4, d5,
input logic [2:0] s,
output logic [WIDTH-1:0] y);
always_comb
casez (s)
3'b000 : y = d0;
3'b001 : y = d1;
3'b010 : y = d2;
3'b011 : y = d3;
3'b10? : y = d4;
3'b11? : y = d5;
endcase // casez (s)
endmodule // mux6
module eqcmp #(parameter WIDTH = 8)
(input logic [WIDTH-1:0] a, b,
output logic y);
assign y = (a == b);
endmodule // eqcmp
module fa (input logic a, b, c, output logic sum, carry);
assign sum = a^b^c;
assign carry = a&b|a&c|b&c;
endmodule // fa
module csa #(parameter WIDTH=8)
(input logic [WIDTH-1:0] a, b, c,
output logic [WIDTH-1:0] sum, carry);
logic [WIDTH:0] carry_temp;
genvar i;
generate
for (i=0;i<WIDTH;i=i+1)
begin : genbit
fa fa_inst (a[i], b[i], c[i], sum[i], carry_temp[i+1]);
end
endgenerate
assign carry = {1'b0, carry_temp[WIDTH-1:1], 1'b0};
endmodule // csa

96
wally-pipelined/src/fpudivsqrt/exception.v
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@ -1,96 +0,0 @@
// Exception logic for the floating point adder. Note: We may
// actually want to move to where the result is computed.
module exception (Ztype, Invalid, Denorm, ANorm, BNorm, A, B, op_type);
input [63:0] A; // 1st input operand (op1)
input [63:0] B; // 2nd input operand (op2)
input op_type; // Determine operation
output [2:0] Ztype; // Indicates type of result (Z)
output Invalid; // Invalid operation exception
output Denorm; // Denormalized input
output ANorm; // A is not zero or Denorm
output BNorm; // B is not zero or Denorm
wire AzeroM; // '1' if the mantissa of A is zero
wire BzeroM; // '1' if the mantissa of B is zero
wire AzeroE; // '1' if the exponent of A is zero
wire BzeroE; // '1' if the exponent of B is zero
wire AonesE; // '1' if the exponent of A is all ones
wire BonesE; // '1' if the exponent of B is all ones
wire ADenorm; // '1' if A is a denomalized number
wire BDenorm; // '1' if B is a denomalized number
wire AInf; // '1' if A is infinite
wire BInf; // '1' if B is infinite
wire AZero; // '1' if A is 0
wire BZero; // '1' if B is 0
wire ANaN; // '1' if A is a not-a-number
wire BNaN; // '1' if B is a not-a-number
wire ASNaN; // '1' if A is a signalling not-a-number
wire BSNaN; // '1' if B is a signalling not-a-number
wire ZQNaN; // '1' if result Z is a quiet NaN
wire ZInf; // '1' if result Z is an infnity
wire square_root; // '1' if square root operation
wire Zero; // '1' if result is zero
parameter [51:0] fifty_two_zeros = 52'h0; // Use parameter?
// Determine if mantissas are all zeros
assign AzeroM = (A[51:0] == fifty_two_zeros);
assign BzeroM = (B[51:0] == fifty_two_zeros);
// Determine if exponents are all ones or all zeros
assign AonesE = A[62]&A[61]&A[60]&A[59]&A[58]&A[57]&A[56]&A[55]&A[54]&A[53]&A[52];
assign BonesE = B[62]&B[61]&B[60]&B[59]&B[58]&B[57]&B[56]&B[55]&B[54]&B[53]&B[52];
assign AzeroE = ~(A[62]|A[61]|A[60]|A[59]|A[58]|A[57]|A[56]|A[55]|A[54]|A[53]|A[52]);
assign BzeroE = ~(B[62]|B[61]|B[60]|B[59]|B[58]|B[57]|B[56]|B[55]|B[54]|B[53]|B[52]);
// Determine special cases. Note: Zero is not really a special case.
assign ADenorm = AzeroE & ~AzeroM;
assign BDenorm = BzeroE & ~BzeroM;
assign AInf = AonesE & AzeroM;
assign BInf = BonesE & BzeroM;
assign ANaN = AonesE & ~AzeroM;
assign BNaN = BonesE & ~BzeroM;
assign ASNaN = ANaN & A[50];
assign BSNaN = ANaN & A[50];
assign AZero = AzeroE & AzeroM;
assign BZero = BzeroE & BzeroE;
// A and B are normalized if their exponents are not zero.
assign ANorm = ~AzeroE;
assign BNorm = ~BzeroE;
// An "Invalid Operation" exception occurs if (A or B is a signalling NaN)
// or (A and B are both Infinite)
assign Invalid = ASNaN | BSNaN | (((AInf & BInf) | (AZero & BZero))&~op_type) |
(A[63] & op_type);
// The Denorm flag is set if A is denormlized or if B is normalized
assign Denorm = ADenorm | BDenorm;
// The result is a quiet NaN if (an "Invalid Operation" exception occurs)
// or (A is a NaN) or (B is a NaN).
assign ZQNaN = Invalid | ANaN | BNaN;
// The result is zero
assign Zero = (AZero | BInf)&~op_type | AZero&op_type;
// The result is +Inf if ((A is Inf) or (B is 0)) and (the
// result is not a quiet NaN).
assign ZInf = (AInf | BZero)&~ZQNaN&~op_type | AInf&op_type&~ZQNaN;
// Set the type of the result as follows:
// Ztype Result
// 000 Normal
// 001 Quiet NaN
// 010 Infinity
// 011 Zero
// 110 DivZero
assign Ztype[0] = ZQNaN | Zero;
assign Ztype[1] = ZInf | Zero;
assign Ztype[2] = BZero&~op_type;
endmodule // exception

57
wally-pipelined/src/fpudivsqrt/f32_div_rd.do
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@ -1,57 +0,0 @@
# Copyright 1991-2016 Mentor Graphics Corporation
#
# Modification by Oklahoma State University
# Use with Testbench
# James Stine, 2008
# Go Cowboys!!!!!!
#
# All Rights Reserved.
#
# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION
# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
# Use this run.do file to run this example.
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
# do run.do
# or, to run from a shell, type the following at the shell prompt:
# vsim -do run.do -c
# (omit the "-c" to see the GUI while running from the shell)
onbreak {resume}
# create library
if [file exists work] {
vdel -all
}
vlib work
# compile source files
vlog bk15.v mult_R4_64_64_cs.v ldf128.v ldf64.v sbtm_a1.sv sbtm_a0.sv sbtm.sv sbtm_a4.sv sbtm_a5.sv sbtm3.sv fsm.v divconvDP.sv convert_inputs.v exception.v rounder.v fpdiv.v tb_f32_div_rd.sv
# start and run simulation
vsim -voptargs=+acc work.tb
#view wave
-- display input and output signals as hexidecimal values
# Diplays All Signals recursively
-- Set Wave Output Items
TreeUpdate [SetDefaultTree]
WaveRestoreZoom {0 ps} {75 ns}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
-- Run the Simulation
-- 39,052 vectors, 390,565ns
run 269690000
quit

57
wally-pipelined/src/fpudivsqrt/f32_div_rne.do
View file

@ -1,57 +0,0 @@
# Copyright 1991-2016 Mentor Graphics Corporation
#
# Modification by Oklahoma State University
# Use with Testbench
# James Stine, 2008
# Go Cowboys!!!!!!
#
# All Rights Reserved.
#
# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION
# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
# Use this run.do file to run this example.
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
# do run.do
# or, to run from a shell, type the following at the shell prompt:
# vsim -do run.do -c
# (omit the "-c" to see the GUI while running from the shell)
onbreak {resume}
# create library
if [file exists work] {
vdel -all
}
vlib work
# compile source files
vlog bk15.v mult_R4_64_64_cs.v ldf128.v ldf64.v sbtm_a1.sv sbtm_a0.sv sbtm.sv sbtm_a4.sv sbtm_a5.sv sbtm3.sv fsm.v divconvDP.sv convert_inputs.v exception.v rounder.v fpdiv.v tb_f32_div_rne.sv
# start and run simulation
vsim -voptargs=+acc work.tb
#view wave
-- display input and output signals as hexidecimal values
# Diplays All Signals recursively
-- Set Wave Output Items
TreeUpdate [SetDefaultTree]
WaveRestoreZoom {0 ps} {75 ns}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
-- Run the Simulation
-- 39,052 vectors, 390,565ns
run 269690000
quit

57
wally-pipelined/src/fpudivsqrt/f32_div_ru.do
View file

@ -1,57 +0,0 @@
# Copyright 1991-2016 Mentor Graphics Corporation
#
# Modification by Oklahoma State University
# Use with Testbench
# James Stine, 2008
# Go Cowboys!!!!!!
#
# All Rights Reserved.
#
# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION
# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
# Use this run.do file to run this example.
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
# do run.do
# or, to run from a shell, type the following at the shell prompt:
# vsim -do run.do -c
# (omit the "-c" to see the GUI while running from the shell)
onbreak {resume}
# create library
if [file exists work] {
vdel -all
}
vlib work
# compile source files
vlog bk15.v mult_R4_64_64_cs.v ldf128.v ldf64.v sbtm_a1.sv sbtm_a0.sv sbtm.sv sbtm_a4.sv sbtm_a5.sv sbtm3.sv fsm.v divconvDP.sv convert_inputs.v exception.v rounder.v fpdiv.v tb_f32_div_ru.sv
# start and run simulation
vsim -voptargs=+acc work.tb
#view wave
-- display input and output signals as hexidecimal values
# Diplays All Signals recursively
-- Set Wave Output Items
TreeUpdate [SetDefaultTree]
WaveRestoreZoom {0 ps} {75 ns}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
-- Run the Simulation
-- 39,052 vectors, 390,565ns
run 269690000
quit

57
wally-pipelined/src/fpudivsqrt/f32_div_rz.do
View file

@ -1,57 +0,0 @@
# Copyright 1991-2016 Mentor Graphics Corporation
#
# Modification by Oklahoma State University
# Use with Testbench
# James Stine, 2008
# Go Cowboys!!!!!!
#
# All Rights Reserved.
#
# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION
# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
# Use this run.do file to run this example.
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
# do run.do
# or, to run from a shell, type the following at the shell prompt:
# vsim -do run.do -c
# (omit the "-c" to see the GUI while running from the shell)
onbreak {resume}
# create library
if [file exists work] {
vdel -all
}
vlib work
# compile source files
vlog bk15.v mult_R4_64_64_cs.v ldf128.v ldf64.v sbtm_a1.sv sbtm_a0.sv sbtm.sv sbtm_a4.sv sbtm_a5.sv sbtm3.sv fsm.v divconvDP.sv convert_inputs.v exception.v rounder.v fpdiv.v tb_f32_div_rz.sv
# start and run simulation
vsim -voptargs=+acc work.tb
#view wave
-- display input and output signals as hexidecimal values
# Diplays All Signals recursively
-- Set Wave Output Items
TreeUpdate [SetDefaultTree]
WaveRestoreZoom {0 ps} {75 ns}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
-- Run the Simulation
-- 39,052 vectors, 390,565ns
run 269690000
quit

56
wally-pipelined/src/fpudivsqrt/f32_sqrt_rd.do
View file

@ -1,56 +0,0 @@
# Copyright 1991-2016 Mentor Graphics Corporation
#
# Modification by Oklahoma State University
# Use with Testbench
# James Stine, 2008
# Go Cowboys!!!!!!
#
# All Rights Reserved.
#
# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION
# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
# Use this run.do file to run this example.
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
# do run.do
# or, to run from a shell, type the following at the shell prompt:
# vsim -do run.do -c
# (omit the "-c" to see the GUI while running from the shell)
onbreak {resume}
# create library
if [file exists work] {
vdel -all
}
vlib work
# compile source files
vlog bk15.v mult_R4_64_64_cs.v ldf128.v ldf64.v sbtm_a1.sv sbtm_a0.sv sbtm.sv sbtm_a4.sv sbtm_a5.sv sbtm3.sv fsm.v divconvDP.sv convert_inputs.v exception.v rounder.v fpdiv.v tb_f32_sqrt_rd.sv
# start and run simulation
vsim -voptargs=+acc work.tb
#view wave
-- display input and output signals as hexidecimal values
# Diplays All Signals recursively
-- Set Wave Output Items
TreeUpdate [SetDefaultTree]
WaveRestoreZoom {0 ps} {75 ns}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
-- Run the Simulation
-- 39,052 vectors, 390,565ns
run 234244000
quit

56
wally-pipelined/src/fpudivsqrt/f32_sqrt_rne.do
View file

@ -1,56 +0,0 @@
# Copyright 1991-2016 Mentor Graphics Corporation
#
# Modification by Oklahoma State University
# Use with Testbench
# James Stine, 2008
# Go Cowboys!!!!!!
#
# All Rights Reserved.
#
# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION
# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
# Use this run.do file to run this example.
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
# do run.do
# or, to run from a shell, type the following at the shell prompt:
# vsim -do run.do -c
# (omit the "-c" to see the GUI while running from the shell)
onbreak {resume}
# create library
if [file exists work] {
vdel -all
}
vlib work
# compile source files
vlog bk15.v mult_R4_64_64_cs.v ldf128.v ldf64.v sbtm_a1.sv sbtm_a0.sv sbtm.sv sbtm_a4.sv sbtm_a5.sv sbtm3.sv fsm.v divconvDP.sv convert_inputs.v exception.v rounder.v fpdiv.v tb_f32_sqrt_rne.sv
# start and run simulation
vsim -voptargs=+acc work.tb
#view wave
-- display input and output signals as hexidecimal values
# Diplays All Signals recursively
-- Set Wave Output Items
TreeUpdate [SetDefaultTree]
WaveRestoreZoom {0 ps} {75 ns}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
-- Run the Simulation
-- 39,052 vectors, 390,565ns
run 234244000
quit

56
wally-pipelined/src/fpudivsqrt/f32_sqrt_ru.do
View file

@ -1,56 +0,0 @@
# Copyright 1991-2016 Mentor Graphics Corporation
#
# Modification by Oklahoma State University
# Use with Testbench
# James Stine, 2008
# Go Cowboys!!!!!!
#
# All Rights Reserved.
#
# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION
# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
# Use this run.do file to run this example.
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
# do run.do
# or, to run from a shell, type the following at the shell prompt:
# vsim -do run.do -c
# (omit the "-c" to see the GUI while running from the shell)
onbreak {resume}
# create library
if [file exists work] {
vdel -all
}
vlib work
# compile source files
vlog bk15.v mult_R4_64_64_cs.v ldf128.v ldf64.v sbtm_a1.sv sbtm_a0.sv sbtm.sv sbtm_a4.sv sbtm_a5.sv sbtm3.sv fsm.v divconvDP.sv convert_inputs.v exception.v rounder.v fpdiv.v tb_f32_sqrt_ru.sv
# start and run simulation
vsim -voptargs=+acc work.tb
#view wave
-- display input and output signals as hexidecimal values
# Diplays All Signals recursively
-- Set Wave Output Items
TreeUpdate [SetDefaultTree]
WaveRestoreZoom {0 ps} {75 ns}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
-- Run the Simulation
-- 39,052 vectors, 390,565ns
run 234244000
quit

56
wally-pipelined/src/fpudivsqrt/f32_sqrt_rz.do
View file

@ -1,56 +0,0 @@
# Copyright 1991-2016 Mentor Graphics Corporation
#
# Modification by Oklahoma State University
# Use with Testbench
# James Stine, 2008
# Go Cowboys!!!!!!
#
# All Rights Reserved.
#
# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION
# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
# Use this run.do file to run this example.
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
# do run.do
# or, to run from a shell, type the following at the shell prompt:
# vsim -do run.do -c
# (omit the "-c" to see the GUI while running from the shell)
onbreak {resume}
# create library
if [file exists work] {
vdel -all
}
vlib work
# compile source files
vlog bk15.v mult_R4_64_64_cs.v ldf128.v ldf64.v sbtm_a1.sv sbtm_a0.sv sbtm.sv sbtm_a4.sv sbtm_a5.sv sbtm3.sv fsm.v divconvDP.sv convert_inputs.v exception.v rounder.v fpdiv.v tb_f32_sqrt_rz.sv
# start and run simulation
vsim -voptargs=+acc work.tb
#view wave
-- display input and output signals as hexidecimal values
# Diplays All Signals recursively
-- Set Wave Output Items
TreeUpdate [SetDefaultTree]
WaveRestoreZoom {0 ps} {75 ns}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
-- Run the Simulation
-- 39,052 vectors, 390,565ns
run 234244000
quit

57
wally-pipelined/src/fpudivsqrt/f64_div_rd.do
View file

@ -1,57 +0,0 @@
# Copyright 1991-2016 Mentor Graphics Corporation
#
# Modification by Oklahoma State University
# Use with Testbench
# James Stine, 2008
# Go Cowboys!!!!!!
#
# All Rights Reserved.
#
# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION
# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
# Use this run.do file to run this example.
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
# do run.do
# or, to run from a shell, type the following at the shell prompt:
# vsim -do run.do -c
# (omit the "-c" to see the GUI while running from the shell)
onbreak {resume}
# create library
if [file exists work] {
vdel -all
}
vlib work
# compile source files
vlog bk15.v mult_R4_64_64_cs.v ldf128.v ldf64.v sbtm_a1.sv sbtm_a0.sv sbtm.sv sbtm_a4.sv sbtm_a5.sv sbtm3.sv fsm.v divconvDP.sv convert_inputs.v exception.v rounder.v fpdiv.v tb_f64_div_rd.sv
# start and run simulation
vsim -voptargs=+acc work.tb
#view wave
-- display input and output signals as hexidecimal values
# Diplays All Signals recursively
-- Set Wave Output Items
TreeUpdate [SetDefaultTree]
WaveRestoreZoom {0 ps} {75 ns}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
-- Run the Simulation
-- 39,052 vectors, 390,565ns
run 338600000
quit

57
wally-pipelined/src/fpudivsqrt/f64_div_rne.do
View file

@ -1,57 +0,0 @@
# Copyright 1991-2016 Mentor Graphics Corporation
#
# Modification by Oklahoma State University
# Use with Testbench
# James Stine, 2008
# Go Cowboys!!!!!!
#
# All Rights Reserved.
#
# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION
# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
# Use this run.do file to run this example.
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
# do run.do
# or, to run from a shell, type the following at the shell prompt:
# vsim -do run.do -c
# (omit the "-c" to see the GUI while running from the shell)
onbreak {resume}
# create library
if [file exists work] {
vdel -all
}
vlib work
# compile source files
vlog bk15.v mult_R4_64_64_cs.v ldf128.v ldf64.v sbtm_a1.sv sbtm_a0.sv sbtm.sv sbtm_a4.sv sbtm_a5.sv sbtm3.sv fsm.v divconvDP.sv convert_inputs.v exception.v rounder.v fpdiv.v tb_f64_div_rne.sv
# start and run simulation
vsim -voptargs=+acc work.tb
#view wave
-- display input and output signals as hexidecimal values
# Diplays All Signals recursively
-- Set Wave Output Items
TreeUpdate [SetDefaultTree]
WaveRestoreZoom {0 ps} {75 ns}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
-- Run the Simulation
-- 39,052 vectors, 390,565ns
run 338600000
quit

57
wally-pipelined/src/fpudivsqrt/f64_div_ru.do
View file

@ -1,57 +0,0 @@
# Copyright 1991-2016 Mentor Graphics Corporation
#
# Modification by Oklahoma State University
# Use with Testbench
# James Stine, 2008
# Go Cowboys!!!!!!
#
# All Rights Reserved.
#
# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION
# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
# Use this run.do file to run this example.
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
# do run.do
# or, to run from a shell, type the following at the shell prompt:
# vsim -do run.do -c
# (omit the "-c" to see the GUI while running from the shell)
onbreak {resume}
# create library
if [file exists work] {
vdel -all
}
vlib work
# compile source files
vlog bk15.v mult_R4_64_64_cs.v ldf128.v ldf64.v sbtm_a1.sv sbtm_a0.sv sbtm.sv sbtm_a4.sv sbtm_a5.sv sbtm3.sv fsm.v divconvDP.sv convert_inputs.v exception.v rounder.v fpdiv.v tb_f64_div_ru.sv
# start and run simulation
vsim -voptargs=+acc work.tb
#view wave
-- display input and output signals as hexidecimal values
# Diplays All Signals recursively
-- Set Wave Output Items
TreeUpdate [SetDefaultTree]
WaveRestoreZoom {0 ps} {75 ns}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
-- Run the Simulation
-- 39,052 vectors, 390,565ns
run 338600000
quit

57
wally-pipelined/src/fpudivsqrt/f64_div_rz.do
View file

@ -1,57 +0,0 @@
# Copyright 1991-2016 Mentor Graphics Corporation
#
# Modification by Oklahoma State University
# Use with Testbench
# James Stine, 2008
# Go Cowboys!!!!!!
#
# All Rights Reserved.
#
# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION
# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
# Use this run.do file to run this example.
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
# do run.do
# or, to run from a shell, type the following at the shell prompt:
# vsim -do run.do -c
# (omit the "-c" to see the GUI while running from the shell)
onbreak {resume}
# create library
if [file exists work] {
vdel -all
}
vlib work
# compile source files
vlog bk15.v mult_R4_64_64_cs.v ldf128.v ldf64.v sbtm_a1.sv sbtm_a0.sv sbtm.sv sbtm_a4.sv sbtm_a5.sv sbtm3.sv fsm.v divconvDP.sv convert_inputs.v exception.v rounder.v fpdiv.v tb_f64_div_rz.sv
# start and run simulation
vsim -voptargs=+acc work.tb
#view wave
-- display input and output signals as hexidecimal values
# Diplays All Signals recursively
-- Set Wave Output Items
TreeUpdate [SetDefaultTree]
WaveRestoreZoom {0 ps} {75 ns}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
-- Run the Simulation
-- 39,052 vectors, 390,565ns
run 338600000
quit

56
wally-pipelined/src/fpudivsqrt/f64_sqrt_rd.do
View file

@ -1,56 +0,0 @@
# Copyright 1991-2016 Mentor Graphics Corporation
#
# Modification by Oklahoma State University
# Use with Testbench
# James Stine, 2008
# Go Cowboys!!!!!!
#
# All Rights Reserved.
#
# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION
# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
# Use this run.do file to run this example.
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
# do run.do
# or, to run from a shell, type the following at the shell prompt:
# vsim -do run.do -c
# (omit the "-c" to see the GUI while running from the shell)
onbreak {resume}
# create library
if [file exists work] {
vdel -all
}
vlib work
# compile source files
vlog bk15.v mult_R4_64_64_cs.v ldf128.v ldf64.v sbtm_a1.sv sbtm_a0.sv sbtm.sv sbtm_a4.sv sbtm_a5.sv sbtm3.sv fsm.v divconvDP.sv convert_inputs.v exception.v rounder.v fpdiv.v tb_f64_sqrt_rd.sv
# start and run simulation
vsim -voptargs=+acc work.tb
#view wave
-- display input and output signals as hexidecimal values
# Diplays All Signals recursively
-- Set Wave Output Items
TreeUpdate [SetDefaultTree]
WaveRestoreZoom {0 ps} {75 ns}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
-- Run the Simulation
-- 39,052 vectors, 390,565ns
run 4364000
quit

56
wally-pipelined/src/fpudivsqrt/f64_sqrt_rne.do
View file

@ -1,56 +0,0 @@
# Copyright 1991-2016 Mentor Graphics Corporation
#
# Modification by Oklahoma State University
# Use with Testbench
# James Stine, 2008
# Go Cowboys!!!!!!
#
# All Rights Reserved.
#
# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION
# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
# Use this run.do file to run this example.
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
# do run.do
# or, to run from a shell, type the following at the shell prompt:
# vsim -do run.do -c
# (omit the "-c" to see the GUI while running from the shell)
onbreak {resume}
# create library
if [file exists work] {
vdel -all
}
vlib work
# compile source files
vlog bk15.v mult_R4_64_64_cs.v ldf128.v ldf64.v sbtm_a1.sv sbtm_a0.sv sbtm.sv sbtm_a4.sv sbtm_a5.sv sbtm3.sv fsm.v divconvDP.sv convert_inputs.v exception.v rounder.v fpdiv.v tb_f64_sqrt_rne.sv
# start and run simulation
vsim -voptargs=+acc work.tb
#view wave
-- display input and output signals as hexidecimal values
# Diplays All Signals recursively
-- Set Wave Output Items
TreeUpdate [SetDefaultTree]
WaveRestoreZoom {0 ps} {75 ns}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
-- Run the Simulation
-- 39,052 vectors, 390,565ns
run 4364000
quit

56
wally-pipelined/src/fpudivsqrt/f64_sqrt_ru.do
View file

@ -1,56 +0,0 @@
# Copyright 1991-2016 Mentor Graphics Corporation
#
# Modification by Oklahoma State University
# Use with Testbench
# James Stine, 2008
# Go Cowboys!!!!!!
#
# All Rights Reserved.
#
# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION
# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
# Use this run.do file to run this example.
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
# do run.do
# or, to run from a shell, type the following at the shell prompt:
# vsim -do run.do -c
# (omit the "-c" to see the GUI while running from the shell)
onbreak {resume}
# create library
if [file exists work] {
vdel -all
}
vlib work
# compile source files
vlog bk15.v mult_R4_64_64_cs.v ldf128.v ldf64.v sbtm_a1.sv sbtm_a0.sv sbtm.sv sbtm_a4.sv sbtm_a5.sv sbtm3.sv fsm.v divconvDP.sv convert_inputs.v exception.v rounder.v fpdiv.v tb_f64_sqrt_ru.sv
# start and run simulation
vsim -voptargs=+acc work.tb
#view wave
-- display input and output signals as hexidecimal values
# Diplays All Signals recursively
-- Set Wave Output Items
TreeUpdate [SetDefaultTree]
WaveRestoreZoom {0 ps} {75 ns}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
-- Run the Simulation
-- 39,052 vectors, 390,565ns
run 4364000
quit

56
wally-pipelined/src/fpudivsqrt/f64_sqrt_rz.do
View file

@ -1,56 +0,0 @@
# Copyright 1991-2016 Mentor Graphics Corporation
#
# Modification by Oklahoma State University
# Use with Testbench
# James Stine, 2008
# Go Cowboys!!!!!!
#
# All Rights Reserved.
#
# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION
# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
# Use this run.do file to run this example.
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
# do run.do
# or, to run from a shell, type the following at the shell prompt:
# vsim -do run.do -c
# (omit the "-c" to see the GUI while running from the shell)
onbreak {resume}
# create library
if [file exists work] {
vdel -all
}
vlib work
# compile source files
vlog bk15.v mult_R4_64_64_cs.v ldf128.v ldf64.v sbtm_a1.sv sbtm_a0.sv sbtm.sv sbtm_a4.sv sbtm_a5.sv sbtm3.sv fsm.v divconvDP.sv convert_inputs.v exception.v rounder.v fpdiv.v tb_f64_sqrt_rz.sv
# start and run simulation
vsim -voptargs=+acc work.tb
#view wave
-- display input and output signals as hexidecimal values
# Diplays All Signals recursively
-- Set Wave Output Items
TreeUpdate [SetDefaultTree]
WaveRestoreZoom {0 ps} {75 ns}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
-- Run the Simulation
-- 39,052 vectors, 390,565ns
run 4364000
quit

94
wally-pipelined/src/fpudivsqrt/fpdiv.do
View file

@ -1,94 +0,0 @@
# Copyright 1991-2016 Mentor Graphics Corporation
#
# Modification by Oklahoma State University
# Use with Testbench
# James Stine, 2008
# Go Cowboys!!!!!!
#
# All Rights Reserved.
#
# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION
# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
# Use this run.do file to run this example.
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
# do run.do
# or, to run from a shell, type the following at the shell prompt:
# vsim -do run.do -c
# (omit the "-c" to see the GUI while running from the shell)
onbreak {resume}
# create library
if [file exists work] {
vdel -all
}
vlib work
# compile source files
vlog bk15.v mult_R4_64_64_cs.v ldf128.v ldf64.v sbtm_a1.sv sbtm_a0.sv sbtm.sv sbtm_a4.sv sbtm_a5.sv sbtm3.sv fsm.v divconvDP.sv convert_inputs.v exception.v rounder.v fpdiv.v test_fpdiv.sv
# start and run simulation
vsim -voptargs=+acc work.tb
view wave
-- display input and output signals as hexidecimal values
# Diplays All Signals recursively
add wave -hex -color gold /tb/dut/clk
add wave -hex -color gold /tb/dut/mantissaA
add wave -hex -color gold /tb/dut/mantissaB
add wave -hex -color gold /tb/dut/op1
add wave -hex -color gold /tb/dut/op2
add wave -hex -color gold /tb/dut/AS_Result
add wave -hex -color gold /tb/dut/Flags
add wave -hex -color gold /tb/dut/Denorm
#add wave -noupdate -divider -height 32 "exponent"
#add wave -hex /tb/dut/exp1
#add wave -hex /tb/dut/exp2
#add wave -hex /tb/dut/expF
#add wave -hex /tb/dut/bias
#add wave -hex /tb/dut/exp_diff
#add wave -hex /tb/dut/exp_odd
#add wave -hex -r /tb/dut/explogic2/*
#add wave -hex -r /tb/dut/explogic1/*
add wave -noupdate -divider -height 32 "FSM"
add wave -hex /tb/dut/control/CURRENT_STATE
add wave -hex /tb/dut/control/NEXT_STATE
add wave -hex -color #0080ff /tb/dut/control/start
add wave -hex -color #0080ff /tb/dut/control/reset
add wave -hex -color #0080ff /tb/dut/control/op_type
add wave -hex -color #0080ff /tb/dut/control/load_rega
add wave -hex -color #0080ff /tb/dut/control/load_regb
add wave -hex -color #0080ff /tb/dut/control/load_regc
add wave -hex -color #0080ff /tb/dut/control/load_regr
add wave -hex -color #0080ff /tb/dut/control/load_regs
add wave -hex -color #0080ff /tb/dut/control/sel_muxa
add wave -hex -color #0080ff /tb/dut/control/sel_muxb
add wave -hex -color #0080ff /tb/dut/control/sel_muxr
add wave -hex -color #0080ff /tb/dut/control/done
add wave -noupdate -divider -height 32 "Convert"
add wave -hex -r /tb/dut/conv1/*
add wave -noupdate -divider -height 32 "Exceptions"
add wave -hex -r /tb/dut/exc1/*
add wave -noupdate -divider -height 32 "Rounder"
add wave -hex -r /tb/dut/round1/*
add wave -noupdate -divider -height 32 "Goldschmidt"
add wave -hex -r /tb/dut/goldy/*
-- Set Wave Output Items
TreeUpdate [SetDefaultTree]
WaveRestoreZoom {0 ps} {75 ns}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
-- Run the Simulation
run 14ns
quit

3400
wally-pipelined/src/fpudivsqrt/fpdiv.out
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File diff suppressed because it is too large Load diff

248
wally-pipelined/src/fpudivsqrt/fpdiv.v
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@ -1,248 +0,0 @@
//
// File name : fpdiv
// Title : Floating-Point Divider/Square-Root
// project : FPU
// Library : fpdiv
// Author(s) : James E. Stine, Jr.
// Purpose : definition of main unit to floating-point div/sqrt
// notes :
//
// Copyright Oklahoma State University
//
// Basic Operations
//
// Step 1: Load operands, set flags, and convert SP to DP
// Step 2: Check for special inputs ( +/- Infinity, NaN)
// Step 3: Exponent Logic
// Step 4: Divide/Sqrt using Goldschmidt
// Step 5: Normalize the result.//
// Shift left until normalized. Normalized when the value to the
// left of the binrary point is 1.
// Step 6: Round the result.//
// Step 7: Put quotient/remainder onto output.
//
`timescale 1ps/1ps
module fpdiv (done, AS_Result, Flags, Denorm, op1, op2, rm, op_type, P, OvEn, UnEn,
start, reset, clk);
input [63:0] op1; // 1st input operand (A)
input [63:0] op2; // 2nd input operand (B)
input [1:0] rm; // Rounding mode - specify values
input op_type; // Function opcode
input P; // Result Precision (0 for double, 1 for single)
input OvEn; // Overflow trap enabled
input UnEn; // Underflow trap enabled
input start;
input reset;
input clk;
output [63:0] AS_Result; // Result of operation
output [4:0] Flags; // IEEE exception flags
output Denorm; // Denorm on input or output
output done;
supply1 vdd;
supply0 vss;
wire [63:0] Float1;
wire [63:0] Float2;
wire [63:0] IntValue;
wire [12:0] exp1, exp2, expF;
wire [12:0] exp_diff, bias;
wire [13:0] exp_sqrt;
wire [12:0] exp_s;
wire [12:0] exp_c;
wire [10:0] exponent, exp_pre;
wire [63:0] Result;
wire [52:0] mantissaA;
wire [52:0] mantissaB;
wire [63:0] sum, sum_tc, sum_corr, sum_norm;
wire [5:0] align_shift;
wire [5:0] norm_shift;
wire [2:0] sel_inv;
wire op1_Norm, op2_Norm;
wire opA_Norm, opB_Norm;
wire Invalid;
wire DenormIn, DenormIO;
wire [4:0] FlagsIn;
wire exp_gt63;
wire Sticky_out;
wire signResult, sign_corr;
wire corr_sign;
wire zeroB;
wire convert;
wire swap;
wire sub;
wire [63:0] q1, qm1, qp1, q0, qm0, qp0;
wire [63:0] rega_out, regb_out, regc_out, regd_out;
wire [127:0] regr_out;
wire [2:0] sel_muxa, sel_muxb;
wire sel_muxr;
wire load_rega, load_regb, load_regc, load_regd, load_regr;
wire donev, sel_muxrv, sel_muxsv;
wire [1:0] sel_muxav, sel_muxbv;
wire load_regav, load_regbv, load_regcv;
wire load_regrv, load_regsv;
// Convert the input operands to their appropriate forms based on
// the orignal operands, the op_type , and their precision P.
// Single precision inputs are converted to double precision
// and the sign of the first operand is set appropratiately based on
// if the operation is absolute value or negation.
convert_inputs conv1 (Float1, Float2, op1, op2, op_type, P);
// Test for exceptions and return the "Invalid Operation" and
// "Denormalized" Input Flags. The "sel_inv" is used in
// the third pipeline stage to select the result. Also, op1_Norm
// and op2_Norm are one if op1 and op2 are not zero or denormalized.
// sub is one if the effective operation is subtaction.
exception exc1 (sel_inv, Invalid, DenormIn, op1_Norm, op2_Norm,
Float1, Float2, op_type);
// Determine Sign/Mantissa
assign signResult = ((Float1[63]^Float2[63])&~op_type) | Float1[63]&op_type;
assign mantissaA = {vdd, Float1[51:0]};
assign mantissaB = {vdd, Float2[51:0]};
// Perform Exponent Subtraction - expA - expB + Bias
assign exp1 = {2'b0, Float1[62:52]};
assign exp2 = {2'b0, Float2[62:52]};
// bias : DP = 2^{11-1}-1 = 1023
assign bias = {3'h0, 10'h3FF};
// Divide exponent
csa #(13) csa1 (exp1, ~exp2, bias, exp_s, exp_c);
exp_add explogic1 (exp_cout1, {open, exp_diff},
{vss, exp_s}, {vss, exp_c}, 1'b1);
// Sqrt exponent (check if exponent is odd)
assign exp_odd = Float1[52] ? vss : vdd;
exp_add explogic2 (exp_cout2, exp_sqrt,
{vss, exp1}, {4'h0, 10'h3ff}, exp_odd);
// Choose correct exponent
assign expF = op_type ? exp_sqrt[13:1] : exp_diff;
// Main Goldschmidt/Division Routine
divconv goldy (q1, qm1, qp1, q0, qm0, qp0,
rega_out, regb_out, regc_out, regd_out,
regr_out, mantissaB, mantissaA,
sel_muxa, sel_muxb, sel_muxr,
reset, clk,
load_rega, load_regb, load_regc, load_regd,
load_regr, load_regs, P, op_type, exp_odd);
// FSM : control divider
fsm control (done, load_rega, load_regb, load_regc, load_regd,
load_regr, load_regs, sel_muxa, sel_muxb, sel_muxr,
clk, reset, start, error, op_type);
// Round the mantissa to a 52-bit value, with the leading one
// removed. The rounding units also handles special cases and
// set the exception flags.
rounder round1 (Result, DenormIO, FlagsIn,
rm, P, OvEn, UnEn, expF,
sel_inv, Invalid, DenormIn, signResult,
q1, qm1, qp1, q0, qm0, qp0, regr_out);
// Store the final result and the exception flags in registers.
flopenr #(64) rega (clk, reset, done, Result, AS_Result);
flopenr #(1) regb (clk, reset, done, DenormIO, Denorm);
flopenr #(5) regc (clk, reset, done, FlagsIn, Flags);
endmodule // fpadd
//
// Brent-Kung Prefix Adder
// (yes, it is 14 bits as my generator is broken for 13 bits :(
// assume, synthesizer will delete stuff not needed )
//
module exp_add (cout, sum, a, b, cin);
input [13:0] a, b;
input cin;
output [13:0] sum;
output cout;
wire [14:0] p,g;
wire [13:0] c;
// pre-computation
assign p={a^b,1'b0};
assign g={a&b, cin};
// prefix tree
brent_kung prefix_tree(c, p[13:0], g[13:0]);
// post-computation
assign sum=p[14:1]^c;
assign cout=g[14]|(p[14]&c[13]);
endmodule // exp_add
module brent_kung (c, p, g);
input [13:0] p;
input [13:0] g;
output [14:1] c;
// parallel-prefix, Brent-Kung
// Stage 1: Generates G/P pairs that span 1 bits
grey b_1_0 (G_1_0, {g[1],g[0]}, p[1]);
black b_3_2 (G_3_2, P_3_2, {g[3],g[2]}, {p[3],p[2]});
black b_5_4 (G_5_4, P_5_4, {g[5],g[4]}, {p[5],p[4]});
black b_7_6 (G_7_6, P_7_6, {g[7],g[6]}, {p[7],p[6]});
black b_9_8 (G_9_8, P_9_8, {g[9],g[8]}, {p[9],p[8]});
black b_11_10 (G_11_10, P_11_10, {g[11],g[10]}, {p[11],p[10]});
black b_13_12 (G_13_12, P_13_12, {g[13],g[12]}, {p[13],p[12]});
// Stage 2: Generates G/P pairs that span 2 bits
grey g_3_0 (G_3_0, {G_3_2,G_1_0}, P_3_2);
black b_7_4 (G_7_4, P_7_4, {G_7_6,G_5_4}, {P_7_6,P_5_4});
black b_11_8 (G_11_8, P_11_8, {G_11_10,G_9_8}, {P_11_10,P_9_8});
// Stage 3: Generates G/P pairs that span 4 bits
grey g_7_0 (G_7_0, {G_7_4,G_3_0}, P_7_4);
// Stage 4: Generates G/P pairs that span 8 bits
// Stage 5: Generates G/P pairs that span 4 bits
grey g_11_0 (G_11_0, {G_11_8,G_7_0}, P_11_8);
// Stage 6: Generates G/P pairs that span 2 bits
grey g_5_0 (G_5_0, {G_5_4,G_3_0}, P_5_4);
grey g_9_0 (G_9_0, {G_9_8,G_7_0}, P_9_8);
grey g_13_0 (G_13_0, {G_13_12,G_11_0}, P_13_12);
// Last grey cell stage
grey g_2_0 (G_2_0, {g[2],G_1_0}, p[2]);
grey g_4_0 (G_4_0, {g[4],G_3_0}, p[4]);
grey g_6_0 (G_6_0, {g[6],G_5_0}, p[6]);
grey g_8_0 (G_8_0, {g[8],G_7_0}, p[8]);
grey g_10_0 (G_10_0, {g[10],G_9_0}, p[10]);
grey g_12_0 (G_12_0, {g[12],G_11_0}, p[12]);
// Final Stage: Apply c_k+1=G_k_0
assign c[1]=g[0];
assign c[2]=G_1_0;
assign c[3]=G_2_0;
assign c[4]=G_3_0;
assign c[5]=G_4_0;
assign c[6]=G_5_0;
assign c[7]=G_6_0;
assign c[8]=G_7_0;
assign c[9]=G_8_0;
assign c[10]=G_9_0;
assign c[11]=G_10_0;
assign c[12]=G_11_0;
assign c[13]=G_12_0;
assign c[14]=G_13_0;
endmodule // brent_kung

459
wally-pipelined/src/fpudivsqrt/fsm.v
View file

@ -1,459 +0,0 @@
module fsm (done, load_rega, load_regb, load_regc,
load_regd, load_regr, load_regs,
sel_muxa, sel_muxb, sel_muxr,
clk, reset, start, error, op_type);
input clk;
input reset;
input start;
input error;
input op_type;
output done;
output load_rega;
output load_regb;
output load_regc;
output load_regd;
output load_regr;
output load_regs;
output [2:0] sel_muxa;
output [2:0] sel_muxb;
output sel_muxr;
reg done; // End of cycles
reg load_rega; // enable for regA
reg load_regb; // enable for regB
reg load_regc; // enable for regC
reg load_regd; // enable for regD
reg load_regr; // enable for rem
reg load_regs; // enable for q,qm,qp
reg [2:0] sel_muxa; // Select muxA
reg [2:0] sel_muxb; // Select muxB
reg sel_muxr; // Select rem mux
reg [4:0] CURRENT_STATE;
reg [4:0] NEXT_STATE;
parameter [4:0]
S0=5'd0, S1=5'd1, S2=5'd2,
S3=5'd3, S4=5'd4, S5=5'd5,
S6=5'd6, S7=5'd7, S8=5'd8,
S9=5'd9, S10=5'd10,
S13=5'd13, S14=5'd14, S15=5'd15,
S16=5'd16, S17=5'd17, S18=5'd18,
S19=5'd19, S20=5'd20, S21=5'd21,
S22=5'd22, S23=5'd23, S24=5'd24,
S25=5'd25, S26=5'd26, S27=5'd27,
S28=5'd28, S29=5'd29, S30=5'd30;
always @(posedge clk)
begin
if(reset==1'b1)
CURRENT_STATE<=S0;
else
CURRENT_STATE<=NEXT_STATE;
end
always @(*)
begin
case(CURRENT_STATE)
S0: // iteration 0
begin
if (start==1'b0)
begin
done = 1'b0;
load_rega = 1'b0;
load_regb = 1'b0;
load_regc = 1'b0;
load_regd = 1'b0;
load_regr = 1'b0;
load_regs = 1'b0;
sel_muxa = 3'b000;
sel_muxb = 3'b000;
sel_muxr = 1'b0;
NEXT_STATE <= S0;
end
else if (start==1'b1 && op_type==1'b0)
begin
done = 1'b0;
load_rega = 1'b0;
load_regb = 1'b1;
load_regc = 1'b0;
load_regd = 1'b0;
load_regr = 1'b0;
load_regs = 1'b0;
sel_muxa = 3'b001;
sel_muxb = 3'b001;
sel_muxr = 1'b0;
NEXT_STATE <= S1;
end // if (start==1'b1 && op_type==1'b0)
else if (start==1'b1 && op_type==1'b1)
begin
done = 1'b0;
load_rega = 1'b0;
load_regb = 1'b1;
load_regc = 1'b0;
load_regd = 1'b0;
load_regr = 1'b0;
load_regs = 1'b0;
sel_muxa = 3'b010;
sel_muxb = 3'b000;
sel_muxr = 1'b0;
NEXT_STATE <= S13;
end
end // case: S0
S1:
begin
done = 1'b0;
load_rega = 1'b1;
load_regb = 1'b0;
load_regc = 1'b1;
load_regd = 1'b0;
load_regr = 1'b0;
load_regs = 1'b0;
sel_muxa = 3'b010;
sel_muxb = 3'b000;
sel_muxr = 1'b0;
NEXT_STATE <= S2;
end
S2: // iteration 1
begin
done = 1'b0;
load_rega = 1'b0;
load_regb = 1'b1;
load_regc = 1'b0;
load_regd = 1'b0;
load_regr = 1'b0;
load_regs = 1'b0;
sel_muxa = 3'b011;
sel_muxb = 3'b011;
sel_muxr = 1'b0;
NEXT_STATE <= S3;
end
S3:
begin
done = 1'b0;
load_rega = 1'b1;
load_regb = 1'b0;
load_regc = 1'b1;
load_regd = 1'b0;
load_regr = 1'b0;
load_regs = 1'b0;
sel_muxa = 3'b000;
sel_muxb = 3'b010;
sel_muxr = 1'b0;
NEXT_STATE <= S4;
end
S4: // iteration 2
begin
done = 1'b0;
load_rega = 1'b0;
load_regb = 1'b1;
load_regc = 1'b0;
load_regd = 1'b0;
load_regr = 1'b0;
load_regs = 1'b0;
sel_muxa = 3'b011;
sel_muxb = 3'b011;
sel_muxr = 1'b0;
NEXT_STATE <= S5;
end
S5:
begin
done = 1'b0;
load_rega = 1'b1;
load_regb = 1'b0;
load_regc = 1'b1;
load_regd = 1'b0;
load_regr = 1'b0;
load_regs = 1'b0;
sel_muxa = 3'b000;
sel_muxb = 3'b010;
sel_muxr = 1'b0; // add
NEXT_STATE <= S6;
end
S6: // iteration 3
begin
done = 1'b0;
load_rega = 1'b0;
load_regb = 1'b1;
load_regc = 1'b0;
load_regd = 1'b0;
load_regr = 1'b0;
load_regs = 1'b0;
sel_muxa = 3'b011;
sel_muxb = 3'b011;
sel_muxr = 1'b0;
NEXT_STATE <= S8;
end
S7:
begin
done = 1'b0;
load_rega = 1'b1;
load_regb = 1'b0;
load_regc = 1'b1;
load_regd = 1'b0;
load_regr = 1'b0;
load_regs = 1'b0;
sel_muxa = 3'b000;
sel_muxb = 3'b010;
sel_muxr = 1'b0;
NEXT_STATE <= S8;
end // case: S7
S8: // q,qm,qp
begin
done = 1'b0;
load_rega = 1'b0;
load_regb = 1'b0;
load_regc = 1'b0;
load_regd = 1'b0;
load_regr = 1'b0;
load_regs = 1'b1;
sel_muxa = 3'b000;
sel_muxb = 3'b000;
sel_muxr = 1'b0;
NEXT_STATE <= S9;
end
S9: // rem
begin
done = 1'b0;
load_rega = 1'b0;
load_regb = 1'b0;
load_regc = 1'b0;
load_regd = 1'b0;
load_regr = 1'b1;
load_regs = 1'b0;
sel_muxa = 3'b000;
sel_muxb = 3'b000;
sel_muxr = 1'b1;
NEXT_STATE <= S10;
end
S10: // done
begin
done = 1'b1;
load_rega = 1'b0;
load_regb = 1'b0;
load_regc = 1'b0;
load_regd = 1'b0;
load_regr = 1'b0;
load_regs = 1'b0;
sel_muxa = 3'b000;
sel_muxb = 3'b000;
sel_muxr = 1'b0;
NEXT_STATE <= S0;
end
S13: // start of sqrt path
begin
done = 1'b0;
load_rega = 1'b0;
load_regb = 1'b0;
load_regc = 1'b0;
load_regd = 1'b1;
load_regr = 1'b0;
load_regs = 1'b0;
sel_muxa = 3'b010;
sel_muxb = 3'b001;
sel_muxr = 1'b0;
NEXT_STATE <= S14;
end
S14:
begin
done = 1'b0;
load_rega = 1'b1;
load_regb = 1'b0;
load_regc = 1'b1;
load_regd = 1'b0;
load_regr = 1'b0;
load_regs = 1'b0;
sel_muxa = 3'b001;
sel_muxb = 3'b100;
sel_muxr = 1'b0;
NEXT_STATE <= S15;
end
S15: // iteration 1
begin
done = 1'b0;
load_rega = 1'b0;
load_regb = 1'b1;
load_regc = 1'b0;
load_regd = 1'b0;
load_regr = 1'b0;
load_regs = 1'b0;
sel_muxa = 3'b011;
sel_muxb = 3'b011;
sel_muxr = 1'b0;
NEXT_STATE <= S16;
end
S16:
begin
done = 1'b0;
load_rega = 1'b0;
load_regb = 1'b0;
load_regc = 1'b0;
load_regd = 1'b1;
load_regr = 1'b0;
load_regs = 1'b0;
sel_muxa = 3'b000;
sel_muxb = 3'b011;
sel_muxr = 1'b0;
NEXT_STATE <= S17;
end
S17:
begin
done = 1'b0;
load_rega = 1'b1;
load_regb = 1'b0;
load_regc = 1'b1;
load_regd = 1'b0;
load_regr = 1'b0;
load_regs = 1'b0;
sel_muxa = 3'b100;
sel_muxb = 3'b010;
sel_muxr = 1'b0;
NEXT_STATE <= S18;
end
S18: // iteration 2
begin
done = 1'b0;
load_rega = 1'b0;
load_regb = 1'b1;
load_regc = 1'b0;
load_regd = 1'b0;
load_regr = 1'b0;
load_regs = 1'b0;
sel_muxa = 3'b011;
sel_muxb = 3'b011;
sel_muxr = 1'b0;
NEXT_STATE <= S19;
end
S19:
begin
done = 1'b0;
load_rega = 1'b0;
load_regb = 1'b0;
load_regc = 1'b0;
load_regd = 1'b1;
load_regr = 1'b0;
load_regs = 1'b0;
sel_muxa = 3'b000;
sel_muxb = 3'b011;
sel_muxr = 1'b0;
NEXT_STATE <= S20;
end
S20:
begin
done = 1'b0;
load_rega = 1'b1;
load_regb = 1'b0;
load_regc = 1'b1;
load_regd = 1'b0;
load_regr = 1'b0;
load_regs = 1'b0;
sel_muxa = 3'b100;
sel_muxb = 3'b010;
sel_muxr = 1'b0;
NEXT_STATE <= S21;
end
S21: // iteration 3
begin
done = 1'b0;
load_rega = 1'b0;
load_regb = 1'b1;
load_regc = 1'b0;
load_regd = 1'b0;
load_regr = 1'b0;
load_regs = 1'b0;
sel_muxa = 3'b011;
sel_muxb = 3'b011;
sel_muxr = 1'b0;
NEXT_STATE <= S22;
end
S22:
begin
done = 1'b0;
load_rega = 1'b0;
load_regb = 1'b0;
load_regc = 1'b0;
load_regd = 1'b1;
load_regr = 1'b0;
load_regs = 1'b0;
sel_muxa = 3'b000;
sel_muxb = 3'b011;
sel_muxr = 1'b0;
NEXT_STATE <= S23;
end
S23:
begin
done = 1'b0;
load_rega = 1'b1;
load_regb = 1'b0;
load_regc = 1'b1;
load_regd = 1'b0;
load_regr = 1'b0;
load_regs = 1'b0;
sel_muxa = 3'b100;
sel_muxb = 3'b010;
sel_muxr = 1'b0;
NEXT_STATE <= S24;
end
S24: // q,qm,qp
begin
done = 1'b0;
load_rega = 1'b0;
load_regb = 1'b0;
load_regc = 1'b0;
load_regd = 1'b0;
load_regr = 1'b0;
load_regs = 1'b1;
sel_muxa = 3'b000;
sel_muxb = 3'b000;
sel_muxr = 1'b0;
NEXT_STATE <= S25;
end
S25: // rem
begin
done = 1'b0;
load_rega = 1'b0;
load_regb = 1'b0;
load_regc = 1'b0;
load_regd = 1'b0;
load_regr = 1'b1;
load_regs = 1'b0;
sel_muxa = 3'b011;
sel_muxb = 3'b110;
sel_muxr = 1'b1;
NEXT_STATE <= S26;
end
S26: // done
begin
done = 1'b1;
load_rega = 1'b0;
load_regb = 1'b0;
load_regc = 1'b0;
load_regd = 1'b0;
load_regr = 1'b0;
load_regs = 1'b0;
sel_muxa = 3'b000;
sel_muxb = 3'b000;
sel_muxr = 1'b0;
NEXT_STATE <= S0;
end
default:
begin
done = 1'b0;
load_rega = 1'b0;
load_regb = 1'b0;
load_regc = 1'b0;
load_regd = 1'b0;
load_regr = 1'b0;
load_regs = 1'b0;
sel_muxa = 3'b000;
sel_muxb = 3'b000;
sel_muxr = 1'b0;
NEXT_STATE <= S0;
end
endcase // case(CURRENT_STATE)
end // always @ (CURRENT_STATE or X)
endmodule // fsm

543
wally-pipelined/src/fpudivsqrt/ldf128.v
View file

@ -1,543 +0,0 @@
// Ladner-Fischer Prefix Adder
module ldf128 (cout, sum, a, b, cin);
input [127:0] a, b;
input cin;
output [127:0] sum;
output cout;
wire [128:0] p,g;
wire [127:0] c;
// pre-computation
assign p={a^b,1'b0};
assign g={a&b, cin};
// prefix tree
ladner_fischer128 prefix_tree (c, p[127:0], g[127:0]);
// post-computation
assign sum=p[128:1]^c;
assign cout=g[128]|(p[128]&c[127]);
endmodule
module ladner_fischer128 (c, p, g);
input [127:0] p;
input [127:0] g;
output [128:1] c;
// parallel-prefix, Ladner-Fischer
// Stage 1: Generates G/P pairs that span 1 bits
grey b_1_0 (G_1_0, {g[1],g[0]}, p[1]);
black b_3_2 (G_3_2, P_3_2, {g[3],g[2]}, {p[3],p[2]});
black b_5_4 (G_5_4, P_5_4, {g[5],g[4]}, {p[5],p[4]});
black b_7_6 (G_7_6, P_7_6, {g[7],g[6]}, {p[7],p[6]});
black b_9_8 (G_9_8, P_9_8, {g[9],g[8]}, {p[9],p[8]});
black b_11_10 (G_11_10, P_11_10, {g[11],g[10]}, {p[11],p[10]});
black b_13_12 (G_13_12, P_13_12, {g[13],g[12]}, {p[13],p[12]});
black b_15_14 (G_15_14, P_15_14, {g[15],g[14]}, {p[15],p[14]});
black b_17_16 (G_17_16, P_17_16, {g[17],g[16]}, {p[17],p[16]});
black b_19_18 (G_19_18, P_19_18, {g[19],g[18]}, {p[19],p[18]});
black b_21_20 (G_21_20, P_21_20, {g[21],g[20]}, {p[21],p[20]});
black b_23_22 (G_23_22, P_23_22, {g[23],g[22]}, {p[23],p[22]});
black b_25_24 (G_25_24, P_25_24, {g[25],g[24]}, {p[25],p[24]});
black b_27_26 (G_27_26, P_27_26, {g[27],g[26]}, {p[27],p[26]});
black b_29_28 (G_29_28, P_29_28, {g[29],g[28]}, {p[29],p[28]});
black b_31_30 (G_31_30, P_31_30, {g[31],g[30]}, {p[31],p[30]});
black b_33_32 (G_33_32, P_33_32, {g[33],g[32]}, {p[33],p[32]});
black b_35_34 (G_35_34, P_35_34, {g[35],g[34]}, {p[35],p[34]});
black b_37_36 (G_37_36, P_37_36, {g[37],g[36]}, {p[37],p[36]});
black b_39_38 (G_39_38, P_39_38, {g[39],g[38]}, {p[39],p[38]});
black b_41_40 (G_41_40, P_41_40, {g[41],g[40]}, {p[41],p[40]});
black b_43_42 (G_43_42, P_43_42, {g[43],g[42]}, {p[43],p[42]});
black b_45_44 (G_45_44, P_45_44, {g[45],g[44]}, {p[45],p[44]});
black b_47_46 (G_47_46, P_47_46, {g[47],g[46]}, {p[47],p[46]});
black b_49_48 (G_49_48, P_49_48, {g[49],g[48]}, {p[49],p[48]});
black b_51_50 (G_51_50, P_51_50, {g[51],g[50]}, {p[51],p[50]});
black b_53_52 (G_53_52, P_53_52, {g[53],g[52]}, {p[53],p[52]});
black b_55_54 (G_55_54, P_55_54, {g[55],g[54]}, {p[55],p[54]});
black b_57_56 (G_57_56, P_57_56, {g[57],g[56]}, {p[57],p[56]});
black b_59_58 (G_59_58, P_59_58, {g[59],g[58]}, {p[59],p[58]});
black b_61_60 (G_61_60, P_61_60, {g[61],g[60]}, {p[61],p[60]});
black b_63_62 (G_63_62, P_63_62, {g[63],g[62]}, {p[63],p[62]});
black b_65_64 (G_65_64, P_65_64, {g[65],g[64]}, {p[65],p[64]});
black b_67_66 (G_67_66, P_67_66, {g[67],g[66]}, {p[67],p[66]});
black b_69_68 (G_69_68, P_69_68, {g[69],g[68]}, {p[69],p[68]});
black b_71_70 (G_71_70, P_71_70, {g[71],g[70]}, {p[71],p[70]});
black b_73_72 (G_73_72, P_73_72, {g[73],g[72]}, {p[73],p[72]});
black b_75_74 (G_75_74, P_75_74, {g[75],g[74]}, {p[75],p[74]});
black b_77_76 (G_77_76, P_77_76, {g[77],g[76]}, {p[77],p[76]});
black b_79_78 (G_79_78, P_79_78, {g[79],g[78]}, {p[79],p[78]});
black b_81_80 (G_81_80, P_81_80, {g[81],g[80]}, {p[81],p[80]});
black b_83_82 (G_83_82, P_83_82, {g[83],g[82]}, {p[83],p[82]});
black b_85_84 (G_85_84, P_85_84, {g[85],g[84]}, {p[85],p[84]});
black b_87_86 (G_87_86, P_87_86, {g[87],g[86]}, {p[87],p[86]});
black b_89_88 (G_89_88, P_89_88, {g[89],g[88]}, {p[89],p[88]});
black b_91_90 (G_91_90, P_91_90, {g[91],g[90]}, {p[91],p[90]});
black b_93_92 (G_93_92, P_93_92, {g[93],g[92]}, {p[93],p[92]});
black b_95_94 (G_95_94, P_95_94, {g[95],g[94]}, {p[95],p[94]});
black b_97_96 (G_97_96, P_97_96, {g[97],g[96]}, {p[97],p[96]});
black b_99_98 (G_99_98, P_99_98, {g[99],g[98]}, {p[99],p[98]});
black b_101_100 (G_101_100, P_101_100, {g[101],g[100]}, {p[101],p[100]});
black b_103_102 (G_103_102, P_103_102, {g[103],g[102]}, {p[103],p[102]});
black b_105_104 (G_105_104, P_105_104, {g[105],g[104]}, {p[105],p[104]});
black b_107_106 (G_107_106, P_107_106, {g[107],g[106]}, {p[107],p[106]});
black b_109_108 (G_109_108, P_109_108, {g[109],g[108]}, {p[109],p[108]});
black b_111_110 (G_111_110, P_111_110, {g[111],g[110]}, {p[111],p[110]});
black b_113_112 (G_113_112, P_113_112, {g[113],g[112]}, {p[113],p[112]});
black b_115_114 (G_115_114, P_115_114, {g[115],g[114]}, {p[115],p[114]});
black b_117_116 (G_117_116, P_117_116, {g[117],g[116]}, {p[117],p[116]});
black b_119_118 (G_119_118, P_119_118, {g[119],g[118]}, {p[119],p[118]});
black b_121_120 (G_121_120, P_121_120, {g[121],g[120]}, {p[121],p[120]});
black b_123_122 (G_123_122, P_123_122, {g[123],g[122]}, {p[123],p[122]});
black b_125_124 (G_125_124, P_125_124, {g[125],g[124]}, {p[125],p[124]});
black b_127_126 (G_127_126, P_127_126, {g[127],g[126]}, {p[127],p[126]});
// Stage 2: Generates G/P pairs that span 2 bits
grey g_3_0 (G_3_0, {G_3_2,G_1_0}, P_3_2);
black b_7_4 (G_7_4, P_7_4, {G_7_6,G_5_4}, {P_7_6,P_5_4});
black b_11_8 (G_11_8, P_11_8, {G_11_10,G_9_8}, {P_11_10,P_9_8});
black b_15_12 (G_15_12, P_15_12, {G_15_14,G_13_12}, {P_15_14,P_13_12});
black b_19_16 (G_19_16, P_19_16, {G_19_18,G_17_16}, {P_19_18,P_17_16});
black b_23_20 (G_23_20, P_23_20, {G_23_22,G_21_20}, {P_23_22,P_21_20});
black b_27_24 (G_27_24, P_27_24, {G_27_26,G_25_24}, {P_27_26,P_25_24});
black b_31_28 (G_31_28, P_31_28, {G_31_30,G_29_28}, {P_31_30,P_29_28});
black b_35_32 (G_35_32, P_35_32, {G_35_34,G_33_32}, {P_35_34,P_33_32});
black b_39_36 (G_39_36, P_39_36, {G_39_38,G_37_36}, {P_39_38,P_37_36});
black b_43_40 (G_43_40, P_43_40, {G_43_42,G_41_40}, {P_43_42,P_41_40});
black b_47_44 (G_47_44, P_47_44, {G_47_46,G_45_44}, {P_47_46,P_45_44});
black b_51_48 (G_51_48, P_51_48, {G_51_50,G_49_48}, {P_51_50,P_49_48});
black b_55_52 (G_55_52, P_55_52, {G_55_54,G_53_52}, {P_55_54,P_53_52});
black b_59_56 (G_59_56, P_59_56, {G_59_58,G_57_56}, {P_59_58,P_57_56});
black b_63_60 (G_63_60, P_63_60, {G_63_62,G_61_60}, {P_63_62,P_61_60});
black b_67_64 (G_67_64, P_67_64, {G_67_66,G_65_64}, {P_67_66,P_65_64});
black b_71_68 (G_71_68, P_71_68, {G_71_70,G_69_68}, {P_71_70,P_69_68});
black b_75_72 (G_75_72, P_75_72, {G_75_74,G_73_72}, {P_75_74,P_73_72});
black b_79_76 (G_79_76, P_79_76, {G_79_78,G_77_76}, {P_79_78,P_77_76});
black b_83_80 (G_83_80, P_83_80, {G_83_82,G_81_80}, {P_83_82,P_81_80});
black b_87_84 (G_87_84, P_87_84, {G_87_86,G_85_84}, {P_87_86,P_85_84});
black b_91_88 (G_91_88, P_91_88, {G_91_90,G_89_88}, {P_91_90,P_89_88});
black b_95_92 (G_95_92, P_95_92, {G_95_94,G_93_92}, {P_95_94,P_93_92});
black b_99_96 (G_99_96, P_99_96, {G_99_98,G_97_96}, {P_99_98,P_97_96});
black b_103_100 (G_103_100, P_103_100, {G_103_102,G_101_100}, {P_103_102,P_101_100});
black b_107_104 (G_107_104, P_107_104, {G_107_106,G_105_104}, {P_107_106,P_105_104});
black b_111_108 (G_111_108, P_111_108, {G_111_110,G_109_108}, {P_111_110,P_109_108});
black b_115_112 (G_115_112, P_115_112, {G_115_114,G_113_112}, {P_115_114,P_113_112});
black b_119_116 (G_119_116, P_119_116, {G_119_118,G_117_116}, {P_119_118,P_117_116});
black b_123_120 (G_123_120, P_123_120, {G_123_122,G_121_120}, {P_123_122,P_121_120});
black b_127_124 (G_127_124, P_127_124, {G_127_126,G_125_124}, {P_127_126,P_125_124});
// Stage 3: Generates G/P pairs that span 4 bits
grey g_5_0 (G_5_0, {G_5_4,G_3_0}, P_5_4);
grey g_7_0 (G_7_0, {G_7_4,G_3_0}, P_7_4);
black b_13_8 (G_13_8, P_13_8, {G_13_12,G_11_8}, {P_13_12,P_11_8});
black b_15_8 (G_15_8, P_15_8, {G_15_12,G_11_8}, {P_15_12,P_11_8});
black b_21_16 (G_21_16, P_21_16, {G_21_20,G_19_16}, {P_21_20,P_19_16});
black b_23_16 (G_23_16, P_23_16, {G_23_20,G_19_16}, {P_23_20,P_19_16});
black b_29_24 (G_29_24, P_29_24, {G_29_28,G_27_24}, {P_29_28,P_27_24});
black b_31_24 (G_31_24, P_31_24, {G_31_28,G_27_24}, {P_31_28,P_27_24});
black b_37_32 (G_37_32, P_37_32, {G_37_36,G_35_32}, {P_37_36,P_35_32});
black b_39_32 (G_39_32, P_39_32, {G_39_36,G_35_32}, {P_39_36,P_35_32});
black b_45_40 (G_45_40, P_45_40, {G_45_44,G_43_40}, {P_45_44,P_43_40});
black b_47_40 (G_47_40, P_47_40, {G_47_44,G_43_40}, {P_47_44,P_43_40});
black b_53_48 (G_53_48, P_53_48, {G_53_52,G_51_48}, {P_53_52,P_51_48});
black b_55_48 (G_55_48, P_55_48, {G_55_52,G_51_48}, {P_55_52,P_51_48});
black b_61_56 (G_61_56, P_61_56, {G_61_60,G_59_56}, {P_61_60,P_59_56});
black b_63_56 (G_63_56, P_63_56, {G_63_60,G_59_56}, {P_63_60,P_59_56});
black b_69_64 (G_69_64, P_69_64, {G_69_68,G_67_64}, {P_69_68,P_67_64});
black b_71_64 (G_71_64, P_71_64, {G_71_68,G_67_64}, {P_71_68,P_67_64});
black b_77_72 (G_77_72, P_77_72, {G_77_76,G_75_72}, {P_77_76,P_75_72});
black b_79_72 (G_79_72, P_79_72, {G_79_76,G_75_72}, {P_79_76,P_75_72});
black b_85_80 (G_85_80, P_85_80, {G_85_84,G_83_80}, {P_85_84,P_83_80});
black b_87_80 (G_87_80, P_87_80, {G_87_84,G_83_80}, {P_87_84,P_83_80});
black b_93_88 (G_93_88, P_93_88, {G_93_92,G_91_88}, {P_93_92,P_91_88});
black b_95_88 (G_95_88, P_95_88, {G_95_92,G_91_88}, {P_95_92,P_91_88});
black b_101_96 (G_101_96, P_101_96, {G_101_100,G_99_96}, {P_101_100,P_99_96});
black b_103_96 (G_103_96, P_103_96, {G_103_100,G_99_96}, {P_103_100,P_99_96});
black b_109_104 (G_109_104, P_109_104, {G_109_108,G_107_104}, {P_109_108,P_107_104});
black b_111_104 (G_111_104, P_111_104, {G_111_108,G_107_104}, {P_111_108,P_107_104});
black b_117_112 (G_117_112, P_117_112, {G_117_116,G_115_112}, {P_117_116,P_115_112});
black b_119_112 (G_119_112, P_119_112, {G_119_116,G_115_112}, {P_119_116,P_115_112});
black b_125_120 (G_125_120, P_125_120, {G_125_124,G_123_120}, {P_125_124,P_123_120});
black b_127_120 (G_127_120, P_127_120, {G_127_124,G_123_120}, {P_127_124,P_123_120});
// Stage 4: Generates G/P pairs that span 8 bits
grey g_9_0 (G_9_0, {G_9_8,G_7_0}, P_9_8);
grey g_11_0 (G_11_0, {G_11_8,G_7_0}, P_11_8);
grey g_13_0 (G_13_0, {G_13_8,G_7_0}, P_13_8);
grey g_15_0 (G_15_0, {G_15_8,G_7_0}, P_15_8);
black b_25_16 (G_25_16, P_25_16, {G_25_24,G_23_16}, {P_25_24,P_23_16});
black b_27_16 (G_27_16, P_27_16, {G_27_24,G_23_16}, {P_27_24,P_23_16});
black b_29_16 (G_29_16, P_29_16, {G_29_24,G_23_16}, {P_29_24,P_23_16});
black b_31_16 (G_31_16, P_31_16, {G_31_24,G_23_16}, {P_31_24,P_23_16});
black b_41_32 (G_41_32, P_41_32, {G_41_40,G_39_32}, {P_41_40,P_39_32});
black b_43_32 (G_43_32, P_43_32, {G_43_40,G_39_32}, {P_43_40,P_39_32});
black b_45_32 (G_45_32, P_45_32, {G_45_40,G_39_32}, {P_45_40,P_39_32});
black b_47_32 (G_47_32, P_47_32, {G_47_40,G_39_32}, {P_47_40,P_39_32});
black b_57_48 (G_57_48, P_57_48, {G_57_56,G_55_48}, {P_57_56,P_55_48});
black b_59_48 (G_59_48, P_59_48, {G_59_56,G_55_48}, {P_59_56,P_55_48});
black b_61_48 (G_61_48, P_61_48, {G_61_56,G_55_48}, {P_61_56,P_55_48});
black b_63_48 (G_63_48, P_63_48, {G_63_56,G_55_48}, {P_63_56,P_55_48});
black b_73_64 (G_73_64, P_73_64, {G_73_72,G_71_64}, {P_73_72,P_71_64});
black b_75_64 (G_75_64, P_75_64, {G_75_72,G_71_64}, {P_75_72,P_71_64});
black b_77_64 (G_77_64, P_77_64, {G_77_72,G_71_64}, {P_77_72,P_71_64});
black b_79_64 (G_79_64, P_79_64, {G_79_72,G_71_64}, {P_79_72,P_71_64});
black b_89_80 (G_89_80, P_89_80, {G_89_88,G_87_80}, {P_89_88,P_87_80});
black b_91_80 (G_91_80, P_91_80, {G_91_88,G_87_80}, {P_91_88,P_87_80});
black b_93_80 (G_93_80, P_93_80, {G_93_88,G_87_80}, {P_93_88,P_87_80});
black b_95_80 (G_95_80, P_95_80, {G_95_88,G_87_80}, {P_95_88,P_87_80});
black b_105_96 (G_105_96, P_105_96, {G_105_104,G_103_96}, {P_105_104,P_103_96});
black b_107_96 (G_107_96, P_107_96, {G_107_104,G_103_96}, {P_107_104,P_103_96});
black b_109_96 (G_109_96, P_109_96, {G_109_104,G_103_96}, {P_109_104,P_103_96});
black b_111_96 (G_111_96, P_111_96, {G_111_104,G_103_96}, {P_111_104,P_103_96});
black b_121_112 (G_121_112, P_121_112, {G_121_120,G_119_112}, {P_121_120,P_119_112});
black b_123_112 (G_123_112, P_123_112, {G_123_120,G_119_112}, {P_123_120,P_119_112});
black b_125_112 (G_125_112, P_125_112, {G_125_120,G_119_112}, {P_125_120,P_119_112});
black b_127_112 (G_127_112, P_127_112, {G_127_120,G_119_112}, {P_127_120,P_119_112});
// Stage 5: Generates G/P pairs that span 16 bits
grey g_17_0 (G_17_0, {G_17_16,G_15_0}, P_17_16);
grey g_19_0 (G_19_0, {G_19_16,G_15_0}, P_19_16);
grey g_21_0 (G_21_0, {G_21_16,G_15_0}, P_21_16);
grey g_23_0 (G_23_0, {G_23_16,G_15_0}, P_23_16);
grey g_25_0 (G_25_0, {G_25_16,G_15_0}, P_25_16);
grey g_27_0 (G_27_0, {G_27_16,G_15_0}, P_27_16);
grey g_29_0 (G_29_0, {G_29_16,G_15_0}, P_29_16);
grey g_31_0 (G_31_0, {G_31_16,G_15_0}, P_31_16);
black b_49_32 (G_49_32, P_49_32, {G_49_48,G_47_32}, {P_49_48,P_47_32});
black b_51_32 (G_51_32, P_51_32, {G_51_48,G_47_32}, {P_51_48,P_47_32});
black b_53_32 (G_53_32, P_53_32, {G_53_48,G_47_32}, {P_53_48,P_47_32});
black b_55_32 (G_55_32, P_55_32, {G_55_48,G_47_32}, {P_55_48,P_47_32});
black b_57_32 (G_57_32, P_57_32, {G_57_48,G_47_32}, {P_57_48,P_47_32});
black b_59_32 (G_59_32, P_59_32, {G_59_48,G_47_32}, {P_59_48,P_47_32});
black b_61_32 (G_61_32, P_61_32, {G_61_48,G_47_32}, {P_61_48,P_47_32});
black b_63_32 (G_63_32, P_63_32, {G_63_48,G_47_32}, {P_63_48,P_47_32});
black b_81_64 (G_81_64, P_81_64, {G_81_80,G_79_64}, {P_81_80,P_79_64});
black b_83_64 (G_83_64, P_83_64, {G_83_80,G_79_64}, {P_83_80,P_79_64});
black b_85_64 (G_85_64, P_85_64, {G_85_80,G_79_64}, {P_85_80,P_79_64});
black b_87_64 (G_87_64, P_87_64, {G_87_80,G_79_64}, {P_87_80,P_79_64});
black b_89_64 (G_89_64, P_89_64, {G_89_80,G_79_64}, {P_89_80,P_79_64});
black b_91_64 (G_91_64, P_91_64, {G_91_80,G_79_64}, {P_91_80,P_79_64});
black b_93_64 (G_93_64, P_93_64, {G_93_80,G_79_64}, {P_93_80,P_79_64});
black b_95_64 (G_95_64, P_95_64, {G_95_80,G_79_64}, {P_95_80,P_79_64});
black b_113_96 (G_113_96, P_113_96, {G_113_112,G_111_96}, {P_113_112,P_111_96});
black b_115_96 (G_115_96, P_115_96, {G_115_112,G_111_96}, {P_115_112,P_111_96});
black b_117_96 (G_117_96, P_117_96, {G_117_112,G_111_96}, {P_117_112,P_111_96});
black b_119_96 (G_119_96, P_119_96, {G_119_112,G_111_96}, {P_119_112,P_111_96});
black b_121_96 (G_121_96, P_121_96, {G_121_112,G_111_96}, {P_121_112,P_111_96});
black b_123_96 (G_123_96, P_123_96, {G_123_112,G_111_96}, {P_123_112,P_111_96});
black b_125_96 (G_125_96, P_125_96, {G_125_112,G_111_96}, {P_125_112,P_111_96});
black b_127_96 (G_127_96, P_127_96, {G_127_112,G_111_96}, {P_127_112,P_111_96});
// Stage 6: Generates G/P pairs that span 32 bits
grey g_33_0 (G_33_0, {G_33_32,G_31_0}, P_33_32);
grey g_35_0 (G_35_0, {G_35_32,G_31_0}, P_35_32);
grey g_37_0 (G_37_0, {G_37_32,G_31_0}, P_37_32);
grey g_39_0 (G_39_0, {G_39_32,G_31_0}, P_39_32);
grey g_41_0 (G_41_0, {G_41_32,G_31_0}, P_41_32);
grey g_43_0 (G_43_0, {G_43_32,G_31_0}, P_43_32);
grey g_45_0 (G_45_0, {G_45_32,G_31_0}, P_45_32);
grey g_47_0 (G_47_0, {G_47_32,G_31_0}, P_47_32);
grey g_49_0 (G_49_0, {G_49_32,G_31_0}, P_49_32);
grey g_51_0 (G_51_0, {G_51_32,G_31_0}, P_51_32);
grey g_53_0 (G_53_0, {G_53_32,G_31_0}, P_53_32);
grey g_55_0 (G_55_0, {G_55_32,G_31_0}, P_55_32);
grey g_57_0 (G_57_0, {G_57_32,G_31_0}, P_57_32);
grey g_59_0 (G_59_0, {G_59_32,G_31_0}, P_59_32);
grey g_61_0 (G_61_0, {G_61_32,G_31_0}, P_61_32);
grey g_63_0 (G_63_0, {G_63_32,G_31_0}, P_63_32);
black b_97_64 (G_97_64, P_97_64, {G_97_96,G_95_64}, {P_97_96,P_95_64});
black b_99_64 (G_99_64, P_99_64, {G_99_96,G_95_64}, {P_99_96,P_95_64});
black b_101_64 (G_101_64, P_101_64, {G_101_96,G_95_64}, {P_101_96,P_95_64});
black b_103_64 (G_103_64, P_103_64, {G_103_96,G_95_64}, {P_103_96,P_95_64});
black b_105_64 (G_105_64, P_105_64, {G_105_96,G_95_64}, {P_105_96,P_95_64});
black b_107_64 (G_107_64, P_107_64, {G_107_96,G_95_64}, {P_107_96,P_95_64});
black b_109_64 (G_109_64, P_109_64, {G_109_96,G_95_64}, {P_109_96,P_95_64});
black b_111_64 (G_111_64, P_111_64, {G_111_96,G_95_64}, {P_111_96,P_95_64});
black b_113_64 (G_113_64, P_113_64, {G_113_96,G_95_64}, {P_113_96,P_95_64});
black b_115_64 (G_115_64, P_115_64, {G_115_96,G_95_64}, {P_115_96,P_95_64});
black b_117_64 (G_117_64, P_117_64, {G_117_96,G_95_64}, {P_117_96,P_95_64});
black b_119_64 (G_119_64, P_119_64, {G_119_96,G_95_64}, {P_119_96,P_95_64});
black b_121_64 (G_121_64, P_121_64, {G_121_96,G_95_64}, {P_121_96,P_95_64});
black b_123_64 (G_123_64, P_123_64, {G_123_96,G_95_64}, {P_123_96,P_95_64});
black b_125_64 (G_125_64, P_125_64, {G_125_96,G_95_64}, {P_125_96,P_95_64});
black b_127_64 (G_127_64, P_127_64, {G_127_96,G_95_64}, {P_127_96,P_95_64});
// Stage 7: Generates G/P pairs that span 64 bits
grey g_65_0 (G_65_0, {G_65_64,G_63_0}, P_65_64);
grey g_67_0 (G_67_0, {G_67_64,G_63_0}, P_67_64);
grey g_69_0 (G_69_0, {G_69_64,G_63_0}, P_69_64);
grey g_71_0 (G_71_0, {G_71_64,G_63_0}, P_71_64);
grey g_73_0 (G_73_0, {G_73_64,G_63_0}, P_73_64);
grey g_75_0 (G_75_0, {G_75_64,G_63_0}, P_75_64);
grey g_77_0 (G_77_0, {G_77_64,G_63_0}, P_77_64);
grey g_79_0 (G_79_0, {G_79_64,G_63_0}, P_79_64);
grey g_81_0 (G_81_0, {G_81_64,G_63_0}, P_81_64);
grey g_83_0 (G_83_0, {G_83_64,G_63_0}, P_83_64);
grey g_85_0 (G_85_0, {G_85_64,G_63_0}, P_85_64);
grey g_87_0 (G_87_0, {G_87_64,G_63_0}, P_87_64);
grey g_89_0 (G_89_0, {G_89_64,G_63_0}, P_89_64);
grey g_91_0 (G_91_0, {G_91_64,G_63_0}, P_91_64);
grey g_93_0 (G_93_0, {G_93_64,G_63_0}, P_93_64);
grey g_95_0 (G_95_0, {G_95_64,G_63_0}, P_95_64);
grey g_97_0 (G_97_0, {G_97_64,G_63_0}, P_97_64);
grey g_99_0 (G_99_0, {G_99_64,G_63_0}, P_99_64);
grey g_101_0 (G_101_0, {G_101_64,G_63_0}, P_101_64);
grey g_103_0 (G_103_0, {G_103_64,G_63_0}, P_103_64);
grey g_105_0 (G_105_0, {G_105_64,G_63_0}, P_105_64);
grey g_107_0 (G_107_0, {G_107_64,G_63_0}, P_107_64);
grey g_109_0 (G_109_0, {G_109_64,G_63_0}, P_109_64);
grey g_111_0 (G_111_0, {G_111_64,G_63_0}, P_111_64);
grey g_113_0 (G_113_0, {G_113_64,G_63_0}, P_113_64);
grey g_115_0 (G_115_0, {G_115_64,G_63_0}, P_115_64);
grey g_117_0 (G_117_0, {G_117_64,G_63_0}, P_117_64);
grey g_119_0 (G_119_0, {G_119_64,G_63_0}, P_119_64);
grey g_121_0 (G_121_0, {G_121_64,G_63_0}, P_121_64);
grey g_123_0 (G_123_0, {G_123_64,G_63_0}, P_123_64);
grey g_125_0 (G_125_0, {G_125_64,G_63_0}, P_125_64);
grey g_127_0 (G_127_0, {G_127_64,G_63_0}, P_127_64);
// Extra grey cell stage
grey g_2_0 (G_2_0, {g[2],G_1_0}, p[2]);
grey g_4_0 (G_4_0, {g[4],G_3_0}, p[4]);
grey g_6_0 (G_6_0, {g[6],G_5_0}, p[6]);
grey g_8_0 (G_8_0, {g[8],G_7_0}, p[8]);
grey g_10_0 (G_10_0, {g[10],G_9_0}, p[10]);
grey g_12_0 (G_12_0, {g[12],G_11_0}, p[12]);
grey g_14_0 (G_14_0, {g[14],G_13_0}, p[14]);
grey g_16_0 (G_16_0, {g[16],G_15_0}, p[16]);
grey g_18_0 (G_18_0, {g[18],G_17_0}, p[18]);
grey g_20_0 (G_20_0, {g[20],G_19_0}, p[20]);
grey g_22_0 (G_22_0, {g[22],G_21_0}, p[22]);
grey g_24_0 (G_24_0, {g[24],G_23_0}, p[24]);
grey g_26_0 (G_26_0, {g[26],G_25_0}, p[26]);
grey g_28_0 (G_28_0, {g[28],G_27_0}, p[28]);
grey g_30_0 (G_30_0, {g[30],G_29_0}, p[30]);
grey g_32_0 (G_32_0, {g[32],G_31_0}, p[32]);
grey g_34_0 (G_34_0, {g[34],G_33_0}, p[34]);
grey g_36_0 (G_36_0, {g[36],G_35_0}, p[36]);
grey g_38_0 (G_38_0, {g[38],G_37_0}, p[38]);
grey g_40_0 (G_40_0, {g[40],G_39_0}, p[40]);
grey g_42_0 (G_42_0, {g[42],G_41_0}, p[42]);
grey g_44_0 (G_44_0, {g[44],G_43_0}, p[44]);
grey g_46_0 (G_46_0, {g[46],G_45_0}, p[46]);
grey g_48_0 (G_48_0, {g[48],G_47_0}, p[48]);
grey g_50_0 (G_50_0, {g[50],G_49_0}, p[50]);
grey g_52_0 (G_52_0, {g[52],G_51_0}, p[52]);
grey g_54_0 (G_54_0, {g[54],G_53_0}, p[54]);
grey g_56_0 (G_56_0, {g[56],G_55_0}, p[56]);
grey g_58_0 (G_58_0, {g[58],G_57_0}, p[58]);
grey g_60_0 (G_60_0, {g[60],G_59_0}, p[60]);
grey g_62_0 (G_62_0, {g[62],G_61_0}, p[62]);
grey g_64_0 (G_64_0, {g[64],G_63_0}, p[64]);
grey g_66_0 (G_66_0, {g[66],G_65_0}, p[66]);
grey g_68_0 (G_68_0, {g[68],G_67_0}, p[68]);
grey g_70_0 (G_70_0, {g[70],G_69_0}, p[70]);
grey g_72_0 (G_72_0, {g[72],G_71_0}, p[72]);
grey g_74_0 (G_74_0, {g[74],G_73_0}, p[74]);
grey g_76_0 (G_76_0, {g[76],G_75_0}, p[76]);
grey g_78_0 (G_78_0, {g[78],G_77_0}, p[78]);
grey g_80_0 (G_80_0, {g[80],G_79_0}, p[80]);
grey g_82_0 (G_82_0, {g[82],G_81_0}, p[82]);
grey g_84_0 (G_84_0, {g[84],G_83_0}, p[84]);
grey g_86_0 (G_86_0, {g[86],G_85_0}, p[86]);
grey g_88_0 (G_88_0, {g[88],G_87_0}, p[88]);
grey g_90_0 (G_90_0, {g[90],G_89_0}, p[90]);
grey g_92_0 (G_92_0, {g[92],G_91_0}, p[92]);
grey g_94_0 (G_94_0, {g[94],G_93_0}, p[94]);
grey g_96_0 (G_96_0, {g[96],G_95_0}, p[96]);
grey g_98_0 (G_98_0, {g[98],G_97_0}, p[98]);
grey g_100_0 (G_100_0, {g[100],G_99_0}, p[100]);
grey g_102_0 (G_102_0, {g[102],G_101_0}, p[102]);
grey g_104_0 (G_104_0, {g[104],G_103_0}, p[104]);
grey g_106_0 (G_106_0, {g[106],G_105_0}, p[106]);
grey g_108_0 (G_108_0, {g[108],G_107_0}, p[108]);
grey g_110_0 (G_110_0, {g[110],G_109_0}, p[110]);
grey g_112_0 (G_112_0, {g[112],G_111_0}, p[112]);
grey g_114_0 (G_114_0, {g[114],G_113_0}, p[114]);
grey g_116_0 (G_116_0, {g[116],G_115_0}, p[116]);
grey g_118_0 (G_118_0, {g[118],G_117_0}, p[118]);
grey g_120_0 (G_120_0, {g[120],G_119_0}, p[120]);
grey g_122_0 (G_122_0, {g[122],G_121_0}, p[122]);
grey g_124_0 (G_124_0, {g[124],G_123_0}, p[124]);
grey g_126_0 (G_126_0, {g[126],G_125_0}, p[126]);
// Final Stage: Apply c_k+1=G_k_0
assign c[1]=g[0];
assign c[2]=G_1_0;
assign c[3]=G_2_0;
assign c[4]=G_3_0;
assign c[5]=G_4_0;
assign c[6]=G_5_0;
assign c[7]=G_6_0;
assign c[8]=G_7_0;
assign c[9]=G_8_0;
assign c[10]=G_9_0;
assign c[11]=G_10_0;
assign c[12]=G_11_0;
assign c[13]=G_12_0;
assign c[14]=G_13_0;
assign c[15]=G_14_0;
assign c[16]=G_15_0;
assign c[17]=G_16_0;
assign c[18]=G_17_0;
assign c[19]=G_18_0;
assign c[20]=G_19_0;
assign c[21]=G_20_0;
assign c[22]=G_21_0;
assign c[23]=G_22_0;
assign c[24]=G_23_0;
assign c[25]=G_24_0;
assign c[26]=G_25_0;
assign c[27]=G_26_0;
assign c[28]=G_27_0;
assign c[29]=G_28_0;
assign c[30]=G_29_0;
assign c[31]=G_30_0;
assign c[32]=G_31_0;
assign c[33]=G_32_0;
assign c[34]=G_33_0;
assign c[35]=G_34_0;
assign c[36]=G_35_0;
assign c[37]=G_36_0;
assign c[38]=G_37_0;
assign c[39]=G_38_0;
assign c[40]=G_39_0;
assign c[41]=G_40_0;
assign c[42]=G_41_0;
assign c[43]=G_42_0;
assign c[44]=G_43_0;
assign c[45]=G_44_0;
assign c[46]=G_45_0;
assign c[47]=G_46_0;
assign c[48]=G_47_0;
assign c[49]=G_48_0;
assign c[50]=G_49_0;
assign c[51]=G_50_0;
assign c[52]=G_51_0;
assign c[53]=G_52_0;
assign c[54]=G_53_0;
assign c[55]=G_54_0;
assign c[56]=G_55_0;
assign c[57]=G_56_0;
assign c[58]=G_57_0;
assign c[59]=G_58_0;
assign c[60]=G_59_0;
assign c[61]=G_60_0;
assign c[62]=G_61_0;
assign c[63]=G_62_0;
assign c[64]=G_63_0;
assign c[65]=G_64_0;
assign c[66]=G_65_0;
assign c[67]=G_66_0;
assign c[68]=G_67_0;
assign c[69]=G_68_0;
assign c[70]=G_69_0;
assign c[71]=G_70_0;
assign c[72]=G_71_0;
assign c[73]=G_72_0;
assign c[74]=G_73_0;
assign c[75]=G_74_0;
assign c[76]=G_75_0;
assign c[77]=G_76_0;
assign c[78]=G_77_0;
assign c[79]=G_78_0;
assign c[80]=G_79_0;
assign c[81]=G_80_0;
assign c[82]=G_81_0;
assign c[83]=G_82_0;
assign c[84]=G_83_0;
assign c[85]=G_84_0;
assign c[86]=G_85_0;
assign c[87]=G_86_0;
assign c[88]=G_87_0;
assign c[89]=G_88_0;
assign c[90]=G_89_0;
assign c[91]=G_90_0;
assign c[92]=G_91_0;
assign c[93]=G_92_0;
assign c[94]=G_93_0;
assign c[95]=G_94_0;
assign c[96]=G_95_0;
assign c[97]=G_96_0;
assign c[98]=G_97_0;
assign c[99]=G_98_0;
assign c[100]=G_99_0;
assign c[101]=G_100_0;
assign c[102]=G_101_0;
assign c[103]=G_102_0;
assign c[104]=G_103_0;
assign c[105]=G_104_0;
assign c[106]=G_105_0;
assign c[107]=G_106_0;
assign c[108]=G_107_0;
assign c[109]=G_108_0;
assign c[110]=G_109_0;
assign c[111]=G_110_0;
assign c[112]=G_111_0;
assign c[113]=G_112_0;
assign c[114]=G_113_0;
assign c[115]=G_114_0;
assign c[116]=G_115_0;
assign c[117]=G_116_0;
assign c[118]=G_117_0;
assign c[119]=G_118_0;
assign c[120]=G_119_0;
assign c[121]=G_120_0;
assign c[122]=G_121_0;
assign c[123]=G_122_0;
assign c[124]=G_123_0;
assign c[125]=G_124_0;
assign c[126]=G_125_0;
assign c[127]=G_126_0;
assign c[128]=G_127_0;
endmodule // ladner_fischer

273
wally-pipelined/src/fpudivsqrt/ldf64.v
View file

@ -1,273 +0,0 @@
// Ladner-Fischer Prefix Adder
module ldf64 (cout, sum, a, b, cin);
input [63:0] a, b;
input cin;
output [63:0] sum;
output cout;
wire [64:0] p,g;
wire [63:0] c;
// pre-computation
assign p={a^b,1'b0};
assign g={a&b, cin};
// prefix tree
ladner_fischer64 prefix_tree(c, p[63:0], g[63:0]);
// post-computation
assign sum=p[64:1]^c;
assign cout=g[64]|(p[64]&c[63]);
endmodule
module ladner_fischer64 (c, p, g);
input [63:0] p;
input [63:0] g;
output [64:1] c;
// parallel-prefix, Ladner-Fischer
// Stage 1: Generates G/P pairs that span 1 bits
grey b_1_0 (G_1_0, {g[1],g[0]}, p[1]);
black b_3_2 (G_3_2, P_3_2, {g[3],g[2]}, {p[3],p[2]});
black b_5_4 (G_5_4, P_5_4, {g[5],g[4]}, {p[5],p[4]});
black b_7_6 (G_7_6, P_7_6, {g[7],g[6]}, {p[7],p[6]});
black b_9_8 (G_9_8, P_9_8, {g[9],g[8]}, {p[9],p[8]});
black b_11_10 (G_11_10, P_11_10, {g[11],g[10]}, {p[11],p[10]});
black b_13_12 (G_13_12, P_13_12, {g[13],g[12]}, {p[13],p[12]});
black b_15_14 (G_15_14, P_15_14, {g[15],g[14]}, {p[15],p[14]});
black b_17_16 (G_17_16, P_17_16, {g[17],g[16]}, {p[17],p[16]});
black b_19_18 (G_19_18, P_19_18, {g[19],g[18]}, {p[19],p[18]});
black b_21_20 (G_21_20, P_21_20, {g[21],g[20]}, {p[21],p[20]});
black b_23_22 (G_23_22, P_23_22, {g[23],g[22]}, {p[23],p[22]});
black b_25_24 (G_25_24, P_25_24, {g[25],g[24]}, {p[25],p[24]});
black b_27_26 (G_27_26, P_27_26, {g[27],g[26]}, {p[27],p[26]});
black b_29_28 (G_29_28, P_29_28, {g[29],g[28]}, {p[29],p[28]});
black b_31_30 (G_31_30, P_31_30, {g[31],g[30]}, {p[31],p[30]});
black b_33_32 (G_33_32, P_33_32, {g[33],g[32]}, {p[33],p[32]});
black b_35_34 (G_35_34, P_35_34, {g[35],g[34]}, {p[35],p[34]});
black b_37_36 (G_37_36, P_37_36, {g[37],g[36]}, {p[37],p[36]});
black b_39_38 (G_39_38, P_39_38, {g[39],g[38]}, {p[39],p[38]});
black b_41_40 (G_41_40, P_41_40, {g[41],g[40]}, {p[41],p[40]});
black b_43_42 (G_43_42, P_43_42, {g[43],g[42]}, {p[43],p[42]});
black b_45_44 (G_45_44, P_45_44, {g[45],g[44]}, {p[45],p[44]});
black b_47_46 (G_47_46, P_47_46, {g[47],g[46]}, {p[47],p[46]});
black b_49_48 (G_49_48, P_49_48, {g[49],g[48]}, {p[49],p[48]});
black b_51_50 (G_51_50, P_51_50, {g[51],g[50]}, {p[51],p[50]});
black b_53_52 (G_53_52, P_53_52, {g[53],g[52]}, {p[53],p[52]});
black b_55_54 (G_55_54, P_55_54, {g[55],g[54]}, {p[55],p[54]});
black b_57_56 (G_57_56, P_57_56, {g[57],g[56]}, {p[57],p[56]});
black b_59_58 (G_59_58, P_59_58, {g[59],g[58]}, {p[59],p[58]});
black b_61_60 (G_61_60, P_61_60, {g[61],g[60]}, {p[61],p[60]});
black b_63_62 (G_63_62, P_63_62, {g[63],g[62]}, {p[63],p[62]});
// Stage 2: Generates G/P pairs that span 2 bits
grey g_3_0 (G_3_0, {G_3_2,G_1_0}, P_3_2);
black b_7_4 (G_7_4, P_7_4, {G_7_6,G_5_4}, {P_7_6,P_5_4});
black b_11_8 (G_11_8, P_11_8, {G_11_10,G_9_8}, {P_11_10,P_9_8});
black b_15_12 (G_15_12, P_15_12, {G_15_14,G_13_12}, {P_15_14,P_13_12});
black b_19_16 (G_19_16, P_19_16, {G_19_18,G_17_16}, {P_19_18,P_17_16});
black b_23_20 (G_23_20, P_23_20, {G_23_22,G_21_20}, {P_23_22,P_21_20});
black b_27_24 (G_27_24, P_27_24, {G_27_26,G_25_24}, {P_27_26,P_25_24});
black b_31_28 (G_31_28, P_31_28, {G_31_30,G_29_28}, {P_31_30,P_29_28});
black b_35_32 (G_35_32, P_35_32, {G_35_34,G_33_32}, {P_35_34,P_33_32});
black b_39_36 (G_39_36, P_39_36, {G_39_38,G_37_36}, {P_39_38,P_37_36});
black b_43_40 (G_43_40, P_43_40, {G_43_42,G_41_40}, {P_43_42,P_41_40});
black b_47_44 (G_47_44, P_47_44, {G_47_46,G_45_44}, {P_47_46,P_45_44});
black b_51_48 (G_51_48, P_51_48, {G_51_50,G_49_48}, {P_51_50,P_49_48});
black b_55_52 (G_55_52, P_55_52, {G_55_54,G_53_52}, {P_55_54,P_53_52});
black b_59_56 (G_59_56, P_59_56, {G_59_58,G_57_56}, {P_59_58,P_57_56});
black b_63_60 (G_63_60, P_63_60, {G_63_62,G_61_60}, {P_63_62,P_61_60});
// Stage 3: Generates G/P pairs that span 4 bits
grey g_5_0 (G_5_0, {G_5_4,G_3_0}, P_5_4);
grey g_7_0 (G_7_0, {G_7_4,G_3_0}, P_7_4);
black b_13_8 (G_13_8, P_13_8, {G_13_12,G_11_8}, {P_13_12,P_11_8});
black b_15_8 (G_15_8, P_15_8, {G_15_12,G_11_8}, {P_15_12,P_11_8});
black b_21_16 (G_21_16, P_21_16, {G_21_20,G_19_16}, {P_21_20,P_19_16});
black b_23_16 (G_23_16, P_23_16, {G_23_20,G_19_16}, {P_23_20,P_19_16});
black b_29_24 (G_29_24, P_29_24, {G_29_28,G_27_24}, {P_29_28,P_27_24});
black b_31_24 (G_31_24, P_31_24, {G_31_28,G_27_24}, {P_31_28,P_27_24});
black b_37_32 (G_37_32, P_37_32, {G_37_36,G_35_32}, {P_37_36,P_35_32});
black b_39_32 (G_39_32, P_39_32, {G_39_36,G_35_32}, {P_39_36,P_35_32});
black b_45_40 (G_45_40, P_45_40, {G_45_44,G_43_40}, {P_45_44,P_43_40});
black b_47_40 (G_47_40, P_47_40, {G_47_44,G_43_40}, {P_47_44,P_43_40});
black b_53_48 (G_53_48, P_53_48, {G_53_52,G_51_48}, {P_53_52,P_51_48});
black b_55_48 (G_55_48, P_55_48, {G_55_52,G_51_48}, {P_55_52,P_51_48});
black b_61_56 (G_61_56, P_61_56, {G_61_60,G_59_56}, {P_61_60,P_59_56});
black b_63_56 (G_63_56, P_63_56, {G_63_60,G_59_56}, {P_63_60,P_59_56});
// Stage 4: Generates G/P pairs that span 8 bits
grey g_9_0 (G_9_0, {G_9_8,G_7_0}, P_9_8);
grey g_11_0 (G_11_0, {G_11_8,G_7_0}, P_11_8);
grey g_13_0 (G_13_0, {G_13_8,G_7_0}, P_13_8);
grey g_15_0 (G_15_0, {G_15_8,G_7_0}, P_15_8);
black b_25_16 (G_25_16, P_25_16, {G_25_24,G_23_16}, {P_25_24,P_23_16});
black b_27_16 (G_27_16, P_27_16, {G_27_24,G_23_16}, {P_27_24,P_23_16});
black b_29_16 (G_29_16, P_29_16, {G_29_24,G_23_16}, {P_29_24,P_23_16});
black b_31_16 (G_31_16, P_31_16, {G_31_24,G_23_16}, {P_31_24,P_23_16});
black b_41_32 (G_41_32, P_41_32, {G_41_40,G_39_32}, {P_41_40,P_39_32});
black b_43_32 (G_43_32, P_43_32, {G_43_40,G_39_32}, {P_43_40,P_39_32});
black b_45_32 (G_45_32, P_45_32, {G_45_40,G_39_32}, {P_45_40,P_39_32});
black b_47_32 (G_47_32, P_47_32, {G_47_40,G_39_32}, {P_47_40,P_39_32});
black b_57_48 (G_57_48, P_57_48, {G_57_56,G_55_48}, {P_57_56,P_55_48});
black b_59_48 (G_59_48, P_59_48, {G_59_56,G_55_48}, {P_59_56,P_55_48});
black b_61_48 (G_61_48, P_61_48, {G_61_56,G_55_48}, {P_61_56,P_55_48});
black b_63_48 (G_63_48, P_63_48, {G_63_56,G_55_48}, {P_63_56,P_55_48});
// Stage 5: Generates G/P pairs that span 16 bits
grey g_17_0 (G_17_0, {G_17_16,G_15_0}, P_17_16);
grey g_19_0 (G_19_0, {G_19_16,G_15_0}, P_19_16);
grey g_21_0 (G_21_0, {G_21_16,G_15_0}, P_21_16);
grey g_23_0 (G_23_0, {G_23_16,G_15_0}, P_23_16);
grey g_25_0 (G_25_0, {G_25_16,G_15_0}, P_25_16);
grey g_27_0 (G_27_0, {G_27_16,G_15_0}, P_27_16);
grey g_29_0 (G_29_0, {G_29_16,G_15_0}, P_29_16);
grey g_31_0 (G_31_0, {G_31_16,G_15_0}, P_31_16);
black b_49_32 (G_49_32, P_49_32, {G_49_48,G_47_32}, {P_49_48,P_47_32});
black b_51_32 (G_51_32, P_51_32, {G_51_48,G_47_32}, {P_51_48,P_47_32});
black b_53_32 (G_53_32, P_53_32, {G_53_48,G_47_32}, {P_53_48,P_47_32});
black b_55_32 (G_55_32, P_55_32, {G_55_48,G_47_32}, {P_55_48,P_47_32});
black b_57_32 (G_57_32, P_57_32, {G_57_48,G_47_32}, {P_57_48,P_47_32});
black b_59_32 (G_59_32, P_59_32, {G_59_48,G_47_32}, {P_59_48,P_47_32});
black b_61_32 (G_61_32, P_61_32, {G_61_48,G_47_32}, {P_61_48,P_47_32});
black b_63_32 (G_63_32, P_63_32, {G_63_48,G_47_32}, {P_63_48,P_47_32});
// Stage 6: Generates G/P pairs that span 32 bits
grey g_33_0 (G_33_0, {G_33_32,G_31_0}, P_33_32);
grey g_35_0 (G_35_0, {G_35_32,G_31_0}, P_35_32);
grey g_37_0 (G_37_0, {G_37_32,G_31_0}, P_37_32);
grey g_39_0 (G_39_0, {G_39_32,G_31_0}, P_39_32);
grey g_41_0 (G_41_0, {G_41_32,G_31_0}, P_41_32);
grey g_43_0 (G_43_0, {G_43_32,G_31_0}, P_43_32);
grey g_45_0 (G_45_0, {G_45_32,G_31_0}, P_45_32);
grey g_47_0 (G_47_0, {G_47_32,G_31_0}, P_47_32);
grey g_49_0 (G_49_0, {G_49_32,G_31_0}, P_49_32);
grey g_51_0 (G_51_0, {G_51_32,G_31_0}, P_51_32);
grey g_53_0 (G_53_0, {G_53_32,G_31_0}, P_53_32);
grey g_55_0 (G_55_0, {G_55_32,G_31_0}, P_55_32);
grey g_57_0 (G_57_0, {G_57_32,G_31_0}, P_57_32);
grey g_59_0 (G_59_0, {G_59_32,G_31_0}, P_59_32);
grey g_61_0 (G_61_0, {G_61_32,G_31_0}, P_61_32);
grey g_63_0 (G_63_0, {G_63_32,G_31_0}, P_63_32);
// Extra grey cell stage
grey g_2_0 (G_2_0, {g[2],G_1_0}, p[2]);
grey g_4_0 (G_4_0, {g[4],G_3_0}, p[4]);
grey g_6_0 (G_6_0, {g[6],G_5_0}, p[6]);
grey g_8_0 (G_8_0, {g[8],G_7_0}, p[8]);
grey g_10_0 (G_10_0, {g[10],G_9_0}, p[10]);
grey g_12_0 (G_12_0, {g[12],G_11_0}, p[12]);
grey g_14_0 (G_14_0, {g[14],G_13_0}, p[14]);
grey g_16_0 (G_16_0, {g[16],G_15_0}, p[16]);
grey g_18_0 (G_18_0, {g[18],G_17_0}, p[18]);
grey g_20_0 (G_20_0, {g[20],G_19_0}, p[20]);
grey g_22_0 (G_22_0, {g[22],G_21_0}, p[22]);
grey g_24_0 (G_24_0, {g[24],G_23_0}, p[24]);
grey g_26_0 (G_26_0, {g[26],G_25_0}, p[26]);
grey g_28_0 (G_28_0, {g[28],G_27_0}, p[28]);
grey g_30_0 (G_30_0, {g[30],G_29_0}, p[30]);
grey g_32_0 (G_32_0, {g[32],G_31_0}, p[32]);
grey g_34_0 (G_34_0, {g[34],G_33_0}, p[34]);
grey g_36_0 (G_36_0, {g[36],G_35_0}, p[36]);
grey g_38_0 (G_38_0, {g[38],G_37_0}, p[38]);
grey g_40_0 (G_40_0, {g[40],G_39_0}, p[40]);
grey g_42_0 (G_42_0, {g[42],G_41_0}, p[42]);
grey g_44_0 (G_44_0, {g[44],G_43_0}, p[44]);
grey g_46_0 (G_46_0, {g[46],G_45_0}, p[46]);
grey g_48_0 (G_48_0, {g[48],G_47_0}, p[48]);
grey g_50_0 (G_50_0, {g[50],G_49_0}, p[50]);
grey g_52_0 (G_52_0, {g[52],G_51_0}, p[52]);
grey g_54_0 (G_54_0, {g[54],G_53_0}, p[54]);
grey g_56_0 (G_56_0, {g[56],G_55_0}, p[56]);
grey g_58_0 (G_58_0, {g[58],G_57_0}, p[58]);
grey g_60_0 (G_60_0, {g[60],G_59_0}, p[60]);
grey g_62_0 (G_62_0, {g[62],G_61_0}, p[62]);
// Final Stage: Apply c_k+1=G_k_0
assign c[1]=g[0];
assign c[2]=G_1_0;
assign c[3]=G_2_0;
assign c[4]=G_3_0;
assign c[5]=G_4_0;
assign c[6]=G_5_0;
assign c[7]=G_6_0;
assign c[8]=G_7_0;
assign c[9]=G_8_0;
assign c[10]=G_9_0;
assign c[11]=G_10_0;
assign c[12]=G_11_0;
assign c[13]=G_12_0;
assign c[14]=G_13_0;
assign c[15]=G_14_0;
assign c[16]=G_15_0;
assign c[17]=G_16_0;
assign c[18]=G_17_0;
assign c[19]=G_18_0;
assign c[20]=G_19_0;
assign c[21]=G_20_0;
assign c[22]=G_21_0;
assign c[23]=G_22_0;
assign c[24]=G_23_0;
assign c[25]=G_24_0;
assign c[26]=G_25_0;
assign c[27]=G_26_0;
assign c[28]=G_27_0;
assign c[29]=G_28_0;
assign c[30]=G_29_0;
assign c[31]=G_30_0;
assign c[32]=G_31_0;
assign c[33]=G_32_0;
assign c[34]=G_33_0;
assign c[35]=G_34_0;
assign c[36]=G_35_0;
assign c[37]=G_36_0;
assign c[38]=G_37_0;
assign c[39]=G_38_0;
assign c[40]=G_39_0;
assign c[41]=G_40_0;
assign c[42]=G_41_0;
assign c[43]=G_42_0;
assign c[44]=G_43_0;
assign c[45]=G_44_0;
assign c[46]=G_45_0;
assign c[47]=G_46_0;
assign c[48]=G_47_0;
assign c[49]=G_48_0;
assign c[50]=G_49_0;
assign c[51]=G_50_0;
assign c[52]=G_51_0;
assign c[53]=G_52_0;
assign c[54]=G_53_0;
assign c[55]=G_54_0;
assign c[56]=G_55_0;
assign c[57]=G_56_0;
assign c[58]=G_57_0;
assign c[59]=G_58_0;
assign c[60]=G_59_0;
assign c[61]=G_60_0;
assign c[62]=G_61_0;
assign c[63]=G_62_0;
assign c[64]=G_63_0;
endmodule // ladner_fischer

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// Brent-Kung Prefix Adder
module exp_add (cout, sum, a, b, cin);
input [12:0] a, b;
input cin;
output [12:0] sum;
output cout;
wire [13:0] p,g;
wire [13:1] h,c;
// pre-computation
assign p={a|b,1'b1};
assign g={a&b, cin};
// prefix tree
brent_kung prefix_tree(h, c, p[12:0], g[12:0]);
// post-computation
assign h[13]=g[13]|c[13];
assign sum=p[13:1]^h|g[13:1]&c;
assign cout=p[13]&h[13];
endmodule
module brent_kung (h, c, p, g);
input [12:0] p;
input [12:0] g;
output [13:1] h;
output [13:1] c;
// parallel-prefix, Brent-Kung
// Stage 1: Generates H/I pairs that span 1 bits
rgry g_1_0 (H_1_0, {g[1],g[0]});
rblk b_3_2 (H_3_2, I_3_2, {g[3],g[2]}, {p[2],p[1]});
rblk b_5_4 (H_5_4, I_5_4, {g[5],g[4]}, {p[4],p[3]});
rblk b_7_6 (H_7_6, I_7_6, {g[7],g[6]}, {p[6],p[5]});
rblk b_9_8 (H_9_8, I_9_8, {g[9],g[8]}, {p[8],p[7]});
rblk b_11_10 (H_11_10, I_11_10, {g[11],g[10]}, {p[10],p[9]});
rblk b_13_12 (H_13_12, I_13_12, {g[13],g[12]}, {p[12],p[11]});
// Stage 2: Generates H/I pairs that span 2 bits
grey g_3_0 (H_3_0, {H_3_2,H_1_0}, I_3_2);
black b_7_4 (H_7_4, I_7_4, {H_7_6,H_5_4}, {I_7_6,I_5_4});
black b_11_8 (H_11_8, I_11_8, {H_11_10,H_9_8}, {I_11_10,I_9_8});
// Stage 3: Generates H/I pairs that span 4 bits
grey g_7_0 (H_7_0, {H_7_4,H_3_0}, I_7_4);
// Stage 4: Generates H/I pairs that span 8 bits
// Stage 5: Generates H/I pairs that span 4 bits
grey g_11_0 (H_11_0, {H_11_8,H_7_0}, I_11_8);
// Stage 6: Generates H/I pairs that span 2 bits
grey g_5_0 (H_5_0, {H_5_4,H_3_0}, I_5_4);
grey g_9_0 (H_9_0, {H_9_8,H_7_0}, I_9_8);
// Last grey cell stage
grey g_2_0 (H_2_0, {g[2],H_1_0}, p[1]);
grey g_4_0 (H_4_0, {g[4],H_3_0}, p[3]);
grey g_6_0 (H_6_0, {g[6],H_5_0}, p[5]);
grey g_8_0 (H_8_0, {g[8],H_7_0}, p[7]);
grey g_10_0 (H_10_0, {g[10],H_9_0}, p[9]);
grey g_12_0 (H_12_0, {g[12],H_11_0}, p[11]);
// Final Stage: Apply c_k+1=p_k&H_k_0
assign c[1]=g[0];
assign h[1]=H_1_0; assign c[2]=p[1]&H_1_0;
assign h[2]=H_2_0; assign c[3]=p[2]&H_2_0;
assign h[3]=H_3_0; assign c[4]=p[3]&H_3_0;
assign h[4]=H_4_0; assign c[5]=p[4]&H_4_0;
assign h[5]=H_5_0; assign c[6]=p[5]&H_5_0;
assign h[6]=H_6_0; assign c[7]=p[6]&H_6_0;
assign h[7]=H_7_0; assign c[8]=p[7]&H_7_0;
assign h[8]=H_8_0; assign c[9]=p[8]&H_8_0;
assign h[9]=H_9_0; assign c[10]=p[9]&H_9_0;
assign h[10]=H_10_0; assign c[11]=p[10]&H_10_0;
assign h[11]=H_11_0; assign c[12]=p[11]&H_11_0;
assign h[12]=H_12_0; assign c[13]=p[12]&H_12_0;
endmodule
// Black cell
module black(gout, pout, gin, pin);
input [1:0] gin, pin;
output gout, pout;
assign pout=pin[1]&pin[0];
assign gout=gin[1]|(pin[1]&gin[0]);
endmodule
// Grey cell
module grey(gout, gin, pin);
input[1:0] gin;
input pin;
output gout;
assign gout=gin[1]|(pin&gin[0]);
endmodule
// reduced Black cell
module rblk(hout, iout, gin, pin);
input [1:0] gin, pin;
output hout, iout;
assign iout=pin[1]&pin[0];
assign hout=gin[1]|gin[0];
endmodule
// reduced Grey cell
module rgry(hout, gin);
input[1:0] gin;
output hout;
assign hout=gin[1]|gin[0];
endmodule

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11995
wally-pipelined/src/fpudivsqrt/mult_R4_64_64_cs.v
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//
// The rounder takes as inputs a 64-bit value to be rounded, A, the
// exponent of the value to be rounded, the sign of the final result, Sign,
// the precision of the results, P, and the two-bit rounding mode, rm.
// It produces a rounded 52-bit result, Z, the exponent of the rounded
// result, Z_exp, and a flag that indicates if the result was rounded,
// Inexact. The rounding mode has the following values.
// rm Modee
// 00 round-to-nearest-even
// 01 round-toward-zero
// 10 round-toward-plus infinity
// 11 round-toward-minus infinity
//
module rounder (Result, DenormIO, Flags, rm, P, OvEn,
UnEn, exp_diff, sel_inv, Invalid, DenormIn,
SignR, q1, qm1, qp1, q0, qm0, qp0, regr_out);
input [1:0] rm;
input P;
input OvEn;
input UnEn;
input [12:0] exp_diff;
input [2:0] sel_inv;
input Invalid;
input DenormIn;
input SignR;
input [63:0] q1;
input [63:0] qm1;
input [63:0] qp1;
input [63:0] q0;
input [63:0] qm0;
input [63:0] qp0;
input [127:0] regr_out;
output [63:0] Result;
output DenormIO;
output [4:0] Flags;
supply1 vdd;
supply0 vss;
wire Rsign;
wire [10:0] Rexp;
wire [12:0] Texp;
wire [51:0] Rmant;
wire [63:0] Tmant;
wire [51:0] Smant;
wire Rzero;
wire Gdp, Gsp, G;
wire UnFlow_SP, UnFlow_DP, UnderFlow;
wire OvFlow_SP, OvFlow_DP, OverFlow;
wire Inexact;
wire Round_zero;
wire Infinite;
wire VeryLarge;
wire Largest;
wire Div0;
wire Adj_exp;
wire Valid;
wire NaN;
wire Texp_l7z;
wire Texp_l7o;
wire OvCon;
wire [1:0] mux_mant;
wire sign_rem;
wire [63:0] q, qm, qp;
wire exp_ovf, exp_ovfSP, exp_ovfDP;
// Remainder = 0?
assign zero_rem = ~(|regr_out);
// Remainder Sign
assign sign_rem = ~regr_out[127];
// choose correct Guard bit [1,2) or [0,1)
assign Gdp = q1[63] ? q1[10] : q0[10];
assign Gsp = q1[63] ? q1[39] : q0[39];
assign G = P ? Gsp : Gdp;
// Selection of Rounding (from logic/switching)
assign mux_mant[1] = (SignR&rm[1]&rm[0]&G) | (!SignR&rm[1]&!rm[0]&G) |
(!rm[1]&!rm[0]&G&!sign_rem) |
(SignR&rm[1]&rm[0]&!zero_rem&!sign_rem) |
(!SignR&rm[1]&!rm[0]&!zero_rem&!sign_rem);
assign mux_mant[0] = (!SignR&rm[0]&!G&!zero_rem&sign_rem) |
(!rm[1]&rm[0]&!G&!zero_rem&sign_rem) |
(SignR&rm[1]&!rm[0]&!G&!zero_rem&sign_rem);
// Which Q?
mux2 #(64) mx1 (q0, q1, q1[63], q);
mux2 #(64) mx2 (qm0, qm1, q1[63], qm);
mux2 #(64) mx3 (qp0, qp1, q1[63], qp);
// Choose Q, Q+1, Q-1
mux3 #(64) mx4 (q, qm, qp, mux_mant, Tmant);
assign Smant = Tmant[62:11];
// Compute the value of the exponent
// exponent is modified if we choose:
// 1.) we choose any qm0, qp0, q0 (since we shift mant)
// 2.) we choose qp and we overflow (for RU)
assign exp_ovf = |{qp[62:40], (qp[39:11] & {29{~P}})};
assign Texp = exp_diff - {{13{vss}}, ~q1[63]} + {{13{vss}}, mux_mant[1]&qp1[63]&~exp_ovf};
// Overflow only occurs for double precision, if Texp[10] to Texp[0] are
// all ones. To encourage sharing with single precision overflow detection,
// the lower 7 bits are tested separately.
assign Texp_l7o = Texp[6]&Texp[5]&Texp[4]&Texp[3]&Texp[2]&Texp[1]&Texp[0];
assign OvFlow_DP = (~Texp[12]&Texp[11]) | (Texp[10]&Texp[9]&Texp[8]&Texp[7]&Texp_l7o);
// Overflow occurs for single precision if (Texp[10] is one) and
// ((Texp[9] or Texp[8] or Texp[7]) is one) or (Texp[6] to Texp[0]
// are all ones.
assign OvFlow_SP = Texp[10]&(Texp[9]|Texp[8]|Texp[7]|Texp_l7o);
// Underflow occurs for double precision if (Texp[11]/Texp[10] is one) or
// Texp[10] to Texp[0] are all zeros.
assign Texp_l7z = ~Texp[6]&~Texp[5]&~Texp[4]&~Texp[3]&~Texp[2]&~Texp[1]&~Texp[0];
assign UnFlow_DP = (Texp[12]&Texp[11]) | ~Texp[11]&~Texp[10]&~Texp[9]&~Texp[8]&~Texp[7]&Texp_l7z;
// Underflow occurs for single precision if (Texp[10] is zero) and
// (Texp[9] or Texp[8] or Texp[7]) is zero.
assign UnFlow_SP = ~Texp[10]&(~Texp[9]|~Texp[8]|~Texp[7]|Texp_l7z);
// Set the overflow and underflow flags. They should not be set if
// the input was infinite or NaN or the output of the adder is zero.
// 00 = Valid
// 10 = NaN
assign Valid = (~sel_inv[2]&~sel_inv[1]&~sel_inv[0]);
assign NaN = ~sel_inv[1]& sel_inv[0];
assign UnderFlow = (P & UnFlow_SP | UnFlow_DP) & Valid;
assign OverFlow = (P & OvFlow_SP | OvFlow_DP) & Valid;
assign Div0 = sel_inv[2]&sel_inv[1]&~sel_inv[0];
// The DenormIO is set if underflow has occurred or if their was a
// denormalized input.
assign DenormIO = DenormIn | UnderFlow;
// The final result is Inexact if any rounding occurred ((i.e., R or S
// is one), or (if the result overflows ) or (if the result underflows and the
// underflow trap is not enabled)) and (value of the result was not previous set
// by an exception case).
assign Inexact = (G|~zero_rem|OverFlow|(UnderFlow&~UnEn))&Valid;
// Set the IEEE Exception Flags: Inexact, Underflow, Overflow, Div_By_0,
// Invlalid.
assign Flags = {Inexact, UnderFlow, OverFlow, Div0, Invalid};
// Determine sign
assign Rzero = UnderFlow | (~sel_inv[2]&sel_inv[1]&sel_inv[0]);
assign Rsign = SignR;
// The exponent of the final result is zero if the final result is
// zero or a denorm, all ones if the final result is NaN or Infinite
// or overflow occurred and the magnitude of the number is
// not rounded toward from zero, and all ones with an LSB of zero
// if overflow occurred and the magnitude of the number is
// rounded toward zero. If the result is single precision,
// Texp[7] shoud be inverted. When the Overflow trap is enabled (OvEn = 1)
// and overflow occurs and the operation is not conversion, bits 10 and 9 are
// inverted for double precision, and bits 7 and 6 are inverted for single precision.
assign Round_zero = ~rm[1]&rm[0] | ~SignR&rm[0] | SignR&rm[1]&~rm[0];
assign VeryLarge = OverFlow & ~OvEn;
assign Infinite = (VeryLarge & ~Round_zero) | sel_inv[1];
assign Largest = VeryLarge & Round_zero;
assign Adj_exp = OverFlow & OvEn;
assign Rexp[10:1] = ({10{~Valid}} |
{Texp[10]&~Adj_exp, Texp[9]&~Adj_exp, Texp[8],
(Texp[7]^P)&~(Adj_exp&P), Texp[6]&~(Adj_exp&P), Texp[5:1]} |
{10{VeryLarge}})&{10{~Rzero | NaN}};
assign Rexp[0] = ({~Valid} | Texp[0] | Infinite)&(~Rzero | NaN)&~Largest;
// If the result is zero or infinity, the mantissa is all zeros.
// If the result is NaN, the mantissa is 10...0
// If the result the largest floating point number, the mantissa
// is all ones. Otherwise, the mantissa is not changed.
assign Rmant[51] = Largest | NaN | (Smant[51]&~Infinite&~Rzero);
assign Rmant[50:0] = {51{Largest}} | (Smant[50:0]&{51{~Infinite&Valid&~Rzero}});
// For single precision, the 8 least significant bits of the exponent
// and 23 most significant bits of the mantissa contain bits used
// for the final result. A double precision result is returned if
// overflow has occurred, the overflow trap is enabled, and a conversion
// is being performed.
assign OvCon = OverFlow & OvEn;
assign Result = (P&~OvCon) ? {Rsign, Rexp[7:0], Rmant[51:29], {32{vss}}}
: {Rsign, Rexp, Rmant};
endmodule // rounder

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#!/bin/sh
vsim -do fpdiv.do -c
tail fpdiv.out

5
wally-pipelined/src/fpudivsqrt/runme_f32div.csh
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#!/bin/sh
vsim -do f32_div_rne.do -c
vsim -do f32_div_rz.do -c
vsim -do f32_div_rd.do -c
vsim -do f32_div_ru.do -c

5
wally-pipelined/src/fpudivsqrt/runme_f32sqrt.csh
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#!/bin/sh
vsim -do f32_sqrt_rne.do -c
vsim -do f32_sqrt_rz.do -c
vsim -do f32_sqrt_rd.do -c
vsim -do f32_sqrt_ru.do -c

5
wally-pipelined/src/fpudivsqrt/runme_f64div.csh
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#!/bin/sh
vsim -do f64_div_rne.do -c
vsim -do f64_div_rz.do -c
vsim -do f64_div_rd.do -c
vsim -do f64_div_ru.do -c

5
wally-pipelined/src/fpudivsqrt/runme_f64sqrt.csh
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#!/bin/sh
vsim -do f64_sqrt_rne.do -c
vsim -do f64_sqrt_rz.do -c
vsim -do f64_sqrt_rd.do -c
vsim -do f64_sqrt_ru.do -c

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wally-pipelined/src/fpudivsqrt/sbtm.sv
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module sbtm (input logic [11:0] a, output logic [10:0] ia_out);
// bit partitions
logic [3:0] x0;
logic [2:0] x1;
logic [3:0] x2;
logic [2:0] x2_1cmp;
// mem outputs
logic [12:0] y0;
logic [4:0] y1;
// input to CPA
logic [14:0] op1;
logic [14:0] op2;
logic [14:0] p;
assign x0 = a[10:7];
assign x1 = a[6:4];
assign x2 = a[3:0];
sbtm_a0 mem1 ({x0, x1}, y0);
// 1s cmp per sbtm/stam
assign x2_1cmp = x2[3] ? ~x2[2:0] : x2[2:0];
sbtm_a1 mem2 ({x0, x2_1cmp}, y1);
assign op1 = {1'b0, y0, 1'b0};
// 1s cmp per sbtm/stam
assign op2 = x2[3] ? {1'b1, {8{1'b1}}, ~y1, 1'b1} :
{1'b0, 8'b0, y1, 1'b1};
// CPA
bk15 cp1 (cout, p, op1, op2, 1'b0);
//assign ia_out = {p[14:4], {53{1'b0}}};
assign ia_out = p[14:4];
endmodule // sbtm

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wally-pipelined/src/fpudivsqrt/sbtm3.sv
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module sbtm2 (input logic [11:0] a, output logic [10:0] y);
// bit partitions
logic [4:0] x0;
logic [2:0] x1;
logic [3:0] x2;
logic [2:0] x2_1cmp;
// mem outputs
logic [13:0] y0;
logic [5:0] y1;
// input to CPA
logic [14:0] op1;
logic [14:0] op2;
logic [14:0] p;
assign x0 = a[11:7];
assign x1 = a[6:4];
assign x2 = a[3:0];
sbtm_a2 mem1 ({x0, x1}, y0);
assign op1 = {y0, 1'b0};
// 1s cmp per sbtm/stam
assign x2_1cmp = x2[3] ? ~x2[2:0] : x2[2:0];
sbtm_a3 mem2 ({x0, x2_1cmp}, y1);
// 1s cmp per sbtm/stam
assign op2 = x2[3] ? {{8{1'b1}}, ~y1, 1'b1} :
{8'b0, y1, 1'b1};
// CPA
bk15 cp1 (cout, p, op1, op2, 1'b0);
assign y = p[14:4];
endmodule // sbtm2

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wally-pipelined/src/fpudivsqrt/sbtm_a0.sv
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module sbtm_a0 (input logic [6:0] a,
output logic [12:0] y);
always_comb
case(a)
7'b0000000: y = 13'b1111111100010;
7'b0000001: y = 13'b1111110100011;
7'b0000010: y = 13'b1111101100101;
7'b0000011: y = 13'b1111100101000;
7'b0000100: y = 13'b1111011101100;
7'b0000101: y = 13'b1111010110000;
7'b0000110: y = 13'b1111001110110;
7'b0000111: y = 13'b1111000111100;
7'b0001000: y = 13'b1111000000100;
7'b0001001: y = 13'b1110111001100;
7'b0001010: y = 13'b1110110010101;
7'b0001011: y = 13'b1110101011110;
7'b0001100: y = 13'b1110100101001;
7'b0001101: y = 13'b1110011110100;
7'b0001110: y = 13'b1110011000000;
7'b0001111: y = 13'b1110010001101;
7'b0010000: y = 13'b1110001011010;
7'b0010001: y = 13'b1110000101000;
7'b0010010: y = 13'b1101111110111;
7'b0010011: y = 13'b1101111000110;
7'b0010100: y = 13'b1101110010111;
7'b0010101: y = 13'b1101101100111;
7'b0010110: y = 13'b1101100111001;
7'b0010111: y = 13'b1101100001011;
7'b0011000: y = 13'b1101011011101;
7'b0011001: y = 13'b1101010110001;
7'b0011010: y = 13'b1101010000100;
7'b0011011: y = 13'b1101001011001;
7'b0011100: y = 13'b1101000101110;
7'b0011101: y = 13'b1101000000011;
7'b0011110: y = 13'b1100111011001;
7'b0011111: y = 13'b1100110101111;
7'b0100000: y = 13'b1100110000110;
7'b0100001: y = 13'b1100101011110;
7'b0100010: y = 13'b1100100110110;
7'b0100011: y = 13'b1100100001111;
7'b0100100: y = 13'b1100011101000;
7'b0100101: y = 13'b1100011000001;
7'b0100110: y = 13'b1100010011011;
7'b0100111: y = 13'b1100001110101;
7'b0101000: y = 13'b1100001010000;
7'b0101001: y = 13'b1100000101011;
7'b0101010: y = 13'b1100000000111;
7'b0101011: y = 13'b1011111100011;
7'b0101100: y = 13'b1011111000000;
7'b0101101: y = 13'b1011110011101;
7'b0101110: y = 13'b1011101111010;
7'b0101111: y = 13'b1011101011000;
7'b0110000: y = 13'b1011100110110;
7'b0110001: y = 13'b1011100010101;
7'b0110010: y = 13'b1011011110011;
7'b0110011: y = 13'b1011011010011;
7'b0110100: y = 13'b1011010110010;
7'b0110101: y = 13'b1011010010010;
7'b0110110: y = 13'b1011001110011;
7'b0110111: y = 13'b1011001010011;
7'b0111000: y = 13'b1011000110100;
7'b0111001: y = 13'b1011000010110;
7'b0111010: y = 13'b1010111110111;
7'b0111011: y = 13'b1010111011001;
7'b0111100: y = 13'b1010110111100;
7'b0111101: y = 13'b1010110011110;
7'b0111110: y = 13'b1010110000001;
7'b0111111: y = 13'b1010101100100;
7'b1000000: y = 13'b1010101001000;
7'b1000001: y = 13'b1010100101100;
7'b1000010: y = 13'b1010100010000;
7'b1000011: y = 13'b1010011110100;
7'b1000100: y = 13'b1010011011001;
7'b1000101: y = 13'b1010010111110;
7'b1000110: y = 13'b1010010100011;
7'b1000111: y = 13'b1010010001001;
7'b1001000: y = 13'b1010001101111;
7'b1001001: y = 13'b1010001010101;
7'b1001010: y = 13'b1010000111011;
7'b1001011: y = 13'b1010000100001;
7'b1001100: y = 13'b1010000001000;
7'b1001101: y = 13'b1001111101111;
7'b1001110: y = 13'b1001111010111;
7'b1001111: y = 13'b1001110111110;
7'b1010000: y = 13'b1001110100110;
7'b1010001: y = 13'b1001110001110;
7'b1010010: y = 13'b1001101110110;
7'b1010011: y = 13'b1001101011111;
7'b1010100: y = 13'b1001101000111;
7'b1010101: y = 13'b1001100110000;
7'b1010110: y = 13'b1001100011001;
7'b1010111: y = 13'b1001100000010;
7'b1011000: y = 13'b1001011101100;
7'b1011001: y = 13'b1001011010110;
7'b1011010: y = 13'b1001011000000;
7'b1011011: y = 13'b1001010101010;
7'b1011100: y = 13'b1001010010100;
7'b1011101: y = 13'b1001001111111;
7'b1011110: y = 13'b1001001101001;
7'b1011111: y = 13'b1001001010100;
7'b1100000: y = 13'b1001000111111;
7'b1100001: y = 13'b1001000101011;
7'b1100010: y = 13'b1001000010110;
7'b1100011: y = 13'b1001000000010;
7'b1100100: y = 13'b1000111101110;
7'b1100101: y = 13'b1000111011010;
7'b1100110: y = 13'b1000111000110;
7'b1100111: y = 13'b1000110110010;
7'b1101000: y = 13'b1000110011111;
7'b1101001: y = 13'b1000110001011;
7'b1101010: y = 13'b1000101111000;
7'b1101011: y = 13'b1000101100101;
7'b1101100: y = 13'b1000101010010;
7'b1101101: y = 13'b1000101000000;
7'b1101110: y = 13'b1000100101101;
7'b1101111: y = 13'b1000100011011;
7'b1110000: y = 13'b1000100001001;
7'b1110001: y = 13'b1000011110110;
7'b1110010: y = 13'b1000011100101;
7'b1110011: y = 13'b1000011010011;
7'b1110100: y = 13'b1000011000001;
7'b1110101: y = 13'b1000010110000;
7'b1110110: y = 13'b1000010011110;
7'b1110111: y = 13'b1000010001101;
7'b1111000: y = 13'b1000001111100;
7'b1111001: y = 13'b1000001101011;
7'b1111010: y = 13'b1000001011010;
7'b1111011: y = 13'b1000001001010;
7'b1111100: y = 13'b1000000111001;
7'b1111101: y = 13'b1000000101001;
7'b1111110: y = 13'b1000000011001;
7'b1111111: y = 13'b1000000001001;
default: y = 13'bxxxxxxxxxxxxx;
endcase // case (a)
endmodule // sbtm_a0

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wally-pipelined/src/fpudivsqrt/sbtm_a1.sv
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module sbtm_a1 (input logic [6:0] a,
output logic [4:0] y);
always_comb
case(a)
7'b0000000: y = 5'b11100;
7'b0000001: y = 5'b11000;
7'b0000010: y = 5'b10100;
7'b0000011: y = 5'b10000;
7'b0000100: y = 5'b01101;
7'b0000101: y = 5'b01001;
7'b0000110: y = 5'b00101;
7'b0000111: y = 5'b00001;
7'b0001000: y = 5'b11001;
7'b0001001: y = 5'b10101;
7'b0001010: y = 5'b10010;
7'b0001011: y = 5'b01111;
7'b0001100: y = 5'b01011;
7'b0001101: y = 5'b01000;
7'b0001110: y = 5'b00101;
7'b0001111: y = 5'b00001;
7'b0010000: y = 5'b10110;
7'b0010001: y = 5'b10011;
7'b0010010: y = 5'b10000;
7'b0010011: y = 5'b01101;
7'b0010100: y = 5'b01010;
7'b0010101: y = 5'b00111;
7'b0010110: y = 5'b00100;
7'b0010111: y = 5'b00001;
7'b0011000: y = 5'b10100;
7'b0011001: y = 5'b10001;
7'b0011010: y = 5'b01110;
7'b0011011: y = 5'b01100;
7'b0011100: y = 5'b01001;
7'b0011101: y = 5'b00110;
7'b0011110: y = 5'b00100;
7'b0011111: y = 5'b00001;
7'b0100000: y = 5'b10010;
7'b0100001: y = 5'b01111;
7'b0100010: y = 5'b01101;
7'b0100011: y = 5'b01010;
7'b0100100: y = 5'b01000;
7'b0100101: y = 5'b00110;
7'b0100110: y = 5'b00011;
7'b0100111: y = 5'b00001;
7'b0101000: y = 5'b10000;
7'b0101001: y = 5'b01110;
7'b0101010: y = 5'b01100;
7'b0101011: y = 5'b01001;
7'b0101100: y = 5'b00111;
7'b0101101: y = 5'b00101;
7'b0101110: y = 5'b00011;
7'b0101111: y = 5'b00001;
7'b0110000: y = 5'b01111;
7'b0110001: y = 5'b01101;
7'b0110010: y = 5'b01011;
7'b0110011: y = 5'b01001;
7'b0110100: y = 5'b00111;
7'b0110101: y = 5'b00101;
7'b0110110: y = 5'b00011;
7'b0110111: y = 5'b00001;
7'b0111000: y = 5'b01101;
7'b0111001: y = 5'b01100;
7'b0111010: y = 5'b01010;
7'b0111011: y = 5'b01000;
7'b0111100: y = 5'b00110;
7'b0111101: y = 5'b00100;
7'b0111110: y = 5'b00010;
7'b0111111: y = 5'b00000;
7'b1000000: y = 5'b01100;
7'b1000001: y = 5'b01011;
7'b1000010: y = 5'b01001;
7'b1000011: y = 5'b00111;
7'b1000100: y = 5'b00101;
7'b1000101: y = 5'b00100;
7'b1000110: y = 5'b00010;
7'b1000111: y = 5'b00000;
7'b1001000: y = 5'b01011;
7'b1001001: y = 5'b01010;
7'b1001010: y = 5'b01000;
7'b1001011: y = 5'b00111;
7'b1001100: y = 5'b00101;
7'b1001101: y = 5'b00011;
7'b1001110: y = 5'b00010;
7'b1001111: y = 5'b00000;
7'b1010000: y = 5'b01010;
7'b1010001: y = 5'b01001;
7'b1010010: y = 5'b01000;
7'b1010011: y = 5'b00110;
7'b1010100: y = 5'b00101;
7'b1010101: y = 5'b00011;
7'b1010110: y = 5'b00010;
7'b1010111: y = 5'b00000;
7'b1011000: y = 5'b01010;
7'b1011001: y = 5'b01000;
7'b1011010: y = 5'b00111;
7'b1011011: y = 5'b00110;
7'b1011100: y = 5'b00100;
7'b1011101: y = 5'b00011;
7'b1011110: y = 5'b00010;
7'b1011111: y = 5'b00000;
7'b1100000: y = 5'b01001;
7'b1100001: y = 5'b01000;
7'b1100010: y = 5'b00110;
7'b1100011: y = 5'b00101;
7'b1100100: y = 5'b00100;
7'b1100101: y = 5'b00011;
7'b1100110: y = 5'b00001;
7'b1100111: y = 5'b00000;
7'b1101000: y = 5'b01000;
7'b1101001: y = 5'b00111;
7'b1101010: y = 5'b00110;
7'b1101011: y = 5'b00101;
7'b1101100: y = 5'b00100;
7'b1101101: y = 5'b00010;
7'b1101110: y = 5'b00001;
7'b1101111: y = 5'b00000;
7'b1110000: y = 5'b01000;
7'b1110001: y = 5'b00111;
7'b1110010: y = 5'b00110;
7'b1110011: y = 5'b00100;
7'b1110100: y = 5'b00011;
7'b1110101: y = 5'b00010;
7'b1110110: y = 5'b00001;
7'b1110111: y = 5'b00000;
7'b1111000: y = 5'b00111;
7'b1111001: y = 5'b00110;
7'b1111010: y = 5'b00101;
7'b1111011: y = 5'b00100;
7'b1111100: y = 5'b00011;
7'b1111101: y = 5'b00010;
7'b1111110: y = 5'b00001;
7'b1111111: y = 5'b00000;
default: y = 5'bxxxxx;
endcase // case (a)
endmodule // sbtm_a0

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wally-pipelined/src/fpudivsqrt/sbtm_a2.sv
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module sbtm_a2 (input logic [6:0] a,
output logic [12:0] y);
always_comb
case(a)
7'b0000000: y = 13'b1111111110001;
7'b0000001: y = 13'b1111111010001;
7'b0000010: y = 13'b1111110110010;
7'b0000011: y = 13'b1111110010011;
7'b0000100: y = 13'b1111101110101;
7'b0000101: y = 13'b1111101010110;
7'b0000110: y = 13'b1111100111001;
7'b0000111: y = 13'b1111100011011;
7'b0001000: y = 13'b1111011111110;
7'b0001001: y = 13'b1111011100001;
7'b0001010: y = 13'b1111011000100;
7'b0001011: y = 13'b1111010101000;
7'b0001100: y = 13'b1111010001100;
7'b0001101: y = 13'b1111001110000;
7'b0001110: y = 13'b1111001010101;
7'b0001111: y = 13'b1111000111010;
7'b0010000: y = 13'b1111000011111;
7'b0010001: y = 13'b1111000000100;
7'b0010010: y = 13'b1110111101010;
7'b0010011: y = 13'b1110111010000;
7'b0010100: y = 13'b1110110110110;
7'b0010101: y = 13'b1110110011101;
7'b0010110: y = 13'b1110110000100;
7'b0010111: y = 13'b1110101101011;
7'b0011000: y = 13'b1110101010010;
7'b0011001: y = 13'b1110100111001;
7'b0011010: y = 13'b1110100100001;
7'b0011011: y = 13'b1110100001001;
7'b0011100: y = 13'b1110011110001;
7'b0011101: y = 13'b1110011011010;
7'b0011110: y = 13'b1110011000010;
7'b0011111: y = 13'b1110010101011;
7'b0100000: y = 13'b1110010010100;
7'b0100001: y = 13'b1110001111110;
7'b0100010: y = 13'b1110001100111;
7'b0100011: y = 13'b1110001010001;
7'b0100100: y = 13'b1110000111011;
7'b0100101: y = 13'b1110000100101;
7'b0100110: y = 13'b1110000001111;
7'b0100111: y = 13'b1101111111010;
7'b0101000: y = 13'b1101111100101;
7'b0101001: y = 13'b1101111010000;
7'b0101010: y = 13'b1101110111011;
7'b0101011: y = 13'b1101110100110;
7'b0101100: y = 13'b1101110010001;
7'b0101101: y = 13'b1101101111101;
7'b0101110: y = 13'b1101101101001;
7'b0101111: y = 13'b1101101010101;
7'b0110000: y = 13'b1101101000001;
7'b0110001: y = 13'b1101100101101;
7'b0110010: y = 13'b1101100011010;
7'b0110011: y = 13'b1101100000110;
7'b0110100: y = 13'b1101011110011;
7'b0110101: y = 13'b1101011100000;
7'b0110110: y = 13'b1101011001101;
7'b0110111: y = 13'b1101010111010;
7'b0111000: y = 13'b1101010101000;
7'b0111001: y = 13'b1101010010101;
7'b0111010: y = 13'b1101010000011;
7'b0111011: y = 13'b1101001110001;
7'b0111100: y = 13'b1101001011111;
7'b0111101: y = 13'b1101001001101;
7'b0111110: y = 13'b1101000111100;
7'b0111111: y = 13'b1101000101010;
7'b1000000: y = 13'b1101000011001;
7'b1000001: y = 13'b1101000000111;
7'b1000010: y = 13'b1100111110110;
7'b1000011: y = 13'b1100111100101;
7'b1000100: y = 13'b1100111010100;
7'b1000101: y = 13'b1100111000011;
7'b1000110: y = 13'b1100110110011;
7'b1000111: y = 13'b1100110100010;
7'b1001000: y = 13'b1100110010010;
7'b1001001: y = 13'b1100110000010;
7'b1001010: y = 13'b1100101110010;
7'b1001011: y = 13'b1100101100001;
7'b1001100: y = 13'b1100101010010;
7'b1001101: y = 13'b1100101000010;
7'b1001110: y = 13'b1100100110010;
7'b1001111: y = 13'b1100100100011;
7'b1010000: y = 13'b1100100010011;
7'b1010001: y = 13'b1100100000100;
7'b1010010: y = 13'b1100011110101;
7'b1010011: y = 13'b1100011100101;
7'b1010100: y = 13'b1100011010110;
7'b1010101: y = 13'b1100011000111;
7'b1010110: y = 13'b1100010111001;
7'b1010111: y = 13'b1100010101010;
7'b1011000: y = 13'b1100010011011;
7'b1011001: y = 13'b1100010001101;
7'b1011010: y = 13'b1100001111110;
7'b1011011: y = 13'b1100001110000;
7'b1011100: y = 13'b1100001100010;
7'b1011101: y = 13'b1100001010100;
7'b1011110: y = 13'b1100001000110;
7'b1011111: y = 13'b1100000111000;
7'b1100000: y = 13'b1100000101010;
7'b1100001: y = 13'b1100000011100;
7'b1100010: y = 13'b1100000001111;
7'b1100011: y = 13'b1100000000001;
7'b1100100: y = 13'b1011111110100;
7'b1100101: y = 13'b1011111100110;
7'b1100110: y = 13'b1011111011001;
7'b1100111: y = 13'b1011111001100;
7'b1101000: y = 13'b1011110111111;
7'b1101001: y = 13'b1011110110010;
7'b1101010: y = 13'b1011110100101;
7'b1101011: y = 13'b1011110011000;
7'b1101100: y = 13'b1011110001011;
7'b1101101: y = 13'b1011101111110;
7'b1101110: y = 13'b1011101110010;
7'b1101111: y = 13'b1011101100101;
7'b1110000: y = 13'b1011101011001;
7'b1110001: y = 13'b1011101001100;
7'b1110010: y = 13'b1011101000000;
7'b1110011: y = 13'b1011100110100;
7'b1110100: y = 13'b1011100101000;
7'b1110101: y = 13'b1011100011100;
7'b1110110: y = 13'b1011100010000;
7'b1110111: y = 13'b1011100000100;
7'b1111000: y = 13'b1011011111000;
7'b1111001: y = 13'b1011011101100;
7'b1111010: y = 13'b1011011100000;
7'b1111011: y = 13'b1011011010101;
7'b1111100: y = 13'b1011011001001;
7'b1111101: y = 13'b1011010111101;
7'b1111110: y = 13'b1011010110010;
7'b1111111: y = 13'b1011010100111;
default: y = 13'bxxxxxxxxxxxxx;
endcase // case (a)
endmodule // sbtm_a0

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module sbtm_a2 (input logic [7:0] a,
output logic [13:0] y);
always_comb
case(a)
8'b01000000: y = 14'b10110100010111;
8'b01000001: y = 14'b10110010111111;
8'b01000010: y = 14'b10110001101000;
8'b01000011: y = 14'b10110000010011;
8'b01000100: y = 14'b10101111000001;
8'b01000101: y = 14'b10101101110000;
8'b01000110: y = 14'b10101100100001;
8'b01000111: y = 14'b10101011010011;
8'b01001000: y = 14'b10101010000111;
8'b01001001: y = 14'b10101000111101;
8'b01001010: y = 14'b10100111110100;
8'b01001011: y = 14'b10100110101101;
8'b01001100: y = 14'b10100101100111;
8'b01001101: y = 14'b10100100100010;
8'b01001110: y = 14'b10100011011111;
8'b01001111: y = 14'b10100010011101;
8'b01010000: y = 14'b10100001011100;
8'b01010001: y = 14'b10100000011100;
8'b01010010: y = 14'b10011111011110;
8'b01010011: y = 14'b10011110100001;
8'b01010100: y = 14'b10011101100100;
8'b01010101: y = 14'b10011100101001;
8'b01010110: y = 14'b10011011101111;
8'b01010111: y = 14'b10011010110110;
8'b01011000: y = 14'b10011001111110;
8'b01011001: y = 14'b10011001000110;
8'b01011010: y = 14'b10011000010000;
8'b01011011: y = 14'b10010111011011;
8'b01011100: y = 14'b10010110100110;
8'b01011101: y = 14'b10010101110011;
8'b01011110: y = 14'b10010101000000;
8'b01011111: y = 14'b10010100001110;
8'b01100000: y = 14'b10010011011100;
8'b01100001: y = 14'b10010010101100;
8'b01100010: y = 14'b10010001111100;
8'b01100011: y = 14'b10010001001101;
8'b01100100: y = 14'b10010000011111;
8'b01100101: y = 14'b10001111110001;
8'b01100110: y = 14'b10001111000100;
8'b01100111: y = 14'b10001110011000;
8'b01101000: y = 14'b10001101101100;
8'b01101001: y = 14'b10001101000001;
8'b01101010: y = 14'b10001100010110;
8'b01101011: y = 14'b10001011101100;
8'b01101100: y = 14'b10001011000011;
8'b01101101: y = 14'b10001010011010;
8'b01101110: y = 14'b10001001110010;
8'b01101111: y = 14'b10001001001010;
8'b01110000: y = 14'b10001000100011;
8'b01110001: y = 14'b10000111111101;
8'b01110010: y = 14'b10000111010111;
8'b01110011: y = 14'b10000110110001;
8'b01110100: y = 14'b10000110001100;
8'b01110101: y = 14'b10000101100111;
8'b01110110: y = 14'b10000101000011;
8'b01110111: y = 14'b10000100011111;
8'b01111000: y = 14'b10000011111100;
8'b01111001: y = 14'b10000011011001;
8'b01111010: y = 14'b10000010110111;
8'b01111011: y = 14'b10000010010101;
8'b01111100: y = 14'b10000001110011;
8'b01111101: y = 14'b10000001010010;
8'b01111110: y = 14'b10000000110001;
8'b01111111: y = 14'b10000000010001;
8'b10000000: y = 14'b01111111110001;
8'b10000001: y = 14'b01111111010001;
8'b10000010: y = 14'b01111110110010;
8'b10000011: y = 14'b01111110010011;
8'b10000100: y = 14'b01111101110101;
8'b10000101: y = 14'b01111101010110;
8'b10000110: y = 14'b01111100111001;
8'b10000111: y = 14'b01111100011011;
8'b10001000: y = 14'b01111011111110;
8'b10001001: y = 14'b01111011100001;
8'b10001010: y = 14'b01111011000100;
8'b10001011: y = 14'b01111010101000;
8'b10001100: y = 14'b01111010001100;
8'b10001101: y = 14'b01111001110000;
8'b10001110: y = 14'b01111001010101;
8'b10001111: y = 14'b01111000111010;
8'b10010000: y = 14'b01111000011111;
8'b10010001: y = 14'b01111000000100;
8'b10010010: y = 14'b01110111101010;
8'b10010011: y = 14'b01110111010000;
8'b10010100: y = 14'b01110110110110;
8'b10010101: y = 14'b01110110011101;
8'b10010110: y = 14'b01110110000100;
8'b10010111: y = 14'b01110101101011;
8'b10011000: y = 14'b01110101010010;
8'b10011001: y = 14'b01110100111001;
8'b10011010: y = 14'b01110100100001;
8'b10011011: y = 14'b01110100001001;
8'b10011100: y = 14'b01110011110001;
8'b10011101: y = 14'b01110011011010;
8'b10011110: y = 14'b01110011000010;
8'b10011111: y = 14'b01110010101011;
8'b10100000: y = 14'b01110010010100;
8'b10100001: y = 14'b01110001111110;
8'b10100010: y = 14'b01110001100111;
8'b10100011: y = 14'b01110001010001;
8'b10100100: y = 14'b01110000111011;
8'b10100101: y = 14'b01110000100101;
8'b10100110: y = 14'b01110000001111;
8'b10100111: y = 14'b01101111111010;
8'b10101000: y = 14'b01101111100101;
8'b10101001: y = 14'b01101111010000;
8'b10101010: y = 14'b01101110111011;
8'b10101011: y = 14'b01101110100110;
8'b10101100: y = 14'b01101110010001;
8'b10101101: y = 14'b01101101111101;
8'b10101110: y = 14'b01101101101001;
8'b10101111: y = 14'b01101101010101;
8'b10110000: y = 14'b01101101000001;
8'b10110001: y = 14'b01101100101101;
8'b10110010: y = 14'b01101100011010;
8'b10110011: y = 14'b01101100000110;
8'b10110100: y = 14'b01101011110011;
8'b10110101: y = 14'b01101011100000;
8'b10110110: y = 14'b01101011001101;
8'b10110111: y = 14'b01101010111010;
8'b10111000: y = 14'b01101010101000;
8'b10111001: y = 14'b01101010010101;
8'b10111010: y = 14'b01101010000011;
8'b10111011: y = 14'b01101001110001;
8'b10111100: y = 14'b01101001011111;
8'b10111101: y = 14'b01101001001101;
8'b10111110: y = 14'b01101000111100;
8'b10111111: y = 14'b01101000101010;
8'b11000000: y = 14'b01101000011001;
8'b11000001: y = 14'b01101000000111;
8'b11000010: y = 14'b01100111110110;
8'b11000011: y = 14'b01100111100101;
8'b11000100: y = 14'b01100111010100;
8'b11000101: y = 14'b01100111000011;
8'b11000110: y = 14'b01100110110011;
8'b11000111: y = 14'b01100110100010;
8'b11001000: y = 14'b01100110010010;
8'b11001001: y = 14'b01100110000010;
8'b11001010: y = 14'b01100101110010;
8'b11001011: y = 14'b01100101100001;
8'b11001100: y = 14'b01100101010010;
8'b11001101: y = 14'b01100101000010;
8'b11001110: y = 14'b01100100110010;
8'b11001111: y = 14'b01100100100011;
8'b11010000: y = 14'b01100100010011;
8'b11010001: y = 14'b01100100000100;
8'b11010010: y = 14'b01100011110101;
8'b11010011: y = 14'b01100011100101;
8'b11010100: y = 14'b01100011010110;
8'b11010101: y = 14'b01100011000111;
8'b11010110: y = 14'b01100010111001;
8'b11010111: y = 14'b01100010101010;
8'b11011000: y = 14'b01100010011011;
8'b11011001: y = 14'b01100010001101;
8'b11011010: y = 14'b01100001111110;
8'b11011011: y = 14'b01100001110000;
8'b11011100: y = 14'b01100001100010;
8'b11011101: y = 14'b01100001010100;
8'b11011110: y = 14'b01100001000110;
8'b11011111: y = 14'b01100000111000;
8'b11100000: y = 14'b01100000101010;
8'b11100001: y = 14'b01100000011100;
8'b11100010: y = 14'b01100000001111;
8'b11100011: y = 14'b01100000000001;
8'b11100100: y = 14'b01011111110100;
8'b11100101: y = 14'b01011111100110;
8'b11100110: y = 14'b01011111011001;
8'b11100111: y = 14'b01011111001100;
8'b11101000: y = 14'b01011110111111;
8'b11101001: y = 14'b01011110110010;
8'b11101010: y = 14'b01011110100101;
8'b11101011: y = 14'b01011110011000;
8'b11101100: y = 14'b01011110001011;
8'b11101101: y = 14'b01011101111110;
8'b11101110: y = 14'b01011101110010;
8'b11101111: y = 14'b01011101100101;
8'b11110000: y = 14'b01011101011001;
8'b11110001: y = 14'b01011101001100;
8'b11110010: y = 14'b01011101000000;
8'b11110011: y = 14'b01011100110100;
8'b11110100: y = 14'b01011100101000;
8'b11110101: y = 14'b01011100011100;
8'b11110110: y = 14'b01011100010000;
8'b11110111: y = 14'b01011100000100;
8'b11111000: y = 14'b01011011111000;
8'b11111001: y = 14'b01011011101100;
8'b11111010: y = 14'b01011011100000;
8'b11111011: y = 14'b01011011010101;
8'b11111100: y = 14'b01011011001001;
8'b11111101: y = 14'b01011010111101;
8'b11111110: y = 14'b01011010110010;
8'b11111111: y = 14'b01011010100111;
default: y = 14'bxxxxxxxxxxxxxx;
endcase // case (a)
endmodule // sbtm_a0

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module sbtm_a3 (input logic [7:0] a,
output logic [5:0] y);
always_comb
case(a)
8'b01000000: y = 6'b100110;
8'b01000001: y = 6'b100001;
8'b01000010: y = 6'b011100;
8'b01000011: y = 6'b010111;
8'b01000100: y = 6'b010010;
8'b01000101: y = 6'b001100;
8'b01000110: y = 6'b000111;
8'b01000111: y = 6'b000010;
8'b01001000: y = 6'b100000;
8'b01001001: y = 6'b011100;
8'b01001010: y = 6'b011000;
8'b01001011: y = 6'b010011;
8'b01001100: y = 6'b001111;
8'b01001101: y = 6'b001010;
8'b01001110: y = 6'b000110;
8'b01001111: y = 6'b000010;
8'b01010000: y = 6'b011100;
8'b01010001: y = 6'b011000;
8'b01010010: y = 6'b010100;
8'b01010011: y = 6'b010000;
8'b01010100: y = 6'b001101;
8'b01010101: y = 6'b001001;
8'b01010110: y = 6'b000101;
8'b01010111: y = 6'b000001;
8'b01011000: y = 6'b011000;
8'b01011001: y = 6'b010101;
8'b01011010: y = 6'b010010;
8'b01011011: y = 6'b001110;
8'b01011100: y = 6'b001011;
8'b01011101: y = 6'b001000;
8'b01011110: y = 6'b000100;
8'b01011111: y = 6'b000001;
8'b01100000: y = 6'b010101;
8'b01100001: y = 6'b010010;
8'b01100010: y = 6'b001111;
8'b01100011: y = 6'b001101;
8'b01100100: y = 6'b001010;
8'b01100101: y = 6'b000111;
8'b01100110: y = 6'b000100;
8'b01100111: y = 6'b000001;
8'b01101000: y = 6'b010011;
8'b01101001: y = 6'b010000;
8'b01101010: y = 6'b001110;
8'b01101011: y = 6'b001011;
8'b01101100: y = 6'b001001;
8'b01101101: y = 6'b000110;
8'b01101110: y = 6'b000011;
8'b01101111: y = 6'b000001;
8'b01110000: y = 6'b010001;
8'b01110001: y = 6'b001111;
8'b01110010: y = 6'b001100;
8'b01110011: y = 6'b001010;
8'b01110100: y = 6'b001000;
8'b01110101: y = 6'b000101;
8'b01110110: y = 6'b000011;
8'b01110111: y = 6'b000001;
8'b01111000: y = 6'b001111;
8'b01111001: y = 6'b001101;
8'b01111010: y = 6'b001011;
8'b01111011: y = 6'b001001;
8'b01111100: y = 6'b000111;
8'b01111101: y = 6'b000101;
8'b01111110: y = 6'b000011;
8'b01111111: y = 6'b000001;
8'b10000000: y = 6'b001110;
8'b10000001: y = 6'b001100;
8'b10000010: y = 6'b001010;
8'b10000011: y = 6'b001000;
8'b10000100: y = 6'b000110;
8'b10000101: y = 6'b000100;
8'b10000110: y = 6'b000010;
8'b10000111: y = 6'b000000;
8'b10001000: y = 6'b001101;
8'b10001001: y = 6'b001011;
8'b10001010: y = 6'b001001;
8'b10001011: y = 6'b000111;
8'b10001100: y = 6'b000110;
8'b10001101: y = 6'b000100;
8'b10001110: y = 6'b000010;
8'b10001111: y = 6'b000000;
8'b10010000: y = 6'b001100;
8'b10010001: y = 6'b001010;
8'b10010010: y = 6'b001000;
8'b10010011: y = 6'b000111;
8'b10010100: y = 6'b000101;
8'b10010101: y = 6'b000100;
8'b10010110: y = 6'b000010;
8'b10010111: y = 6'b000000;
8'b10011000: y = 6'b001011;
8'b10011001: y = 6'b001001;
8'b10011010: y = 6'b001000;
8'b10011011: y = 6'b000110;
8'b10011100: y = 6'b000101;
8'b10011101: y = 6'b000011;
8'b10011110: y = 6'b000010;
8'b10011111: y = 6'b000000;
8'b10100000: y = 6'b001010;
8'b10100001: y = 6'b001000;
8'b10100010: y = 6'b000111;
8'b10100011: y = 6'b000110;
8'b10100100: y = 6'b000100;
8'b10100101: y = 6'b000011;
8'b10100110: y = 6'b000010;
8'b10100111: y = 6'b000000;
8'b10101000: y = 6'b001001;
8'b10101001: y = 6'b001000;
8'b10101010: y = 6'b000111;
8'b10101011: y = 6'b000101;
8'b10101100: y = 6'b000100;
8'b10101101: y = 6'b000011;
8'b10101110: y = 6'b000001;
8'b10101111: y = 6'b000000;
8'b10110000: y = 6'b001000;
8'b10110001: y = 6'b000111;
8'b10110010: y = 6'b000110;
8'b10110011: y = 6'b000101;
8'b10110100: y = 6'b000100;
8'b10110101: y = 6'b000010;
8'b10110110: y = 6'b000001;
8'b10110111: y = 6'b000000;
8'b10111000: y = 6'b001000;
8'b10111001: y = 6'b000111;
8'b10111010: y = 6'b000110;
8'b10111011: y = 6'b000101;
8'b10111100: y = 6'b000011;
8'b10111101: y = 6'b000010;
8'b10111110: y = 6'b000001;
8'b10111111: y = 6'b000000;
8'b11000000: y = 6'b000111;
8'b11000001: y = 6'b000110;
8'b11000010: y = 6'b000101;
8'b11000011: y = 6'b000100;
8'b11000100: y = 6'b000011;
8'b11000101: y = 6'b000010;
8'b11000110: y = 6'b000001;
8'b11000111: y = 6'b000000;
8'b11001000: y = 6'b000111;
8'b11001001: y = 6'b000110;
8'b11001010: y = 6'b000101;
8'b11001011: y = 6'b000100;
8'b11001100: y = 6'b000011;
8'b11001101: y = 6'b000010;
8'b11001110: y = 6'b000001;
8'b11001111: y = 6'b000000;
8'b11010000: y = 6'b000111;
8'b11010001: y = 6'b000110;
8'b11010010: y = 6'b000101;
8'b11010011: y = 6'b000100;
8'b11010100: y = 6'b000011;
8'b11010101: y = 6'b000010;
8'b11010110: y = 6'b000001;
8'b11010111: y = 6'b000000;
8'b11011000: y = 6'b000110;
8'b11011001: y = 6'b000101;
8'b11011010: y = 6'b000100;
8'b11011011: y = 6'b000011;
8'b11011100: y = 6'b000011;
8'b11011101: y = 6'b000010;
8'b11011110: y = 6'b000001;
8'b11011111: y = 6'b000000;
8'b11100000: y = 6'b000110;
8'b11100001: y = 6'b000101;
8'b11100010: y = 6'b000100;
8'b11100011: y = 6'b000011;
8'b11100100: y = 6'b000010;
8'b11100101: y = 6'b000010;
8'b11100110: y = 6'b000001;
8'b11100111: y = 6'b000000;
8'b11101000: y = 6'b000101;
8'b11101001: y = 6'b000101;
8'b11101010: y = 6'b000100;
8'b11101011: y = 6'b000011;
8'b11101100: y = 6'b000010;
8'b11101101: y = 6'b000001;
8'b11101110: y = 6'b000001;
8'b11101111: y = 6'b000000;
8'b11110000: y = 6'b000101;
8'b11110001: y = 6'b000100;
8'b11110010: y = 6'b000100;
8'b11110011: y = 6'b000011;
8'b11110100: y = 6'b000010;
8'b11110101: y = 6'b000001;
8'b11110110: y = 6'b000001;
8'b11110111: y = 6'b000000;
8'b11111000: y = 6'b000101;
8'b11111001: y = 6'b000100;
8'b11111010: y = 6'b000011;
8'b11111011: y = 6'b000011;
8'b11111100: y = 6'b000010;
8'b11111101: y = 6'b000001;
8'b11111110: y = 6'b000001;
8'b11111111: y = 6'b000000;
default: y = 6'bxxxxxx;
endcase // case (a)
endmodule // sbtm_a0

6
wally-pipelined/src/fpudivsqrt/sim.csh
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@ -1,6 +0,0 @@
#!/bin/sh
runme_f64div.csh
runme_f32div.csh
runme_f64sqrt_csh
runme_f32sqrt.csh
echo "Simulation Ended, Go Pokes!..."

112
wally-pipelined/src/fpudivsqrt/sk14.v
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@ -1,112 +0,0 @@
// Sklansky Prefix Adder
module exp_add (cout, sum, a, b, cin);
input [13:0] a, b;
input cin;
output [13:0] sum;
output cout;
wire [14:0] p,g;
wire [13:0] c;
// pre-computation
assign p={a^b,1'b0};
assign g={a&b, cin};
// prefix tree
sklansky prefix_tree(c, p[13:0], g[13:0]);
// post-computation
assign sum=p[14:1]^c;
assign cout=g[14]|(p[14]&c[13]);
endmodule
module sklansky (c, p, g);
input [13:0] p;
input [13:0] g;
output [14:1] c;
// parallel-prefix, Sklansky
// Stage 1: Generates G/P pairs that span 1 bits
grey b_1_0 (G_1_0, {g[1],g[0]}, p[1]);
black b_3_2 (G_3_2, P_3_2, {g[3],g[2]}, {p[3],p[2]});
black b_5_4 (G_5_4, P_5_4, {g[5],g[4]}, {p[5],p[4]});
black b_7_6 (G_7_6, P_7_6, {g[7],g[6]}, {p[7],p[6]});
black b_9_8 (G_9_8, P_9_8, {g[9],g[8]}, {p[9],p[8]});
black b_11_10 (G_11_10, P_11_10, {g[11],g[10]}, {p[11],p[10]});
black b_13_12 (G_13_12, P_13_12, {g[13],g[12]}, {p[13],p[12]});
// Stage 2: Generates G/P pairs that span 2 bits
grey g_2_0 (G_2_0, {g[2],G_1_0}, p[2]);
grey g_3_0 (G_3_0, {G_3_2,G_1_0}, P_3_2);
black b_6_4 (G_6_4, P_6_4, {g[6],G_5_4}, {p[6],P_5_4});
black b_7_4 (G_7_4, P_7_4, {G_7_6,G_5_4}, {P_7_6,P_5_4});
black b_10_8 (G_10_8, P_10_8, {g[10],G_9_8}, {p[10],P_9_8});
black b_11_8 (G_11_8, P_11_8, {G_11_10,G_9_8}, {P_11_10,P_9_8});
black b_14_12 (G_14_12, P_14_12, {g[14],G_13_12}, {p[14],P_13_12});
black b_15_12 (G_15_12, P_15_12, {G_15_14,G_13_12}, {P_15_14,P_13_12});
// Stage 3: Generates G/P pairs that span 4 bits
grey g_4_0 (G_4_0, {g[4],G_3_0}, p[4]);
grey g_5_0 (G_5_0, {G_5_4,G_3_0}, P_5_4);
grey g_6_0 (G_6_0, {G_6_4,G_3_0}, P_6_4);
grey g_7_0 (G_7_0, {G_7_4,G_3_0}, P_7_4);
black b_12_8 (G_12_8, P_12_8, {g[12],G_11_8}, {p[12],P_11_8});
black b_13_8 (G_13_8, P_13_8, {G_13_12,G_11_8}, {P_13_12,P_11_8});
black b_14_8 (G_14_8, P_14_8, {G_14_12,G_11_8}, {P_14_12,P_11_8});
black b_15_8 (G_15_8, P_15_8, {G_15_12,G_11_8}, {P_15_12,P_11_8});
// Stage 4: Generates G/P pairs that span 8 bits
grey g_8_0 (G_8_0, {g[8],G_7_0}, p[8]);
grey g_9_0 (G_9_0, {G_9_8,G_7_0}, P_9_8);
grey g_10_0 (G_10_0, {G_10_8,G_7_0}, P_10_8);
grey g_11_0 (G_11_0, {G_11_8,G_7_0}, P_11_8);
grey g_12_0 (G_12_0, {G_12_8,G_7_0}, P_12_8);
grey g_13_0 (G_13_0, {G_13_8,G_7_0}, P_13_8);
grey g_14_0 (G_14_0, {G_14_8,G_7_0}, P_14_8);
grey g_15_0 (G_15_0, {G_15_8,G_7_0}, P_15_8);
// Final Stage: Apply c_k+1=G_k_0
assign c[1]=g[0];
assign c[2]=G_1_0;
assign c[3]=G_2_0;
assign c[4]=G_3_0;
assign c[5]=G_4_0;
assign c[6]=G_5_0;
assign c[7]=G_6_0;
assign c[8]=G_7_0;
assign c[9]=G_8_0;
assign c[10]=G_9_0;
assign c[11]=G_10_0;
assign c[12]=G_11_0;
assign c[13]=G_12_0;
assign c[14]=G_13_0;
endmodule
// Black cell
module black(gout, pout, gin, pin);
input [1:0] gin, pin;
output gout, pout;
assign pout=pin[1]&pin[0];
assign gout=gin[1]|(pin[1]&gin[0]);
endmodule
// Grey cell
module grey(gout, gin, pin);
input[1:0] gin;
input pin;
output gout;
assign gout=gin[1]|(pin&gin[0]);
endmodule

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wally-pipelined/src/fpudivsqrt/tb_f32_div_rd.sv
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// testbench
module tb ();
logic [31:0] op1;
logic [31:0] op2;
logic [1:0] rm;
logic op_type;
logic P;
logic OvEn;
logic UnEn;
logic start;
logic reset;
logic [63:0] AS_Result;
logic [4:0] Flags;
logic Denorm;
logic done;
logic clk;
logic [31:0] yexpected;
logic [63:0] vectornum, errors; // bookkeeping variables
logic [103:0] testvectors[50000:0]; // array of testvectors
logic [7:0] flags_expected;
integer handle3;
integer desc3;
// instantiate device under test
fpdiv dut (done, AS_Result, Flags, Denorm, {op1, 32'h0}, {op2, 32'h0}, rm, op_type, P, OvEn, UnEn,
start, reset, clk);
initial
begin
clk = 1'b1;
forever #333 clk = ~clk;
end
initial
begin
handle3 = $fopen("f32_div_rd.out");
$readmemh("f32_div_rd.tv", testvectors);
vectornum = 0; errors = 0;
start = 1'b0;
// reset
reset = 1; #27; reset = 0;
end
initial
begin
desc3 = handle3;
#0 op_type = 1'b0;
#0 P = 1'b1;
#0 rm = 2'b11;
#0 OvEn = 1'b0;
#0 UnEn = 1'b0;
end
always @(posedge clk)
begin
if (~reset)
begin
#0; {op1, op2, yexpected, flags_expected} = testvectors[vectornum];
#50 start = 1'b1;
repeat (2)
@(posedge clk);
// deassert start after 2 cycles
start = 1'b0;
repeat (10)
@(posedge clk);
$fdisplay(desc3, "%h_%h_%h_%b_%b | %h_%b", op1, op2, AS_Result, Flags, Denorm, yexpected, (AS_Result[63:32]==yexpected));
vectornum = vectornum + 1;
end // if (~reset)
$display("%d vectors processed", vectornum);
end // always @ (posedge clk)
endmodule // tb

80
wally-pipelined/src/fpudivsqrt/tb_f32_div_rne.sv
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// testbench
module tb ();
logic [31:0] op1;
logic [31:0] op2;
logic [1:0] rm;
logic op_type;
logic P;
logic OvEn;
logic UnEn;
logic start;
logic reset;
logic [63:0] AS_Result;
logic [4:0] Flags;
logic Denorm;
logic done;
logic clk;
logic [31:0] yexpected;
logic [63:0] vectornum, errors; // bookkeeping variables
logic [103:0] testvectors[50000:0]; // array of testvectors
logic [7:0] flags_expected;
integer handle3;
integer desc3;
// instantiate device under test
fpdiv dut (done, AS_Result, Flags, Denorm, {op1, 32'h0}, {op2, 32'h0}, rm, op_type, P, OvEn, UnEn,
start, reset, clk);
initial
begin
clk = 1'b1;
forever #333 clk = ~clk;
end
initial
begin
handle3 = $fopen("f32_div_rne.out");
$readmemh("f32_div_rne.tv", testvectors);
vectornum = 0; errors = 0;
start = 1'b0;
// reset
reset = 1; #27; reset = 0;
end
initial
begin
desc3 = handle3;
#0 op_type = 1'b0;
#0 P = 1'b1;
#0 rm = 2'b00;
#0 OvEn = 1'b0;
#0 UnEn = 1'b0;
end
always @(posedge clk)
begin
if (~reset)
begin
#0; {op1, op2, yexpected, flags_expected} = testvectors[vectornum];
#50 start = 1'b1;
repeat (2)
@(posedge clk);
// deassert start after 2 cycles
start = 1'b0;
repeat (10)
@(posedge clk);
$fdisplay(desc3, "%h_%h_%h_%b_%b | %h_%b", op1, op2, AS_Result, Flags, Denorm, yexpected, (AS_Result[63:32]==yexpected));
vectornum = vectornum + 1;
end // if (~reset)
$display("%d vectors processed", vectornum);
end // always @ (posedge clk)
endmodule // tb

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wally-pipelined/src/fpudivsqrt/tb_f32_div_ru.sv
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// testbench
module tb ();
logic [31:0] op1;
logic [31:0] op2;
logic [1:0] rm;
logic op_type;
logic P;
logic OvEn;
logic UnEn;
logic start;
logic reset;
logic [63:0] AS_Result;
logic [4:0] Flags;
logic Denorm;
logic done;
logic clk;
logic [31:0] yexpected;
logic [63:0] vectornum, errors; // bookkeeping variables
logic [103:0] testvectors[50000:0]; // array of testvectors
logic [7:0] flags_expected;
integer handle3;
integer desc3;
// instantiate device under test
fpdiv dut (done, AS_Result, Flags, Denorm, {op1, 32'h0}, {op2, 32'h0}, rm, op_type, P, OvEn, UnEn,
start, reset, clk);
initial
begin
clk = 1'b1;
forever #333 clk = ~clk;
end
initial
begin
handle3 = $fopen("f32_div_ru.out");
$readmemh("f32_div_ru.tv", testvectors);
vectornum = 0; errors = 0;
start = 1'b0;
// reset
reset = 1; #27; reset = 0;
end
initial
begin
desc3 = handle3;
#0 op_type = 1'b0;
#0 P = 1'b1;
#0 rm = 2'b10;
#0 OvEn = 1'b0;
#0 UnEn = 1'b0;
end
always @(posedge clk)
begin
if (~reset)
begin
#0; {op1, op2, yexpected, flags_expected} = testvectors[vectornum];
#50 start = 1'b1;
repeat (2)
@(posedge clk);
// deassert start after 2 cycles
start = 1'b0;
repeat (10)
@(posedge clk);
$fdisplay(desc3, "%h_%h_%h_%b_%b | %h_%b", op1, op2, AS_Result, Flags, Denorm, yexpected, (AS_Result[63:32]==yexpected));
vectornum = vectornum + 1;
end // if (~reset)
$display("%d vectors processed", vectornum);
end // always @ (posedge clk)
endmodule // tb

80
wally-pipelined/src/fpudivsqrt/tb_f32_div_rz.sv
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// testbench
module tb ();
logic [31:0] op1;
logic [31:0] op2;
logic [1:0] rm;
logic op_type;
logic P;
logic OvEn;
logic UnEn;
logic start;
logic reset;
logic [63:0] AS_Result;
logic [4:0] Flags;
logic Denorm;
logic done;
logic clk;
logic [31:0] yexpected;
logic [63:0] vectornum, errors; // bookkeeping variables
logic [103:0] testvectors[50000:0]; // array of testvectors
logic [7:0] flags_expected;
integer handle3;
integer desc3;
// instantiate device under test
fpdiv dut (done, AS_Result, Flags, Denorm, {op1, 32'h0}, {op2, 32'h0}, rm, op_type, P, OvEn, UnEn,
start, reset, clk);
initial
begin
clk = 1'b1;
forever #333 clk = ~clk;
end
initial
begin
handle3 = $fopen("f32_div_rz.out");
$readmemh("f32_div_rz.tv", testvectors);
vectornum = 0; errors = 0;
start = 1'b0;
// reset
reset = 1; #27; reset = 0;
end
initial
begin
desc3 = handle3;
#0 op_type = 1'b0;
#0 P = 1'b1;
#0 rm = 2'b01;
#0 OvEn = 1'b0;
#0 UnEn = 1'b0;
end
always @(posedge clk)
begin
if (~reset)
begin
#0; {op1, op2, yexpected, flags_expected} = testvectors[vectornum];
#50 start = 1'b1;
repeat (2)
@(posedge clk);
// deassert start after 2 cycles
start = 1'b0;
repeat (10)
@(posedge clk);
$fdisplay(desc3, "%h_%h_%h_%b_%b | %h_%b", op1, op2, AS_Result, Flags, Denorm, yexpected, (AS_Result[63:32]==yexpected));
vectornum = vectornum + 1;
end // if (~reset)
$display("%d vectors processed", vectornum);
end // always @ (posedge clk)
endmodule // tb

79
wally-pipelined/src/fpudivsqrt/tb_f32_sqrt_rd.sv
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// testbench
module tb ();
logic [31:0] op1;
logic [1:0] rm;
logic op_type;
logic P;
logic OvEn;
logic UnEn;
logic start;
logic reset;
logic [63:0] AS_Result;
logic [4:0] Flags;
logic Denorm;
logic done;
logic clk;
logic [31:0] yexpected;
logic [63:0] vectornum, errors; // bookkeeping variables
logic [71:0] testvectors[50000:0]; // array of testvectors
logic [7:0] flags_expected;
integer handle3;
integer desc3;
// instantiate device under test
fpdiv dut (done, AS_Result, Flags, Denorm, {op1, 32'h0}, 64'h0, rm, op_type, P, OvEn, UnEn,
start, reset, clk);
initial
begin
clk = 1'b1;
forever #333 clk = ~clk;
end
initial
begin
handle3 = $fopen("f32_sqrt_rd.out");
$readmemh("f32_sqrt_rd.tv", testvectors);
vectornum = 0; errors = 0;
start = 1'b0;
// reset
reset = 1; #27; reset = 0;
end
initial
begin
desc3 = handle3;
#0 op_type = 1'b1;
#0 P = 1'b1;
#0 rm = 2'b11;
#0 OvEn = 1'b0;
#0 UnEn = 1'b0;
end
always @(posedge clk)
begin
if (~reset)
begin
#0; {op1, yexpected, flags_expected} = testvectors[vectornum];
#50 start = 1'b1;
repeat (2)
@(posedge clk);
// deassert start after 2 cycles
start = 1'b0;
repeat (15)
@(posedge clk);
$fdisplay(desc3, "%h_%h_%b_%b | %h_%b", op1, AS_Result, Flags, Denorm, yexpected, (AS_Result[63:32]==yexpected));
vectornum = vectornum + 1;
end // if (~reset)
$display("%d vectors processed", vectornum);
end // always @ (posedge clk)
endmodule // tb

79
wally-pipelined/src/fpudivsqrt/tb_f32_sqrt_rne.sv
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// testbench
module tb ();
logic [31:0] op1;
logic [1:0] rm;
logic op_type;
logic P;
logic OvEn;
logic UnEn;
logic start;
logic reset;
logic [63:0] AS_Result;
logic [4:0] Flags;
logic Denorm;
logic done;
logic clk;
logic [31:0] yexpected;
logic [63:0] vectornum, errors; // bookkeeping variables
logic [71:0] testvectors[50000:0]; // array of testvectors
logic [7:0] flags_expected;
integer handle3;
integer desc3;
// instantiate device under test
fpdiv dut (done, AS_Result, Flags, Denorm, {op1, 32'h0}, 64'h0, rm, op_type, P, OvEn, UnEn,
start, reset, clk);
initial
begin
clk = 1'b1;
forever #333 clk = ~clk;
end
initial
begin
handle3 = $fopen("f32_sqrt_rne.out");
$readmemh("f32_sqrt_rne.tv", testvectors);
vectornum = 0; errors = 0;
start = 1'b0;
// reset
reset = 1; #27; reset = 0;
end
initial
begin
desc3 = handle3;
#0 op_type = 1'b1;
#0 P = 1'b1;
#0 rm = 2'b00;
#0 OvEn = 1'b0;
#0 UnEn = 1'b0;
end
always @(posedge clk)
begin
if (~reset)
begin
#0; {op1, yexpected, flags_expected} = testvectors[vectornum];
#50 start = 1'b1;
repeat (2)
@(posedge clk);
// deassert start after 2 cycles
start = 1'b0;
repeat (15)
@(posedge clk);
$fdisplay(desc3, "%h_%h_%b_%b | %h_%b", op1, AS_Result, Flags, Denorm, yexpected, (AS_Result[63:32]==yexpected));
vectornum = vectornum + 1;
end // if (~reset)
$display("%d vectors processed", vectornum);
end // always @ (posedge clk)
endmodule // tb

79
wally-pipelined/src/fpudivsqrt/tb_f32_sqrt_ru.sv
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// testbench
module tb ();
logic [31:0] op1;
logic [1:0] rm;
logic op_type;
logic P;
logic OvEn;
logic UnEn;
logic start;
logic reset;
logic [63:0] AS_Result;
logic [4:0] Flags;
logic Denorm;
logic done;
logic clk;
logic [31:0] yexpected;
logic [63:0] vectornum, errors; // bookkeeping variables
logic [71:0] testvectors[50000:0]; // array of testvectors
logic [7:0] flags_expected;
integer handle3;
integer desc3;
// instantiate device under test
fpdiv dut (done, AS_Result, Flags, Denorm, {op1, 32'h0}, 64'h0, rm, op_type, P, OvEn, UnEn,
start, reset, clk);
initial
begin
clk = 1'b1;
forever #333 clk = ~clk;
end
initial
begin
handle3 = $fopen("f32_sqrt_ru.out");
$readmemh("f32_sqrt_ru.tv", testvectors);
vectornum = 0; errors = 0;
start = 1'b0;
// reset
reset = 1; #27; reset = 0;
end
initial
begin
desc3 = handle3;
#0 op_type = 1'b1;
#0 P = 1'b1;
#0 rm = 2'b10;
#0 OvEn = 1'b0;
#0 UnEn = 1'b0;
end
always @(posedge clk)
begin
if (~reset)
begin
#0; {op1, yexpected, flags_expected} = testvectors[vectornum];
#50 start = 1'b1;
repeat (2)
@(posedge clk);
// deassert start after 2 cycles
start = 1'b0;
repeat (15)
@(posedge clk);
$fdisplay(desc3, "%h_%h_%b_%b | %h_%b", op1, AS_Result, Flags, Denorm, yexpected, (AS_Result[63:32]==yexpected));
vectornum = vectornum + 1;
end // if (~reset)
$display("%d vectors processed", vectornum);
end // always @ (posedge clk)
endmodule // tb

79
wally-pipelined/src/fpudivsqrt/tb_f32_sqrt_rz.sv
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// testbench
module tb ();
logic [31:0] op1;
logic [1:0] rm;
logic op_type;
logic P;
logic OvEn;
logic UnEn;
logic start;
logic reset;
logic [63:0] AS_Result;
logic [4:0] Flags;
logic Denorm;
logic done;
logic clk;
logic [31:0] yexpected;
logic [63:0] vectornum, errors; // bookkeeping variables
logic [71:0] testvectors[50000:0]; // array of testvectors
logic [7:0] flags_expected;
integer handle3;
integer desc3;
// instantiate device under test
fpdiv dut (done, AS_Result, Flags, Denorm, {op1, 32'h0}, 64'h0, rm, op_type, P, OvEn, UnEn,
start, reset, clk);
initial
begin
clk = 1'b1;
forever #333 clk = ~clk;
end
initial
begin
handle3 = $fopen("f32_sqrt_rz.out");
$readmemh("f32_sqrt_rz.tv", testvectors);
vectornum = 0; errors = 0;
start = 1'b0;
// reset
reset = 1; #27; reset = 0;
end
initial
begin
desc3 = handle3;
#0 op_type = 1'b1;
#0 P = 1'b1;
#0 rm = 2'b01;
#0 OvEn = 1'b0;
#0 UnEn = 1'b0;
end
always @(posedge clk)
begin
if (~reset)
begin
#0; {op1, yexpected, flags_expected} = testvectors[vectornum];
#50 start = 1'b1;
repeat (2)
@(posedge clk);
// deassert start after 2 cycles
start = 1'b0;
repeat (15)
@(posedge clk);
$fdisplay(desc3, "%h_%h_%b_%b | %h_%b", op1, AS_Result, Flags, Denorm, yexpected, (AS_Result[63:32]==yexpected));
vectornum = vectornum + 1;
end // if (~reset)
$display("%d vectors processed", vectornum);
end // always @ (posedge clk)
endmodule // tb

80
wally-pipelined/src/fpudivsqrt/tb_f64_div_rd.sv
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// testbench
module tb ();
logic [63:0] op1;
logic [63:0] op2;
logic [1:0] rm;
logic op_type;
logic P;
logic OvEn;
logic UnEn;
logic start;
logic reset;
logic [63:0] AS_Result;
logic [4:0] Flags;
logic Denorm;
logic done;
logic clk;
logic [63:0] yexpected;
logic [63:0] vectornum, errors; // bookkeeping variables
logic [199:0] testvectors[50000:0]; // array of testvectors
logic [7:0] flags_expected;
integer handle3;
integer desc3;
// instantiate device under test
fpdiv dut (done, AS_Result, Flags, Denorm, op1, op2, rm, op_type, P, OvEn, UnEn,
start, reset, clk);
initial
begin
clk = 1'b1;
forever #333 clk = ~clk;
end
initial
begin
handle3 = $fopen("f64_div_rd.out");
$readmemh("f64_div_rd.tv", testvectors);
vectornum = 0; errors = 0;
start = 1'b0;
// reset
reset = 1; #27; reset = 0;
end
initial
begin
desc3 = handle3;
#0 op_type = 1'b0;
#0 P = 1'b0;
#0 rm = 2'b11;
#0 OvEn = 1'b0;
#0 UnEn = 1'b0;
end
always @(posedge clk)
begin
if (~reset)
begin
#0; {op1, op2, yexpected, flags_expected} = testvectors[vectornum];
#50 start = 1'b1;
repeat (2)
@(posedge clk);
// deassert start after 2 cycles
start = 1'b0;
repeat (10)
@(posedge clk);
$fdisplay(desc3, "%h_%h_%h_%b_%b | %h_%b", op1, op2, AS_Result, Flags, Denorm, yexpected, (AS_Result==yexpected));
vectornum = vectornum + 1;
end // if (~reset)
$display("%d vectors processed", vectornum);
end // always @ (posedge clk)
endmodule // tb

80
wally-pipelined/src/fpudivsqrt/tb_f64_div_rne.sv
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// testbench
module tb ();
logic [63:0] op1;
logic [63:0] op2;
logic [1:0] rm;
logic op_type;
logic P;
logic OvEn;
logic UnEn;
logic start;
logic reset;
logic [63:0] AS_Result;
logic [4:0] Flags;
logic Denorm;
logic done;
logic clk;
logic [63:0] yexpected;
logic [63:0] vectornum, errors; // bookkeeping variables
logic [199:0] testvectors[50000:0]; // array of testvectors
logic [7:0] flags_expected;
integer handle3;
integer desc3;
// instantiate device under test
fpdiv dut (done, AS_Result, Flags, Denorm, op1, op2, rm, op_type, P, OvEn, UnEn,
start, reset, clk);
initial
begin
clk = 1'b1;
forever #333 clk = ~clk;
end
initial
begin
handle3 = $fopen("f64_div_rne.out");
$readmemh("f64_div_rne.tv", testvectors);
vectornum = 0; errors = 0;
start = 1'b0;
// reset
reset = 1; #27; reset = 0;
end
initial
begin
desc3 = handle3;
#0 op_type = 1'b0;
#0 P = 1'b0;
#0 rm = 2'b00;
#0 OvEn = 1'b0;
#0 UnEn = 1'b0;
end
always @(posedge clk)
begin
if (~reset)
begin
#0; {op1, op2, yexpected, flags_expected} = testvectors[vectornum];
#50 start = 1'b1;
repeat (2)
@(posedge clk);
// deassert start after 2 cycles
start = 1'b0;
repeat (10)
@(posedge clk);
$fdisplay(desc3, "%h_%h_%h_%b_%b | %h_%b", op1, op2, AS_Result, Flags, Denorm, yexpected, (AS_Result==yexpected));
vectornum = vectornum + 1;
end // if (~reset)
$display("%d vectors processed", vectornum);
end // always @ (posedge clk)
endmodule // tb

80
wally-pipelined/src/fpudivsqrt/tb_f64_div_ru.sv
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@ -1,80 +0,0 @@
// testbench
module tb ();
logic [63:0] op1;
logic [63:0] op2;
logic [1:0] rm;
logic op_type;
logic P;
logic OvEn;
logic UnEn;
logic start;
logic reset;
logic [63:0] AS_Result;
logic [4:0] Flags;
logic Denorm;
logic done;
logic clk;
logic [63:0] yexpected;
logic [63:0] vectornum, errors; // bookkeeping variables
logic [199:0] testvectors[50000:0]; // array of testvectors
logic [7:0] flags_expected;
integer handle3;
integer desc3;
// instantiate device under test
fpdiv dut (done, AS_Result, Flags, Denorm, op1, op2, rm, op_type, P, OvEn, UnEn,
start, reset, clk);
initial
begin
clk = 1'b1;
forever #333 clk = ~clk;
end
initial
begin
handle3 = $fopen("f64_div_ru.out");
$readmemh("f64_div_ru.tv", testvectors);
vectornum = 0; errors = 0;
start = 1'b0;
// reset
reset = 1; #27; reset = 0;
end
initial
begin
desc3 = handle3;
#0 op_type = 1'b0;
#0 P = 1'b0;
#0 rm = 2'b10;
#0 OvEn = 1'b0;
#0 UnEn = 1'b0;
end
always @(posedge clk)
begin
if (~reset)
begin
#0; {op1, op2, yexpected, flags_expected} = testvectors[vectornum];
#50 start = 1'b1;
repeat (2)
@(posedge clk);
// deassert start after 2 cycles
start = 1'b0;
repeat (10)
@(posedge clk);
$fdisplay(desc3, "%h_%h_%h_%b_%b | %h_%b", op1, op2, AS_Result, Flags, Denorm, yexpected, (AS_Result==yexpected));
vectornum = vectornum + 1;
end // if (~reset)
$display("%d vectors processed", vectornum);
end // always @ (posedge clk)
endmodule // tb

80
wally-pipelined/src/fpudivsqrt/tb_f64_div_rz.sv
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@ -1,80 +0,0 @@
// testbench
module tb ();
logic [63:0] op1;
logic [63:0] op2;
logic [1:0] rm;
logic op_type;
logic P;
logic OvEn;
logic UnEn;
logic start;
logic reset;
logic [63:0] AS_Result;
logic [4:0] Flags;
logic Denorm;
logic done;
logic clk;
logic [63:0] yexpected;
logic [63:0] vectornum, errors; // bookkeeping variables
logic [199:0] testvectors[50000:0]; // array of testvectors
logic [7:0] flags_expected;
integer handle3;
integer desc3;
// instantiate device under test
fpdiv dut (done, AS_Result, Flags, Denorm, op1, op2, rm, op_type, P, OvEn, UnEn,
start, reset, clk);
initial
begin
clk = 1'b1;
forever #333 clk = ~clk;
end
initial
begin
handle3 = $fopen("f64_div_rz.out");
$readmemh("f64_div_rz.tv", testvectors);
vectornum = 0; errors = 0;
start = 1'b0;
// reset
reset = 1; #27; reset = 0;
end
initial
begin
desc3 = handle3;
#0 op_type = 1'b0;
#0 P = 1'b0;
#0 rm = 2'b01;
#0 OvEn = 1'b0;
#0 UnEn = 1'b0;
end
always @(posedge clk)
begin
if (~reset)
begin
#0; {op1, op2, yexpected, flags_expected} = testvectors[vectornum];
#50 start = 1'b1;
repeat (2)
@(posedge clk);
// deassert start after 2 cycles
start = 1'b0;
repeat (10)
@(posedge clk);
$fdisplay(desc3, "%h_%h_%h_%b_%b | %h_%b", op1, op2, AS_Result, Flags, Denorm, yexpected, (AS_Result==yexpected));
vectornum = vectornum + 1;
end // if (~reset)
$display("%d vectors processed", vectornum);
end // always @ (posedge clk)
endmodule // tb

79
wally-pipelined/src/fpudivsqrt/tb_f64_sqrt_rd.sv
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@ -1,79 +0,0 @@
// testbench
module tb ();
logic [63:0] op1;
logic [1:0] rm;
logic op_type;
logic P;
logic OvEn;
logic UnEn;
logic start;
logic reset;
logic [63:0] AS_Result;
logic [4:0] Flags;
logic Denorm;
logic done;
logic clk;
logic [63:0] yexpected;
logic [63:0] vectornum, errors; // bookkeeping variables
logic [135:0] testvectors[50000:0]; // array of testvectors
logic [7:0] flags_expected;
integer handle3;
integer desc3;
// instantiate device under test
fpdiv dut (done, AS_Result, Flags, Denorm, op1, 64'h0, rm, op_type, P, OvEn, UnEn,
start, reset, clk);
initial
begin
clk = 1'b1;
forever #333 clk = ~clk;
end
initial
begin
handle3 = $fopen("f64_sqrt_rd.out");
$readmemh("f64_sqrt_rd.tv", testvectors);
vectornum = 0; errors = 0;
start = 1'b0;
// reset
reset = 1; #27; reset = 0;
end
initial
begin
desc3 = handle3;
#0 op_type = 1'b1;
#0 P = 1'b0;
#0 rm = 2'b11;
#0 OvEn = 1'b0;
#0 UnEn = 1'b0;
end
always @(posedge clk)
begin
if (~reset)
begin
#0; {op1, yexpected, flags_expected} = testvectors[vectornum];
#50 start = 1'b1;
repeat (2)
@(posedge clk);
// deassert start after 2 cycles
start = 1'b0;
repeat (15)
@(posedge clk);
$fdisplay(desc3, "%h_%h_%b_%b | %h_%b", op1, AS_Result, Flags, Denorm, yexpected, (AS_Result==yexpected));
vectornum = vectornum + 1;
end // if (~reset)
$display("%d vectors processed", vectornum);
end // always @ (posedge clk)
endmodule // tb

79
wally-pipelined/src/fpudivsqrt/tb_f64_sqrt_rne.sv
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@ -1,79 +0,0 @@
// testbench
module tb ();
logic [63:0] op1;
logic [1:0] rm;
logic op_type;
logic P;
logic OvEn;
logic UnEn;
logic start;
logic reset;
logic [63:0] AS_Result;
logic [4:0] Flags;
logic Denorm;
logic done;
logic clk;
logic [63:0] yexpected;
logic [63:0] vectornum, errors; // bookkeeping variables
logic [135:0] testvectors[50000:0]; // array of testvectors
logic [7:0] flags_expected;
integer handle3;
integer desc3;
// instantiate device under test
fpdiv dut (done, AS_Result, Flags, Denorm, op1, 64'h0, rm, op_type, P, OvEn, UnEn,
start, reset, clk);
initial
begin
clk = 1'b1;
forever #333 clk = ~clk;
end
initial
begin
handle3 = $fopen("f64_sqrt_rne.out");
$readmemh("f64_sqrt_rne.tv", testvectors);
vectornum = 0; errors = 0;
start = 1'b0;
// reset
reset = 1; #27; reset = 0;
end
initial
begin
desc3 = handle3;
#0 op_type = 1'b1;
#0 P = 1'b0;
#0 rm = 2'b00;
#0 OvEn = 1'b0;
#0 UnEn = 1'b0;
end
always @(posedge clk)
begin
if (~reset)
begin
#0; {op1, yexpected, flags_expected} = testvectors[vectornum];
#50 start = 1'b1;
repeat (2)
@(posedge clk);
// deassert start after 2 cycles
start = 1'b0;
repeat (15)
@(posedge clk);
$fdisplay(desc3, "%h_%h_%b_%b | %h_%b", op1, AS_Result, Flags, Denorm, yexpected, (AS_Result==yexpected));
vectornum = vectornum + 1;
end // if (~reset)
$display("%d vectors processed", vectornum);
end // always @ (posedge clk)
endmodule // tb

79
wally-pipelined/src/fpudivsqrt/tb_f64_sqrt_ru.sv
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@ -1,79 +0,0 @@
// testbench
module tb ();
logic [63:0] op1;
logic [1:0] rm;
logic op_type;
logic P;
logic OvEn;
logic UnEn;
logic start;
logic reset;
logic [63:0] AS_Result;
logic [4:0] Flags;
logic Denorm;
logic done;
logic clk;
logic [63:0] yexpected;
logic [63:0] vectornum, errors; // bookkeeping variables
logic [135:0] testvectors[50000:0]; // array of testvectors
logic [7:0] flags_expected;
integer handle3;
integer desc3;
// instantiate device under test
fpdiv dut (done, AS_Result, Flags, Denorm, op1, 64'h0, rm, op_type, P, OvEn, UnEn,
start, reset, clk);
initial
begin
clk = 1'b1;
forever #333 clk = ~clk;
end
initial
begin
handle3 = $fopen("f64_sqrt_ru.out");
$readmemh("f64_sqrt_ru.tv", testvectors);
vectornum = 0; errors = 0;
start = 1'b0;
// reset
reset = 1; #27; reset = 0;
end
initial
begin
desc3 = handle3;
#0 op_type = 1'b1;
#0 P = 1'b0;
#0 rm = 2'b10;
#0 OvEn = 1'b0;
#0 UnEn = 1'b0;
end
always @(posedge clk)
begin
if (~reset)
begin
#0; {op1, yexpected, flags_expected} = testvectors[vectornum];
#50 start = 1'b1;
repeat (2)
@(posedge clk);
// deassert start after 2 cycles
start = 1'b0;
repeat (15)
@(posedge clk);
$fdisplay(desc3, "%h_%h_%b_%b | %h_%b", op1, AS_Result, Flags, Denorm, yexpected, (AS_Result==yexpected));
vectornum = vectornum + 1;
end // if (~reset)
$display("%d vectors processed", vectornum);
end // always @ (posedge clk)
endmodule // tb

79
wally-pipelined/src/fpudivsqrt/tb_f64_sqrt_rz.sv
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@ -1,79 +0,0 @@
// testbench
module tb ();
logic [63:0] op1;
logic [1:0] rm;
logic op_type;
logic P;
logic OvEn;
logic UnEn;
logic start;
logic reset;
logic [63:0] AS_Result;
logic [4:0] Flags;
logic Denorm;
logic done;
logic clk;
logic [63:0] yexpected;
logic [63:0] vectornum, errors; // bookkeeping variables
logic [135:0] testvectors[50000:0]; // array of testvectors
logic [7:0] flags_expected;
integer handle3;
integer desc3;
// instantiate device under test
fpdiv dut (done, AS_Result, Flags, Denorm, op1, 64'h0, rm, op_type, P, OvEn, UnEn,
start, reset, clk);
initial
begin
clk = 1'b1;
forever #333 clk = ~clk;
end
initial
begin
handle3 = $fopen("f64_sqrt_rz.out");
$readmemh("f64_sqrt_rz.tv", testvectors);
vectornum = 0; errors = 0;
start = 1'b0;
// reset
reset = 1; #27; reset = 0;
end
initial
begin
desc3 = handle3;
#0 op_type = 1'b1;
#0 P = 1'b0;
#0 rm = 2'b01;
#0 OvEn = 1'b0;
#0 UnEn = 1'b0;
end
always @(posedge clk)
begin
if (~reset)
begin
#0; {op1, yexpected, flags_expected} = testvectors[vectornum];
#50 start = 1'b1;
repeat (2)
@(posedge clk);
// deassert start after 2 cycles
start = 1'b0;
repeat (15)
@(posedge clk);
$fdisplay(desc3, "%h_%h_%b_%b | %h_%b", op1, AS_Result, Flags, Denorm, yexpected, (AS_Result==yexpected));
vectornum = vectornum + 1;
end // if (~reset)
$display("%d vectors processed", vectornum);
end // always @ (posedge clk)
endmodule // tb

72
wally-pipelined/src/fpudivsqrt/test_divconvDP.sv
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@ -1,72 +0,0 @@
module tb;
logic [52:0] d, n;
logic reset;
logic [63:0] q, qm, qp, rega_out, regb_out, regc_out;
logic [127:0] regr_out;
logic start;
logic error;
logic op_type;
logic done;
logic load_rega;
logic load_regb;
logic load_regc;
logic load_regr;
logic [1:0] sel_muxa;
logic [1:0] sel_muxb;
logic sel_muxr;
logic clk;
integer handle3;
integer desc3;
divconv dut (q, qm, qp, rega_out, regb_out, regc_out, regr_out,
d, n, sel_muxa, sel_muxb, sel_muxr, reset, clk,
load_rega, load_regb, load_regc, load_regr);
fsm control (done, load_rega, load_regb, load_regc, load_regr,
sel_muxa, sel_muxb, sel_muxr,
clk, reset, start, error, op_type);
initial
begin
clk = 1'b1;
forever #5 clk = ~clk;
end
initial
begin
handle3 = $fopen("divconvDP.out");
#700 $finish;
end
always
begin
desc3 = handle3;
#5 $fdisplay(desc3, "%b %b %b | %h %h | %h %h %h | %h %h %h %h", sel_muxa,
sel_muxb, sel_muxr, d, n, q, qm, qp, rega_out, regb_out, regc_out, regr_out);
end
initial
begin
#0 start = 1'b0;
#0 n = 53'h1C_0000_0000_0000; // 1.75
#0 d = 53'h1E_0000_0000_0000; // 1.875
#0 reset = 1'b1;
#20 reset = 1'b0;
#20 start = 1'b1;
#40 start = 1'b0;
end
endmodule // tb

169
wally-pipelined/src/fpudivsqrt/test_fpdiv.sv
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@ -1,169 +0,0 @@
`timescale 1ps/1ps
module tb;
logic [63:0] op1;
logic [63:0] op2;
logic [1:0] rm;
logic op_type;
logic P;
logic OvEn;
logic UnEn;
logic start;
logic reset;
logic clk;
logic [63:0] AS_Result;
logic [4:0] Flags;
logic Denorm;
logic done;
integer handle3;
integer desc3;
fpdiv dut (done, AS_Result, Flags, Denorm, op1, op2, rm, op_type, P, OvEn, UnEn,
start, reset, clk);
initial
begin
clk = 1'b1;
forever #333 clk = ~clk;
end
initial
begin
handle3 = $fopen("fpdiv.out");
end
always
begin
desc3 = handle3;
#5 $fdisplay(desc3, "%h %h | %h %h %h",
op1, op2, AS_Result, Flags, Denorm);
end
initial
begin
#0 start = 1'b0;
#0 P = 1'b1;
#0 OvEn = 1'b0;
#0 UnEn = 1'b0;
// 00 round-to-nearest-even
// 01 round-toward-zero
// 10 round-toward-plus infinity
// 11 round-toward-minus infinity
#0 rm = 2'b00;
#0 op_type = 1'b1;
#0 op1 = 64'h3ffc_0000_0000_0000; // 1.75
#0 op2 = 64'h3ffe_0000_0000_0000; // 1.875
#0 op1 = 64'h3ffe_e219_652b_d3c3; // 1.9302
#0 op2 = 64'h3ff7_346d_c5d6_3886; // 1.4503
#0 op1 = 64'h404f_b1d4_9518_2a99; // 63.3893
#0 op2 = 64'h4020_9b94_d940_7896; // 8.30387
#0 op1 = 64'h3ff6_3d98_4781_6b47; // 1.390037803
#0 op2 = 64'h3fd7_b540_56e5_c87a; // 0.370437703
#0 op1 = 64'h3fed_c505_fada_95fd; // 0.930300703
#0 op2 = 64'h4029_dc59_e3a1_24a8; // 12.9303733
#0 op1 = 64'h41E0_0003_FFFB_FFFF;
#0 op2 = 64'hBFDF_FFFF_FFEF_FFFF;
#0 op1 = 64'h41E0_0003_FFFB_FFFF;
#0 op2 = 64'h3FDF_FFFF_FFEF_FFFF;
#0 op1 = 64'hB68F_FFF8_0000_00FF;
#0 op2 = 64'h3F90_8000_0007_FFFF;
#0 op1 = 64'h0000_0000_0000_0000;
#0 op2 = 64'hA57F_319E_DE38_F755;
#0 op1 = 64'hC1DF_FFFF_FFE0_0080;
#0 op2 = 64'h3FA4_8EDF_3623_F076;
#0 op1 = 64'hC030_00FF_FFFF_FFE0;
#0 op2 = 64'h47EF_FDFF_FDFF_FFFF;
#0 op1 = 64'h4030_00FF_FFFF_FFE0;
#0 op2 = 64'h47EF_FDFF_FDFF_FFFF;
#0 op1 = 64'h5555_5555_5555_5555; // 1.75
#0 op2 = 64'haaaa_aaaa_aaaa_aaaa; // 1.875
#0 op1 = 64'h3ffc_0000_0000_0000; // 1.75
#0 op2 = 64'h0000_0000_0000_0000; // 0.00 (Div0 exception)
#0 op1 = 64'h3ff7_10cb_0000_0000;
#0 op2 = 64'h3fb9_a36e_0000_0000;
#0 op1 = 64'h37e0_0000_0000_0001;
#0 op2 = 64'h3be6_a09e_667f_3bce;
#0 op1 = 64'h37e0_0000_0000_0001;
#0 op1 = 64'h43d3_6fa3_cad3_f59e;
#0 op1 = 64'h2470_0000_ffff_ffef;
#0 op1 = 64'h7ff0_0000_0000_0000;
#0 op1 = 64'h7fef_ffff_ffff_ffff;
#0 op1 = 64'hffe0_0000_0000_0000;
#0 op2 = 64'h7fe0_0000_0000_0001;
#0 op1 = 64'h69ff_ff7f_0000_0000;
#0 op2 = 64'h0;
#0 op1 = 64'h3f7f_ffff_0000_0000;
#0 op1 = 64'h4180_0000_0000_0000;
//#0 op1 = 64'h3fe0_0000_0000_0000; // 1.75 (SP)
//#0 op2 = 64'h3ff0_0000_0000_0000; // 1.875 (SP)
//#0 op1 = 64'h3ff7_10cb_0000_0000; // 1.75 (SP)
//#0 op2 = 64'h3fb9_a36e_0000_0000; // 1.875 (SP)
//#0 op1 = 64'h427d_8ea5_0000_0000; // 1.75 (SP)
//#0 op2 = 64'h4104_dca7_0000_0000; // 1.875 (SP)
//#0 op1 = 64'h3fb1_ecc2_0000_0000; // 1.75 (SP)
//#0 op2 = 64'h3ebd_aa03_0000_0000; // 1.875 (SP)
//#0 op1 = 64'h3f6e_2830_0000_0000;
//#0 op2 = 64'h414e_e2cf_0000_0000;
//#0 op1 = 64'h8683_f7ff_0000_0000;
//#0 op2 = 64'hc07f_3fff_0000_0000;
//#0 op1 = 64'h0100_0000_0000_0000;
//#0 op2 = 64'h3400_00ef_0000_0000;
//#0 op1 = 64'hbed5_6444_0000_0000;
//#0 op2 = 64'h3e7f_f400_0000_0000;
//#0 op1 = 64'h0100_087f_0000_0000;
//#0 op2 = 64'hfe80_4fff_0000_0000;
//#0 op1 = 64'hc513_492f_a359_69e3;
//#0 op2 = 64'hbfcf_fdff_ffff_ffef;
//#0 op1 = 64'h41E0_0003_FFFB_FFFF;
//#0 op2 = 64'hBFDF_FFFF_FFEF_FFFF;
//#0 op1 = 64'hf17ffffffff7fff0;
//#0 op2 = 64'h001ffffffffffffe;
//#0 op1 = 64'hC040_0000_0000_1000;
//#0 op2 = 64'h802f_ff7f_ffff_ffc0;
//#0 op1 = 64'h3800008000000002;
//#0 op2 = 64'h7ff0000000000000;
//#0 op1 = 64'h8020200007fffffe;
//#0 op2 = 64'hc59000000000083f;
//#0 op1 = 64'h0140008000fffffe;
//#0 op2 = 64'hd2e0001ffffffffb;
//#0 op1 = 64'h4013_95a7_515b_e3d9;
//#0 op2 = 64'h8010_0000_0004_0007;
//#0 op1 = 64'h0010_0000_0000_0000;
//#0 op2 = 64'h3fff_ffff_ffff_ffff;
//#0 op1 = 64'h0010_0000_0000_0000;
//#0 op2 = 64'h4000_0000_0000_0001;
//#0 op1 = 64'h4000000000000001;
//#0 op2 = 64'h403000004007fffe; // _3fbfffff7ff00207_00000_0 | 3fbfffff7ff00206_0
//#0 op1 = 64'hffe0_0000_0000_0000;
//#0 op2 = 64'hc0a0_0000_4008_0000;
//#0 op1 = 64'hffe0_0000_0000_0001;
//#0 op2 = 64'hbfd0_0000_0000_0000;
//#0 op1 = 64'h801f_ffff_ffff_ffff;
//#0 op2 = 64'h4000_0000_0000_0000;
#0 reset = 1'b1;
#1000 reset = 1'b0;
#3000 start = 1'b1;
#800 start = 1'b0;
end
endmodule // tb

758
wally-pipelined/src/fpufma/struct/adder.v
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@ -1,758 +0,0 @@
// The following module make up the basic building blocks that
// are used by the cla64, cla_sub64, and cla52.
module INVBLOCK ( GIN, GOUT );
input GIN;
output GOUT;
assign GOUT = ~ GIN;
endmodule // INVBLOCK
module XXOR1 ( A, B, GIN, SUM );
input A;
input B;
input GIN;
output SUM;
assign SUM = ( ~ (A ^ B)) ^ GIN;
endmodule // XXOR1
module BLOCK0 ( A, B, POUT, GOUT );
input A;
input B;
output POUT;
output GOUT;
assign POUT = ~ (A | B);
assign GOUT = ~ (A & B);
endmodule // BLOCK0
module BLOCK1 ( PIN1, PIN2, GIN1, GIN2, POUT, GOUT );
input PIN1;
input PIN2;
input GIN1;
input GIN2;
output POUT;
output GOUT;
assign POUT = ~ (PIN1 | PIN2);
assign GOUT = ~ (GIN2 & (PIN2 | GIN1));
endmodule // BLOCK1
module BLOCK2 ( PIN1, PIN2, GIN1, GIN2, POUT, GOUT );
input PIN1;
input PIN2;
input GIN1;
input GIN2;
output POUT;
output GOUT;
assign POUT = ~ (PIN1 & PIN2);
assign GOUT = ~ (GIN2 | (PIN2 & GIN1));
endmodule // BLOCK2
module BLOCK1A ( PIN2, GIN1, GIN2, GOUT );
input PIN2;
input GIN1;
input GIN2;
output GOUT;
assign GOUT = ~ (GIN2 & (PIN2 | GIN1));
endmodule // BLOCK1A
module BLOCK2A ( PIN2, GIN1, GIN2, GOUT );
input PIN2;
input GIN1;
input GIN2;
output GOUT;
assign GOUT = ~ (GIN2 | (PIN2 & GIN1));
endmodule
module PRESTAGE_64 ( A, B, CIN, POUT, GOUT );
input [0:63] A;
input [0:63] B;
input CIN;
output [0:63] POUT;
output [0:64] GOUT;
BLOCK0 U10 (A[0] , B[0] , POUT[0] , GOUT[1] );
BLOCK0 U11 (A[1] , B[1] , POUT[1] , GOUT[2] );
BLOCK0 U12 (A[2] , B[2] , POUT[2] , GOUT[3] );
BLOCK0 U13 (A[3] , B[3] , POUT[3] , GOUT[4] );
BLOCK0 U14 (A[4] , B[4] , POUT[4] , GOUT[5] );
BLOCK0 U15 (A[5] , B[5] , POUT[5] , GOUT[6] );
BLOCK0 U16 (A[6] , B[6] , POUT[6] , GOUT[7] );
BLOCK0 U17 (A[7] , B[7] , POUT[7] , GOUT[8] );
BLOCK0 U18 (A[8] , B[8] , POUT[8] , GOUT[9] );
BLOCK0 U19 (A[9] , B[9] , POUT[9] , GOUT[10] );
BLOCK0 U110 (A[10] , B[10] , POUT[10] , GOUT[11] );
BLOCK0 U111 (A[11] , B[11] , POUT[11] , GOUT[12] );
BLOCK0 U112 (A[12] , B[12] , POUT[12] , GOUT[13] );
BLOCK0 U113 (A[13] , B[13] , POUT[13] , GOUT[14] );
BLOCK0 U114 (A[14] , B[14] , POUT[14] , GOUT[15] );
BLOCK0 U115 (A[15] , B[15] , POUT[15] , GOUT[16] );
BLOCK0 U116 (A[16] , B[16] , POUT[16] , GOUT[17] );
BLOCK0 U117 (A[17] , B[17] , POUT[17] , GOUT[18] );
BLOCK0 U118 (A[18] , B[18] , POUT[18] , GOUT[19] );
BLOCK0 U119 (A[19] , B[19] , POUT[19] , GOUT[20] );
BLOCK0 U120 (A[20] , B[20] , POUT[20] , GOUT[21] );
BLOCK0 U121 (A[21] , B[21] , POUT[21] , GOUT[22] );
BLOCK0 U122 (A[22] , B[22] , POUT[22] , GOUT[23] );
BLOCK0 U123 (A[23] , B[23] , POUT[23] , GOUT[24] );
BLOCK0 U124 (A[24] , B[24] , POUT[24] , GOUT[25] );
BLOCK0 U125 (A[25] , B[25] , POUT[25] , GOUT[26] );
BLOCK0 U126 (A[26] , B[26] , POUT[26] , GOUT[27] );
BLOCK0 U127 (A[27] , B[27] , POUT[27] , GOUT[28] );
BLOCK0 U128 (A[28] , B[28] , POUT[28] , GOUT[29] );
BLOCK0 U129 (A[29] , B[29] , POUT[29] , GOUT[30] );
BLOCK0 U130 (A[30] , B[30] , POUT[30] , GOUT[31] );
BLOCK0 U131 (A[31] , B[31] , POUT[31] , GOUT[32] );
BLOCK0 U132 (A[32] , B[32] , POUT[32] , GOUT[33] );
BLOCK0 U133 (A[33] , B[33] , POUT[33] , GOUT[34] );
BLOCK0 U134 (A[34] , B[34] , POUT[34] , GOUT[35] );
BLOCK0 U135 (A[35] , B[35] , POUT[35] , GOUT[36] );
BLOCK0 U136 (A[36] , B[36] , POUT[36] , GOUT[37] );
BLOCK0 U137 (A[37] , B[37] , POUT[37] , GOUT[38] );
BLOCK0 U138 (A[38] , B[38] , POUT[38] , GOUT[39] );
BLOCK0 U139 (A[39] , B[39] , POUT[39] , GOUT[40] );
BLOCK0 U140 (A[40] , B[40] , POUT[40] , GOUT[41] );
BLOCK0 U141 (A[41] , B[41] , POUT[41] , GOUT[42] );
BLOCK0 U142 (A[42] , B[42] , POUT[42] , GOUT[43] );
BLOCK0 U143 (A[43] , B[43] , POUT[43] , GOUT[44] );
BLOCK0 U144 (A[44] , B[44] , POUT[44] , GOUT[45] );
BLOCK0 U145 (A[45] , B[45] , POUT[45] , GOUT[46] );
BLOCK0 U146 (A[46] , B[46] , POUT[46] , GOUT[47] );
BLOCK0 U147 (A[47] , B[47] , POUT[47] , GOUT[48] );
BLOCK0 U148 (A[48] , B[48] , POUT[48] , GOUT[49] );
BLOCK0 U149 (A[49] , B[49] , POUT[49] , GOUT[50] );
BLOCK0 U150 (A[50] , B[50] , POUT[50] , GOUT[51] );
BLOCK0 U151 (A[51] , B[51] , POUT[51] , GOUT[52] );
BLOCK0 U152 (A[52] , B[52] , POUT[52] , GOUT[53] );
BLOCK0 U153 (A[53] , B[53] , POUT[53] , GOUT[54] );
BLOCK0 U154 (A[54] , B[54] , POUT[54] , GOUT[55] );
BLOCK0 U155 (A[55] , B[55] , POUT[55] , GOUT[56] );
BLOCK0 U156 (A[56] , B[56] , POUT[56] , GOUT[57] );
BLOCK0 U157 (A[57] , B[57] , POUT[57] , GOUT[58] );
BLOCK0 U158 (A[58] , B[58] , POUT[58] , GOUT[59] );
BLOCK0 U159 (A[59] , B[59] , POUT[59] , GOUT[60] );
BLOCK0 U160 (A[60] , B[60] , POUT[60] , GOUT[61] );
BLOCK0 U161 (A[61] , B[61] , POUT[61] , GOUT[62] );
BLOCK0 U162 (A[62] , B[62] , POUT[62] , GOUT[63] );
BLOCK0 U163 (A[63] , B[63] , POUT[63] , GOUT[64] );
INVBLOCK U2 (CIN , GOUT[0] );
endmodule // PRESTAGE_64
module DBLC_0_64 ( PIN, GIN, POUT, GOUT );
input [0:63] PIN;
input [0:64] GIN;
output [0:62] POUT;
output [0:64] GOUT;
INVBLOCK U10 (GIN[0] , GOUT[0] );
BLOCK1A U21 (PIN[0] , GIN[0] , GIN[1] , GOUT[1] );
BLOCK1 U32 (PIN[0] , PIN[1] , GIN[1] , GIN[2] , POUT[0] , GOUT[2] );
BLOCK1 U33 (PIN[1] , PIN[2] , GIN[2] , GIN[3] , POUT[1] , GOUT[3] );
BLOCK1 U34 (PIN[2] , PIN[3] , GIN[3] , GIN[4] , POUT[2] , GOUT[4] );
BLOCK1 U35 (PIN[3] , PIN[4] , GIN[4] , GIN[5] , POUT[3] , GOUT[5] );
BLOCK1 U36 (PIN[4] , PIN[5] , GIN[5] , GIN[6] , POUT[4] , GOUT[6] );
BLOCK1 U37 (PIN[5] , PIN[6] , GIN[6] , GIN[7] , POUT[5] , GOUT[7] );
BLOCK1 U38 (PIN[6] , PIN[7] , GIN[7] , GIN[8] , POUT[6] , GOUT[8] );
BLOCK1 U39 (PIN[7] , PIN[8] , GIN[8] , GIN[9] , POUT[7] , GOUT[9] );
BLOCK1 U310 (PIN[8] , PIN[9] , GIN[9] , GIN[10] , POUT[8] , GOUT[10] );
BLOCK1 U311 (PIN[9] , PIN[10] , GIN[10] , GIN[11] , POUT[9] , GOUT[11] );
BLOCK1 U312 (PIN[10] , PIN[11] , GIN[11] , GIN[12] , POUT[10] , GOUT[12] );
BLOCK1 U313 (PIN[11] , PIN[12] , GIN[12] , GIN[13] , POUT[11] , GOUT[13] );
BLOCK1 U314 (PIN[12] , PIN[13] , GIN[13] , GIN[14] , POUT[12] , GOUT[14] );
BLOCK1 U315 (PIN[13] , PIN[14] , GIN[14] , GIN[15] , POUT[13] , GOUT[15] );
BLOCK1 U316 (PIN[14] , PIN[15] , GIN[15] , GIN[16] , POUT[14] , GOUT[16] );
BLOCK1 U317 (PIN[15] , PIN[16] , GIN[16] , GIN[17] , POUT[15] , GOUT[17] );
BLOCK1 U318 (PIN[16] , PIN[17] , GIN[17] , GIN[18] , POUT[16] , GOUT[18] );
BLOCK1 U319 (PIN[17] , PIN[18] , GIN[18] , GIN[19] , POUT[17] , GOUT[19] );
BLOCK1 U320 (PIN[18] , PIN[19] , GIN[19] , GIN[20] , POUT[18] , GOUT[20] );
BLOCK1 U321 (PIN[19] , PIN[20] , GIN[20] , GIN[21] , POUT[19] , GOUT[21] );
BLOCK1 U322 (PIN[20] , PIN[21] , GIN[21] , GIN[22] , POUT[20] , GOUT[22] );
BLOCK1 U323 (PIN[21] , PIN[22] , GIN[22] , GIN[23] , POUT[21] , GOUT[23] );
BLOCK1 U324 (PIN[22] , PIN[23] , GIN[23] , GIN[24] , POUT[22] , GOUT[24] );
BLOCK1 U325 (PIN[23] , PIN[24] , GIN[24] , GIN[25] , POUT[23] , GOUT[25] );
BLOCK1 U326 (PIN[24] , PIN[25] , GIN[25] , GIN[26] , POUT[24] , GOUT[26] );
BLOCK1 U327 (PIN[25] , PIN[26] , GIN[26] , GIN[27] , POUT[25] , GOUT[27] );
BLOCK1 U328 (PIN[26] , PIN[27] , GIN[27] , GIN[28] , POUT[26] , GOUT[28] );
BLOCK1 U329 (PIN[27] , PIN[28] , GIN[28] , GIN[29] , POUT[27] , GOUT[29] );
BLOCK1 U330 (PIN[28] , PIN[29] , GIN[29] , GIN[30] , POUT[28] , GOUT[30] );
BLOCK1 U331 (PIN[29] , PIN[30] , GIN[30] , GIN[31] , POUT[29] , GOUT[31] );
BLOCK1 U332 (PIN[30] , PIN[31] , GIN[31] , GIN[32] , POUT[30] , GOUT[32] );
BLOCK1 U333 (PIN[31] , PIN[32] , GIN[32] , GIN[33] , POUT[31] , GOUT[33] );
BLOCK1 U334 (PIN[32] , PIN[33] , GIN[33] , GIN[34] , POUT[32] , GOUT[34] );
BLOCK1 U335 (PIN[33] , PIN[34] , GIN[34] , GIN[35] , POUT[33] , GOUT[35] );
BLOCK1 U336 (PIN[34] , PIN[35] , GIN[35] , GIN[36] , POUT[34] , GOUT[36] );
BLOCK1 U337 (PIN[35] , PIN[36] , GIN[36] , GIN[37] , POUT[35] , GOUT[37] );
BLOCK1 U338 (PIN[36] , PIN[37] , GIN[37] , GIN[38] , POUT[36] , GOUT[38] );
BLOCK1 U339 (PIN[37] , PIN[38] , GIN[38] , GIN[39] , POUT[37] , GOUT[39] );
BLOCK1 U340 (PIN[38] , PIN[39] , GIN[39] , GIN[40] , POUT[38] , GOUT[40] );
BLOCK1 U341 (PIN[39] , PIN[40] , GIN[40] , GIN[41] , POUT[39] , GOUT[41] );
BLOCK1 U342 (PIN[40] , PIN[41] , GIN[41] , GIN[42] , POUT[40] , GOUT[42] );
BLOCK1 U343 (PIN[41] , PIN[42] , GIN[42] , GIN[43] , POUT[41] , GOUT[43] );
BLOCK1 U344 (PIN[42] , PIN[43] , GIN[43] , GIN[44] , POUT[42] , GOUT[44] );
BLOCK1 U345 (PIN[43] , PIN[44] , GIN[44] , GIN[45] , POUT[43] , GOUT[45] );
BLOCK1 U346 (PIN[44] , PIN[45] , GIN[45] , GIN[46] , POUT[44] , GOUT[46] );
BLOCK1 U347 (PIN[45] , PIN[46] , GIN[46] , GIN[47] , POUT[45] , GOUT[47] );
BLOCK1 U348 (PIN[46] , PIN[47] , GIN[47] , GIN[48] , POUT[46] , GOUT[48] );
BLOCK1 U349 (PIN[47] , PIN[48] , GIN[48] , GIN[49] , POUT[47] , GOUT[49] );
BLOCK1 U350 (PIN[48] , PIN[49] , GIN[49] , GIN[50] , POUT[48] , GOUT[50] );
BLOCK1 U351 (PIN[49] , PIN[50] , GIN[50] , GIN[51] , POUT[49] , GOUT[51] );
BLOCK1 U352 (PIN[50] , PIN[51] , GIN[51] , GIN[52] , POUT[50] , GOUT[52] );
BLOCK1 U353 (PIN[51] , PIN[52] , GIN[52] , GIN[53] , POUT[51] , GOUT[53] );
BLOCK1 U354 (PIN[52] , PIN[53] , GIN[53] , GIN[54] , POUT[52] , GOUT[54] );
BLOCK1 U355 (PIN[53] , PIN[54] , GIN[54] , GIN[55] , POUT[53] , GOUT[55] );
BLOCK1 U356 (PIN[54] , PIN[55] , GIN[55] , GIN[56] , POUT[54] , GOUT[56] );
BLOCK1 U357 (PIN[55] , PIN[56] , GIN[56] , GIN[57] , POUT[55] , GOUT[57] );
BLOCK1 U358 (PIN[56] , PIN[57] , GIN[57] , GIN[58] , POUT[56] , GOUT[58] );
BLOCK1 U359 (PIN[57] , PIN[58] , GIN[58] , GIN[59] , POUT[57] , GOUT[59] );
BLOCK1 U360 (PIN[58] , PIN[59] , GIN[59] , GIN[60] , POUT[58] , GOUT[60] );
BLOCK1 U361 (PIN[59] , PIN[60] , GIN[60] , GIN[61] , POUT[59] , GOUT[61] );
BLOCK1 U362 (PIN[60] , PIN[61] , GIN[61] , GIN[62] , POUT[60] , GOUT[62] );
BLOCK1 U363 (PIN[61] , PIN[62] , GIN[62] , GIN[63] , POUT[61] , GOUT[63] );
BLOCK1 U364 (PIN[62] , PIN[63] , GIN[63] , GIN[64] , POUT[62] , GOUT[64] );
endmodule // DBLC_0_64
module DBLC_1_64 ( PIN, GIN, POUT, GOUT );
input [0:62] PIN;
input [0:64] GIN;
output [0:60] POUT;
output [0:64] GOUT;
INVBLOCK U10 (GIN[0] , GOUT[0] );
INVBLOCK U11 (GIN[1] , GOUT[1] );
BLOCK2A U22 (PIN[0] , GIN[0] , GIN[2] , GOUT[2] );
BLOCK2A U23 (PIN[1] , GIN[1] , GIN[3] , GOUT[3] );
BLOCK2 U34 (PIN[0] , PIN[2] , GIN[2] , GIN[4] , POUT[0] , GOUT[4] );
BLOCK2 U35 (PIN[1] , PIN[3] , GIN[3] , GIN[5] , POUT[1] , GOUT[5] );
BLOCK2 U36 (PIN[2] , PIN[4] , GIN[4] , GIN[6] , POUT[2] , GOUT[6] );
BLOCK2 U37 (PIN[3] , PIN[5] , GIN[5] , GIN[7] , POUT[3] , GOUT[7] );
BLOCK2 U38 (PIN[4] , PIN[6] , GIN[6] , GIN[8] , POUT[4] , GOUT[8] );
BLOCK2 U39 (PIN[5] , PIN[7] , GIN[7] , GIN[9] , POUT[5] , GOUT[9] );
BLOCK2 U310 (PIN[6] , PIN[8] , GIN[8] , GIN[10] , POUT[6] , GOUT[10] );
BLOCK2 U311 (PIN[7] , PIN[9] , GIN[9] , GIN[11] , POUT[7] , GOUT[11] );
BLOCK2 U312 (PIN[8] , PIN[10] , GIN[10] , GIN[12] , POUT[8] , GOUT[12] );
BLOCK2 U313 (PIN[9] , PIN[11] , GIN[11] , GIN[13] , POUT[9] , GOUT[13] );
BLOCK2 U314 (PIN[10] , PIN[12] , GIN[12] , GIN[14] , POUT[10] , GOUT[14] );
BLOCK2 U315 (PIN[11] , PIN[13] , GIN[13] , GIN[15] , POUT[11] , GOUT[15] );
BLOCK2 U316 (PIN[12] , PIN[14] , GIN[14] , GIN[16] , POUT[12] , GOUT[16] );
BLOCK2 U317 (PIN[13] , PIN[15] , GIN[15] , GIN[17] , POUT[13] , GOUT[17] );
BLOCK2 U318 (PIN[14] , PIN[16] , GIN[16] , GIN[18] , POUT[14] , GOUT[18] );
BLOCK2 U319 (PIN[15] , PIN[17] , GIN[17] , GIN[19] , POUT[15] , GOUT[19] );
BLOCK2 U320 (PIN[16] , PIN[18] , GIN[18] , GIN[20] , POUT[16] , GOUT[20] );
BLOCK2 U321 (PIN[17] , PIN[19] , GIN[19] , GIN[21] , POUT[17] , GOUT[21] );
BLOCK2 U322 (PIN[18] , PIN[20] , GIN[20] , GIN[22] , POUT[18] , GOUT[22] );
BLOCK2 U323 (PIN[19] , PIN[21] , GIN[21] , GIN[23] , POUT[19] , GOUT[23] );
BLOCK2 U324 (PIN[20] , PIN[22] , GIN[22] , GIN[24] , POUT[20] , GOUT[24] );
BLOCK2 U325 (PIN[21] , PIN[23] , GIN[23] , GIN[25] , POUT[21] , GOUT[25] );
BLOCK2 U326 (PIN[22] , PIN[24] , GIN[24] , GIN[26] , POUT[22] , GOUT[26] );
BLOCK2 U327 (PIN[23] , PIN[25] , GIN[25] , GIN[27] , POUT[23] , GOUT[27] );
BLOCK2 U328 (PIN[24] , PIN[26] , GIN[26] , GIN[28] , POUT[24] , GOUT[28] );
BLOCK2 U329 (PIN[25] , PIN[27] , GIN[27] , GIN[29] , POUT[25] , GOUT[29] );
BLOCK2 U330 (PIN[26] , PIN[28] , GIN[28] , GIN[30] , POUT[26] , GOUT[30] );
BLOCK2 U331 (PIN[27] , PIN[29] , GIN[29] , GIN[31] , POUT[27] , GOUT[31] );
BLOCK2 U332 (PIN[28] , PIN[30] , GIN[30] , GIN[32] , POUT[28] , GOUT[32] );
BLOCK2 U333 (PIN[29] , PIN[31] , GIN[31] , GIN[33] , POUT[29] , GOUT[33] );
BLOCK2 U334 (PIN[30] , PIN[32] , GIN[32] , GIN[34] , POUT[30] , GOUT[34] );
BLOCK2 U335 (PIN[31] , PIN[33] , GIN[33] , GIN[35] , POUT[31] , GOUT[35] );
BLOCK2 U336 (PIN[32] , PIN[34] , GIN[34] , GIN[36] , POUT[32] , GOUT[36] );
BLOCK2 U337 (PIN[33] , PIN[35] , GIN[35] , GIN[37] , POUT[33] , GOUT[37] );
BLOCK2 U338 (PIN[34] , PIN[36] , GIN[36] , GIN[38] , POUT[34] , GOUT[38] );
BLOCK2 U339 (PIN[35] , PIN[37] , GIN[37] , GIN[39] , POUT[35] , GOUT[39] );
BLOCK2 U340 (PIN[36] , PIN[38] , GIN[38] , GIN[40] , POUT[36] , GOUT[40] );
BLOCK2 U341 (PIN[37] , PIN[39] , GIN[39] , GIN[41] , POUT[37] , GOUT[41] );
BLOCK2 U342 (PIN[38] , PIN[40] , GIN[40] , GIN[42] , POUT[38] , GOUT[42] );
BLOCK2 U343 (PIN[39] , PIN[41] , GIN[41] , GIN[43] , POUT[39] , GOUT[43] );
BLOCK2 U344 (PIN[40] , PIN[42] , GIN[42] , GIN[44] , POUT[40] , GOUT[44] );
BLOCK2 U345 (PIN[41] , PIN[43] , GIN[43] , GIN[45] , POUT[41] , GOUT[45] );
BLOCK2 U346 (PIN[42] , PIN[44] , GIN[44] , GIN[46] , POUT[42] , GOUT[46] );
BLOCK2 U347 (PIN[43] , PIN[45] , GIN[45] , GIN[47] , POUT[43] , GOUT[47] );
BLOCK2 U348 (PIN[44] , PIN[46] , GIN[46] , GIN[48] , POUT[44] , GOUT[48] );
BLOCK2 U349 (PIN[45] , PIN[47] , GIN[47] , GIN[49] , POUT[45] , GOUT[49] );
BLOCK2 U350 (PIN[46] , PIN[48] , GIN[48] , GIN[50] , POUT[46] , GOUT[50] );
BLOCK2 U351 (PIN[47] , PIN[49] , GIN[49] , GIN[51] , POUT[47] , GOUT[51] );
BLOCK2 U352 (PIN[48] , PIN[50] , GIN[50] , GIN[52] , POUT[48] , GOUT[52] );
BLOCK2 U353 (PIN[49] , PIN[51] , GIN[51] , GIN[53] , POUT[49] , GOUT[53] );
BLOCK2 U354 (PIN[50] , PIN[52] , GIN[52] , GIN[54] , POUT[50] , GOUT[54] );
BLOCK2 U355 (PIN[51] , PIN[53] , GIN[53] , GIN[55] , POUT[51] , GOUT[55] );
BLOCK2 U356 (PIN[52] , PIN[54] , GIN[54] , GIN[56] , POUT[52] , GOUT[56] );
BLOCK2 U357 (PIN[53] , PIN[55] , GIN[55] , GIN[57] , POUT[53] , GOUT[57] );
BLOCK2 U358 (PIN[54] , PIN[56] , GIN[56] , GIN[58] , POUT[54] , GOUT[58] );
BLOCK2 U359 (PIN[55] , PIN[57] , GIN[57] , GIN[59] , POUT[55] , GOUT[59] );
BLOCK2 U360 (PIN[56] , PIN[58] , GIN[58] , GIN[60] , POUT[56] , GOUT[60] );
BLOCK2 U361 (PIN[57] , PIN[59] , GIN[59] , GIN[61] , POUT[57] , GOUT[61] );
BLOCK2 U362 (PIN[58] , PIN[60] , GIN[60] , GIN[62] , POUT[58] , GOUT[62] );
BLOCK2 U363 (PIN[59] , PIN[61] , GIN[61] , GIN[63] , POUT[59] , GOUT[63] );
BLOCK2 U364 (PIN[60] , PIN[62] , GIN[62] , GIN[64] , POUT[60] , GOUT[64] );
endmodule // DBLC_1_64
module DBLC_2_64 ( PIN, GIN, POUT, GOUT );
input [0:60] PIN;
input [0:64] GIN;
output [0:56] POUT;
output [0:64] GOUT;
INVBLOCK U10 (GIN[0] , GOUT[0] );
INVBLOCK U11 (GIN[1] , GOUT[1] );
INVBLOCK U12 (GIN[2] , GOUT[2] );
INVBLOCK U13 (GIN[3] , GOUT[3] );
BLOCK1A U24 (PIN[0] , GIN[0] , GIN[4] , GOUT[4] );
BLOCK1A U25 (PIN[1] , GIN[1] , GIN[5] , GOUT[5] );
BLOCK1A U26 (PIN[2] , GIN[2] , GIN[6] , GOUT[6] );
BLOCK1A U27 (PIN[3] , GIN[3] , GIN[7] , GOUT[7] );
BLOCK1 U38 (PIN[0] , PIN[4] , GIN[4] , GIN[8] , POUT[0] , GOUT[8] );
BLOCK1 U39 (PIN[1] , PIN[5] , GIN[5] , GIN[9] , POUT[1] , GOUT[9] );
BLOCK1 U310 (PIN[2] , PIN[6] , GIN[6] , GIN[10] , POUT[2] , GOUT[10] );
BLOCK1 U311 (PIN[3] , PIN[7] , GIN[7] , GIN[11] , POUT[3] , GOUT[11] );
BLOCK1 U312 (PIN[4] , PIN[8] , GIN[8] , GIN[12] , POUT[4] , GOUT[12] );
BLOCK1 U313 (PIN[5] , PIN[9] , GIN[9] , GIN[13] , POUT[5] , GOUT[13] );
BLOCK1 U314 (PIN[6] , PIN[10] , GIN[10] , GIN[14] , POUT[6] , GOUT[14] );
BLOCK1 U315 (PIN[7] , PIN[11] , GIN[11] , GIN[15] , POUT[7] , GOUT[15] );
BLOCK1 U316 (PIN[8] , PIN[12] , GIN[12] , GIN[16] , POUT[8] , GOUT[16] );
BLOCK1 U317 (PIN[9] , PIN[13] , GIN[13] , GIN[17] , POUT[9] , GOUT[17] );
BLOCK1 U318 (PIN[10] , PIN[14] , GIN[14] , GIN[18] , POUT[10] , GOUT[18] );
BLOCK1 U319 (PIN[11] , PIN[15] , GIN[15] , GIN[19] , POUT[11] , GOUT[19] );
BLOCK1 U320 (PIN[12] , PIN[16] , GIN[16] , GIN[20] , POUT[12] , GOUT[20] );
BLOCK1 U321 (PIN[13] , PIN[17] , GIN[17] , GIN[21] , POUT[13] , GOUT[21] );
BLOCK1 U322 (PIN[14] , PIN[18] , GIN[18] , GIN[22] , POUT[14] , GOUT[22] );
BLOCK1 U323 (PIN[15] , PIN[19] , GIN[19] , GIN[23] , POUT[15] , GOUT[23] );
BLOCK1 U324 (PIN[16] , PIN[20] , GIN[20] , GIN[24] , POUT[16] , GOUT[24] );
BLOCK1 U325 (PIN[17] , PIN[21] , GIN[21] , GIN[25] , POUT[17] , GOUT[25] );
BLOCK1 U326 (PIN[18] , PIN[22] , GIN[22] , GIN[26] , POUT[18] , GOUT[26] );
BLOCK1 U327 (PIN[19] , PIN[23] , GIN[23] , GIN[27] , POUT[19] , GOUT[27] );
BLOCK1 U328 (PIN[20] , PIN[24] , GIN[24] , GIN[28] , POUT[20] , GOUT[28] );
BLOCK1 U329 (PIN[21] , PIN[25] , GIN[25] , GIN[29] , POUT[21] , GOUT[29] );
BLOCK1 U330 (PIN[22] , PIN[26] , GIN[26] , GIN[30] , POUT[22] , GOUT[30] );
BLOCK1 U331 (PIN[23] , PIN[27] , GIN[27] , GIN[31] , POUT[23] , GOUT[31] );
BLOCK1 U332 (PIN[24] , PIN[28] , GIN[28] , GIN[32] , POUT[24] , GOUT[32] );
BLOCK1 U333 (PIN[25] , PIN[29] , GIN[29] , GIN[33] , POUT[25] , GOUT[33] );
BLOCK1 U334 (PIN[26] , PIN[30] , GIN[30] , GIN[34] , POUT[26] , GOUT[34] );
BLOCK1 U335 (PIN[27] , PIN[31] , GIN[31] , GIN[35] , POUT[27] , GOUT[35] );
BLOCK1 U336 (PIN[28] , PIN[32] , GIN[32] , GIN[36] , POUT[28] , GOUT[36] );
BLOCK1 U337 (PIN[29] , PIN[33] , GIN[33] , GIN[37] , POUT[29] , GOUT[37] );
BLOCK1 U338 (PIN[30] , PIN[34] , GIN[34] , GIN[38] , POUT[30] , GOUT[38] );
BLOCK1 U339 (PIN[31] , PIN[35] , GIN[35] , GIN[39] , POUT[31] , GOUT[39] );
BLOCK1 U340 (PIN[32] , PIN[36] , GIN[36] , GIN[40] , POUT[32] , GOUT[40] );
BLOCK1 U341 (PIN[33] , PIN[37] , GIN[37] , GIN[41] , POUT[33] , GOUT[41] );
BLOCK1 U342 (PIN[34] , PIN[38] , GIN[38] , GIN[42] , POUT[34] , GOUT[42] );
BLOCK1 U343 (PIN[35] , PIN[39] , GIN[39] , GIN[43] , POUT[35] , GOUT[43] );
BLOCK1 U344 (PIN[36] , PIN[40] , GIN[40] , GIN[44] , POUT[36] , GOUT[44] );
BLOCK1 U345 (PIN[37] , PIN[41] , GIN[41] , GIN[45] , POUT[37] , GOUT[45] );
BLOCK1 U346 (PIN[38] , PIN[42] , GIN[42] , GIN[46] , POUT[38] , GOUT[46] );
BLOCK1 U347 (PIN[39] , PIN[43] , GIN[43] , GIN[47] , POUT[39] , GOUT[47] );
BLOCK1 U348 (PIN[40] , PIN[44] , GIN[44] , GIN[48] , POUT[40] , GOUT[48] );
BLOCK1 U349 (PIN[41] , PIN[45] , GIN[45] , GIN[49] , POUT[41] , GOUT[49] );
BLOCK1 U350 (PIN[42] , PIN[46] , GIN[46] , GIN[50] , POUT[42] , GOUT[50] );
BLOCK1 U351 (PIN[43] , PIN[47] , GIN[47] , GIN[51] , POUT[43] , GOUT[51] );
BLOCK1 U352 (PIN[44] , PIN[48] , GIN[48] , GIN[52] , POUT[44] , GOUT[52] );
BLOCK1 U353 (PIN[45] , PIN[49] , GIN[49] , GIN[53] , POUT[45] , GOUT[53] );
BLOCK1 U354 (PIN[46] , PIN[50] , GIN[50] , GIN[54] , POUT[46] , GOUT[54] );
BLOCK1 U355 (PIN[47] , PIN[51] , GIN[51] , GIN[55] , POUT[47] , GOUT[55] );
BLOCK1 U356 (PIN[48] , PIN[52] , GIN[52] , GIN[56] , POUT[48] , GOUT[56] );
BLOCK1 U357 (PIN[49] , PIN[53] , GIN[53] , GIN[57] , POUT[49] , GOUT[57] );
BLOCK1 U358 (PIN[50] , PIN[54] , GIN[54] , GIN[58] , POUT[50] , GOUT[58] );
BLOCK1 U359 (PIN[51] , PIN[55] , GIN[55] , GIN[59] , POUT[51] , GOUT[59] );
BLOCK1 U360 (PIN[52] , PIN[56] , GIN[56] , GIN[60] , POUT[52] , GOUT[60] );
BLOCK1 U361 (PIN[53] , PIN[57] , GIN[57] , GIN[61] , POUT[53] , GOUT[61] );
BLOCK1 U362 (PIN[54] , PIN[58] , GIN[58] , GIN[62] , POUT[54] , GOUT[62] );
BLOCK1 U363 (PIN[55] , PIN[59] , GIN[59] , GIN[63] , POUT[55] , GOUT[63] );
BLOCK1 U364 (PIN[56] , PIN[60] , GIN[60] , GIN[64] , POUT[56] , GOUT[64] );
endmodule // DBLC_2_64
module DBLC_3_64 ( PIN, GIN, POUT, GOUT );
input [0:56] PIN;
input [0:64] GIN;
output [0:48] POUT;
output [0:64] GOUT;
INVBLOCK U10 (GIN[0] , GOUT[0] );
INVBLOCK U11 (GIN[1] , GOUT[1] );
INVBLOCK U12 (GIN[2] , GOUT[2] );
INVBLOCK U13 (GIN[3] , GOUT[3] );
INVBLOCK U14 (GIN[4] , GOUT[4] );
INVBLOCK U15 (GIN[5] , GOUT[5] );
INVBLOCK U16 (GIN[6] , GOUT[6] );
INVBLOCK U17 (GIN[7] , GOUT[7] );
BLOCK2A U28 (PIN[0] , GIN[0] , GIN[8] , GOUT[8] );
BLOCK2A U29 (PIN[1] , GIN[1] , GIN[9] , GOUT[9] );
BLOCK2A U210 (PIN[2] , GIN[2] , GIN[10] , GOUT[10] );
BLOCK2A U211 (PIN[3] , GIN[3] , GIN[11] , GOUT[11] );
BLOCK2A U212 (PIN[4] , GIN[4] , GIN[12] , GOUT[12] );
BLOCK2A U213 (PIN[5] , GIN[5] , GIN[13] , GOUT[13] );
BLOCK2A U214 (PIN[6] , GIN[6] , GIN[14] , GOUT[14] );
BLOCK2A U215 (PIN[7] , GIN[7] , GIN[15] , GOUT[15] );
BLOCK2 U316 (PIN[0] , PIN[8] , GIN[8] , GIN[16] , POUT[0] , GOUT[16] );
BLOCK2 U317 (PIN[1] , PIN[9] , GIN[9] , GIN[17] , POUT[1] , GOUT[17] );
BLOCK2 U318 (PIN[2] , PIN[10] , GIN[10] , GIN[18] , POUT[2] , GOUT[18] );
BLOCK2 U319 (PIN[3] , PIN[11] , GIN[11] , GIN[19] , POUT[3] , GOUT[19] );
BLOCK2 U320 (PIN[4] , PIN[12] , GIN[12] , GIN[20] , POUT[4] , GOUT[20] );
BLOCK2 U321 (PIN[5] , PIN[13] , GIN[13] , GIN[21] , POUT[5] , GOUT[21] );
BLOCK2 U322 (PIN[6] , PIN[14] , GIN[14] , GIN[22] , POUT[6] , GOUT[22] );
BLOCK2 U323 (PIN[7] , PIN[15] , GIN[15] , GIN[23] , POUT[7] , GOUT[23] );
BLOCK2 U324 (PIN[8] , PIN[16] , GIN[16] , GIN[24] , POUT[8] , GOUT[24] );
BLOCK2 U325 (PIN[9] , PIN[17] , GIN[17] , GIN[25] , POUT[9] , GOUT[25] );
BLOCK2 U326 (PIN[10] , PIN[18] , GIN[18] , GIN[26] , POUT[10] , GOUT[26] );
BLOCK2 U327 (PIN[11] , PIN[19] , GIN[19] , GIN[27] , POUT[11] , GOUT[27] );
BLOCK2 U328 (PIN[12] , PIN[20] , GIN[20] , GIN[28] , POUT[12] , GOUT[28] );
BLOCK2 U329 (PIN[13] , PIN[21] , GIN[21] , GIN[29] , POUT[13] , GOUT[29] );
BLOCK2 U330 (PIN[14] , PIN[22] , GIN[22] , GIN[30] , POUT[14] , GOUT[30] );
BLOCK2 U331 (PIN[15] , PIN[23] , GIN[23] , GIN[31] , POUT[15] , GOUT[31] );
BLOCK2 U332 (PIN[16] , PIN[24] , GIN[24] , GIN[32] , POUT[16] , GOUT[32] );
BLOCK2 U333 (PIN[17] , PIN[25] , GIN[25] , GIN[33] , POUT[17] , GOUT[33] );
BLOCK2 U334 (PIN[18] , PIN[26] , GIN[26] , GIN[34] , POUT[18] , GOUT[34] );
BLOCK2 U335 (PIN[19] , PIN[27] , GIN[27] , GIN[35] , POUT[19] , GOUT[35] );
BLOCK2 U336 (PIN[20] , PIN[28] , GIN[28] , GIN[36] , POUT[20] , GOUT[36] );
BLOCK2 U337 (PIN[21] , PIN[29] , GIN[29] , GIN[37] , POUT[21] , GOUT[37] );
BLOCK2 U338 (PIN[22] , PIN[30] , GIN[30] , GIN[38] , POUT[22] , GOUT[38] );
BLOCK2 U339 (PIN[23] , PIN[31] , GIN[31] , GIN[39] , POUT[23] , GOUT[39] );
BLOCK2 U340 (PIN[24] , PIN[32] , GIN[32] , GIN[40] , POUT[24] , GOUT[40] );
BLOCK2 U341 (PIN[25] , PIN[33] , GIN[33] , GIN[41] , POUT[25] , GOUT[41] );
BLOCK2 U342 (PIN[26] , PIN[34] , GIN[34] , GIN[42] , POUT[26] , GOUT[42] );
BLOCK2 U343 (PIN[27] , PIN[35] , GIN[35] , GIN[43] , POUT[27] , GOUT[43] );
BLOCK2 U344 (PIN[28] , PIN[36] , GIN[36] , GIN[44] , POUT[28] , GOUT[44] );
BLOCK2 U345 (PIN[29] , PIN[37] , GIN[37] , GIN[45] , POUT[29] , GOUT[45] );
BLOCK2 U346 (PIN[30] , PIN[38] , GIN[38] , GIN[46] , POUT[30] , GOUT[46] );
BLOCK2 U347 (PIN[31] , PIN[39] , GIN[39] , GIN[47] , POUT[31] , GOUT[47] );
BLOCK2 U348 (PIN[32] , PIN[40] , GIN[40] , GIN[48] , POUT[32] , GOUT[48] );
BLOCK2 U349 (PIN[33] , PIN[41] , GIN[41] , GIN[49] , POUT[33] , GOUT[49] );
BLOCK2 U350 (PIN[34] , PIN[42] , GIN[42] , GIN[50] , POUT[34] , GOUT[50] );
BLOCK2 U351 (PIN[35] , PIN[43] , GIN[43] , GIN[51] , POUT[35] , GOUT[51] );
BLOCK2 U352 (PIN[36] , PIN[44] , GIN[44] , GIN[52] , POUT[36] , GOUT[52] );
BLOCK2 U353 (PIN[37] , PIN[45] , GIN[45] , GIN[53] , POUT[37] , GOUT[53] );
BLOCK2 U354 (PIN[38] , PIN[46] , GIN[46] , GIN[54] , POUT[38] , GOUT[54] );
BLOCK2 U355 (PIN[39] , PIN[47] , GIN[47] , GIN[55] , POUT[39] , GOUT[55] );
BLOCK2 U356 (PIN[40] , PIN[48] , GIN[48] , GIN[56] , POUT[40] , GOUT[56] );
BLOCK2 U357 (PIN[41] , PIN[49] , GIN[49] , GIN[57] , POUT[41] , GOUT[57] );
BLOCK2 U358 (PIN[42] , PIN[50] , GIN[50] , GIN[58] , POUT[42] , GOUT[58] );
BLOCK2 U359 (PIN[43] , PIN[51] , GIN[51] , GIN[59] , POUT[43] , GOUT[59] );
BLOCK2 U360 (PIN[44] , PIN[52] , GIN[52] , GIN[60] , POUT[44] , GOUT[60] );
BLOCK2 U361 (PIN[45] , PIN[53] , GIN[53] , GIN[61] , POUT[45] , GOUT[61] );
BLOCK2 U362 (PIN[46] , PIN[54] , GIN[54] , GIN[62] , POUT[46] , GOUT[62] );
BLOCK2 U363 (PIN[47] , PIN[55] , GIN[55] , GIN[63] , POUT[47] , GOUT[63] );
BLOCK2 U364 (PIN[48] , PIN[56] , GIN[56] , GIN[64] , POUT[48] , GOUT[64] );
endmodule // DBLC_3_64
module DBLC_4_64 ( PIN, GIN, POUT, GOUT );
input [0:48] PIN;
input [0:64] GIN;
output [0:32] POUT;
output [0:64] GOUT;
INVBLOCK U10 (GIN[0] , GOUT[0] );
INVBLOCK U11 (GIN[1] , GOUT[1] );
INVBLOCK U12 (GIN[2] , GOUT[2] );
INVBLOCK U13 (GIN[3] , GOUT[3] );
INVBLOCK U14 (GIN[4] , GOUT[4] );
INVBLOCK U15 (GIN[5] , GOUT[5] );
INVBLOCK U16 (GIN[6] , GOUT[6] );
INVBLOCK U17 (GIN[7] , GOUT[7] );
INVBLOCK U18 (GIN[8] , GOUT[8] );
INVBLOCK U19 (GIN[9] , GOUT[9] );
INVBLOCK U110 (GIN[10] , GOUT[10] );
INVBLOCK U111 (GIN[11] , GOUT[11] );
INVBLOCK U112 (GIN[12] , GOUT[12] );
INVBLOCK U113 (GIN[13] , GOUT[13] );
INVBLOCK U114 (GIN[14] , GOUT[14] );
INVBLOCK U115 (GIN[15] , GOUT[15] );
BLOCK1A U216 (PIN[0] , GIN[0] , GIN[16] , GOUT[16] );
BLOCK1A U217 (PIN[1] , GIN[1] , GIN[17] , GOUT[17] );
BLOCK1A U218 (PIN[2] , GIN[2] , GIN[18] , GOUT[18] );
BLOCK1A U219 (PIN[3] , GIN[3] , GIN[19] , GOUT[19] );
BLOCK1A U220 (PIN[4] , GIN[4] , GIN[20] , GOUT[20] );
BLOCK1A U221 (PIN[5] , GIN[5] , GIN[21] , GOUT[21] );
BLOCK1A U222 (PIN[6] , GIN[6] , GIN[22] , GOUT[22] );
BLOCK1A U223 (PIN[7] , GIN[7] , GIN[23] , GOUT[23] );
BLOCK1A U224 (PIN[8] , GIN[8] , GIN[24] , GOUT[24] );
BLOCK1A U225 (PIN[9] , GIN[9] , GIN[25] , GOUT[25] );
BLOCK1A U226 (PIN[10] , GIN[10] , GIN[26] , GOUT[26] );
BLOCK1A U227 (PIN[11] , GIN[11] , GIN[27] , GOUT[27] );
BLOCK1A U228 (PIN[12] , GIN[12] , GIN[28] , GOUT[28] );
BLOCK1A U229 (PIN[13] , GIN[13] , GIN[29] , GOUT[29] );
BLOCK1A U230 (PIN[14] , GIN[14] , GIN[30] , GOUT[30] );
BLOCK1A U231 (PIN[15] , GIN[15] , GIN[31] , GOUT[31] );
BLOCK1 U332 (PIN[0] , PIN[16] , GIN[16] , GIN[32] , POUT[0] , GOUT[32] );
BLOCK1 U333 (PIN[1] , PIN[17] , GIN[17] , GIN[33] , POUT[1] , GOUT[33] );
BLOCK1 U334 (PIN[2] , PIN[18] , GIN[18] , GIN[34] , POUT[2] , GOUT[34] );
BLOCK1 U335 (PIN[3] , PIN[19] , GIN[19] , GIN[35] , POUT[3] , GOUT[35] );
BLOCK1 U336 (PIN[4] , PIN[20] , GIN[20] , GIN[36] , POUT[4] , GOUT[36] );
BLOCK1 U337 (PIN[5] , PIN[21] , GIN[21] , GIN[37] , POUT[5] , GOUT[37] );
BLOCK1 U338 (PIN[6] , PIN[22] , GIN[22] , GIN[38] , POUT[6] , GOUT[38] );
BLOCK1 U339 (PIN[7] , PIN[23] , GIN[23] , GIN[39] , POUT[7] , GOUT[39] );
BLOCK1 U340 (PIN[8] , PIN[24] , GIN[24] , GIN[40] , POUT[8] , GOUT[40] );
BLOCK1 U341 (PIN[9] , PIN[25] , GIN[25] , GIN[41] , POUT[9] , GOUT[41] );
BLOCK1 U342 (PIN[10] , PIN[26] , GIN[26] , GIN[42] , POUT[10] , GOUT[42] );
BLOCK1 U343 (PIN[11] , PIN[27] , GIN[27] , GIN[43] , POUT[11] , GOUT[43] );
BLOCK1 U344 (PIN[12] , PIN[28] , GIN[28] , GIN[44] , POUT[12] , GOUT[44] );
BLOCK1 U345 (PIN[13] , PIN[29] , GIN[29] , GIN[45] , POUT[13] , GOUT[45] );
BLOCK1 U346 (PIN[14] , PIN[30] , GIN[30] , GIN[46] , POUT[14] , GOUT[46] );
BLOCK1 U347 (PIN[15] , PIN[31] , GIN[31] , GIN[47] , POUT[15] , GOUT[47] );
BLOCK1 U348 (PIN[16] , PIN[32] , GIN[32] , GIN[48] , POUT[16] , GOUT[48] );
BLOCK1 U349 (PIN[17] , PIN[33] , GIN[33] , GIN[49] , POUT[17] , GOUT[49] );
BLOCK1 U350 (PIN[18] , PIN[34] , GIN[34] , GIN[50] , POUT[18] , GOUT[50] );
BLOCK1 U351 (PIN[19] , PIN[35] , GIN[35] , GIN[51] , POUT[19] , GOUT[51] );
BLOCK1 U352 (PIN[20] , PIN[36] , GIN[36] , GIN[52] , POUT[20] , GOUT[52] );
BLOCK1 U353 (PIN[21] , PIN[37] , GIN[37] , GIN[53] , POUT[21] , GOUT[53] );
BLOCK1 U354 (PIN[22] , PIN[38] , GIN[38] , GIN[54] , POUT[22] , GOUT[54] );
BLOCK1 U355 (PIN[23] , PIN[39] , GIN[39] , GIN[55] , POUT[23] , GOUT[55] );
BLOCK1 U356 (PIN[24] , PIN[40] , GIN[40] , GIN[56] , POUT[24] , GOUT[56] );
BLOCK1 U357 (PIN[25] , PIN[41] , GIN[41] , GIN[57] , POUT[25] , GOUT[57] );
BLOCK1 U358 (PIN[26] , PIN[42] , GIN[42] , GIN[58] , POUT[26] , GOUT[58] );
BLOCK1 U359 (PIN[27] , PIN[43] , GIN[43] , GIN[59] , POUT[27] , GOUT[59] );
BLOCK1 U360 (PIN[28] , PIN[44] , GIN[44] , GIN[60] , POUT[28] , GOUT[60] );
BLOCK1 U361 (PIN[29] , PIN[45] , GIN[45] , GIN[61] , POUT[29] , GOUT[61] );
BLOCK1 U362 (PIN[30] , PIN[46] , GIN[46] , GIN[62] , POUT[30] , GOUT[62] );
BLOCK1 U363 (PIN[31] , PIN[47] , GIN[47] , GIN[63] , POUT[31] , GOUT[63] );
BLOCK1 U364 (PIN[32] , PIN[48] , GIN[48] , GIN[64] , POUT[32] , GOUT[64] );
endmodule // DBLC_4_64
module DBLC_5_64 ( PIN, GIN, POUT, GOUT );
input [0:32] PIN;
input [0:64] GIN;
output [0:0] POUT;
output [0:64] GOUT;
INVBLOCK U10 (GIN[0] , GOUT[0] );
INVBLOCK U11 (GIN[1] , GOUT[1] );
INVBLOCK U12 (GIN[2] , GOUT[2] );
INVBLOCK U13 (GIN[3] , GOUT[3] );
INVBLOCK U14 (GIN[4] , GOUT[4] );
INVBLOCK U15 (GIN[5] , GOUT[5] );
INVBLOCK U16 (GIN[6] , GOUT[6] );
INVBLOCK U17 (GIN[7] , GOUT[7] );
INVBLOCK U18 (GIN[8] , GOUT[8] );
INVBLOCK U19 (GIN[9] , GOUT[9] );
INVBLOCK U110 (GIN[10] , GOUT[10] );
INVBLOCK U111 (GIN[11] , GOUT[11] );
INVBLOCK U112 (GIN[12] , GOUT[12] );
INVBLOCK U113 (GIN[13] , GOUT[13] );
INVBLOCK U114 (GIN[14] , GOUT[14] );
INVBLOCK U115 (GIN[15] , GOUT[15] );
INVBLOCK U116 (GIN[16] , GOUT[16] );
INVBLOCK U117 (GIN[17] , GOUT[17] );
INVBLOCK U118 (GIN[18] , GOUT[18] );
INVBLOCK U119 (GIN[19] , GOUT[19] );
INVBLOCK U120 (GIN[20] , GOUT[20] );
INVBLOCK U121 (GIN[21] , GOUT[21] );
INVBLOCK U122 (GIN[22] , GOUT[22] );
INVBLOCK U123 (GIN[23] , GOUT[23] );
INVBLOCK U124 (GIN[24] , GOUT[24] );
INVBLOCK U125 (GIN[25] , GOUT[25] );
INVBLOCK U126 (GIN[26] , GOUT[26] );
INVBLOCK U127 (GIN[27] , GOUT[27] );
INVBLOCK U128 (GIN[28] , GOUT[28] );
INVBLOCK U129 (GIN[29] , GOUT[29] );
INVBLOCK U130 (GIN[30] , GOUT[30] );
INVBLOCK U131 (GIN[31] , GOUT[31] );
BLOCK2A U232 (PIN[0] , GIN[0] , GIN[32] , GOUT[32] );
BLOCK2A U233 (PIN[1] , GIN[1] , GIN[33] , GOUT[33] );
BLOCK2A U234 (PIN[2] , GIN[2] , GIN[34] , GOUT[34] );
BLOCK2A U235 (PIN[3] , GIN[3] , GIN[35] , GOUT[35] );
BLOCK2A U236 (PIN[4] , GIN[4] , GIN[36] , GOUT[36] );
BLOCK2A U237 (PIN[5] , GIN[5] , GIN[37] , GOUT[37] );
BLOCK2A U238 (PIN[6] , GIN[6] , GIN[38] , GOUT[38] );
BLOCK2A U239 (PIN[7] , GIN[7] , GIN[39] , GOUT[39] );
BLOCK2A U240 (PIN[8] , GIN[8] , GIN[40] , GOUT[40] );
BLOCK2A U241 (PIN[9] , GIN[9] , GIN[41] , GOUT[41] );
BLOCK2A U242 (PIN[10] , GIN[10] , GIN[42] , GOUT[42] );
BLOCK2A U243 (PIN[11] , GIN[11] , GIN[43] , GOUT[43] );
BLOCK2A U244 (PIN[12] , GIN[12] , GIN[44] , GOUT[44] );
BLOCK2A U245 (PIN[13] , GIN[13] , GIN[45] , GOUT[45] );
BLOCK2A U246 (PIN[14] , GIN[14] , GIN[46] , GOUT[46] );
BLOCK2A U247 (PIN[15] , GIN[15] , GIN[47] , GOUT[47] );
BLOCK2A U248 (PIN[16] , GIN[16] , GIN[48] , GOUT[48] );
BLOCK2A U249 (PIN[17] , GIN[17] , GIN[49] , GOUT[49] );
BLOCK2A U250 (PIN[18] , GIN[18] , GIN[50] , GOUT[50] );
BLOCK2A U251 (PIN[19] , GIN[19] , GIN[51] , GOUT[51] );
BLOCK2A U252 (PIN[20] , GIN[20] , GIN[52] , GOUT[52] );
BLOCK2A U253 (PIN[21] , GIN[21] , GIN[53] , GOUT[53] );
BLOCK2A U254 (PIN[22] , GIN[22] , GIN[54] , GOUT[54] );
BLOCK2A U255 (PIN[23] , GIN[23] , GIN[55] , GOUT[55] );
BLOCK2A U256 (PIN[24] , GIN[24] , GIN[56] , GOUT[56] );
BLOCK2A U257 (PIN[25] , GIN[25] , GIN[57] , GOUT[57] );
BLOCK2A U258 (PIN[26] , GIN[26] , GIN[58] , GOUT[58] );
BLOCK2A U259 (PIN[27] , GIN[27] , GIN[59] , GOUT[59] );
BLOCK2A U260 (PIN[28] , GIN[28] , GIN[60] , GOUT[60] );
BLOCK2A U261 (PIN[29] , GIN[29] , GIN[61] , GOUT[61] );
BLOCK2A U262 (PIN[30] , GIN[30] , GIN[62] , GOUT[62] );
BLOCK2A U263 (PIN[31] , GIN[31] , GIN[63] , GOUT[63] );
BLOCK2 U364 (PIN[0] , PIN[32] , GIN[32] , GIN[64] , POUT[0] , GOUT[64] );
endmodule // DBLC_5_64
module XORSTAGE_64 ( A, B, PBIT, CARRY, SUM, COUT );
input [0:63] A;
input [0:63] B;
input PBIT;
input [0:64] CARRY;
output [0:63] SUM;
output COUT;
XXOR1 U20 (A[0] , B[0] , CARRY[0] , SUM[0] );
XXOR1 U21 (A[1] , B[1] , CARRY[1] , SUM[1] );
XXOR1 U22 (A[2] , B[2] , CARRY[2] , SUM[2] );
XXOR1 U23 (A[3] , B[3] , CARRY[3] , SUM[3] );
XXOR1 U24 (A[4] , B[4] , CARRY[4] , SUM[4] );
XXOR1 U25 (A[5] , B[5] , CARRY[5] , SUM[5] );
XXOR1 U26 (A[6] , B[6] , CARRY[6] , SUM[6] );
XXOR1 U27 (A[7] , B[7] , CARRY[7] , SUM[7] );
XXOR1 U28 (A[8] , B[8] , CARRY[8] , SUM[8] );
XXOR1 U29 (A[9] , B[9] , CARRY[9] , SUM[9] );
XXOR1 U210 (A[10] , B[10] , CARRY[10] , SUM[10] );
XXOR1 U211 (A[11] , B[11] , CARRY[11] , SUM[11] );
XXOR1 U212 (A[12] , B[12] , CARRY[12] , SUM[12] );
XXOR1 U213 (A[13] , B[13] , CARRY[13] , SUM[13] );
XXOR1 U214 (A[14] , B[14] , CARRY[14] , SUM[14] );
XXOR1 U215 (A[15] , B[15] , CARRY[15] , SUM[15] );
XXOR1 U216 (A[16] , B[16] , CARRY[16] , SUM[16] );
XXOR1 U217 (A[17] , B[17] , CARRY[17] , SUM[17] );
XXOR1 U218 (A[18] , B[18] , CARRY[18] , SUM[18] );
XXOR1 U219 (A[19] , B[19] , CARRY[19] , SUM[19] );
XXOR1 U220 (A[20] , B[20] , CARRY[20] , SUM[20] );
XXOR1 U221 (A[21] , B[21] , CARRY[21] , SUM[21] );
XXOR1 U222 (A[22] , B[22] , CARRY[22] , SUM[22] );
XXOR1 U223 (A[23] , B[23] , CARRY[23] , SUM[23] );
XXOR1 U224 (A[24] , B[24] , CARRY[24] , SUM[24] );
XXOR1 U225 (A[25] , B[25] , CARRY[25] , SUM[25] );
XXOR1 U226 (A[26] , B[26] , CARRY[26] , SUM[26] );
XXOR1 U227 (A[27] , B[27] , CARRY[27] , SUM[27] );
XXOR1 U228 (A[28] , B[28] , CARRY[28] , SUM[28] );
XXOR1 U229 (A[29] , B[29] , CARRY[29] , SUM[29] );
XXOR1 U230 (A[30] , B[30] , CARRY[30] , SUM[30] );
XXOR1 U231 (A[31] , B[31] , CARRY[31] , SUM[31] );
XXOR1 U232 (A[32] , B[32] , CARRY[32] , SUM[32] );
XXOR1 U233 (A[33] , B[33] , CARRY[33] , SUM[33] );
XXOR1 U234 (A[34] , B[34] , CARRY[34] , SUM[34] );
XXOR1 U235 (A[35] , B[35] , CARRY[35] , SUM[35] );
XXOR1 U236 (A[36] , B[36] , CARRY[36] , SUM[36] );
XXOR1 U237 (A[37] , B[37] , CARRY[37] , SUM[37] );
XXOR1 U238 (A[38] , B[38] , CARRY[38] , SUM[38] );
XXOR1 U239 (A[39] , B[39] , CARRY[39] , SUM[39] );
XXOR1 U240 (A[40] , B[40] , CARRY[40] , SUM[40] );
XXOR1 U241 (A[41] , B[41] , CARRY[41] , SUM[41] );
XXOR1 U242 (A[42] , B[42] , CARRY[42] , SUM[42] );
XXOR1 U243 (A[43] , B[43] , CARRY[43] , SUM[43] );
XXOR1 U244 (A[44] , B[44] , CARRY[44] , SUM[44] );
XXOR1 U245 (A[45] , B[45] , CARRY[45] , SUM[45] );
XXOR1 U246 (A[46] , B[46] , CARRY[46] , SUM[46] );
XXOR1 U247 (A[47] , B[47] , CARRY[47] , SUM[47] );
XXOR1 U248 (A[48] , B[48] , CARRY[48] , SUM[48] );
XXOR1 U249 (A[49] , B[49] , CARRY[49] , SUM[49] );
XXOR1 U250 (A[50] , B[50] , CARRY[50] , SUM[50] );
XXOR1 U251 (A[51] , B[51] , CARRY[51] , SUM[51] );
XXOR1 U252 (A[52] , B[52] , CARRY[52] , SUM[52] );
XXOR1 U253 (A[53] , B[53] , CARRY[53] , SUM[53] );
XXOR1 U254 (A[54] , B[54] , CARRY[54] , SUM[54] );
XXOR1 U255 (A[55] , B[55] , CARRY[55] , SUM[55] );
XXOR1 U256 (A[56] , B[56] , CARRY[56] , SUM[56] );
XXOR1 U257 (A[57] , B[57] , CARRY[57] , SUM[57] );
XXOR1 U258 (A[58] , B[58] , CARRY[58] , SUM[58] );
XXOR1 U259 (A[59] , B[59] , CARRY[59] , SUM[59] );
XXOR1 U260 (A[60] , B[60] , CARRY[60] , SUM[60] );
XXOR1 U261 (A[61] , B[61] , CARRY[61] , SUM[61] );
XXOR1 U262 (A[62] , B[62] , CARRY[62] , SUM[62] );
XXOR1 U263 (A[63] , B[63] , CARRY[63] , SUM[63] );
BLOCK1A U1 (PBIT , CARRY[0] , CARRY[64] , COUT );
endmodule // XORSTAGE_64
module DBLCTREE_64 ( PIN, GIN, GOUT, POUT );
input [0:63] PIN;
input [0:64] GIN;
output [0:64] GOUT;
output [0:0] POUT;
wire [0:62] INTPROP_0;
wire [0:64] INTGEN_0;
wire [0:60] INTPROP_1;
wire [0:64] INTGEN_1;
wire [0:56] INTPROP_2;
wire [0:64] INTGEN_2;
wire [0:48] INTPROP_3;
wire [0:64] INTGEN_3;
wire [0:32] INTPROP_4;
wire [0:64] INTGEN_4;
DBLC_0_64 U_0 (.PIN(PIN) , .GIN(GIN) , .POUT(INTPROP_0) , .GOUT(INTGEN_0) );
DBLC_1_64 U_1 (.PIN(INTPROP_0) , .GIN(INTGEN_0) , .POUT(INTPROP_1) , .GOUT(INTGEN_1) );
DBLC_2_64 U_2 (.PIN(INTPROP_1) , .GIN(INTGEN_1) , .POUT(INTPROP_2) , .GOUT(INTGEN_2) );
DBLC_3_64 U_3 (.PIN(INTPROP_2) , .GIN(INTGEN_2) , .POUT(INTPROP_3) , .GOUT(INTGEN_3) );
DBLC_4_64 U_4 (.PIN(INTPROP_3) , .GIN(INTGEN_3) , .POUT(INTPROP_4) , .GOUT(INTGEN_4) );
DBLC_5_64 U_5 (.PIN(INTPROP_4) , .GIN(INTGEN_4) , .POUT(POUT) , .GOUT(GOUT) );
endmodule // DBLCTREE_64
module DBLCADDER_64_64 ( OPA, OPB, CIN, SUM, COUT );
input [0:63] OPA;
input [0:63] OPB;
input CIN;
output [0:63] SUM;
output COUT;
wire [0:63] INTPROP;
wire [0:64] INTGEN;
wire [0:0] PBIT;
wire [0:64] CARRY;
PRESTAGE_64 U1 (OPA , OPB , CIN , INTPROP , INTGEN );
DBLCTREE_64 U2 (INTPROP , INTGEN , CARRY , PBIT );
XORSTAGE_64 U3 (OPA[0:63] , OPB[0:63] , PBIT[0] , CARRY[0:64] , SUM , COUT );
endmodule

420
wally-pipelined/src/fpufma/struct/cla64.v
View file

@ -1,420 +0,0 @@
// This module implements a 64-bit carry lookehead adder/subtractor.
// It is used to perform the primary addition in the floating point
// adder
module cla64 (S, X, Y, Sub);
input [63:0] X;
input [63:0] Y;
input Sub;
output [63:0] S;
wire CO;
wire [0:63] A,B,Q, Bbar;
DBLCADDER_64_64 U1 (A , Bbar , Sub , Q , CO );
assign A[0] = X[0];
assign B[0] = Y[0];
assign A[1] = X[1];
assign B[1] = Y[1];
assign A[2] = X[2];
assign B[2] = Y[2];
assign A[3] = X[3];
assign B[3] = Y[3];
assign A[4] = X[4];
assign B[4] = Y[4];
assign A[5] = X[5];
assign B[5] = Y[5];
assign A[6] = X[6];
assign B[6] = Y[6];
assign A[7] = X[7];
assign B[7] = Y[7];
assign A[8] = X[8];
assign B[8] = Y[8];
assign A[9] = X[9];
assign B[9] = Y[9];
assign A[10] = X[10];
assign B[10] = Y[10];
assign A[11] = X[11];
assign B[11] = Y[11];
assign A[12] = X[12];
assign B[12] = Y[12];
assign A[13] = X[13];
assign B[13] = Y[13];
assign A[14] = X[14];
assign B[14] = Y[14];
assign A[15] = X[15];
assign B[15] = Y[15];
assign A[16] = X[16];
assign B[16] = Y[16];
assign A[17] = X[17];
assign B[17] = Y[17];
assign A[18] = X[18];
assign B[18] = Y[18];
assign A[19] = X[19];
assign B[19] = Y[19];
assign A[20] = X[20];
assign B[20] = Y[20];
assign A[21] = X[21];
assign B[21] = Y[21];
assign A[22] = X[22];
assign B[22] = Y[22];
assign A[23] = X[23];
assign B[23] = Y[23];
assign A[24] = X[24];
assign B[24] = Y[24];
assign A[25] = X[25];
assign B[25] = Y[25];
assign A[26] = X[26];
assign B[26] = Y[26];
assign A[27] = X[27];
assign B[27] = Y[27];
assign A[28] = X[28];
assign B[28] = Y[28];
assign A[29] = X[29];
assign B[29] = Y[29];
assign A[30] = X[30];
assign B[30] = Y[30];
assign A[31] = X[31];
assign B[31] = Y[31];
assign A[32] = X[32];
assign B[32] = Y[32];
assign A[33] = X[33];
assign B[33] = Y[33];
assign A[34] = X[34];
assign B[34] = Y[34];
assign A[35] = X[35];
assign B[35] = Y[35];
assign A[36] = X[36];
assign B[36] = Y[36];
assign A[37] = X[37];
assign B[37] = Y[37];
assign A[38] = X[38];
assign B[38] = Y[38];
assign A[39] = X[39];
assign B[39] = Y[39];
assign A[40] = X[40];
assign B[40] = Y[40];
assign A[41] = X[41];
assign B[41] = Y[41];
assign A[42] = X[42];
assign B[42] = Y[42];
assign A[43] = X[43];
assign B[43] = Y[43];
assign A[44] = X[44];
assign B[44] = Y[44];
assign A[45] = X[45];
assign B[45] = Y[45];
assign A[46] = X[46];
assign B[46] = Y[46];
assign A[47] = X[47];
assign B[47] = Y[47];
assign A[48] = X[48];
assign B[48] = Y[48];
assign A[49] = X[49];
assign B[49] = Y[49];
assign A[50] = X[50];
assign B[50] = Y[50];
assign A[51] = X[51];
assign B[51] = Y[51];
assign A[52] = X[52];
assign B[52] = Y[52];
assign A[53] = X[53];
assign B[53] = Y[53];
assign A[54] = X[54];
assign B[54] = Y[54];
assign A[55] = X[55];
assign B[55] = Y[55];
assign A[56] = X[56];
assign B[56] = Y[56];
assign A[57] = X[57];
assign B[57] = Y[57];
assign A[58] = X[58];
assign B[58] = Y[58];
assign A[59] = X[59];
assign B[59] = Y[59];
assign A[60] = X[60];
assign B[60] = Y[60];
assign A[61] = X[61];
assign B[61] = Y[61];
assign A[62] = X[62];
assign B[62] = Y[62];
assign A[63] = X[63];
assign B[63] = Y[63];
assign S[0] = Q[0];
assign S[1] = Q[1];
assign S[2] = Q[2];
assign S[3] = Q[3];
assign S[4] = Q[4];
assign S[5] = Q[5];
assign S[6] = Q[6];
assign S[7] = Q[7];
assign S[8] = Q[8];
assign S[9] = Q[9];
assign S[10] = Q[10];
assign S[11] = Q[11];
assign S[12] = Q[12];
assign S[13] = Q[13];
assign S[14] = Q[14];
assign S[15] = Q[15];
assign S[16] = Q[16];
assign S[17] = Q[17];
assign S[18] = Q[18];
assign S[19] = Q[19];
assign S[20] = Q[20];
assign S[21] = Q[21];
assign S[22] = Q[22];
assign S[23] = Q[23];
assign S[24] = Q[24];
assign S[25] = Q[25];
assign S[26] = Q[26];
assign S[27] = Q[27];
assign S[28] = Q[28];
assign S[29] = Q[29];
assign S[30] = Q[30];
assign S[31] = Q[31];
assign S[32] = Q[32];
assign S[33] = Q[33];
assign S[34] = Q[34];
assign S[35] = Q[35];
assign S[36] = Q[36];
assign S[37] = Q[37];
assign S[38] = Q[38];
assign S[39] = Q[39];
assign S[40] = Q[40];
assign S[41] = Q[41];
assign S[42] = Q[42];
assign S[43] = Q[43];
assign S[44] = Q[44];
assign S[45] = Q[45];
assign S[46] = Q[46];
assign S[47] = Q[47];
assign S[48] = Q[48];
assign S[49] = Q[49];
assign S[50] = Q[50];
assign S[51] = Q[51];
assign S[52] = Q[52];
assign S[53] = Q[53];
assign S[54] = Q[54];
assign S[55] = Q[55];
assign S[56] = Q[56];
assign S[57] = Q[57];
assign S[58] = Q[58];
assign S[59] = Q[59];
assign S[60] = Q[60];
assign S[61] = Q[61];
assign S[62] = Q[62];
assign S[63] = Q[63];
assign Bbar = B ^ {64{Sub}};
endmodule // cla64
// This module performs 64-bit subtraction. It is used to get the two's complement
// of main addition or subtraction in the floating point adder.
module cla_sub64 (S, X, Y);
input [63:0] X;
input [63:0] Y;
output [63:0] S;
wire CO;
wire VDD = 1'b1;
wire [0:63] A,B,Q, Bbar;
DBLCADDER_64_64 U1 (A , Bbar , VDD, Q , CO );
assign A[0] = X[0];
assign B[0] = Y[0];
assign A[1] = X[1];
assign B[1] = Y[1];
assign A[2] = X[2];
assign B[2] = Y[2];
assign A[3] = X[3];
assign B[3] = Y[3];
assign A[4] = X[4];
assign B[4] = Y[4];
assign A[5] = X[5];
assign B[5] = Y[5];
assign A[6] = X[6];
assign B[6] = Y[6];
assign A[7] = X[7];
assign B[7] = Y[7];
assign A[8] = X[8];
assign B[8] = Y[8];
assign A[9] = X[9];
assign B[9] = Y[9];
assign A[10] = X[10];
assign B[10] = Y[10];
assign A[11] = X[11];
assign B[11] = Y[11];
assign A[12] = X[12];
assign B[12] = Y[12];
assign A[13] = X[13];
assign B[13] = Y[13];
assign A[14] = X[14];
assign B[14] = Y[14];
assign A[15] = X[15];
assign B[15] = Y[15];
assign A[16] = X[16];
assign B[16] = Y[16];
assign A[17] = X[17];
assign B[17] = Y[17];
assign A[18] = X[18];
assign B[18] = Y[18];
assign A[19] = X[19];
assign B[19] = Y[19];
assign A[20] = X[20];
assign B[20] = Y[20];
assign A[21] = X[21];
assign B[21] = Y[21];
assign A[22] = X[22];
assign B[22] = Y[22];
assign A[23] = X[23];
assign B[23] = Y[23];
assign A[24] = X[24];
assign B[24] = Y[24];
assign A[25] = X[25];
assign B[25] = Y[25];
assign A[26] = X[26];
assign B[26] = Y[26];
assign A[27] = X[27];
assign B[27] = Y[27];
assign A[28] = X[28];
assign B[28] = Y[28];
assign A[29] = X[29];
assign B[29] = Y[29];
assign A[30] = X[30];
assign B[30] = Y[30];
assign A[31] = X[31];
assign B[31] = Y[31];
assign A[32] = X[32];
assign B[32] = Y[32];
assign A[33] = X[33];
assign B[33] = Y[33];
assign A[34] = X[34];
assign B[34] = Y[34];
assign A[35] = X[35];
assign B[35] = Y[35];
assign A[36] = X[36];
assign B[36] = Y[36];
assign A[37] = X[37];
assign B[37] = Y[37];
assign A[38] = X[38];
assign B[38] = Y[38];
assign A[39] = X[39];
assign B[39] = Y[39];
assign A[40] = X[40];
assign B[40] = Y[40];
assign A[41] = X[41];
assign B[41] = Y[41];
assign A[42] = X[42];
assign B[42] = Y[42];
assign A[43] = X[43];
assign B[43] = Y[43];
assign A[44] = X[44];
assign B[44] = Y[44];
assign A[45] = X[45];
assign B[45] = Y[45];
assign A[46] = X[46];
assign B[46] = Y[46];
assign A[47] = X[47];
assign B[47] = Y[47];
assign A[48] = X[48];
assign B[48] = Y[48];
assign A[49] = X[49];
assign B[49] = Y[49];
assign A[50] = X[50];
assign B[50] = Y[50];
assign A[51] = X[51];
assign B[51] = Y[51];
assign A[52] = X[52];
assign B[52] = Y[52];
assign A[53] = X[53];
assign B[53] = Y[53];
assign A[54] = X[54];
assign B[54] = Y[54];
assign A[55] = X[55];
assign B[55] = Y[55];
assign A[56] = X[56];
assign B[56] = Y[56];
assign A[57] = X[57];
assign B[57] = Y[57];
assign A[58] = X[58];
assign B[58] = Y[58];
assign A[59] = X[59];
assign B[59] = Y[59];
assign A[60] = X[60];
assign B[60] = Y[60];
assign A[61] = X[61];
assign B[61] = Y[61];
assign A[62] = X[62];
assign B[62] = Y[62];
assign A[63] = X[63];
assign B[63] = Y[63];
assign S[0] = Q[0];
assign S[1] = Q[1];
assign S[2] = Q[2];
assign S[3] = Q[3];
assign S[4] = Q[4];
assign S[5] = Q[5];
assign S[6] = Q[6];
assign S[7] = Q[7];
assign S[8] = Q[8];
assign S[9] = Q[9];
assign S[10] = Q[10];
assign S[11] = Q[11];
assign S[12] = Q[12];
assign S[13] = Q[13];
assign S[14] = Q[14];
assign S[15] = Q[15];
assign S[16] = Q[16];
assign S[17] = Q[17];
assign S[18] = Q[18];
assign S[19] = Q[19];
assign S[20] = Q[20];
assign S[21] = Q[21];
assign S[22] = Q[22];
assign S[23] = Q[23];
assign S[24] = Q[24];
assign S[25] = Q[25];
assign S[26] = Q[26];
assign S[27] = Q[27];
assign S[28] = Q[28];
assign S[29] = Q[29];
assign S[30] = Q[30];
assign S[31] = Q[31];
assign S[32] = Q[32];
assign S[33] = Q[33];
assign S[34] = Q[34];
assign S[35] = Q[35];
assign S[36] = Q[36];
assign S[37] = Q[37];
assign S[38] = Q[38];
assign S[39] = Q[39];
assign S[40] = Q[40];
assign S[41] = Q[41];
assign S[42] = Q[42];
assign S[43] = Q[43];
assign S[44] = Q[44];
assign S[45] = Q[45];
assign S[46] = Q[46];
assign S[47] = Q[47];
assign S[48] = Q[48];
assign S[49] = Q[49];
assign S[50] = Q[50];
assign S[51] = Q[51];
assign S[52] = Q[52];
assign S[53] = Q[53];
assign S[54] = Q[54];
assign S[55] = Q[55];
assign S[56] = Q[56];
assign S[57] = Q[57];
assign S[58] = Q[58];
assign S[59] = Q[59];
assign S[60] = Q[60];
assign S[61] = Q[61];
assign S[62] = Q[62];
assign S[63] = Q[63];
assign Bbar = ~B;
endmodule // cla_sub64

170
wally-pipelined/src/fpufma/struct/lzd_denorm.v
View file

@ -1,170 +0,0 @@
module lz2 (P, V, B0, B1);
input B0;
input B1;
output P;
output V;
assign V = B0 | B1;
assign P = B0 & ~B1;
endmodule // lz2
// Note: This module is not made out of two lz2's - why not? (MJS)
module lz4 (ZP, ZV, B0, B1, V0, V1);
input B0;
input B1;
input V0;
input V1;
output [1:0] ZP;
output ZV;
assign ZP[0] = V0 ? B0 : B1;
assign ZP[1] = ~V0;
assign ZV = V0 | V1;
endmodule // lz4
// Note: This module is not made out of two lz4's - why not? (MJS)
module lz8 (ZP, ZV, B);
input [7:0] B;
wire s1p0;
wire s1v0;
wire s1p1;
wire s1v1;
wire s2p0;
wire s2v0;
wire s2p1;
wire s2v1;
wire [1:0] ZPa;
wire [1:0] ZPb;
wire ZVa;
wire ZVb;
output [2:0] ZP;
output ZV;
lz2 l1(s1p0, s1v0, B[2], B[3]);
lz2 l2(s1p1, s1v1, B[0], B[1]);
lz4 l3(ZPa, ZVa, s1p0, s1p1, s1v0, s1v1);
lz2 l4(s2p0, s2v0, B[6], B[7]);
lz2 l5(s2p1, s2v1, B[4], B[5]);
lz4 l6(ZPb, ZVb, s2p0, s2p1, s2v0, s2v1);
assign ZP[1:0] = ZVb ? ZPb : ZPa;
assign ZP[2] = ~ZVb;
assign ZV = ZVa | ZVb;
endmodule // lz8
module lz16 (ZP, ZV, B);
input [15:0] B;
wire [2:0] ZPa;
wire [2:0] ZPb;
wire ZVa;
wire ZVb;
output [3:0] ZP;
output ZV;
lz8 l1(ZPa, ZVa, B[7:0]);
lz8 l2(ZPb, ZVb, B[15:8]);
assign ZP[2:0] = ZVb ? ZPb : ZPa;
assign ZP[3] = ~ZVb;
assign ZV = ZVa | ZVb;
endmodule // lz16
module lz32 (ZP, ZV, B);
input [31:0] B;
wire [3:0] ZPa;
wire [3:0] ZPb;
wire ZVa;
wire ZVb;
output [4:0] ZP;
output ZV;
lz16 l1(ZPa, ZVa, B[15:0]);
lz16 l2(ZPb, ZVb, B[31:16]);
assign ZP[3:0] = ZVb ? ZPb : ZPa;
assign ZP[4] = ~ZVb;
assign ZV = ZVa | ZVb;
endmodule // lz32
// This module returns the number of leading zeros ZP in the 64-bit
// number B. If there are no ones in B, then ZP and ZV are both 0.
module lz64 (ZP, ZV, B);
input [63:0] B;
wire [4:0] ZPa;
wire [4:0] ZPb;
wire ZVa;
wire ZVb;
output [5:0] ZP;
output ZV;
lz32 l1(ZPa, ZVa, B[31:0]);
lz32 l2(ZPb, ZVb, B[63:32]);
assign ZV = ZVa | ZVb;
assign ZP[4:0] = (ZVb ? ZPb : ZPa) & {5{ZV}};
assign ZP[5] = ~ZVb & ZV;
endmodule // lz64
// This module returns the number of leading zeros ZP in the 52-bit
// number B. If there are no ones in B, then ZP and ZV are both 0.
module lz52 (ZP, ZV, B);
input [51:0] B;
wire [4:0] ZP_32;
wire [3:0] ZP_16;
wire [1:0] ZP_4;
wire ZV_32;
wire ZV_16;
wire ZV_4;
wire ZP_2_1;
wire ZP_2_2;
wire ZV_2_1;
wire ZV_2_2;
output [5:0] ZP;
output ZV;
lz32 l1 (ZP_32, ZV_32, B[51:20]);
lz16 l2 (ZP_16, ZV_16, B[19:4]);
lz2 l3_1 (ZP_2_1, ZV_2_1, B[3], B[2]);
lz2 l3_2 (ZP_2_2, ZV_2_2, B[1], B[0]);
lz4 l3_final (ZP_4, ZV_4, ZP_2_1, ZP_2_2, ZV_2_1, ZV_2_2);
assign ZV = ZV_32 | ZV_16 | ZV_4;
assign ZP[5] = ~ZV_32;
assign ZP[4] = ZV_32 ? ZP_32[4] : ~ZV_16;
assign ZP[3:2] = ZV_32 ? ZP_32[3:2] : (ZV_16 ? ZP_16[3:2] : 2'b0);
assign ZP[1:0] = ZV_32 ? ZP_32[1:0] : (ZV_16 ? ZP_16[1:0] : ZP_4);
endmodule // lz52

11514
wally-pipelined/src/fpufma/struct/mult_R4_64_64_cs.sv
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162
wally-pipelined/src/fpufma/struct/shifter_denorm.v
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@ -1,162 +0,0 @@
// MJS - This module implements a 57-bit 2-to-1 multiplexor, which is
// used in the barrel shifter for significand alignment.
module mux21x57 (Z, A, B, Sel);
input [56:0] A;
input [56:0] B;
input Sel;
output [56:0] Z;
assign Z = Sel ? B : A;
endmodule // mux21x57
// MJS - This module implements a 64-bit 2-to-1 multiplexor, which is
// used in the barrel shifter for significand normalization.
module mux21x64 (Z, A, B, Sel);
input [63:0] A;
input [63:0] B;
input Sel;
output [63:0] Z;
assign Z = Sel ? B : A;
endmodule // mux21x64
// The implementation of the barrel shifter was modified to use
// fewer gates. It is now implemented using six 64-bit 2-to-1 muxes. The
// barrel shifter takes a 64-bit input A and shifts it left by up to
// 63-bits, as specified by Shift, to produce a 63-bit output Z.
// Bits to the right are filled with zeros.
// The 64 bit shift is implemented using 6 stages of shifts of 32
// 16, 8, 4, 2, and 1 bit shifts.
module barrel_shifter_l64 (Z, A, Shift);
input [63:0] A;
input [5:0] Shift;
wire [63:0] stage1;
wire [63:0] stage2;
wire [63:0] stage3;
wire [63:0] stage4;
wire [63:0] stage5;
wire [31:0] thirtytwozeros = 32'h0;
wire [15:0] sixteenzeros = 16'h0;
wire [ 7:0] eightzeros = 8'h0;
wire [ 3:0] fourzeros = 4'h0;
wire [ 1:0] twozeros = 2'b00;
wire onezero = 1'b0;
output [63:0] Z;
mux21x64 mx01(stage1, A, {A[31:0], thirtytwozeros}, Shift[5]);
mux21x64 mx02(stage2, stage1, {stage1[47:0], sixteenzeros}, Shift[4]);
mux21x64 mx03(stage3, stage2, {stage2[55:0], eightzeros}, Shift[3]);
mux21x64 mx04(stage4, stage3, {stage3[59:0], fourzeros}, Shift[2]);
mux21x64 mx05(stage5, stage4, {stage4[61:0], twozeros}, Shift[1]);
mux21x64 mx06(Z , stage5, {stage5[62:0], onezero}, Shift[0]);
endmodule // barrel_shifter_l63
// The implementation of the barrel shifter was modified to use
// fewer gates. It is now implemented using six 57-bit 2-to-1 muxes. The
// barrel shifter takes a 57-bit input A and right shifts it by up to
// 63-bits, as specified by Shift, to produce a 57-bit output Z.
// It also computes a Sticky bit, which is set to
// one if any of the bits that were shifted out was one.
// Bits shifted into the left are filled with zeros.
// The 63 bit shift is implemented using 6 stages of shifts of 32
// 16, 8, 4, 2, and 1 bits.
module barrel_shifter_r57 (Z, Sticky, A, Shift);
input [56:0] A;
input [5:0] Shift;
output Sticky;
output [56:0] Z;
wire [56:0] stage1;
wire [56:0] stage2;
wire [56:0] stage3;
wire [56:0] stage4;
wire [56:0] stage5;
wire [62:0] sixtythreezeros = 63'h0;
wire [31:0] thirtytwozeros = 32'h0;
wire [15:0] sixteenzeros = 16'h0;
wire [ 7:0] eightzeros = 8'h0;
wire [ 3:0] fourzeros = 4'h0;
wire [ 1:0] twozeros = 2'b00;
wire onezero = 1'b0;
wire [62:0] S;
// Shift operations
mux21x57 mx01(stage1, A, {thirtytwozeros, A[56:32]}, Shift[5]);
mux21x57 mx02(stage2, stage1, {sixteenzeros, stage1[56:16]}, Shift[4]);
mux21x57 mx03(stage3, stage2, {eightzeros, stage2[56:8]}, Shift[3]);
mux21x57 mx04(stage4, stage3, {fourzeros, stage3[56:4]}, Shift[2]);
mux21x57 mx05(stage5, stage4, {twozeros, stage4[56:2]}, Shift[1]);
mux21x57 mx06(Z , stage5, {onezero, stage5[56:1]}, Shift[0]);
// Sticky bit calculation. The Sticky bit is set to one if any of the
// bits that were shifter out were one
assign S[31:0] = {32{Shift[5]}} & A[31:0];
assign S[47:32] = {16{Shift[4]}} & stage1[15:0];
assign S[55:48] = { 8{Shift[3]}} & stage2[7:0];
assign S[59:56] = { 4{Shift[2]}} & stage3[3:0];
assign S[61:60] = { 2{Shift[1]}} & stage4[1:0];
assign S[62] = Shift[0] & stage5[0];
assign Sticky = (S != sixtythreezeros);
endmodule // barrel_shifter_r57
module barrel_shifter_r64 (Z, Sticky, A, Shift);
input [63:0] A;
input [5:0] Shift;
output Sticky;
output [63:0] Z;
wire [63:0] stage1;
wire [63:0] stage2;
wire [63:0] stage3;
wire [63:0] stage4;
wire [63:0] stage5;
wire [62:0] sixtythreezeros = 63'h0;
wire [31:0] thirtytwozeros = 32'h0;
wire [15:0] sixteenzeros = 16'h0;
wire [ 7:0] eightzeros = 8'h0;
wire [ 3:0] fourzeros = 4'h0;
wire [ 1:0] twozeros = 2'b00;
wire onezero = 1'b0;
wire [62:0] S;
// Shift operations
mux21x64 mx01(stage1, A, {thirtytwozeros, A[63:32]}, Shift[5]);
mux21x64 mx02(stage2, stage1, {sixteenzeros, stage1[63:16]}, Shift[4]);
mux21x64 mx03(stage3, stage2, {eightzeros, stage2[63:8]}, Shift[3]);
mux21x64 mx04(stage4, stage3, {fourzeros, stage3[63:4]}, Shift[2]);
mux21x64 mx05(stage5, stage4, {twozeros, stage4[63:2]}, Shift[1]);
mux21x64 mx06(Z , stage5, {onezero, stage5[63:1]}, Shift[0]);
// Sticky bit calculation. The Sticky bit is set to one if any of the
// bits that were shifter out were one
assign S[31:0] = {32{Shift[5]}} & A[31:0];
assign S[47:32] = {16{Shift[4]}} & stage1[15:0];
assign S[55:48] = { 8{Shift[3]}} & stage2[7:0];
assign S[59:56] = { 4{Shift[2]}} & stage3[3:0];
assign S[61:60] = { 2{Shift[1]}} & stage4[1:0];
assign S[62] = Shift[0] & stage5[0];
assign Sticky = (S != sixtythreezeros);
endmodule // barrel_shifter_r64

3
wally-pipelined/src/hazard/hazard.sv
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@ -26,11 +26,14 @@
`include "wally-config.vh"
module hazard(
// Detect hazardsss
input logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E, RdE, RdM, RdW,
input logic PCSrcE, MemReadE,
input logic RegWriteM, RegWriteW, CSRWritePendingDEM, RetM, TrapM,
input logic InstrStall, DataStall,
// Forwaring controls
output logic [1:0] ForwardAE, ForwardBE,
// Stall outputs
output logic StallF, StallD, FlushD, FlushE, FlushM, FlushW,
output logic LoadStallD);

2
wally-pipelined/src/ieu/alu.sv
View file

@ -53,7 +53,7 @@ module alu #(parameter WIDTH=32) (
assign arith = alucontrol[3]; // sra
assign w64 = alucontrol[4];
assign right = (alucontrol[2:0] == 3'b101); // sra or srl
shifter #(WIDTH) sh(a, b[5:0], right, arith, w64, shift);
shifter sh(a, b[5:0], right, arith, w64, shift);
// OR optionally passes zero when ALUControl[3] is set, supporting lui
assign bor = alucontrol[3] ? b : a|b;

4
wally-pipelined/src/ieu/controller.sv
View file

@ -29,8 +29,8 @@
module controller(
input logic clk, reset,
// Decode stage control signals
input logic [6:0] OpD,
input logic [2:0] Funct3D,
input logic [6:0] OpD,
input logic [2:0] Funct3D,
input logic Funct7b5D,
output logic [2:0] ImmSrcD,
input logic StallD, FlushD,

6
wally-pipelined/src/ieu/extend.sv
View file

@ -26,9 +26,9 @@
`include "wally-config.vh"
module extend (
input logic [31:7] InstrD,
input logic [2:0] ImmSrcD,
output logic [`XLEN-1:0] ExtImmD);
input logic [31:7] InstrD,
input logic [2:0] ImmSrcD,
output logic [`XLEN-1:0 ] ExtImmD);
always_comb
case(ImmSrcD)

54
wally-pipelined/src/ieu/ieu.sv
View file

@ -26,32 +26,38 @@
`include "wally-config.vh"
module ieu (
input logic clk, reset,
output logic [1:0] MemRWM,
output logic [`XLEN-1:0] DataAdrM, WriteDataM,
input logic [`XLEN-1:0] ReadDataM,
input logic DataMisalignedM,
input logic DataAccessFaultM,
input logic [1:0] ForwardAE, ForwardBE,
input logic StallD, FlushD, FlushE, FlushM, FlushW,
output logic PCSrcE,
output logic RegWriteM,
output logic MemReadE,
output logic RegWriteW,
output logic CSRWriteM, PrivilegedM,
output logic CSRWritePendingDEM,
output logic [2:0] Funct3M,
output logic [`XLEN-1:0] SrcAM,
input logic clk, reset,
// Decode Stage interface
input logic [31:0] InstrD,
input logic IllegalIEUInstrFaultD,
output logic IllegalBaseInstrFaultD,
// Execute Stage interface
input logic [`XLEN-1:0] PCE,
output logic [`XLEN-1:0] PCTargetE,
input logic [31:0] InstrD,
input logic [`XLEN-1:0] PCE, PCLinkW,
// Memory stage interface
input logic [`XLEN-1:0] ReadDataM,
input logic DataMisalignedM,
input logic DataAccessFaultM,
input logic [`XLEN-1:0] CSRReadValM,
input logic IllegalIEUInstrFaultD,
output logic IllegalBaseInstrFaultD,
output logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E, RdE, RdM, RdW,
output logic InstrValidW,
input logic RetM, TrapM,
input logic LoadStallD
output logic [1:0] MemRWM,
output logic [`XLEN-1:0] DataAdrM, WriteDataM,
output logic [`XLEN-1:0] SrcAM,
output logic [2:0] Funct3M,
// Writeback stage
input logic [`XLEN-1:0] PCLinkW,
output logic InstrValidW,
// hazards
input logic StallD, FlushD, FlushE, FlushM, FlushW,
input logic LoadStallD,
input logic [1:0] ForwardAE, ForwardBE,
input logic RetM, TrapM,
output logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E, RdE, RdM, RdW,
output logic PCSrcE,
output logic MemReadE,
output logic RegWriteM,
output logic RegWriteW,
output logic CSRWriteM, PrivilegedM,
output logic CSRWritePendingDEM
);
logic [2:0] ImmSrcD;

6
wally-pipelined/src/ieu/regfile.sv
View file

@ -26,9 +26,9 @@
`include "wally-config.vh"
module regfile (
input logic clk, reset,
input logic we3,
input logic [ 4:0] a1, a2, a3,
input logic clk, reset,
input logic we3,
input logic [ 4:0] a1, a2, a3,
input logic [`XLEN-1:0] wd3,
output logic [`XLEN-1:0] rd1, rd2);

14
wally-pipelined/src/ieu/shifter.sv
View file

@ -25,11 +25,11 @@
`include "wally-config.vh"
module shifter #(parameter WIDTH=32) (
input logic [WIDTH-1:0] a,
input logic [5:0] amt,
input logic right, arith, w64,
output logic [WIDTH-1:0] y);
module shifter (
input logic [`XLEN-1:0] a,
input logic [5:0] amt,
input logic right, arith, w64,
output logic [`XLEN-1:0] y);
// The best shifter architecture differs based on `XLEN.
// for RV32, only 32-bit shifts are needed. These are
@ -38,7 +38,7 @@ module shifter #(parameter WIDTH=32) (
// extension.
generate
if (WIDTH==32) begin
if (`XLEN==32) begin
// funnel shifter (see CMOS VLSI Design 4e Section 11.8.1, note Table 11.11 shift types wrong)
logic [62:0] z, zshift;
logic [4:0] offset;
@ -55,7 +55,7 @@ module shifter #(parameter WIDTH=32) (
// funnel operation
assign zshift = z >> offset;
assign y = zshift[WIDTH-1:0];
assign y = zshift[31:0];
end else begin // RV64
// funnel shifter followed by masking
// research idea: investigate shifter designs for mixed 32/64-bit shifts

27
wally-pipelined/src/ifu/ifu.sv
View file

@ -27,19 +27,26 @@
`include "wally-config.vh"
module ifu (
input logic clk, reset,
input logic StallF, StallD, FlushD, FlushE, FlushM, FlushW,
input logic PCSrcE,
input logic [31:0] InstrF,
input logic clk, reset,
input logic StallF, StallD, FlushD, FlushE, FlushM, FlushW,
// Fetch
input logic [31:0] InstrF,
output logic [`XLEN-1:0] PCF,
// Execute
input logic PCSrcE,
input logic [`XLEN-1:0] PCTargetE,
input logic RetM, TrapM,
output logic [`XLEN-1:0] PCE,
// Mem
input logic RetM, TrapM,
input logic [`XLEN-1:0] PrivilegedNextPCM,
output logic [31:0] InstrD, InstrM,
output logic [`XLEN-1:0] PCF, PCE, PCM,
output logic [31:0] InstrD, InstrM,
output logic [`XLEN-1:0] PCM,
// Writeback
output logic [`XLEN-1:0] PCLinkW,
input logic IllegalBaseInstrFaultD,
output logic IllegalIEUInstrFaultD,
output logic InstrMisalignedFaultM,
// Faults
input logic IllegalBaseInstrFaultD,
output logic IllegalIEUInstrFaultD,
output logic InstrMisalignedFaultM,
output logic [`XLEN-1:0] InstrMisalignedAdrM
);

26
wally-pipelined/src/privileged/csr.sv
View file

@ -27,25 +27,25 @@
`include "wally-config.vh"
module csr (
input logic clk, reset,
input logic [31:0] InstrM,
input logic clk, reset,
input logic [31:0] InstrM,
input logic [`XLEN-1:0] PCM, SrcAM,
input logic CSRWriteM, TrapM, MTrapM, STrapM, UTrapM, mretM, sretM, uretM,
input logic TimerIntM, ExtIntM, SwIntM,
input logic InstrValidW, FloatRegWriteW, LoadStallD,
input logic [1:0] NextPrivilegeModeM, PrivilegeModeW,
input logic CSRWriteM, TrapM, MTrapM, STrapM, UTrapM, mretM, sretM, uretM,
input logic TimerIntM, ExtIntM, SwIntM,
input logic InstrValidW, FloatRegWriteW, LoadStallD,
input logic [1:0] NextPrivilegeModeM, PrivilegeModeW,
input logic [`XLEN-1:0] CauseM, NextFaultMtvalM,
output logic [1:0] STATUS_MPP,
output logic STATUS_SPP, STATUS_TSR,
output logic [1:0] STATUS_MPP,
output logic STATUS_SPP, STATUS_TSR,
output logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, UEPC_REGW, UTVEC_REGW, STVEC_REGW, MTVEC_REGW,
output logic [`XLEN-1:0] MEDELEG_REGW, MIDELEG_REGW, SEDELEG_REGW, SIDELEG_REGW,
output logic [11:0] MIP_REGW, MIE_REGW,
output logic STATUS_MIE, STATUS_SIE,
input logic [4:0] SetFflagsM,
output logic [2:0] FRM_REGW,
output logic [11:0] MIP_REGW, MIE_REGW,
output logic STATUS_MIE, STATUS_SIE,
input logic [4:0] SetFflagsM,
output logic [2:0] FRM_REGW,
// output logic [11:0] MIP_REGW, SIP_REGW, UIP_REGW, MIE_REGW, SIE_REGW, UIE_REGW,
output logic [`XLEN-1:0] CSRReadValM,
output logic IllegalCSRAccessM
output logic IllegalCSRAccessM
);
logic [`XLEN-1:0] CSRMReadValM, CSRSReadValM, CSRUReadValM, CSRNReadValM, CSRCReadValM;

12
wally-pipelined/src/privileged/csrc.sv
View file

@ -63,14 +63,14 @@ module csrc #(parameter
// ... more counters
HPMCOUNTER31H = 12'hC9F
) (
input logic clk, reset,
input logic InstrValidW, LoadStallD, CSRMWriteM,
input logic [11:0] CSRAdrM,
input logic [1:0] PrivilegeModeW,
input logic clk, reset,
input logic InstrValidW, LoadStallD, CSRMWriteM,
input logic [11:0] CSRAdrM,
input logic [1:0] PrivilegeModeW,
input logic [`XLEN-1:0] CSRWriteValM,
input logic [31:0] MCOUNTINHIBIT_REGW, MCOUNTEREN_REGW, SCOUNTEREN_REGW,
input logic [31:0] MCOUNTINHIBIT_REGW, MCOUNTEREN_REGW, SCOUNTEREN_REGW,
output logic [`XLEN-1:0] CSRCReadValM,
output logic IllegalCSRCAccessM
output logic IllegalCSRCAccessM
);
generate

10
wally-pipelined/src/privileged/csri.sv
View file

@ -32,12 +32,12 @@ module csri #(parameter
MIP = 12'h344,
SIE = 12'h104,
SIP = 12'h144) (
input logic clk, reset,
input logic CSRMWriteM, CSRSWriteM,
input logic [11:0] CSRAdrM,
input logic ExtIntM, TimerIntM, SwIntM,
input logic clk, reset,
input logic CSRMWriteM, CSRSWriteM,
input logic [11:0] CSRAdrM,
input logic ExtIntM, TimerIntM, SwIntM,
input logic [`XLEN-1:0] MIDELEG_REGW,
output logic [11:0] MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW,
output logic [11:0] MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW,
input logic [`XLEN-1:0] CSRWriteValM
);

14
wally-pipelined/src/privileged/csrm.sv
View file

@ -61,17 +61,17 @@ module csrm #(parameter
DPC = 12'h7B1,
DSCRATCH0 = 12'h7B2,
DSCRATCH1 = 12'h7B3) (
input logic clk, reset,
input logic CSRMWriteM, MTrapM,
input logic [11:0] CSRAdrM,
input logic clk, reset,
input logic CSRMWriteM, MTrapM,
input logic [11:0] CSRAdrM,
input logic [`XLEN-1:0] NextEPCM, NextCauseM, NextMtvalM, MSTATUS_REGW,
input logic [`XLEN-1:0] CSRWriteValM,
output logic [`XLEN-1:0] CSRMReadValM, MEPC_REGW, MTVEC_REGW,
output logic [31:0] MCOUNTEREN_REGW, MCOUNTINHIBIT_REGW,
output logic [31:0] MCOUNTEREN_REGW, MCOUNTINHIBIT_REGW,
output logic [`XLEN-1:0] MEDELEG_REGW, MIDELEG_REGW,
input logic [11:0] MIP_REGW, MIE_REGW,
output logic WriteMSTATUSM,
output logic IllegalCSRMAccessM
input logic [11:0] MIP_REGW, MIE_REGW,
output logic WriteMSTATUSM,
output logic IllegalCSRMAccessM
);
logic [`XLEN-1:0] MISA_REGW;

12
wally-pipelined/src/privileged/csrn.sv
View file

@ -35,15 +35,15 @@ module csrn #(parameter
UCAUSE = 12'h042,
UTVAL = 12'h043,
UIP = 12'h044) (
input logic clk, reset,
input logic CSRNWriteM, UTrapM,
input logic [11:0] CSRAdrM,
input logic clk, reset,
input logic CSRNWriteM, UTrapM,
input logic [11:0] CSRAdrM,
input logic [`XLEN-1:0] NextEPCM, NextCauseM, NextMtvalM, USTATUS_REGW,
input logic [`XLEN-1:0] CSRWriteValM,
output logic [`XLEN-1:0] CSRNReadValM, UEPC_REGW, UTVEC_REGW,
input logic [11:0] UIP_REGW, UIE_REGW,
output logic WriteUSTATUSM,
output logic IllegalCSRNAccessM
input logic [11:0] UIP_REGW, UIE_REGW,
output logic WriteUSTATUSM,
output logic IllegalCSRNAccessM
);
// User mode CSRs below only needed when user mode traps are supported

14
wally-pipelined/src/privileged/csrs.sv
View file

@ -40,17 +40,17 @@ module csrs #(parameter
STVAL = 12'h143,
SIP= 12'h144,
SATP = 12'h180) (
input logic clk, reset,
input logic CSRSWriteM, STrapM,
input logic [11:0] CSRAdrM,
input logic clk, reset,
input logic CSRSWriteM, STrapM,
input logic [11:0] CSRAdrM,
input logic [`XLEN-1:0] NextEPCM, NextCauseM, NextMtvalM, SSTATUS_REGW,
input logic [`XLEN-1:0] CSRWriteValM,
output logic [`XLEN-1:0] CSRSReadValM, SEPC_REGW, STVEC_REGW,
output logic [31:0] SCOUNTEREN_REGW,
output logic [31:0] SCOUNTEREN_REGW,
output logic [`XLEN-1:0] SEDELEG_REGW, SIDELEG_REGW,
input logic [11:0] SIP_REGW, SIE_REGW,
output logic WriteSSTATUSM,
output logic IllegalCSRSAccessM
input logic [11:0] SIP_REGW, SIE_REGW,
output logic WriteSSTATUSM,
output logic IllegalCSRSAccessM
);
logic [`XLEN-1:0] zero = 0;

15
wally-pipelined/src/privileged/csrsr.sv
View file

@ -27,15 +27,16 @@
`include "wally-config.vh"
module csrsr (
input logic clk, reset,
input logic WriteMSTATUSM, WriteSSTATUSM, WriteUSTATUSM, TrapM, FloatRegWriteW,
input logic [1:0] NextPrivilegeModeM, PrivilegeModeW,
input logic mretM, sretM, uretM,
input logic clk, reset,
input logic WriteMSTATUSM, WriteSSTATUSM, WriteUSTATUSM,
input logic TrapM, FloatRegWriteW,
input logic [1:0] NextPrivilegeModeM, PrivilegeModeW,
input logic mretM, sretM, uretM,
input logic [`XLEN-1:0] CSRWriteValM,
output logic [`XLEN-1:0] MSTATUS_REGW, SSTATUS_REGW, USTATUS_REGW,
output logic [1:0] STATUS_MPP,
output logic STATUS_SPP, STATUS_TSR,
output logic STATUS_MIE, STATUS_SIE
output logic [1:0] STATUS_MPP,
output logic STATUS_SPP, STATUS_TSR,
output logic STATUS_MIE, STATUS_SIE
);
logic STATUS_SD, STATUS_TW, STATUS_TVM, STATUS_MXR, STATUS_SUM, STATUS_SUM_INT, STATUS_MPRV, STATUS_MPRV_INT;

12
wally-pipelined/src/privileged/csru.sv
View file

@ -31,14 +31,14 @@ module csru #(parameter
FFLAGS = 12'h001,
FRM = 12'h002,
FCSR = 12'h003) (
input logic clk, reset,
input logic CSRUWriteM,
input logic [11:0] CSRAdrM,
input logic clk, reset,
input logic CSRUWriteM,
input logic [11:0] CSRAdrM,
input logic [`XLEN-1:0] CSRWriteValM,
output logic [`XLEN-1:0] CSRUReadValM,
input logic [4:0] SetFflagsM,
output logic [2:0] FRM_REGW,
output logic IllegalCSRUAccessM
input logic [4:0] SetFflagsM,
output logic [2:0] FRM_REGW,
output logic IllegalCSRUAccessM
);
// Floating Point CSRs in User Mode only needed if Floating Point is supported

26
wally-pipelined/src/privileged/privileged.sv
View file

@ -27,24 +27,24 @@
`include "wally-config.vh"
module privileged (
input logic clk, reset,
input logic CSRWriteM,
input logic clk, reset,
input logic CSRWriteM,
input logic [`XLEN-1:0] SrcAM,
input logic [31:0] InstrM,
input logic [31:0] InstrM,
input logic [`XLEN-1:0] PCM,
output logic [`XLEN-1:0] CSRReadValM,
output logic [`XLEN-1:0] PrivilegedNextPCM,
output logic RetM, TrapM,
input logic InstrValidW, FloatRegWriteW, LoadStallD,
input logic PrivilegedM,
input logic InstrMisalignedFaultM, InstrAccessFaultF, IllegalIEUInstrFaultD,
input logic LoadMisalignedFaultM, LoadAccessFaultM,
input logic StoreMisalignedFaultM, StoreAccessFaultM,
input logic TimerIntM, ExtIntM, SwIntM,
output logic RetM, TrapM,
input logic InstrValidW, FloatRegWriteW, LoadStallD,
input logic PrivilegedM,
input logic InstrMisalignedFaultM, InstrAccessFaultF, IllegalIEUInstrFaultD,
input logic LoadMisalignedFaultM, LoadAccessFaultM,
input logic StoreMisalignedFaultM, StoreAccessFaultM,
input logic TimerIntM, ExtIntM, SwIntM,
input logic [`XLEN-1:0] InstrMisalignedAdrM, DataAdrM,
input logic [4:0] SetFflagsM,
output logic [2:0] FRM_REGW,
input logic FlushD, FlushE, FlushM, StallD
input logic [4:0] SetFflagsM,
output logic [2:0] FRM_REGW,
input logic FlushD, FlushE, FlushM, StallD
);
logic [1:0] NextPrivilegeModeM, PrivilegeModeW;

22
wally-pipelined/src/privileged/trap.sv
View file

@ -27,19 +27,19 @@
`include "wally-config.vh"
module trap (
input logic reset,
input logic InstrMisalignedFaultM, InstrAccessFaultM, IllegalInstrFaultM,
input logic BreakpointFaultM, LoadMisalignedFaultM, StoreMisalignedFaultM,
input logic LoadAccessFaultM, StoreAccessFaultM, EcallFaultM, InstrPageFaultM,
input logic LoadPageFaultM, StorePageFaultM,
input logic mretM, sretM, uretM,
input logic [1:0] PrivilegeModeW, NextPrivilegeModeM,
input logic reset,
input logic InstrMisalignedFaultM, InstrAccessFaultM, IllegalInstrFaultM,
input logic BreakpointFaultM, LoadMisalignedFaultM, StoreMisalignedFaultM,
input logic LoadAccessFaultM, StoreAccessFaultM, EcallFaultM, InstrPageFaultM,
input logic LoadPageFaultM, StorePageFaultM,
input logic mretM, sretM, uretM,
input logic [1:0] PrivilegeModeW, NextPrivilegeModeM,
input logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, UEPC_REGW, UTVEC_REGW, STVEC_REGW, MTVEC_REGW,
input logic [11:0] MIP_REGW, MIE_REGW,
input logic STATUS_MIE, STATUS_SIE,
input logic [11:0] MIP_REGW, MIE_REGW,
input logic STATUS_MIE, STATUS_SIE,
input logic [`XLEN-1:0] InstrMisalignedAdrM, DataAdrM,
input logic [31:0] InstrM,
output logic TrapM, MTrapM, STrapM, UTrapM, RetM,
input logic [31:0] InstrM,
output logic TrapM, MTrapM, STrapM, UTrapM, RetM,
output logic [`XLEN-1:0] PrivilegedNextPCM, CauseM, NextFaultMtvalM
// output logic [11:0] MIP_REGW, SIP_REGW, UIP_REGW, MIE_REGW, SIE_REGW, UIE_REGW,
// input logic WriteMIPM, WriteSIPM, WriteUIPM, WriteMIEM, WriteSIEM, WriteUIEM

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