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Merge branch 'main' of github.com:rosethompson/cvw

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Rose Thompson 2025-05-04 11:33:38 -05:00
commit 9407bf1f89
2 changed files with 6 additions and 6 deletions
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11
bin/regression-wally
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@ -446,13 +446,12 @@ def selectTests(args, sims, coverStr):
addTests(tests_buildrootbootlockstep, lockstepsim, coverStr, configs) # lockstep with Questa and ImperasDV runs overnight addTests(tests_buildrootbootlockstep, lockstepsim, coverStr, configs) # lockstep with Questa and ImperasDV runs overnight
# only run RV64GC tests on in code coverage mode # only run RV64GC tests on in code coverage mode
if args.ccov: if args.ccov:
addTestsByDir(f"{archVerifDir}/tests/rv64/", "rv64gc", coveragesim, coverStr, configs) addTestsByDir(f"{archVerifDir}/tests/rv64/", "rv64gc", coveragesim, coverStr, configs, lockstepMode=1)
addTestsByDir(f"{archVerifDir}/tests/priv/rv64/", "rv64gc", coveragesim, coverStr, configs) # doesn't help coverage much dh 4/12/25 addTestsByDir(f"{archVerifDir}/tests/priv/rv64/", "rv64gc", coveragesim, coverStr, configs, lockstepMode=1) # doesn't help coverage much dh 4/12/25
addTestsByDir(WALLY+"/tests/coverage/", "rv64gc", coveragesim, coverStr, configs) addTestsByDir(WALLY+"/tests/coverage/", "rv64gc", coveragesim, coverStr, configs, lockstepMode=1)
# Extra tests from riscv-arch-test that should be run as part of the functional coverage suite # Extra tests from riscv-arch-test that should be run as part of the functional coverage suite
addTestsByDir(f"{WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/pmp", "rv64gc", coveragesim, coverStr, configs) addTestsByDir(f"{WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/pmp", "rv64gc", coveragesim, coverStr, configs, lockstepMode=1)
addTestsByDir(f"{WALLY}/tests/riscof/work/wally-riscv-arch-test/rv64i_m/privilege", "rv64gc", coveragesim, coverStr, configs) addTestsByDir(f"{WALLY}/tests/riscof/work/wally-riscv-arch-test/rv64i_m/privilege", "rv64gc", coveragesim, coverStr, configs, lockstepMode=1)
# addTestsByDir(f"{WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/F", "rv64gc", coveragesim, coverStr, configs) # doesn't help fdivsqrt coverage 4/3/2025
# run tests in lockstep in functional coverage mode # run tests in lockstep in functional coverage mode
if args.fcov or args.nightly: if args.fcov or args.nightly:
addTestsByDir(f"{archVerifDir}/tests/rv32/", "rv32gc", coveragesim, coverStr, configs, lockstepMode=1) addTestsByDir(f"{archVerifDir}/tests/rv32/", "rv32gc", coveragesim, coverStr, configs, lockstepMode=1)

1
tests/coverage/tlbmisc.S
View file

@ -174,6 +174,7 @@ ConcurrentICacheMissDTLBMiss:
csrc menvcfg, t5 # menvcfg.PBMTE = 0 csrc menvcfg, t5 # menvcfg.PBMTE = 0
li a0, 1 li a0, 1
ecall # switch back to supervisor mode ecall # switch back to supervisor mode
sfence.vma # synchronize TLB after changing menvcfg.PBMTE
li t0, 0x80806000 li t0, 0x80806000
jalr ra, t0 # jump to page to exercise ITLB with PBMT !=0 when ENVCFG_PMTE=0 jalr ra, t0 # jump to page to exercise ITLB with PBMT !=0 when ENVCFG_PMTE=0