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Merge pull request #731 from infinitymdm/soc

Browse source 
Bring soc branch up to date with main
This commit is contained in:
Rose Thompson 2024-04-15 18:25:57 -05:00 • committed by GitHub
commit 951559006e
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GPG key ID: B5690EEEBB952194
246 changed files with 263786 additions and 7120 deletions
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18
.gitignore vendored
View file

@ -46,7 +46,6 @@ linux/buildroot
linux/testvector-generation/boottrace.S
linux/testvector-generation/boottrace_disasm.log
sim/slack-notifier/slack-webhook-url.txt
sim/logs
fpga/generator/IP
fpga/generator/vivado.*
fpga/generator/.Xil/*
@ -61,8 +60,13 @@ examples/asm/example/example
examples/C/sum/sum
examples/C/fir/fir
examples/fp/softfloat_demo/softfloat_demo
examples/fp/softfloat_demo/softfloat_demoDP
examples/fp/softfloat_demo/softfloat_demoQP
examples/fp/softfloat_demo/softfloat_demoSP
examples/fp/fpcalc/fpcalc
examples/fp/sqrttest/sqrttest
examples/C/inline/inline
examples/C/mcmodel/mcmodel
examples/C/sum_mixed/sum_mixed
examples/asm/trap/trap
examples/asm/etc/pause
@ -89,7 +93,6 @@ synthDC/hdl
sim/power.saif
tests/fp/vectors/*.tv
synthDC/Summary.csv
sim/wkdir
tests/custom/work
tests/custom/*/*/*.list
tests/custom/*/*/*.elf
@ -112,8 +115,6 @@ tests/wally-riscv-arch-test/riscv-test-suite/rv*i_m/I/src/*.S
tests/wally-riscv-arch-test/riscv-test-suite/rv*i_m/I/Makefrag
sim/branch_BP_GSHARE10.log
sim/branch_BP_GSHARE16.log
sim/cov/
sim/covhtmlreport/
sim/imperas.log
sim/results-error/
sim/test1.rep
@ -186,3 +187,12 @@ sim/branch/*
sim/obj_dir
examples/verilog/fulladder/obj_dir
config/deriv
sim/questa/cov
sim/questa/covhtmlreport/
sim/questa/logs
sim/questa/wkdir
sim/verilator/logs
sim/verilator/wkdir
sim/vcs/logs
sim/vcs/wkdir
benchmarks/coremark/coremark_results.csv

21
Makefile
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@ -6,7 +6,7 @@ all:
make install
make riscof
make testfloat
make verify
# make verify
make coverage
make benchmarks
@ -39,8 +39,25 @@ imperasdv:
iter-elf.bash --search ${WALLY}/tests/riscof/work/wally-riscv-arch-test/rv64i_m
iter-elf.bash --search ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m
imperasdv_cov:
touch ${WALLY}/sim/seed0.txt
echo "0" > ${WALLY}/sim/seed0.txt
# /opt/riscv/ImperasDV-OpenHW/scripts/cvw/run-elf-cov.bash --verbose --seed 0 --search ${WALLY}/tests/riscof/work/wally-riscv-arch-test/rv64i_m
# /opt/riscv/ImperasDV-OpenHW/scripts/cvw/run-elf-cov.bash --elf ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/I/src/add-01.S/dut/my.elf --seed ${WALLY}/sim/seed0.txt --coverdb ${WALLY}/sim/cov/rv64gc_arch64i.ucdb --verbose
/opt/riscv/ImperasDV-OpenHW/scripts/cvw/run-elf-cov.bash --elf ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/I/src/add-01.S/dut/my.elf --seed ${WALLY}/sim/seed0.txt --coverdb riscv.ucdb --verbose
vcover report -details -html sim/riscv.ucdb
funcovreg:
#iter-elf.bash --search ${WALLY}/tests/riscof/work/wally-riscv-arch-test/rv64i_m --cover
#iter-elf.bash --search ${WALLY}/tests/riscof/work/wally-riscv-arch-test/rv64i_m/I --cover
#iter-elf.bash --search ${WALLY}/tests/riscof/work/wally-riscv-arch-test/rv64i_m/privilege --cover
#iter-elf.bash --search ${WALLY}/tests/riscof/work/wally-riscv-arch-test/rv64i_m/Q --cover
rm -f ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/*/src/*/dut/my.elf
iter-elf.bash --search ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/I --cover
vcover report -details -html sim/riscv.ucdb
coverage:
cd ${WALLY}/sim; ./regresssion-wally -coverage -fp
cd ${WALLY}/sim; ./regression-wally -coverage -fp
benchmarks:
make coremark

8
README.md
View file

@ -128,4 +128,12 @@ If you want to implement your own version of the chip, your tool and license com
Startups can expect to spend more than $1 million on CAD tools to get a chip to market. Commercial CAD tools are not realistically available to individuals without a university or company connection.
## Adding Cron Job for nightly builds
If you want to add a cronjob you can do the following:
1) `crontab -e`
2) add this code:
```
0 3 * * * BASH_ENV=~/.bashrc bash -l -c "PATH_TO_CVW/cvw/bin/wrapper_nightly_runs.sh > PATH_TO_LOG_FOLDER/cron.log"
```

2
addins/riscv-arch-test

@ -1 +1 @@
Subproject commit 8a52b016dbe1e2733cc168b9d6e5c93e39059d4d
Subproject commit 8a0cdceca9f0b91b81905eb8497f6586bf8d1c6b

3
benchmarks/coremark/Makefile
View file

@ -28,7 +28,8 @@ PORT_CFLAGS = -g -mabi=$(ABI) -march=$(ARCH) -static -falign-functions=16 \
all: $(work_dir)/coremark.bare.riscv.elf.memfile
run:
(cd ../../sim && (time vsim -c -do "do wally-batch.do rv$(XLEN)gc coremark" 2>&1 | tee $(work_dir)/coremark.sim.log))
time wsim rv$(XLEN)gc coremark 2>&1 | tee $(work_dir)/coremark.sim.log
#(cd ../../sim && (time vsim -c -do "do wally-batch.do rv$(XLEN)gc coremark" 2>&1 | tee $(work_dir)/coremark.sim.log))
$(work_dir)/coremark.bare.riscv.elf.memfile: $(work_dir)/coremark.bare.riscv
riscv64-unknown-elf-objdump -D $< > $<.elf.objdump

107
benchmarks/coremark/coremark_sweep.py Executable file
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@ -0,0 +1,107 @@
#!/usr/bin/python
##################################################
## coremark_sweep.py
## Written: Shreesh Kulkarni, kshreesh5@gmail.com
## Created: 20 March 2024
## Modified: 08 April 2024
## Purpose: Wally Coremark sweep Script for both 32 and 64 bit configs with csv file extraction.
## Documentation:
# A component of the CORE-V-WALLY configurable RISC-V project.
# https://github.com/openhwgroup/cvw
# Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
#
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
# except in compliance with the License, or, at your option, the Apache License version 2.0. You
# may obtain a copy of the License at
# https://solderpad.org/licenses/SHL-2.1/
# Unless required by applicable law or agreed to in writing, any work distributed under the
# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
# either express or implied. See the License for the specific language governing permissions
# and limitations under the License.
###########################################################################################
import os
import re
import csv
# list of architectures to run.
arch_list = [
"rv32gc_zba_zbb_zbc",
"rv32im_zicsr_zba_zbb_zbc",
"rv32gc",
"rv32imc_zicsr",
"rv32im_zicsr",
"rv32i_zicsr",
"rv64gc_zba_zbb_zbc",
"rv64im_zicsr_zba_zbb_zbc",
"rv64gc",
"rv64imc_zicsr",
"rv64im_zicsr",
"rv64i_zicsr"
]
str="32"
# Define regular expressions to match the desired fields
mt_regex = r"Elapsed MTIME: (\d+).*?Elapsed MINSTRET: (\d+).*?COREMARK/MHz Score: [\d,]+ / [\d,]+ = (\d+\.\d+).*?CPI: \d+ / \d+ = (\d+\.\d+).*?Load Stalls (\d+).*?Store Stalls (\d+).*?D-Cache Accesses (\d+).*?D-Cache Misses (\d+).*?I-Cache Accesses (\d+).*?I-Cache Misses (\d+).*?Branches (\d+).*?Branches Miss Predictions (\d+).*?BTB Misses (\d+).*?Jump and JR (\d+).*?RAS Wrong (\d+).*?Returns (\d+).*?BP Class Wrong (\d+)"
#cpi_regex = r"CPI: \d+ / \d+ = (\d+\.\d+)"
#cmhz_regex = r"COREMARK/MHz Score: [\d,]+ / [\d,]+ = (\d+\.\d+)"
# Open a CSV file to write the results
with open('coremark_results.csv', mode='w', newline='') as csvfile:
fieldnames = ['Architecture', 'MTIME','MINSTRET','CM / MHz','CPI','Load Stalls','Store Stalls','D$ Accesses',
'D$ Misses','I$ Accesses','I$ Misses','Branches','Branch Mispredicts','BTB Misses',
'Jump/JR','RAS Wrong','Returns','BP Class Pred Wrong']
writer = csv.DictWriter(csvfile, fieldnames=fieldnames)
writer.writeheader()
# Loop through each architecture and run the make commands
for arch in arch_list:
if(str in arch):
xlen_value='32'
else:
xlen_value='64'
os.system("make clean")
make_all = f"make all XLEN={xlen_value} ARCH={arch}"
os.system(make_all)
make_run = f"make run XLEN={xlen_value} ARCH={arch}"
print("Running: " + make_run)
output = os.popen(make_run).read() # Capture the output of the command
# Extract the Coremark values using regular expressions
mt_match = re.search(mt_regex, output,re.DOTALL)
#cpi_match = re.search(cpi_regex,output,re.DOTALL)
#cmhz_match = re.search(cmhz_regex,output,re.DOTALL)
#minstret_match = re.search(minstret_regex,output)
# Write the architecture and extracted values to the CSV file
mtime = mt_match.group(1)
minstret= mt_match.group(2)
cmhz= mt_match.group(3)
cpi= mt_match.group(4)
lstalls= mt_match.group(5)
swtalls= mt_match.group(6)
dacc= mt_match.group(7)
dmiss= mt_match.group(8)
iacc= mt_match.group(9)
imiss= mt_match.group(10)
br= mt_match.group(11)
brm= mt_match.group(12)
btb= mt_match.group(13)
jmp= mt_match.group(14)
ras= mt_match.group(15)
ret= mt_match.group(16)
bpc= mt_match.group(17)
#minstret = mt_instret_match.group(2)
writer.writerow({'Architecture': arch, 'MTIME': mtime,'MINSTRET':minstret,'CM / MHz':cmhz,'CPI':cpi,
'Load Stalls':lstalls,
'Store Stalls':swtalls,'D$ Accesses':dacc,'D$ Misses':dmiss,'I$ Accesses':iacc,'I$ Misses':imiss,
'Branches':br,'Branch Mispredicts':brm,'BTB Misses':btb,'Jump/JR':jmp,'RAS Wrong':ras,'Returns':ret,'BP Class Pred Wrong':bpc})

11
bin/CModelBranchAccuracy.sh
View file

@ -31,7 +31,7 @@
Directory="$1"
Files="$1/*.log"
for Pred in "bimodal" "gshare"
for Pred in "bimodal" "gshare" "local4" "local8" "local10"
do
for Size in $(seq 6 2 16)
do
@ -39,6 +39,15 @@ do
SizeString="$Size $Size 18 1"
elif [ $Pred = "bimodal" ]; then
SizeString="$Size 18 1"
elif [ $Pred = "local4" ]; then
SizeString="$Size 4 18 1"
Pred="yehpatt"
elif [ $Pred = "local8" ]; then
SizeString="$Size 8 18 1"
Pred="yehpatt"
elif [ $Pred = "local10" ]; then
SizeString="$Size 10 18 1"
Pred="yehpatt"
fi
Product=1.0

25
bin/docker.sh Normal file
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@ -0,0 +1,25 @@
# script to install docker
# based on https://docs.docker.com/engine/install/ubuntu/
# from Kunlin Han, entered by David Harris
# Add Docker's official GPG key:
sudo apt-get update
sudo apt-get install ca-certificates curl
sudo install -m 0755 -d /etc/apt/keyrings
sudo curl -fsSL https://download.docker.com/linux/ubuntu/gpg -o /etc/apt/keyrings/docker.asc
sudo chmod a+r /etc/apt/keyrings/docker.asc
# Add the repository to Apt sources:
echo \
"deb [arch=$(dpkg --print-architecture) signed-by=/etc/apt/keyrings/docker.asc] https://download.docker.com/linux/ubuntu \
$(. /etc/os-release && echo "$VERSION_CODENAME") stable" | \
sudo tee /etc/apt/sources.list.d/docker.list > /dev/null
sudo apt-get update
sudo apt-get install docker-ce docker-ce-cli containerd.io docker-buildx-plugin docker-compose-plugin
# verify
sudo docker run hello-world
# install podman
sudo apt-get -y install podman

2
sim/lint-wally → bin/lint-wally
View file

@ -21,7 +21,7 @@ if [ "$1" == "-nightly" ]; then
fi
done
else
configs=(rv32e rv64gc rv32gc rv32imc rv32i rv64i div_2_1i_rv64gc ) # add fdqh_rv64gc when working
configs=(rv32e rv64gc rv32gc rv32imc rv32i rv64i ) # add fdqh_rv64gc when working
fi
for config in ${configs[@]}; do

549
bin/nightly_build.py
View file

@ -54,6 +54,8 @@ Dependencies:
- re
- markdown
- subprocess
- argparse
- logging
Bash:
- mutt (email sender)
@ -69,6 +71,11 @@ from datetime import datetime
import re
import markdown
import subprocess
import argparse
import logging
from pathlib import Path
@ -83,21 +90,16 @@ class FolderManager:
base_dir (str): The base directory where folders will be managed and repository will be cloned.
"""
env_extract_var = 'WALLY'
print(f"The environemntal variable is {env_extract_var}")
self.base_dir = os.environ.get(env_extract_var)
print(f"The base directory is: {self.base_dir}")
self.base_parent_dir = os.path.dirname(self.base_dir)
# print(f"The new WALLY vairable is: {os.environ.get('WALLY')}")
# print(f"The Base Directory is now : {self.base_dir}")
# print(f"The Base Parent Directory is now : {self.base_parent_dir}")
# logger.info(f"Base directory: {self.base_dir}")
# logger.info(f"Parent Base directory: {self.base_parent_dir}")
def create_preliminary_folders(self, folders):
def create_folders(self, folders):
"""
Create preliminary folders if they do not exist.
These folders are:
nightly_runs/repos/
nightly_runs/results/
Args:
folders (list): A list of folder names to be created.
@ -108,31 +110,10 @@ class FolderManager:
for folder in folders:
folder_path = os.path.join(self.base_parent_dir, folder)
if not os.path.exists(folder_path):
os.makedirs(folder_path)
def create_new_folder(self, folders):
"""
Create a new folder based on the current date if it does not already exist.
Args:
folder_name (str): The base name for the new folder.
Returns:
str: The path of the newly created folder if created, None otherwise.
"""
todays_date = datetime.now().strftime("%Y-%m-%d")
return_folder_path = []
for folder in folders:
folder_path = os.path.join(self.base_parent_dir, folder, todays_date)
if not os.path.exists(folder_path):
os.makedirs(folder_path)
return_folder_path.append(folder_path)
else:
return_folder_path.append(None) # Folder already exists
return return_folder_path
# if not os.path.exists(folder_path):
# os.makedirs(folder_path)
if not os.path.exists(folder):
os.makedirs(folder)
def clone_repository(self, folder, repo_url):
"""
@ -145,24 +126,24 @@ class FolderManager:
None
"""
todays_date = datetime.now().strftime("%Y-%m-%d")
repo_folder = os.path.join(self.base_parent_dir, folder, todays_date, 'cvw')
tmp_folder = os.path.join(repo_folder, "tmp") # temprorary files will be stored in here
if not os.path.exists(repo_folder):
os.makedirs(repo_folder)
os.system(f"git clone --recurse-submodules {repo_url} {repo_folder}")
cvw = folder.joinpath("cvw")
tmp_folder = os.path.join(cvw, "tmp") # temprorary files will be stored in here
if not cvw.exists():
os.system(f"git clone --recurse-submodules {repo_url} {cvw}")
os.makedirs(tmp_folder)
# logger.info(f"Repository cloned: {repo_url}")
class TestRunner:
"""A class for making, running, and formatting test results."""
def __init__(self):
self.base_dir = os.environ.get('WALLY')
self.base_parent_dir = os.path.dirname(self.base_dir)
def __init__(self, logger, log_dir):
self.todays_date = datetime.now().strftime("%Y-%m-%d")
self.current_datetime = datetime.now()
#self.temp_dir = self.base_parent_dir
#print(f"Base Directory: {self.base_parent_dir}")
self.logger = logger
self.logger.info("Test runner object is initialized")
self.log_dir = log_dir
def copy_setup_script(self, folder):
"""
@ -171,36 +152,37 @@ class TestRunner:
The setup script will be copied from the base directory to a specific folder structure inside the base directory.
Args:
folder: the "nightly_runs/repos/"
folder: the "nightly-runs/repos/"
folder: the "nightly-runs/repos/"
Returns:
bool: True if the script is copied successfully, False otherwise.
bool: True if the script is copied successfuly, False otherwise.
"""
# Get today's date in YYYY-MM-DD format
todays_date = datetime.now().strftime("%Y-%m-%d")
self.todays_date = datetime.now().strftime("%Y-%m-%d")
# Define the source and destination paths
source_script = os.path.join(self.base_dir, "setup_host.sh")
destination_folder = os.path.join(self.base_parent_dir, folder, todays_date, 'cvw')
source_script = os.path.join(self.cvw, "setup_host.sh")
destination_folder = os.path.join(self.base_parent_dir, folder, self.todays_date, 'cvw')
# Check if the source script exists
if not os.path.exists(source_script):
print(f"Error: Source script '{source_script}' not found.")
self.logger.error(f"Error: Source script '{source_script}' not found.")
return False
# Check if the destination folder exists, create it if necessary
if not os.path.exists(destination_folder):
print(f"Error: Destination folder '{destination_folder}' not found.")
self.logger.error(f"Error: Destination folder '{destination_folder}' not found.")
return False
# Copy the script to the destination folder
try:
shutil.copy(source_script, destination_folder)
#print(f"Setup script copied to: {destination_folder}")
self.logger.info(f"Setup script copied to: {destination_folder}")
return True
except Exception as e:
print(f"Error copying setup script: {e}")
self.logger.error(f"Error copying setup script: {e}")
return False
@ -215,20 +197,47 @@ class TestRunner:
None
"""
# find the new repository made
todays_date = datetime.now().strftime("%Y-%m-%d")
wally_path = os.path.join(self.base_parent_dir, folder, todays_date, 'cvw')
cvw = folder.joinpath("cvw")
self.logger.info(f"cvw is: {cvw}")
# set the WALLY environmental variable to the new repository
os.environ["WALLY"] = wally_path
os.environ["WALLY"] = str(cvw)
self.base_dir = os.environ.get('WALLY')
self.base_parent_dir = os.path.dirname(self.base_dir)
self.temp_dir = self.base_parent_dir
self.cvw = cvw
self.sim_dir = cvw.joinpath("sim")
self.base_parent_dir = folder
self.results_dir = folder.joinpath("results")
self.logger.info(f"Tests are going to be ran from: {self.cvw}")
def change_time_dur(self, time_duriation=1):
# Prepare the command to execute the Makefile
regression_path = self.sim_dir.joinpath("regression-wally")
self.logger.info(f"Regression file path: {regression_path}")
try:
os.chdir(self.sim_dir)
except Exception as e:
self.logger.error(f"Error nagivating to the make file path. Error: {e}")
file_path = "regression-wally"
line_number = 450 # TIMEOUT_DUR = 1 day at this line in regression-wally
new_line = f" TIMEOUT_DUR = {60*time_duriation}"
with open(file_path, 'r') as file:
lines = file.readlines()
if line_number < 1 or line_number > len(lines):
self.logger.error("Error: Line number out of range.")
return False
lines[line_number - 1] = new_line + '\n'
with open(file_path, 'w') as file:
file.writelines(lines)
self.logger.info(f"Timeduration in ./regression-wally has been changed to: {time_duriation*60} seconds")
return True
# print(f"The new WALLY vairable is: {os.environ.get('WALLY')}")
# print(f"The Base Directory is now : {self.base_dir}")
# print(f"The Base Parent Directory is now : {self.base_parent_dir}")
def execute_makefile(self, target=None):
"""
Execute a Makefile with optional target.
@ -242,17 +251,18 @@ class TestRunner:
False if the tests didnt pass
"""
# Prepare the command to execute the Makefile
make_file_path = os.path.join(self.base_dir, "sim")
os.chdir(make_file_path)
output_file = os.path.join(self.base_dir, "tmp", "make_output.log")
os.chdir(self.sim_dir)
output_file = self.log_dir.joinpath(f"make-{target}-output.log")
command = ["make"]
# Add target to the command if specified
if target:
command.append(target)
#print(f"The command is: {command}")
self.logger.info(f"Command used: {command[0]} {command[1]}")
else:
self.logger.info(f"Command used: {command[0]}")
# Execute the command using subprocess and save the output into a file
with open(output_file, "w") as f:
@ -266,10 +276,10 @@ class TestRunner:
# Check the result
if result.returncode == 0:
#print(f"Makefile executed successfully{' with target ' + target if target else ''}.")
self.logger.info(f"Tests have been made with target: {target}")
return True
else:
#print("Error executing Makefile.")
self.logger.error(f"Error making the tests. Target: {target}")
return False
def run_tests(self, test_type=None, test_name=None, test_exctention=None):
@ -284,28 +294,33 @@ class TestRunner:
"""
# Prepare the function to execute the simulation
test_file_path = os.path.join(self.base_dir, "sim")
output_file = os.path.join(self.base_dir, "tmp", f"{test_name}-output.log")
os.chdir(test_file_path)
output_file = self.log_dir.joinpath(f"{test_name}-output.log")
os.chdir(self.sim_dir)
if test_exctention:
command = [test_type, test_name, test_exctention]
self.logger.info(f"Command used to run tests: {test_type} {test_name} {test_exctention}")
else:
command = [test_type, test_name]
self.logger.info(f"Command used to run tests: {test_type} {test_name}")
# Execute the command using subprocess and save the output into a file
with open(output_file, "w") as f:
formatted_datetime = self.current_datetime.strftime("%Y-%m-%d %H:%M:%S")
f.write(formatted_datetime)
f.write("\n\n")
result = subprocess.run(command, stdout=f, stderr=subprocess.STDOUT, text=True)
# Check if the command executed successfully
try:
with open(output_file, "w") as f:
formatted_datetime = self.current_datetime.strftime("%Y-%m-%d %H:%M:%S")
f.write(formatted_datetime)
f.write("\n\n")
result = subprocess.run(command, stdout=f, stderr=subprocess.STDOUT, text=True)
except Exception as e:
self.logger.error("There was an error in running the tests in the run_tests function: {e}")
# Check if the command executed successfuly
if result.returncode or result.returncode == 0:
self.logger.info(f"Test ran successfuly. Test type: {test_type}, test name: {test_name}, test extention: {test_exctention}")
return True, output_file
else:
print("Error:", result.returncode)
self.logger.error(f"Error making test. Test type: {test_type}, test name: {test_name}, test extention: {test_exctention}")
return False, output_file
@ -336,11 +351,10 @@ class TestRunner:
while index < len(lines):
# Remove ANSI escape codes
line = re.sub(r'\x1b\[[0-9;]*[mGK]', '', lines[index])
#print(line)
if "Success" in line:
passed_configs.append(line.split(':')[0].strip())
elif "passed lint" in line:
#print(line)
passed_configs.append(line.split(' ')[0].strip())
#passed_configs.append(line) # potentially use a space
elif "failed lint" in line:
@ -351,7 +365,6 @@ class TestRunner:
try:
config_name = line.split(':')[0].strip()
log_file = os.path.abspath("logs/"+config_name+".log")
#print(f"The log file saving to: {log_file} in the current working directory: {os.getcwd()}")
failed_configs.append((config_name, log_file))
except:
failed_configs.append((config_name, "Log file not found"))
@ -365,8 +378,7 @@ class TestRunner:
if len(failed_configs) != 0:
failed_configs.sort()
#print(f"The passed configs are: {passed_configs}")
#print(f"The failed configs are {failed_configs}")
self.logger.info(f"Cleaned test results. Passed configs {passed_configs}. Failed configs: {failed_configs}")
return passed_configs, failed_configs
def rewrite_to_markdown(self, test_name, passed_configs, failed_configs):
@ -383,17 +395,16 @@ class TestRunner:
# Implement markdown rewriting logic here
timestamp = datetime.now().strftime("%Y-%m-%d")
output_directory = os.path.join(self.base_parent_dir, "../../results", timestamp)
os.chdir(output_directory)
current_directory = os.getcwd()
output_file = os.path.join(current_directory, f"{test_name}.md")
#print("Current directory:", current_directory)
#print("Output File:", output_file)
# output_directory = self.base_parent_dir.joinpath("results")
os.chdir(self.results_dir)
# current_directory = os.getcwd()
output_file = os.path.join(self.results_dir, f"{test_name}.md")
with open(output_file, 'w') as md_file:
# Title
md_file.write(f"\n\n# Regression Test Results - {timestamp}\n\n")
md_file.write(f"\n\n# Regression Test Results - {self.todays_date}\n\n")
#md_file.write(f"\n\n<div class=\"regression\">\n# Regression Test Results - {timestamp}\n</div>\n\n")
# File Path
@ -412,7 +423,9 @@ class TestRunner:
for config in passed_configs:
md_file.write(f"- <span class=\"success\" style=\"color: green;\">{config}</span>\n")
def combine_markdown_files(self, passed_tests, failed_tests, test_list, total_number_failures, total_number_success, test_type="default", markdown_file=None):
self.logger.info("writing test outputs to markdown")
def combine_markdown_files(self, passed_tests, failed_tests, test_list, total_number_failures, total_number_success, test_type="default", markdown_file=None, args=None):
"""
First we want to display the server properties like:
- Server full name
@ -430,17 +443,14 @@ class TestRunner:
Returns:
None
"""
timestamp = datetime.now().strftime("%Y-%m-%d")
output_directory = os.path.join(self.base_parent_dir, "../../results", timestamp)
os.chdir(output_directory)
current_directory = os.getcwd()
output_file = os.path.join(current_directory, "results.md")
os.chdir(self.results_dir)
output_file = self.results_dir.joinpath("results.md")
with open(output_file, 'w') as md_file:
# Title
md_file.write(f"\n\n# Nightly Test Results - {timestamp}\n\n")
md_file.write(f"\n\n# Nightly Test Results - {self.todays_date}\n\n")
# Host information
try:
# Run hostname command
@ -451,6 +461,9 @@ class TestRunner:
os_info = subprocess.check_output(['uname', '-a']).strip().decode('utf-8')
md_file.write(f"\n**Operating System Information:** {os_info}")
md_file.write("\n")
md_file.write(f"\n**Command used to execute test:** python nightly_build.py --path {args.path} --repository {args.repository} --target {args.target} --send_email {args.send_email}")
md_file.write("\n")
except subprocess.CalledProcessError as e:
# Handle if the command fails
md_file.write(f"Failed to identify host and Operating System information: {str(e)}")
@ -465,13 +478,10 @@ class TestRunner:
# Failed Tests
md_file.write(f"\n\n## Failed Tests")
md_file.write(f"\nTotal failed tests: {total_number_failures}")
md_file.write(f"\n**Total failed tests: {total_number_failures}**")
for (test_item, item) in zip(test_list, failed_tests):
md_file.write(f"\n\n### {test_item[1]} test")
md_file.write(f"\n**General Information**\n")
md_file.write(f"\n* Test type: {test_item[0]}\n")
md_file.write(f"\n* Test name: {test_item[1]}\n")
md_file.write(f"\n* Test extension: {test_item[2]}\n\n")
md_file.write(f"\n**Command used:** {test_item[0]} {test_item[1]} {test_item[2]}\n\n")
md_file.write(f"**Failed Tests:**\n")
@ -488,17 +498,14 @@ class TestRunner:
md_file.write("\n")
md_file.write(f"* <span class=\"failure\" style=\"color: red;\">{config}</span> ({log_file})\n")
md_file.write("\n")
# Successfull Tests
# Successful Tests
md_file.write(f"\n\n## Successfull Tests")
md_file.write(f"\n**Total successfull tests: {total_number_success}**")
md_file.write(f"\n\n## Successful Tests")
md_file.write(f"\n**Total successful tests: {total_number_success}**")
for (test_item, item) in zip(test_list, passed_tests):
md_file.write(f"\n\n### {test_item[1]} test")
md_file.write(f"\n**General Information**\n")
md_file.write(f"\n* Test type: {test_item[0]}")
md_file.write(f"\n* Test name: {test_item[1]}")
md_file.write(f"\n* Test extension: {test_item[2]}\n\n")
md_file.write(f"\n**Successfull Tests:**\n")
md_file.write(f"\n**Command used:** {test_item[0]} {test_item[1]} {test_item[2]}\n\n")
md_file.write(f"\n**Successful Tests:**\n")
@ -514,7 +521,8 @@ class TestRunner:
md_file.write(f"* <span class=\"success\" style=\"color: green;\">{config}</span>\n")
md_file.write("\n")
self.logger.info("Combining markdown files")
def convert_to_html(self, markdown_file="results.md", html_file="results.html"):
"""
@ -528,9 +536,7 @@ class TestRunner:
None
"""
# Implement markdown to HTML conversion logic here
todays_date = self.current_datetime.strftime("%Y-%m-%d")
markdown_file_path = os.path.join(self.base_parent_dir, "../../results", todays_date)
os.chdir(markdown_file_path)
os.chdir(self.results_dir)
with open(markdown_file, 'r') as md_file:
md_content = md_file.read()
@ -539,7 +545,7 @@ class TestRunner:
with open(html_file, 'w') as html_file:
html_file.write(html_content)
self.logger.info("Converting markdown file to html file.")
def send_email(self, sender_email=None, receiver_emails=None, subject="Nightly Regression Test"):
"""
@ -557,137 +563,214 @@ class TestRunner:
# check if there are any emails
if not receiver_emails:
print("No receiver emails provided.")
self.logger.ERROR("No receiver emails provided.")
return
# grab thge html file
todays_date = self.current_datetime.strftime("%Y-%m-%d")
html_file_path = os.path.join(self.base_parent_dir, "../../results", todays_date)
os.chdir(html_file_path)
# grab the html file
os.chdir(self.results_dir)
html_file = "results.html"
with open(html_file, 'r') as html_file:
body = html_file.read()
for receiver_email in receiver_emails:
# Compose the mutt command for each receiver email
command = [
'mutt',
'-s', subject,
'-e', 'set content_type=text/html',
'-e', 'my_hdr From: James Stine <james.stine@okstate.edu>',
'--', receiver_email
]
# Open a subprocess to run the mutt command
process = subprocess.Popen(command, stdin=subprocess.PIPE)
# Write the email body to the subprocess
process.communicate(body.encode('utf-8'))
#############################################
# SETUP #
#############################################
folder_manager = FolderManager() # creates the object
# setting the path on where to clone new repositories of cvw
path = folder_manager.create_preliminary_folders(["nightly_runs/repos/", "nightly_runs/results/"])
new_folder = folder_manager.create_new_folder(["nightly_runs/repos/", "nightly_runs/results/"])
# clone the cvw repo
folder_manager.clone_repository("nightly_runs/repos/", "https://github.com/openhwgroup/cvw.git")
#############################################
# SETUP #
#############################################
test_runner = TestRunner() # creates the object
test_runner.set_env_var("nightly_runs/repos/") # ensures that the new WALLY environmental variable is set correctly
#############################################
# MAKE TESTS #
#############################################
# target = "wally-riscv-arch-test"
target = "all"
if test_runner.execute_makefile(target = target):
print(f"The {target} tests were made successfully")
#############################################
# RUN TESTS #
#############################################
test_list = [["python", "regression-wally", "-nightly"], ["bash", "lint-wally", "-nightly"], ["bash", "coverage", "--search"]]
output_log_list = [] # a list where the output markdown file lcoations will be saved to
total_number_failures = 0 # an integer where the total number failures from all of the tests will be collected
total_number_success = 0 # an integer where the total number of sucess will be collected
total_failures = []
total_success = []
for test_type, test_name, test_exctention in test_list:
print("--------------------------------------------------------------")
print(f"Test type: {test_type}")
print(f"Test name: {test_name}")
print(f"Test extenction: {test_exctention}")
check, output_location = test_runner.run_tests(test_type=test_type, test_name=test_name, test_exctention=test_exctention)
print(check)
print(output_location)
if check: # this checks if the test actually ran successfully
output_log_list.append(output_location)
# format tests to markdown
try:
passed, failed = test_runner.clean_format_output(input_file = output_location)
except:
print("There was an error cleaning the data")
print(f"The # of failures are for {test_name}: {len(failed)}")
total_number_failures+= len(failed)
total_failures.append(failed)
print(f"The # of sucesses are for {test_name}: {len(passed)}")
total_number_success += len(passed)
total_success.append(passed)
test_runner.rewrite_to_markdown(test_name, passed, failed)
print(f"The total sucesses are: {total_number_success}")
print(f"The total failures are: {total_number_failures}")
for receiver_email in receiver_emails:
# Compose the mutt command for each receiver email
command = [
'/usr/bin/mutt',
'-s', subject,
'-e', 'set content_type=text/html',
'-e', 'my_hdr From: James Stine <james.stine@okstate.edu>',
'--', receiver_email
]
try:
# Open a subprocess to run the mutt command
process = subprocess.Popen(command, stdin=subprocess.PIPE)
# Write the email body to the subprocess
process.communicate(body.encode('utf-8'))
self.logger.info("Sent email")
except expression as identifier:
self.logger.error(f"Error sending email with error: {identifier}")
except expression as identifier:
self.logger.error(f"Error sending email with error: {identifier}")
def main():
#############################################
# ARG PARSER #
#############################################
parser = argparse.ArgumentParser(description='Nightly Verification Testing for WALLY.')
parser.add_argument('--path',default = "nightly", help='specify the path for where the nightly repositories will be cloned ex: "nightly-runs')
parser.add_argument('--repository',default = "https://github.com/openhwgroup/cvw", help='specify which github repository you want to clone')
parser.add_argument('--target', default = "all", help='types of tests you can make are: all, wally-riscv-arch-test')
parser.add_argument('--send_email',default = "yes", help='do you want to send emails: "yes" or "y"')
args = parser.parse_args()
#############################################
# FORMAT TESTS #
#############################################
#############################################
# SETUP #
#############################################
# file paths for where the results and repos will be saved: repos and results can be changed to whatever
today = datetime.now().strftime("%Y-%m-%d")
cvw_path = Path.home().joinpath(args.path, today)
results_path = Path.home().joinpath(args.path, today, "results")
log_path = Path.home().joinpath(args.path, today, "logs")
log_file_path = log_path.joinpath("nightly_build.log")
# creates the object
folder_manager = FolderManager()
# Combine multiple markdown files into one file
# setting the path on where to clone new repositories of cvw
folder_manager.create_folders([cvw_path, results_path, log_path])
test_runner.combine_markdown_files(passed_tests = total_success, failed_tests = total_failures, test_list = test_list, total_number_failures = total_number_failures, total_number_success = total_number_success, test_type=target, markdown_file=None)
# clone the cvw repo
folder_manager.clone_repository(cvw_path, args.repository)
#############################################
# LOGGER #
#############################################
# Set up the logger
logger = logging.getLogger(__name__)
logger.setLevel(logging.DEBUG)
# Create a file handler
#file_handler = logging.FileHandler('../../logs/nightly_build.log')
file_handler = logging.FileHandler(log_file_path)
file_handler.setLevel(logging.DEBUG)
# Create a console handler
console_handler = logging.StreamHandler()
console_handler.setLevel(logging.INFO)
# Create a formatter and add it to the handlers
formatter = logging.Formatter('%(asctime)s - %(levelname)s - %(message)s')
file_handler.setFormatter(formatter)
console_handler.setFormatter(formatter)
# Add the handlers to the logger
logger.addHandler(file_handler)
logger.addHandler(console_handler)
logger.info(f"arg parser path: {args.path}")
logger.info(f"arg parser repository: {args.repository}")
logger.info(f"arg parser target: {args.target}")
logger.info(f"arg parser send_email: {args.send_email}")
logger.info(f"cvw path: {cvw_path}")
logger.info(f"results path: {results_path}")
logger.info(f"log folder path: {log_path}")
logger.info(f"log file path: {log_file_path}")
test_runner = TestRunner(logger, log_path) # creates the object
test_runner.set_env_var(cvw_path) # ensures that the new WALLY environmental variable is set correctly
#############################################
# WRITE MD TESTS #
#############################################
test_runner.convert_to_html()
#############################################
# TMP SETUP #
#############################################
"""
The goal of this section is to replace the TIMEOUT_DUR for regression tests.
"""
if test_runner.change_time_dur(time_duriation=1):
pass
else:
logger.error("Error occured changing the TIMEOUT duration in './regression-wally'")
#############################################
# MAKE TESTS #
#############################################
if args.target != "no":
# test_runner.execute_makefile(target = "deriv")
test_runner.execute_makefile(target = args.target)
#############################################
# RUN TESTS #
#############################################
test_list = [["python", "regression-wally", "-nightly"], ["bash", "lint-wally", "-nightly"], ["bash", "coverage", "--search"]]
output_log_list = [] # a list where the output markdown file lcoations will be saved to
total_number_failures = 0 # an integer where the total number failures from all of the tests will be collected
total_number_success = 0 # an integer where the total number of sucess will be collected
total_failures = []
total_success = []
for test_type, test_name, test_exctention in test_list:
check, output_location = test_runner.run_tests(test_type=test_type, test_name=test_name, test_exctention=test_exctention)
try:
if check: # this checks if the test actually ran successfuly
output_log_list.append(output_location)
logger.info(f"{test_name} ran successfuly. Output location: {output_location}")
# format tests to markdown
try:
passed, failed = test_runner.clean_format_output(input_file = output_location)
logger.info(f"{test_name} has been formatted to markdown")
except:
logger.ERROR(f"Error occured with formatting {test_name}")
logger.info(f"The # of failures are for {test_name}: {len(failed)}")
total_number_failures+= len(failed)
total_failures.append(failed)
logger.info(f"The # of sucesses are for {test_name}: {len(passed)}")
total_number_success += len(passed)
total_success.append(passed)
test_runner.rewrite_to_markdown(test_name, passed, failed)
except Exception as e:
logger.error("There was an error in running the tests: {e}")
logger.info(f"The total sucesses for all tests ran are: {total_number_success}")
logger.info(f"The total failures for all tests ran are: {total_number_failures}")
#############################################
# SEND EMAIL #
#############################################
sender_email = 'james.stine@okstate.edu'
receiver_emails = ['thomas.kidd@okstate.edu', 'james.stine@okstate.edu', 'harris@g.hmc.edu', 'rose.thompson10@okstate.edu']
test_runner.send_email(sender_email=sender_email, receiver_emails=receiver_emails)
#############################################
# FORMAT TESTS #
#############################################
# Combine multiple markdown files into one file
try:
test_runner.combine_markdown_files(passed_tests = total_success, failed_tests = total_failures, test_list = test_list, total_number_failures = total_number_failures, total_number_success = total_number_success, test_type=args.target, markdown_file=None, args=args)
except Exception as e:
logger.error(f"Error combining the markdown tests called from main: {e}")
#############################################
# WRITE MD TESTS #
#############################################
test_runner.convert_to_html()
#############################################
# SEND EMAIL #
#############################################
sender_email = 'james.stine@okstate.edu'
receiver_emails = ['thomas.kidd@okstate.edu', 'james.stine@okstate.edu', 'harris@g.hmc.edu', 'rose.thompson10@okstate.edu', 'sarah.harris@unlv.edu', 'nlucio@hmc.edu']
testing_emails = ['thomas.kidd@okstate.edu']
if (args.send_email == "yes" or args.send_email == "y"):
test_runner.send_email(sender_email=sender_email, receiver_emails=receiver_emails)
if (args.send_email == "test"):
test_runner.send_email(sender_email=sender_email, receiver_emails=testing_emails)
if __name__ == "__main__":
main()

84
bin/parseHPMC.py
View file

@ -34,12 +34,12 @@ import numpy as np
import argparse
RefDataBP = [('twobitCModel6', 'twobitCModel', 64, 10.0060297551637), ('twobitCModel8', 'twobitCModel', 256, 8.4320392215602), ('twobitCModel10', 'twobitCModel', 1024, 7.29493318805151),
('twobitCModel12', 'twobitCModel', 4096, 6.84739616147794), ('twobitCModel14', 'twobitCModel', 16384, 5.68432926870082), ('twobitCModel16', 'twobitCModel', 65536, 5.68432926870082),
('gshareCModel6', 'gshareCModel', 64, 11.4737703417701), ('gshareCModel8', 'gshareCModel', 256, 8.52341470761974), ('gshareCModel10', 'gshareCModel', 1024, 6.32975690693015),
('gshareCModel12', 'gshareCModel', 4096, 4.55424632377659), ('gshareCModel14', 'gshareCModel', 16384, 3.54251547725509), ('gshareCModel16', 'gshareCModel', 65536, 1.90424999467293)]
RefDataBTB = [('BTBCModel6', 'BTBCModel', 64, 1.51480272475844), ('BTBCModel8', 'BTBCModel', 256, 0.209057900418965), ('BTBCModel10', 'BTBCModel', 1024, 0.0117345454469572),
('BTBCModel12', 'BTBCModel', 4096, 0.00125540990359826), ('BTBCModel14', 'BTBCModel', 16384, 0.000732471628510962), ('BTBCModel16', 'BTBCModel', 65536, 0.000732471628510962)]
RefDataBP = [('twobitCModel6', 'twobitCModel', 64, 128, 10.0060297551637), ('twobitCModel8', 'twobitCModel', 256, 512, 8.4320392215602), ('twobitCModel10', 'twobitCModel', 1024, 2048, 7.29493318805151),
('twobitCModel12', 'twobitCModel', 4096, 8192, 6.84739616147794), ('twobitCModel14', 'twobitCModel', 16384, 32768, 5.68432926870082), ('twobitCModel16', 'twobitCModel', 65536, 131072, 5.68432926870082),
('gshareCModel6', 'gshareCModel', 64, 128, 11.4737703417701), ('gshareCModel8', 'gshareCModel', 256, 512, 8.52341470761974), ('gshareCModel10', 'gshareCModel', 1024, 2048, 6.32975690693015),
('gshareCModel12', 'gshareCModel', 4096, 8192, 4.55424632377659), ('gshareCModel14', 'gshareCModel', 16384, 32768, 3.54251547725509), ('gshareCModel16', 'gshareCModel', 65536, 131072, 1.90424999467293)]
RefDataBTB = [('BTBCModel6', 'BTBCModel', 64, 128, 1.51480272475844), ('BTBCModel8', 'BTBCModel', 256, 512, 0.209057900418965), ('BTBCModel10', 'BTBCModel', 1024, 2048, 0.0117345454469572),
('BTBCModel12', 'BTBCModel', 4096, 8192, 0.00125540990359826), ('BTBCModel14', 'BTBCModel', 16384, 32768, 0.000732471628510962), ('BTBCModel16', 'BTBCModel', 65536, 131072, 0.000732471628510962)]
def ParseBranchListFile(path):
'''Take the path to the list of Questa Sim log files containing the performance counters outputs. File
@ -120,25 +120,45 @@ def ComputeGeometricAverage(benchmarks):
benchmarks.append(('Mean', '', AllAve))
def GenerateName(predictorType, predictorParams):
if(predictorType == 'gshare' or predictorType == 'twobit' or predictorType == 'btb' or predictorType == 'class' or predictorType == 'ras'):
if(predictorType == 'gshare' or predictorType == 'twobit' or predictorType == 'btb' or predictorType == 'class' or predictorType == 'ras' or predictorType == 'global'):
return predictorType + predictorParams[0]
elif(predictorParams == 'local'):
elif(predictorType == 'local'):
return predictorType + predictorParams[0] + '_' + predictorParams[1]
else:
print(f'Error unsupported predictor type {predictorType}')
sys.exit(-1)
def GenerateDisplayName(predictorType, predictorParams):
if(predictorType == 'gshare' or predictorType == 'twobit' or predictorType == 'btb' or predictorType == 'class' or predictorType == 'ras' or predictorType == 'global'):
return predictorType
elif(predictorType == 'local'):
return predictorType + predictorParams[0]
else:
print(f'Error unsupported predictor type {predictorType}')
sys.exit(-1)
def ComputePredNumEntries(predictorType, predictorParams):
if(predictorType == 'gshare' or predictorType == 'twobit' or predictorType == 'btb' or predictorType == 'class'):
if(predictorType == 'gshare' or predictorType == 'twobit' or predictorType == 'btb' or predictorType == 'class' or predictorType == 'global'):
return 2**int(predictorParams[0])
elif(predictorType == 'ras'):
return int(predictorParams[0])
elif(predictorParams == 'local'):
elif(predictorType == 'local'):
return 2**int(predictorParams[0]) * int(predictorParams[1]) + 2**int(predictorParams[1])
else:
print(f'Error unsupported predictor type {predictorType}')
sys.exit(-1)
def ComputePredSize(predictorType, predictorParams):
if(predictorType == 'gshare' or predictorType == 'twobit' or predictorType == 'btb' or predictorType == 'class' or predictorType == 'global'):
return 2*2**int(predictorParams[0])
elif(predictorType == 'ras'):
return int(predictorParams[0])
elif(predictorType == 'local'):
return 2**int(predictorParams[0]) * int(predictorParams[1]) + 2*2**int(predictorParams[1])
else:
print(f'Error unsupported predictor type {predictorType}')
sys.exit(-1)
def BuildDataBase(predictorLogs):
# Once done with the following loop, performanceCounterList will contain the predictor type and size along with the
# raw performance counter data and the processed data on a per benchmark basis. It also includes the geometric mean.
@ -164,16 +184,16 @@ def BuildDataBase(predictorLogs):
ComputeStats(performanceCounters)
ComputeGeometricAverage(performanceCounters)
#print(performanceCounters)
performanceCounterList.append([GenerateName(predictorType, predictorParams), predictorType, performanceCounters, ComputePredNumEntries(predictorType, predictorParams)])
performanceCounterList.append([GenerateName(predictorType, predictorParams), GenerateDisplayName(predictorType, predictorParams), performanceCounters, ComputePredNumEntries(predictorType, predictorParams), ComputePredSize(predictorType, predictorParams)])
return performanceCounterList
def ReorderDataBase(performanceCounterList):
# Reorder the data so the benchmark name comes first, then the branch predictor configuration
benchmarkFirstList = []
for (predictorName, predictorPrefixName, benchmarks, entries) in performanceCounterList:
for (predictorName, predictorPrefixName, benchmarks, entries, size) in performanceCounterList:
for benchmark in benchmarks:
(nameString, opt, dataDict) = benchmark
benchmarkFirstList.append((nameString, opt, predictorName, predictorPrefixName, entries, dataDict))
benchmarkFirstList.append((nameString, opt, predictorName, predictorPrefixName, entries, size, dataDict))
return benchmarkFirstList
def ExtractSelectedData(benchmarkFirstList):
@ -181,7 +201,8 @@ def ExtractSelectedData(benchmarkFirstList):
# namestring + opt, config
benchmarkDict = { }
for benchmark in benchmarkFirstList:
(name, opt, config, prefixName, entries, dataDict) = benchmark
(name, opt, config, prefixName, entries, size, dataDict) = benchmark
#print(f'config = {config}, prefixName = {prefixName} entries = {entries}')
# use this code to distinguish speed opt and size opt.
#if opt == 'bd_speedopt_speed': NewName = name+'Sp'
#elif opt == 'bd_sizeopt_speed': NewName = name+'Sz'
@ -190,18 +211,19 @@ def ExtractSelectedData(benchmarkFirstList):
#print(NewName)
#NewName = name+'_'+opt
if NewName in benchmarkDict:
benchmarkDict[NewName].append((config, prefixName, entries, dataDict[ReportPredictorType]))
benchmarkDict[NewName].append((config, prefixName, entries, size, dataDict[ReportPredictorType]))
else:
benchmarkDict[NewName] = [(config, prefixName, entries, dataDict[ReportPredictorType])]
benchmarkDict[NewName] = [(config, prefixName, entries, size, dataDict[ReportPredictorType])]
return benchmarkDict
def ReportAsTable(benchmarkDict):
refLine = benchmarkDict['Mean']
FirstLine = []
SecondLine = []
for (name, typ, size, val) in refLine:
for Elements in refLine:
(name, typ, size, entries, val) = Elements
FirstLine.append(name)
SecondLine.append(size)
SecondLine.append(entries if not args.size else size)
sys.stdout.write('benchmark\t\t')
for name in FirstLine:
@ -216,7 +238,7 @@ def ReportAsTable(benchmarkDict):
if(args.summary):
sys.stdout.write('Mean\t\t\t')
for (name, typ, size, val) in refLine:
for (name, typ, size, entries, val) in refLine:
sys.stdout.write('%0.2f\t\t' % (val if not args.invert else 100 - val))
sys.stdout.write('\n')
@ -226,7 +248,7 @@ def ReportAsTable(benchmarkDict):
if(length < 8): sys.stdout.write('%s\t\t\t' % benchmark)
elif(length < 16): sys.stdout.write('%s\t\t' % benchmark)
else: sys.stdout.write('%s\t' % benchmark)
for (name, typ, size, val) in benchmarkDict[benchmark]:
for (name, typ, entries, size, val) in benchmarkDict[benchmark]:
sys.stdout.write('%0.2f\t\t' % (val if not args.invert else 100 -val))
sys.stdout.write('\n')
@ -234,14 +256,14 @@ def ReportAsText(benchmarkDict):
if(args.summary):
mean = benchmarkDict['Mean']
print('Mean')
for (name, typ, size, val) in mean:
sys.stdout.write('%s %s %0.2f\n' % (name, size, val if not args.invert else 100 - val))
for (name, typ, entries. size, val) in mean:
sys.stdout.write('%s %s %0.2f\n' % (name, entries if not args.size else size, val if not args.invert else 100 - val))
if(not args.summary):
for benchmark in benchmarkDict:
print(benchmark)
for (name, type, size, val) in benchmarkDict[benchmark]:
sys.stdout.write('%s %s %0.2f\n' % (name, size, val if not args.invert else 100 - val))
for (name, type, entries, size, val) in benchmarkDict[benchmark]:
sys.stdout.write('%s %s %0.2f\n' % (name, entries if not args.size else size, val if not args.invert else 100 - val))
def Inversion(lst):
return [x if not args.invert else 100 - x for x in lst]
@ -306,11 +328,11 @@ def ReportAsGraph(benchmarkDict, bar, FileName):
# branch predictors with various parameterizations
# group the parameterizations by the common typ.
sequencies = {}
for (name, typ, size, value) in benchmarkDict['Mean']:
for (name, typ, entries, size, value) in benchmarkDict['Mean']:
if not typ in sequencies:
sequencies[typ] = [(size, value)]
sequencies[typ] = [(entries if not args.size else int(size/8), value)]
else:
sequencies[typ].append((size,value))
sequencies[typ].append((entries if not args.size else int(size/8) ,value))
# then graph the common typ as a single line+scatter plot
# finally repeat for all typs of branch predictors and overlay
fig, axes = plt.subplots()
@ -327,7 +349,8 @@ def ReportAsGraph(benchmarkDict, bar, FileName):
axes.legend(loc='upper left')
axes.set_xscale("log")
axes.set_ylabel('Prediction Accuracy')
axes.set_xlabel('Entries')
Xlabel = 'Entries' if not args.size else 'Size (bytes)'
axes.set_xlabel(Xlabel)
axes.set_xticks(xdata)
axes.set_xticklabels(xdata)
axes.grid(color='b', alpha=0.5, linestyle='dashed', linewidth=0.5)
@ -368,7 +391,7 @@ def ReportAsGraph(benchmarkDict, bar, FileName):
for benchmarkName in benchmarkDict:
currBenchmark = benchmarkDict[benchmarkName]
xlabelList.append(benchmarkName)
for (name, typ, size, value) in currBenchmark:
for (name, typ, entries, size, value) in currBenchmark:
if(name not in seriesDict):
seriesDict[name] = [value]
else:
@ -381,7 +404,7 @@ def ReportAsGraph(benchmarkDict, bar, FileName):
for benchmarkName in benchmarkDict:
currBenchmark = benchmarkDict[benchmarkName]
xlabelListBig.append(benchmarkName)
for (name, typ, size, value) in currBenchmark:
for (name, typ, entries, size, value) in currBenchmark:
if(name not in seriesDictBig):
seriesDictBig[name] = [value]
else:
@ -410,6 +433,7 @@ parser.add_argument('-s', '--summary', action='store_const', help='Show only the
parser.add_argument('-b', '--bar', action='store_const', help='Plot graphs.', default=False, const=True)
parser.add_argument('-g', '--reference', action='store_const', help='Include the golden reference model from branch-predictor-simulator. Data stored statically at the top of %(prog)s. If you need to regenreate use CModelBranchAcurracy.sh', default=False, const=True)
parser.add_argument('-i', '--invert', action='store_const', help='Invert metric. Example Branch miss prediction becomes prediction accuracy. 100 - miss rate', default=False, const=True)
parser.add_argument('--size', action='store_const', help='Display x-axis as size in bits rather than number of table entries', default=False, const=True)
displayMode = parser.add_mutually_exclusive_group()
displayMode.add_argument('--text', action='store_const', help='Display in text format only.', default=False, const=True)

427
bin/regression-wally Executable file
View file

@ -0,0 +1,427 @@
#!/usr/bin/python3
##################################
#
# regression-wally
# David_Harris@Hmc.edu 25 January 2021
# Modified by Jarred Allen <jaallen@g.hmc.edu>
#
# Run a regression with multiple configurations in parallel and exit with
# non-zero status code if an error happened, as well as printing human-readable
# output.
#
##################################
import sys,os,shutil
import multiprocessing
#import os
from collections import namedtuple
from multiprocessing import Pool, TimeoutError
##################################
# Define lists of configurations and tests to run on each configuration
##################################
# The tests are a list with one element for each configuration
# The element consists of the configuration name, a list of test suites to run,
# optionally a string to pass to the simulator, and optionally a nonstandard grep string to check for success
INSTR_LIMIT = 1000000 # multiple of 100000; 4M is interesting because it gets into the kernel and enabling VM
tests = [
["rv32e", ["arch32e"]],
["rv32i", ["arch32i"]],
["rv32imc", ["arch32i", "arch32c", "arch32m", "wally32periph"]],
["rv32gc", ["arch32f", "arch32d", "arch32f_fma", "arch32d_fma", "arch32f_divsqrt", "arch32d_divsqrt",
"arch32i", "arch32priv", "arch32c", "arch32m", "arch32a", "arch32zifencei", "arch32zicond",
"arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "arch32zfh", "arch32zfh_fma",
"arch32zfh_divsqrt", "arch32zfaf", "wally32a", "wally32priv", "wally32periph",
"arch32zbkb", "arch32zbkc", "arch32zbkx", "arch32zknd", "arch32zkne", "arch32zknh"]], # "arch32zcb", "arch32zfad",
["rv64i", ["arch64i"]],
["buildroot", ["buildroot"], [f"+INSTR_LIMIT={INSTR_LIMIT}"], str(INSTR_LIMIT)+" instructions"]
]
# Separate out floating-point tests for RV64 to speed up coverage
tests64gc_nofp = [
["rv64gc", ["coverage64gc", "arch64i", "arch64priv", "arch64c", "arch64m",
"arch64zifencei", "arch64zicond", "arch64a", "wally64a", "wally64periph", "wally64priv",
"arch64zbkb", "arch64zbkc", "arch64zbkx", "arch64zknd", "arch64zkne", "arch64zknh",
"arch64zba", "arch64zbb", "arch64zbc", "arch64zbs"]] # add when working: "arch64zcb", "arch64zicboz"
]
tests64gc_fp = [
["rv64gc", ["arch64f", "arch64d", "arch64zfh",
"arch64f_fma", "arch64d_fma", "arch64zfh_fma",
"arch64f_divsqrt", "arch64d_divsqrt", "arch64zfh_divsqrt",
"arch64zfaf", "arch64zfad"]]
]
derivconfigtests = [
# memory system
["tlb2_rv32gc", ["wally32priv"]],
["tlb16_rv32gc", ["wally32priv"]],
["tlb2_rv64gc", ["wally64priv"]],
["tlb16_rv64gc", ["wally64priv"]],
["way_1_4096_512_rv32gc", ["arch32i"]],
["way_2_4096_512_rv32gc", ["arch32i"]],
["way_8_4096_512_rv32gc", ["arch32i"]],
["way_4_2048_512_rv32gc", ["arch32i"]],
["way_4_4096_256_rv32gc", ["arch32i"]],
["way_1_4096_512_rv64gc", ["arch64i"]],
["way_2_4096_512_rv64gc", ["arch64i"]],
["way_8_4096_512_rv64gc", ["arch64i"]],
["way_4_2048_512_rv64gc", ["arch64i"]],
["way_4_4096_256_rv64gc", ["arch64i"]],
["way_4_4096_1024_rv64gc", ["arch64i"]],
["ram_0_0_rv64gc", ["ahb64"]],
["ram_1_0_rv64gc", ["ahb64"]],
["ram_1_1_rv64gc", ["ahb64"]],
["ram_2_0_rv64gc", ["ahb64"]],
["ram_2_1_rv64gc", ["ahb64"]],
# RV32 cacheless designs will not work unless DTIM supports FLEN > XLEN. This support is not planned.
# ["nodcache_rv32gc", ["ahb32"]],
# ["nocache_rv32gc", ["ahb32"]],
["noicache_rv32gc", ["ahb32"]],
["noicache_rv64gc", ["ahb64"]],
["nodcache_rv64gc", ["ahb64"]],
["nocache_rv64gc", ["ahb64"]],
### add misaligned tests
# fp/int divider permutations
["div_2_1_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
["div_2_1i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
["div_2_2_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
["div_2_2i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
["div_2_4_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
["div_2_4i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
["div_4_1_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
["div_4_1i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
["div_4_2_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
["div_4_2i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
["div_4_4_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
["div_4_4i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
["div_2_1_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
["div_2_1i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
["div_2_2_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
["div_2_2i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
["div_2_4_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
["div_2_4i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
["div_4_1_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
["div_4_1i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
["div_4_2_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
["div_4_2i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
["div_4_4_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
["div_4_4i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
# fpu permutations
["f_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma"]],
["fh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32zfh", "arch32zfh_divsqrt"]],
["fdh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32d", "arch32d_divsqrt", "arch32d_fma", "arch32zfh", "arch32zfh_divsqrt"]],
["fdq_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32d", "arch32d_divsqrt", "arch32d_fma", "arch32i"]],
["fdqh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32d", "arch32d_divsqrt", "arch32d_fma", "arch32zfh", "arch32zfh_divsqrt", "arch32i"]],
["f_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma"]],
["fh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64zfh", "arch64zfh_divsqrt"]],
["fdh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64zfh", "arch64zfh_divsqrt"]],
["fdq_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64i"]],
["fdqh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64zfh", "arch64zfh_divsqrt", "arch64i", "wally64q"]],
]
bpredtests = [
["bpred_TWOBIT_6_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
["bpred_TWOBIT_8_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
["bpred_TWOBIT_10_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
["bpred_TWOBIT_12_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
["bpred_TWOBIT_14_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
["bpred_TWOBIT_16_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
["bpred_TWOBIT_6_16_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
["bpred_TWOBIT_8_16_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
["bpred_TWOBIT_10_16_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
["bpred_TWOBIT_12_16_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
["bpred_TWOBIT_14_16_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
["bpred_TWOBIT_16_16_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
["bpred_GSHARE_6_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
["bpred_GSHARE_6_16_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
["bpred_GSHARE_8_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
["bpred_GSHARE_8_16_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
["bpred_GSHARE_10_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
["bpred_GSHARE_10_16_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
["bpred_GSHARE_12_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
["bpred_GSHARE_12_16_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
["bpred_GSHARE_14_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
["bpred_GSHARE_14_16_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
["bpred_GSHARE_16_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
["bpred_GSHARE_16_16_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
# btb
["bpred_GSHARE_10_16_6_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
["bpred_GSHARE_10_16_6_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
["bpred_GSHARE_10_16_8_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
["bpred_GSHARE_10_16_8_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
["bpred_GSHARE_10_16_12_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
["bpred_GSHARE_10_16_12_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
# ras
["bpred_GSHARE_10_2_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
["bpred_GSHARE_10_2_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
["bpred_GSHARE_10_3_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
["bpred_GSHARE_10_3_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
["bpred_GSHARE_10_4_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
["bpred_GSHARE_10_4_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
["bpred_GSHARE_10_6_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
["bpred_GSHARE_10_6_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
["bpred_GSHARE_10_10_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
["bpred_GSHARE_10_10_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"]
]
##################################
# Data Types & Functions
##################################
TestCase = namedtuple("TestCase", ['name', 'variant', 'cmd', 'grepstr'])
# name: the name of this test configuration (used in printing human-readable
# output and picking logfile names)
# cmd: the command to run to test (should include the logfile as '{}', and
# the command needs to write to that file)
# grepstr: the string to grep through the log file for. The test succeeds iff
# grep finds that string in the logfile (is used by grep, so it may
# be any pattern grep accepts, see `man 1 grep` for more info).
class bcolors:
HEADER = '\033[95m'
OKBLUE = '\033[94m'
OKCYAN = '\033[96m'
OKGREEN = '\033[92m'
WARNING = '\033[93m'
FAIL = '\033[91m'
ENDC = '\033[0m'
BOLD = '\033[1m'
UNDERLINE = '\033[4m'
def addTests(tests, sim):
for test in tests:
config = test[0];
suites = test[1];
if (len(test) >= 3):
args = " --args " + " ".join(test[2])
else:
args = ""
if (len(test) >= 4):
gs = test[3]
else:
gs = "All tests ran without failures"
cmdPrefix="wsim --sim " + sim + " " + config
for t in suites:
tc = TestCase(
name=t,
variant=config,
cmd=cmdPrefix + " " + t + args,
grepstr=gs)
configs.append(tc)
def search_log_for_text(text, logfile):
"""Search through the given log file for text, returning True if it is found or False if it is not"""
grepcmd = "grep -e '%s' '%s' > /dev/null" % (text, logfile)
# print(" search_log_for_text invoking %s" % grepcmd)
return os.system(grepcmd) == 0
def run_test_case(config):
"""Run the given test case, and return 0 if the test suceeds and 1 if it fails"""
logname = WALLY + "/sim/questa/logs/"+config.variant+"_"+config.name+".log" ### *** fix hardwiring to questa log
#cmd = config.cmd + " > " + logname
if ("lint-wally" in config.cmd):
cmd = config.cmd + " | tee " + logname
else:
cmd = config.cmd + " > " + logname
os.chdir(regressionDir)
# print(" run_test_case invoking %s" % cmd)
os.system(cmd)
if search_log_for_text(config.grepstr, logname):
print(f"{bcolors.OKGREEN}%s_%s: Success{bcolors.ENDC}" % (config.variant, config.name))
return 0
else:
print(f"{bcolors.FAIL}%s_%s: Failures detected in output{bcolors.ENDC}" % (config.variant, config.name))
print(" Check %s" % logname)
return 1
##################################
# Main body
##################################
WALLY = os.environ.get('WALLY')
regressionDir = WALLY + '/sim'
os.chdir(regressionDir)
coveragesim = "questa" # Questa is required for code/functional coverage
defaultsim = "questa" # Default simulator for all other tests; change to Verilator when flow is ready
coverage = '--coverage' in sys.argv
fp = '--fp' in sys.argv
nightly = '--nightly' in sys.argv
testfloat = '--testfloat' in sys.argv
soc = '--soc' in sys.argv
if (nightly):
nightMode = "--nightly";
sims = ["questa", "verilator", "vcs"]
else:
nightMode = "";
sims = [defaultsim]
if (coverage): # only run RV64GC tests in coverage mode
coverStr = '--coverage'
else:
coverStr = ''
# Run Lint
configs = [
TestCase(
name="lints",
variant="all",
cmd="lint-wally " + nightMode,
grepstr="lints run with no errors or warnings"
)
]
if (coverage): # only run RV64GC tests on Questa in coverage mode
addTests(tests64gc_nofp, "questa")
if (fp):
addTests(tests64gc_fp, "questa")
else:
for sim in sims:
addTests(tests, sim)
addTests(tests64gc_nofp, sim)
addTests(tests64gc_fp, sim)
# run derivative configurations in nightly regression
if (nightly):
addTests(derivconfigtests, defaultsim)
# testfloat tests
if (testfloat):
configs = []
testfloatconfigs = ["fdqh_ieee_rv64gc", "fdq_ieee_rv64gc", "fdh_ieee_rv64gc", "fd_ieee_rv64gc", "fh_ieee_rv64gc", "f_ieee_rv64gc", "fdqh_ieee_rv32gc", "f_ieee_rv32gc"]
for config in testfloatconfigs:
tests = ["div", "sqrt", "add", "sub", "mul", "cvtint", "cvtfp", "fma", "cmp"]
if ("f_" in config):
tests.remove("cvtfp")
for test in tests:
tc = TestCase(
name=test,
variant=config,
cmd="wsim --tb testbench_fp " + config + " " + test,
grepstr="All Tests completed with 0 errors")
configs.append(tc)
testfloatdivconfigs = [
"fdh_ieee_div_2_1_rv32gc", "fdh_ieee_div_2_1_rv64gc", "fdh_ieee_div_2_2_rv32gc",
"fdh_ieee_div_2_2_rv64gc", "fdh_ieee_div_2_4_rv32gc", "fdh_ieee_div_2_4_rv64gc",
"fdh_ieee_div_4_1_rv32gc", "fdh_ieee_div_4_1_rv64gc", "fdh_ieee_div_4_2_rv32gc",
"fdh_ieee_div_4_2_rv64gc", "fdh_ieee_div_4_4_rv32gc", "fdh_ieee_div_4_4_rv64gc",
"fd_ieee_div_2_1_rv32gc", "fd_ieee_div_2_1_rv64gc", "fd_ieee_div_2_2_rv32gc",
"fd_ieee_div_2_2_rv64gc", "fd_ieee_div_2_4_rv32gc", "fd_ieee_div_2_4_rv64gc",
"fd_ieee_div_4_1_rv32gc", "fd_ieee_div_4_1_rv64gc", "fd_ieee_div_4_2_rv32gc",
"fd_ieee_div_4_2_rv64gc", "fd_ieee_div_4_4_rv32gc", "fd_ieee_div_4_4_rv64gc",
"fdqh_ieee_div_2_1_rv32gc", "fdqh_ieee_div_2_1_rv64gc", "fdqh_ieee_div_2_2_rv32gc",
"fdqh_ieee_div_2_2_rv64gc", "fdqh_ieee_div_2_4_rv32gc", "fdqh_ieee_div_2_4_rv64gc",
"fdqh_ieee_div_4_1_rv32gc", "fdqh_ieee_div_4_1_rv64gc", "fdqh_ieee_div_4_2_rv32gc",
"fdqh_ieee_div_4_2_rv64gc", "fdqh_ieee_div_4_4_rv32gc", "fdqh_ieee_div_4_4_rv64gc",
"fdq_ieee_div_2_1_rv32gc", "fdq_ieee_div_2_1_rv64gc", "fdq_ieee_div_2_2_rv32gc",
"fdq_ieee_div_2_2_rv64gc", "fdq_ieee_div_2_4_rv32gc", "fdq_ieee_div_2_4_rv64gc",
"fdq_ieee_div_4_1_rv32gc", "fdq_ieee_div_4_1_rv64gc", "fdq_ieee_div_4_2_rv32gc",
"fdq_ieee_div_4_2_rv64gc", "fdq_ieee_div_4_4_rv32gc", "fdq_ieee_div_4_4_rv64gc",
"fh_ieee_div_2_1_rv32gc", "fh_ieee_div_2_1_rv64gc", "fh_ieee_div_2_2_rv32gc",
"fh_ieee_div_2_2_rv64gc", "fh_ieee_div_2_4_rv32gc", "fh_ieee_div_2_4_rv64gc",
"fh_ieee_div_4_1_rv32gc", "fh_ieee_div_4_1_rv64gc", "fh_ieee_div_4_2_rv32gc",
"fh_ieee_div_4_2_rv64gc", "fh_ieee_div_4_4_rv32gc", "fh_ieee_div_4_4_rv64gc",
"f_ieee_div_2_1_rv32gc", "f_ieee_div_2_1_rv64gc", "f_ieee_div_2_2_rv32gc",
"f_ieee_div_2_2_rv64gc", "f_ieee_div_2_4_rv32gc", "f_ieee_div_2_4_rv64gc",
"f_ieee_div_4_1_rv32gc", "f_ieee_div_4_1_rv64gc", "f_ieee_div_4_2_rv32gc",
"f_ieee_div_4_2_rv64gc", "f_ieee_div_4_4_rv32gc", "f_ieee_div_4_4_rv64gc"
]
for config in testfloatdivconfigs:
# div test case
tests = ["div", "sqrt"]
if ("ieee" in config):
tests.append("cvtint")
tests.append("cvtfp")
if ("f_" in config):
tests.remove("cvtfp")
for test in tests:
tc = TestCase(
name=test,
variant=config,
cmd="wsim --tb testbench_fp --sim questa " + config + " " + test,
grepstr="All Tests completed with 0 errors")
configs.append(tc)
if (soc):
configs = []
addTests(tests64gc_nofp, defaultsim)
def main():
"""Run the tests and count the failures"""
global configs, coverage
os.chdir(regressionDir)
for d in ["questa/logs", "questa/wkdir", "verilator/logs", "verilator/wkdir", "vcs/logs", "vcs/wkdir"]:
try:
os.mkdir(d)
except:
pass
if '--makeTests' in sys.argv:
os.chdir(regressionDir)
os.system('./make-tests.sh | tee ./logs/make-tests.log')
if '--all' in sys.argv:
TIMEOUT_DUR = 30*7200 # seconds
#configs.append(getBuildrootTC(boot=True))
elif '--buildroot' in sys.argv:
TIMEOUT_DUR = 30*7200 # seconds
#configs=[getBuildrootTC(boot=True)]
elif '--coverage' in sys.argv:
TIMEOUT_DUR = 20*60 # seconds
# Presently don't run buildroot because it has a different config and can't be merged with the rv64gc coverage.
# Also it is slow to run.
# configs.append(getBuildrootTC(boot=False))
os.system('rm -f cov/*.ucdb')
elif '--nightly' in sys.argv:
TIMEOUT_DUR = 60*1440 # 1 day
#configs.append(getBuildrootTC(boot=False))
elif '--testfloat' in sys.argv:
TIMEOUT_DUR = 60*60 # seconds
elif '--soc' in sys.argv:
TIMEOUT_DUR = 10*60 # seconds
# Don't run buildroot because soc is based on rv64gc
else:
TIMEOUT_DUR = 10*60 # seconds
#configs.append(getBuildrootTC(boot=False))
# Scale the number of concurrent processes to the number of test cases, but
# max out at a limited number of concurrent processes to not overwhelm the system
with Pool(processes=min(len(configs),multiprocessing.cpu_count())) as pool:
num_fail = 0
results = {}
for config in configs:
results[config] = pool.apply_async(run_test_case,(config,))
for (config,result) in results.items():
try:
num_fail+=result.get(timeout=TIMEOUT_DUR)
except TimeoutError:
num_fail+=1
print(f"{bcolors.FAIL}%s_%s: Timeout - runtime exceeded %d seconds{bcolors.ENDC}" % (config.variant, config.name, TIMEOUT_DUR))
# Coverage report
if coverage:
os.system('make coverage')
# Count the number of failures
if num_fail:
print(f"{bcolors.FAIL}Regression failed with %s failed configurations{bcolors.ENDC}" % num_fail)
else:
print(f"{bcolors.OKGREEN}SUCCESS! All tests ran without failures{bcolors.ENDC}")
return num_fail
if __name__ == '__main__':
exit(main())

25
bin/wally-tool-chain-install.sh
View file

@ -46,9 +46,9 @@ sudo mkdir -p $RISCV
# Update and Upgrade tools (see https://itsfoss.com/apt-update-vs-upgrade/)
sudo apt update -y
sudo apt upgrade -y
sudo apt install -y git gawk make texinfo bison flex build-essential python3 libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp-dev libglib2.0-dev python3-pip pkg-config opam z3 zlib1g-dev automake autotools-dev libmpc-dev libmpfr-dev gperf libtool patchutils bc
sudo apt install -y git gawk make texinfo bison flex build-essential python3 libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp-dev libglib2.0-dev python3-pip pkg-config opam z3 zlib1g-dev automake autotools-dev libmpc-dev libmpfr-dev gperf libtool patchutils bc mutt
# Other python libraries used through the book.
sudo pip3 install sphinx sphinx_rtd_theme matplotlib scipy scikit-learn adjustText lief
sudo pip3 install sphinx sphinx_rtd_theme matplotlib scipy scikit-learn adjustText lief markdown
# needed for Ubuntu 22.04, gcc cross compiler expects python not python2 or python3.
if ! command -v python &> /dev/null
@ -60,12 +60,10 @@ fi
# gcc cross-compiler (https://github.com/riscv-collab/riscv-gnu-toolchain)
# To install GCC from source can take hours to compile.
# This configuration enables multilib to target many flavors of RISC-V.
# This book is tested with GCC 12.2 (tagged 2023.01.31), but will likely work with newer versions as well.
# Note that GCC12.2 has binutils 2.39, which has a known performance bug that causes
# objdump to run 100x slower than in previous versions, causing riscof to make versy slowly.
# However GCC12.x is needed for bit manipulation instructions. There is an open issue to fix this:
# https://github.com/riscv-collab/riscv-gnu-toolchain/issues/1188
# This book is tested with GCC 13.2.0
# Versions newer than 2023-12-20 fail to compile the RISC-V arch test with an error:
# cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/jalr-01.S:72: Error: illegal operands `la x0,5b'
# PR *** submitted to fix riscv-arch-test to be compatible with latest GCC by modifying test_macros.h for TEST_JALR_OP
cd $RISCV
git clone https://github.com/riscv/riscv-gnu-toolchain
cd riscv-gnu-toolchain
@ -99,7 +97,7 @@ make install
# Spike (https://github.com/riscv-software-src/riscv-isa-sim)
# Spike also takes a while to install and compile, but this can be done concurrently
#with the GCC installation. After the build, we need to change two Makefiles to support atomic instructions.
# with the GCC installation.
cd $RISCV
git clone https://github.com/riscv-software-src/riscv-isa-sim
mkdir -p riscv-isa-sim/build
@ -107,10 +105,7 @@ cd riscv-isa-sim/build
../configure --prefix=$RISCV
make -j ${NUM_THREADS}
make install
cd ../arch_test_target/spike/device
# dh 2/5/24: these should be obsolete
#sed -i 's/--isa=rv32ic/--isa=rv32iac/' rv32i_m/privilege/Makefile.include
#sed -i 's/--isa=rv64ic/--isa=rv64iac/' rv64i_m/privilege/Makefile.include
# Wally needs Verilator 5.021 or later.
# Verilator needs to be built from scratch to get the latest version
@ -181,8 +176,8 @@ git clone https://github.com/riscv/sail-riscv.git
cd sail-riscv
# For now, use checkout that is stable for Wally
#git checkout 72b2516d10d472ac77482fd959a9401ce3487f60 # not new enough for Zicboz?
make -j ${NUM_THREADS}
ARCH=RV32 make -j ${NUM_THREADS}
make -j ${NUM_THREADS} c_emulator/riscv_sim_RV64
ARCH=RV32 make -j ${NUM_THREADS} c_emulator/riscv_sim_RV32
sudo ln -sf $RISCV/sail-riscv/c_emulator/riscv_sim_RV64 /usr/bin/riscv_sim_RV64
sudo ln -sf $RISCV/sail-riscv/c_emulator/riscv_sim_RV32 /usr/bin/riscv_sim_RV32

17
bin/wrapper_nightly_runs.sh
View file

@ -1,15 +1,8 @@
#!/bin/bash
date
# Variables
LOG=$HOME/nightly_runs/logs/from_wrapper.log # you can store your log file where you would like
PYTHON_SCRIPT=$HOME/nightly_runs/cvw/bin/ # cvw can be anywhere you would like it. Make sure to point your variable there
SETUP_SCRIPT=$HOME/nightly_runs/cvw/ # cvw can be anywhere you would like it. Make sure to point your variable there
date > $LOG 2>&1
PYTHON_SCRIPT=$HOME/nightly-runs/cvw/bin/ # cvw can be anywhere you would like it. Make sure to point your variable there
SETUP_SCRIPT=$HOME/nightly-runs/cvw/ # cvw can be anywhere you would like it. Make sure to point your variable there
echo "Current directory"
pwd
@ -19,10 +12,10 @@ echo "Current directory"
pwd
echo "Sourcing setup_host"
source ./setup_host.sh >> $LOG 2>&1
echo "Sourcing setup_tools"
source ./setup.sh
cd $PYTHON_SCRIPT
pwd
echo "Running python file"
python nightly_build.py >> $LOG 2>&1
python nightly_build.py
echo "Finished"

70
bin/wsim Executable file
View file

@ -0,0 +1,70 @@
#!/usr/bin/python3
#
# wsim
# David_Harris@hmc.edu 5 April 2024
# Invoke a Wally simulation for a desired configuration and test suite or ELF on the specified simulator
# usage: wsim CONFIG TESTSUITE [-s/--sim SIMULATOR] [-g/--gui]
# example: wsim rv64gc arch64i
# example: wsim rv64gc tests/riscof/work/riscv-arch-test/rv64i_m/I/src/ref/ref.elf
# example: wsim rv32i arch32i -s verilator
# example: wsim fdqh_ieee_rv64gc add -t testbench_fp # run TestFloat
#
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
import argparse
import os
# Parse arguments
parser = argparse.ArgumentParser()
parser.add_argument("config", help="Configuration file")
parser.add_argument("testsuite", help="Test suite or ELF file")
parser.add_argument("--sim", "-s", help="Simulator", choices=["questa", "verilator", "vcs"], default="questa")
parser.add_argument("--tb", "-t", help="Testbench", choices=["testbench", "testbench_fp"], default="testbench")
parser.add_argument("--gui", "-g", help="Simulate with GUI", action="store_true")
parser.add_argument("--coverage", "-c", help="Code & Functional Coverage", action="store_true")
parser.add_argument("--args", "-a", help="Optional arguments passed to simulator via $value$plusargs", default="")
args = parser.parse_args()
print("Config=" + args.config + " tests=" + args.testsuite + " sim=" + args.sim + " gui=" + str(args.gui) + " args='" + args.args + "'")
# Validate arguments
if (args.gui):
if (args.sim != "questa"):
print("GUI option only supported for Questa")
exit(1)
if (args.coverage):
if (args.sim != "questa"):
print("Coverage option only available for Questa")
exit(1)
# create the output sub-directories.
WALLY = os.environ.get('WALLY')
regressionDir = WALLY + '/sim/'
for d in ["logs", "wkdir", "cov"]:
try:
os.mkdir(regressionDir+args.sim+"/"+d)
except:
pass
# Launch selected simulator
cd = "cd $WALLY/sim/" +args.sim
if (args.sim == "questa"):
if (args.tb == "testbench_fp"):
args.args = " -GTEST=" + args.testsuite + " " + args.args
# cmd = "do wally.do " + args.config + " " + args.testsuite + " " + args.tb + " " + " -GTEST=" + args.testsuite + " " + args.args
# else:
# cmd = "do wally.do " + args.config + " " + args.testsuite + " " + args.tb + " " + args.args
cmd = "do wally.do " + args.config + " " + args.testsuite + " " + args.tb + " " + args.args
if (args.coverage):
cmd += " -coverage"
if (args.gui): # launch Questa with GUI; add +acc to keep variables accessible
cmd = cd + "; vsim -do \"" + cmd + " +acc\""
else: # launch Questa in batch mode
cmd = cd + "; vsim -c -do \"" + cmd + "\""
print("Running Questa with command: " + cmd)
os.system(cmd)
elif (args.sim == "verilator"):
print("Running Verilator on %s %s", args.config, args.testsuite)
elif (args.sim == "vcs"):
print("Running VCS on %s %s", args.config, args.testsuite)

272
config/derivlist.txt
View file

@ -587,6 +587,9 @@ IEEE754 1
deriv fd_ieee_rv64gc fd_rv64gc
IEEE754 1
deriv fdh_ieee_rv64gc fdh_rv64gc
IEEE754 1
deriv fdq_ieee_rv64gc fdq_rv64gc
IEEE754 1
@ -616,6 +619,10 @@ deriv f_div_4_2_rv32gc div_4_2_rv32gc
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 0
deriv f_div_4_4_rv32gc div_4_4_rv32gc
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 0
deriv f_div_2_1_rv64gc div_2_1_rv64gc
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 0
@ -662,6 +669,10 @@ deriv fh_div_4_2_rv32gc div_4_2_rv32gc
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 1
deriv fh_div_4_4_rv32gc div_4_4_rv32gc
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 1
deriv fh_div_2_1_rv64gc div_2_1_rv64gc
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 1
@ -708,6 +719,10 @@ deriv fd_div_4_2_rv32gc div_4_2_rv32gc
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 0
deriv fd_div_4_4_rv32gc div_4_4_rv32gc
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 0
deriv fd_div_2_1_rv64gc div_2_1_rv64gc
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 0
@ -755,6 +770,10 @@ deriv fdh_div_4_2_rv32gc div_4_2_rv32gc
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 1
deriv fdh_div_4_4_rv32gc div_4_4_rv32gc
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 1
deriv fdh_div_2_1_rv64gc div_2_1_rv64gc
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 1
@ -801,6 +820,10 @@ deriv fdq_div_4_2_rv32gc div_4_2_rv32gc
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 0
deriv fdq_div_4_4_rv32gc div_4_4_rv32gc
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 0
deriv fdq_div_2_1_rv64gc div_2_1_rv64gc
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 0
@ -847,6 +870,10 @@ deriv fdqh_div_4_2_rv32gc div_4_2_rv32gc
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 1
deriv fdqh_div_4_4_rv32gc div_4_4_rv32gc
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 1
deriv fdqh_div_2_1_rv64gc div_2_1_rv64gc
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 1
@ -888,6 +915,9 @@ IEEE754 1
deriv f_ieee_div_4_2_rv32gc f_div_4_2_rv32gc
IEEE754 1
deriv f_ieee_div_4_4_rv32gc f_div_4_4_rv32gc
IEEE754 1
deriv f_ieee_div_2_1_rv64gc f_div_2_1_rv64gc
IEEE754 1
@ -922,6 +952,9 @@ IEEE754 1
deriv fh_ieee_div_4_2_rv32gc fh_div_4_2_rv32gc
IEEE754 1
deriv fh_ieee_div_4_4_rv32gc fh_div_4_4_rv32gc
IEEE754 1
deriv fh_ieee_div_2_1_rv64gc fh_div_2_1_rv64gc
IEEE754 1
@ -956,6 +989,9 @@ IEEE754 1
deriv fd_ieee_div_4_2_rv32gc fd_div_4_2_rv32gc
IEEE754 1
deriv fd_ieee_div_4_4_rv32gc fd_div_4_4_rv32gc
IEEE754 1
deriv fd_ieee_div_2_1_rv64gc fd_div_2_1_rv64gc
IEEE754 1
@ -991,6 +1027,9 @@ IEEE754 1
deriv fdh_ieee_div_4_2_rv32gc fdh_div_4_2_rv32gc
IEEE754 1
deriv fdh_ieee_div_4_4_rv32gc fdh_div_4_4_rv32gc
IEEE754 1
deriv fdh_ieee_div_2_1_rv64gc fdh_div_2_1_rv64gc
IEEE754 1
@ -1025,6 +1064,9 @@ IEEE754 1
deriv fdq_ieee_div_4_2_rv32gc fdq_div_4_2_rv32gc
IEEE754 1
deriv fdq_ieee_div_4_4_rv32gc fdq_div_4_4_rv32gc
IEEE754 1
deriv fdq_ieee_div_2_1_rv64gc fdq_div_2_1_rv64gc
IEEE754 1
@ -1060,6 +1102,9 @@ IEEE754 1
deriv fdqh_ieee_div_4_2_rv32gc fdqh_div_4_2_rv32gc
IEEE754 1
deriv fdqh_ieee_div_4_4_rv32gc fdqh_div_4_4_rv32gc
IEEE754 1
deriv fdqh_ieee_div_2_1_rv64gc fdqh_div_2_1_rv64gc
IEEE754 1
@ -1078,4 +1123,231 @@ IEEE754 1
deriv fdqh_ieee_div_4_4_rv64gc fdqh_div_4_4_rv64gc
IEEE754 1
#### DIVIDER VARIANTS WITH IDIV ON FPU
deriv f_ieee_div_2_1i_rv32gc f_ieee_div_2_1_rv32gc
IDIV_ON_FPU 1
deriv f_ieee_div_2_2i_rv32gc f_ieee_div_2_2_rv32gc
IDIV_ON_FPU 1
deriv f_ieee_div_2_4i_rv32gc f_ieee_div_2_4_rv32gc
IDIV_ON_FPU 1
deriv f_ieee_div_4_1i_rv32gc f_ieee_div_4_1_rv32gc
IDIV_ON_FPU 1
deriv f_ieee_div_4_2i_rv32gc f_ieee_div_4_2_rv32gc
IDIV_ON_FPU 1
deriv f_ieee_div_4_4i_rv32gc f_ieee_div_4_4_rv32gc
IDIV_ON_FPU 1
deriv f_ieee_div_2_1i_rv64gc f_ieee_div_2_1_rv64gc
IDIV_ON_FPU 1
deriv f_ieee_div_2_2i_rv64gc f_ieee_div_2_2_rv64gc
IDIV_ON_FPU 1
deriv f_ieee_div_2_4i_rv64gc f_ieee_div_2_4_rv64gc
IDIV_ON_FPU 1
deriv f_ieee_div_4_1i_rv64gc f_ieee_div_4_1_rv64gc
IDIV_ON_FPU 1
deriv f_ieee_div_4_2i_rv64gc f_ieee_div_4_2_rv64gc
IDIV_ON_FPU 1
deriv f_ieee_div_4_4i_rv64gc f_ieee_div_4_4_rv64gc
IDIV_ON_FPU 1
#### FH_only, RK variable
deriv fh_ieee_div_2_1i_rv32gc fh_ieee_div_2_1_rv32gc
IDIV_ON_FPU 1
deriv fh_ieee_div_2_2i_rv32gc fh_ieee_div_2_2_rv32gc
IDIV_ON_FPU 1
deriv fh_ieee_div_2_4i_rv32gc fh_ieee_div_2_4_rv32gc
IDIV_ON_FPU 1
deriv fh_ieee_div_4_1i_rv32gc fh_ieee_div_4_1_rv32gc
IDIV_ON_FPU 1
deriv fh_ieee_div_4_2i_rv32gc fh_ieee_div_4_2_rv32gc
IDIV_ON_FPU 1
deriv fh_ieee_div_4_4i_rv32gc fh_ieee_div_4_4_rv32gc
IDIV_ON_FPU 1
deriv fh_ieee_div_2_1i_rv64gc fh_ieee_div_2_1_rv64gc
IDIV_ON_FPU 1
deriv fh_ieee_div_2_2i_rv64gc fh_ieee_div_2_2_rv64gc
IDIV_ON_FPU 1
deriv fh_ieee_div_2_4i_rv64gc fh_ieee_div_2_4_rv64gc
IDIV_ON_FPU 1
deriv fh_ieee_div_4_1i_rv64gc fh_ieee_div_4_1_rv64gc
IDIV_ON_FPU 1
deriv fh_ieee_div_4_2i_rv64gc fh_ieee_div_4_2_rv64gc
IDIV_ON_FPU 1
deriv fh_ieee_div_4_4i_rv64gc fh_ieee_div_4_4_rv64gc
IDIV_ON_FPU 1
# FD only , rk variable
deriv fd_ieee_div_2_1i_rv32gc fd_ieee_div_2_1_rv32gc
IDIV_ON_FPU 1
deriv fd_ieee_div_2_2i_rv32gc fd_ieee_div_2_2_rv32gc
IDIV_ON_FPU 1
deriv fd_ieee_div_2_4i_rv32gc fd_ieee_div_2_4_rv32gc
IDIV_ON_FPU 1
deriv fd_ieee_div_4_1i_rv32gc fd_ieee_div_4_1_rv32gc
IDIV_ON_FPU 1
deriv fd_ieee_div_4_2i_rv32gc fd_ieee_div_4_2_rv32gc
IDIV_ON_FPU 1
deriv fd_ieee_div_4_4i_rv32gc fd_ieee_div_4_4_rv32gc
IDIV_ON_FPU 1
deriv fd_ieee_div_2_1i_rv64gc fd_ieee_div_2_1_rv64gc
IDIV_ON_FPU 1
deriv fd_ieee_div_2_2i_rv64gc fd_ieee_div_2_2_rv64gc
IDIV_ON_FPU 1
deriv fd_ieee_div_2_4i_rv64gc fd_ieee_div_2_4_rv64gc
IDIV_ON_FPU 1
deriv fd_ieee_div_4_1i_rv64gc fd_ieee_div_4_1_rv64gc
IDIV_ON_FPU 1
deriv fd_ieee_div_4_2i_rv64gc fd_ieee_div_4_2_rv64gc
IDIV_ON_FPU 1
deriv fd_ieee_div_4_4i_rv64gc fd_ieee_div_4_4_rv64gc
IDIV_ON_FPU 1
# FDH only , rk variable
deriv fdh_ieee_div_2_1i_rv32gc fdh_ieee_div_2_1_rv32gc
IDIV_ON_FPU 1
deriv fdh_ieee_div_2_2i_rv32gc fdh_ieee_div_2_2_rv32gc
IDIV_ON_FPU 1
deriv fdh_ieee_div_2_4i_rv32gc fdh_ieee_div_2_4_rv32gc
IDIV_ON_FPU 1
deriv fdh_ieee_div_4_1i_rv32gc fdh_ieee_div_4_1_rv32gc
IDIV_ON_FPU 1
deriv fdh_ieee_div_4_2i_rv32gc fdh_ieee_div_4_2_rv32gc
IDIV_ON_FPU 1
deriv fdh_ieee_div_4_4i_rv32gc fdh_ieee_div_4_4_rv32gc
IDIV_ON_FPU 1
deriv fdh_ieee_div_2_1i_rv64gc fdh_ieee_div_2_1_rv64gc
IDIV_ON_FPU 1
deriv fdh_ieee_div_2_2i_rv64gc fdh_ieee_div_2_2_rv64gc
IDIV_ON_FPU 1
deriv fdh_ieee_div_2_4i_rv64gc fdh_ieee_div_2_4_rv64gc
IDIV_ON_FPU 1
deriv fdh_ieee_div_4_1i_rv64gc fdh_ieee_div_4_1_rv64gc
IDIV_ON_FPU 1
deriv fdh_ieee_div_4_2i_rv64gc fdh_ieee_div_4_2_rv64gc
IDIV_ON_FPU 1
deriv fdh_ieee_div_4_4i_rv64gc fdh_ieee_div_4_4_rv64gc
IDIV_ON_FPU 1
# FDQ only , rk variable
deriv fdq_ieee_div_2_1i_rv32gc fdq_ieee_div_2_1_rv32gc
IDIV_ON_FPU 1
deriv fdq_ieee_div_2_2i_rv32gc fdq_ieee_div_2_2_rv32gc
IDIV_ON_FPU 1
deriv fdq_ieee_div_2_4i_rv32gc fdq_ieee_div_2_4_rv32gc
IDIV_ON_FPU 1
deriv fdq_ieee_div_4_1i_rv32gc fdq_ieee_div_4_1_rv32gc
IDIV_ON_FPU 1
deriv fdq_ieee_div_4_2i_rv32gc fdq_ieee_div_4_2_rv32gc
IDIV_ON_FPU 1
deriv fdq_ieee_div_4_4i_rv32gc fdq_ieee_div_4_4_rv32gc
IDIV_ON_FPU 1
deriv fdq_ieee_div_2_1i_rv64gc fdq_ieee_div_2_1_rv64gc
IDIV_ON_FPU 1
deriv fdq_ieee_div_2_2i_rv64gc fdq_ieee_div_2_2_rv64gc
IDIV_ON_FPU 1
deriv fdq_ieee_div_2_4i_rv64gc fdq_ieee_div_2_4_rv64gc
IDIV_ON_FPU 1
deriv fdq_ieee_div_4_1i_rv64gc fdq_ieee_div_4_1_rv64gc
IDIV_ON_FPU 1
deriv fdq_ieee_div_4_2i_rv64gc fdq_ieee_div_4_2_rv64gc
IDIV_ON_FPU 1
deriv fdq_ieee_div_4_4i_rv64gc fdq_ieee_div_4_4_rv64gc
IDIV_ON_FPU 1
# FDQH only , rk variable
deriv fdqh_ieee_div_2_1i_rv32gc fdqh_ieee_div_2_1_rv32gc
IDIV_ON_FPU 1
deriv fdqh_ieee_div_2_2i_rv32gc fdqh_ieee_div_2_2_rv32gc
IDIV_ON_FPU 1
deriv fdqh_ieee_div_2_4i_rv32gc fdqh_ieee_div_2_4_rv32gc
IDIV_ON_FPU 1
deriv fdqh_ieee_div_4_1i_rv32gc fdqh_ieee_div_4_1_rv32gc
IDIV_ON_FPU 1
deriv fdqh_ieee_div_4_2i_rv32gc fdqh_ieee_div_4_2_rv32gc
IDIV_ON_FPU 1
deriv fdqh_ieee_div_4_4i_rv32gc fdqh_ieee_div_4_4_rv32gc
IDIV_ON_FPU 1
deriv fdqh_ieee_div_2_1i_rv64gc fdqh_ieee_div_2_1_rv64gc
IDIV_ON_FPU 1
deriv fdqh_ieee_div_2_2i_rv64gc fdqh_ieee_div_2_2_rv64gc
IDIV_ON_FPU 1
deriv fdqh_ieee_div_2_4i_rv64gc fdqh_ieee_div_2_4_rv64gc
IDIV_ON_FPU 1
deriv fdqh_ieee_div_4_1i_rv64gc fdqh_ieee_div_4_1_rv64gc
IDIV_ON_FPU 1
deriv fdqh_ieee_div_4_2i_rv64gc fdqh_ieee_div_4_2_rv64gc
IDIV_ON_FPU 1
deriv fdqh_ieee_div_4_4i_rv64gc fdqh_ieee_div_4_4_rv64gc
IDIV_ON_FPU 1

12
config/shared/config-shared.vh
View file

@ -1,3 +1,6 @@
//max function
`define max(a,b) (((a) > (b)) ? (a) : (b))
// constants defining different privilege modes
// defined in Table 1.1 of the privileged spec
localparam M_MODE = (2'b11);
@ -107,12 +110,13 @@ localparam DURLEN = $clog2(FPDUR); // enough bi
localparam DIVBLEN = $clog2(DIVb+1); // enough bits to count number of fractional bits + 1 integer bit
// largest length in IEU/FPU
localparam CVTLEN = ((NF<XLEN) ? (XLEN) : (NF)); // max(XLEN, NF)
localparam LLEN = (($unsigned(FLEN)<$unsigned(XLEN)) ? ($unsigned(XLEN)) : ($unsigned(FLEN)));
localparam BASECVTLEN = `max(XLEN, NF); // convert length excluding Zfa fcvtmod.w.d
localparam CVTLEN = ZFA_SUPPORTED ? `max(BASECVTLEN, 32'd84) : BASECVTLEN; // fcvtmod.w.d needs at least 32+52 because a double with 52 fractional bits might be into upper bits of 32 bit word
localparam LLEN = `max($unsigned(FLEN), $unsigned(XLEN));
localparam LOGCVTLEN = $unsigned($clog2(CVTLEN+1));
localparam NORMSHIFTSZ = (((CVTLEN+NF+1)>(DIVb + 1 +NF+1) & (CVTLEN+NF+1)>(3*NF+6)) ? (CVTLEN+NF+1) : ((DIVb + 1 +NF+1) > (3*NF+6) ? (DIVb + 1 +NF+1) : (3*NF+6))); // max(CVTLEN+NF+1, DIVb + 1 + NF + 1, 3*NF+6)
localparam NORMSHIFTSZ = `max(`max((CVTLEN+NF+1), (DIVb + 1 + NF + 1)), (3*NF+6));
localparam LOGNORMSHIFTSZ = ($clog2(NORMSHIFTSZ));
localparam CORRSHIFTSZ = (NORMSHIFTSZ-2 > (DIVMINb + 1 + NF)) ? NORMSHIFTSZ-2 : (DIVMINb+1+NF); // max(NORMSHIFTSZ-2, DIVMINb + 1 + NF)
localparam CORRSHIFTSZ = `max((NORMSHIFTSZ-2), (DIVMINb + 1 + NF));
// Disable spurious Verilator warnings

8
examples/C/mcmodel/Makefile Normal file
View file

@ -0,0 +1,8 @@
all:
riscv64-unknown-elf-gcc -O3 -march=rv64gc -mcmodel=medlow mcmodel.c -o mcmodel_medlow
riscv64-unknown-elf-objdump -d mcmodel_medlow > mcmodel_medlow.objdump
riscv64-unknown-elf-gcc -O3 -march=rv64gc -mcmodel=medany mcmodel.c -o mcmodel_medany
riscv64-unknown-elf-objdump -d mcmodel_medany > mcmodel_medany.objdump
clean:
rm mcmodel_*

10
examples/C/mcmodel/mcmodel.c Normal file
View file

@ -0,0 +1,10 @@
// mcmodel.c
// Demonstrate different code generation with mcmodel = medany vs. medlow
long a;
long b[2000];
int main(void)
{
return a + b[1000];
}

15
linux/Makefile
View file

@ -1,4 +1,3 @@
RISCV := /opt/riscv
#BUILDROOT := ${RISCV}/buildroot-test
BUILDROOT := buildroot
IMAGES := ${BUILDROOT}/output/images
@ -32,6 +31,8 @@ OBJDUMPS := $(foreach name, $(OBJDUMPS), $(DIS)/$(name).objdump)
all: clean download Image disassemble install
all_nosudo: clean download Image disassemble install_nosudo
Image:
bash -c "unset LD_LIBRARY_PATH; make -C $(BUILDROOT) --jobs;"
$(MAKE) generate
@ -40,6 +41,18 @@ install:
sudo rm -rf $(RISCV)/$(BUILDROOT)
sudo mv $(BUILDROOT) $(RISCV)/$(BUILDROOT)
install_nosudo:
rm -rf $(RISCV)/$(BUILDROOT)
mv $(BUILDROOT) $(RISCV)/$(BUILDROOT)
dumptvs:
sudo mkdir -p $(RISCV)/linux-testvectors
cd testvector-generation; sudo ./genInitMem.sh
dumptvs_nosudo:
mkdir -p $(RISCV)/linux-testvectors
cd testvector-generation; ./genInitMem.sh
# Temp rule for debugging
test:
echo $(shell find $(BUILDROOT)/output/build -maxdepth 2 -type d -regex ".*/linux-[0-9]+\.[0-9]+\.[0-9]+$$")

4
linux/sdcard/flash-sd.sh
View file

@ -74,9 +74,9 @@ fi
# Prefix partition with "p" for non-SCSI disks (mmcblk, nvme)
if [[ $SDCARD == "/dev/sd"* ]]; then
$PART_PREFIX=""
PART_PREFIX=""
else
$PART_PREFIX="p"
PART_PREFIX="p"
fi
# If no images directory, images have not been built

36
setup.csh
View file

@ -5,48 +5,20 @@
echo "Executing Wally setup.csh"
# Path to Wally repository
setenv WALLY $PWD
echo '$WALLY set to ' ${WALLY}
# Extend alias which makes extending PATH much easier.
alias extend 'if (-d \!:2) if ("$\!:1" \!~ *"\!:2"*) setenv \!:1 ${\!:1}:\!:2;echo Added \!:2 to \!:1'
alias prepend 'if (-d \!:2) if ("$\!:1" \!~ *"\!:2"*) setenv \!:1 "\!:2":${\!:1};echo Added \!:2 to \!:1'
# License servers and commercial CAD tool paths
# Must edit these based on your local environment. Ask your sysadmin.
setenv MGLS_LICENSE_FILE 27002@zircon.eng.hmc.edu # Change this to your Siemens license server
setenv SNPSLMD_LICENSE_FILE 27020@zircon.eng.hmc.edu # Change this to your Synopsys license server
setenv QUESTAPATH /cad/mentor/questa_sim-2022.4_2/questasim/bin # Change this for your path to Questa
setenv SNPSPATH /cad/synopsys/SYN/bin # Change this for your path to Design Compiler
# Path to RISC-V Tools
setenv RISCV /opt/riscv # change this if you installed the tools in a different location
# Tools
# Questa and Synopsys
extend PATH $QUESTAPATH
extend PATH $SNPSPATH
# GCC
prepend LD_LIBRARY_PATH $RISCV/riscv-gnu-toolchain/lib
prepend LD_LIBRARY_PATH $RISCV/riscv-gnu-toolchain/riscv64-unknown-elf/lib
extend PATH $RISCV/riscv-gnu-toolchain/bin # GCC tools
extend PATH $RISCV/riscv-gnu-toolchain/riscv64-unknown-elf/bin # GCC tools
# Spike
extend LD_LIBRARY_PATH $RISCV/lib
extend PATH $RISCV/bin
# Path to Wally repository
setenv WALLY $PWD
echo '$WALLY set to ' ${WALLY}
# utility functions in Wally repository
extend PATH $WALLY/bin
# Verilator
extend PATH /usr/local/bin/verilator # Change this for your path to Verilator
# ModelSim/Questa (vsim)
# Note: 2022.1 complains on cache/sram1p1r1w about StoredData cannot be driven by multiple always_ff blocks. Ues 2021.2 for now
# Imperas; put this in if you are using it
#set path = ($RISCV/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64 $path)
#setenv LD_LIBRARY_PATH $RISCV/imperas_riscv_tests/riscv-ovpsim-plus/bin/Linux64:$LD_LIBRARY_PATH # remove if no imperas
# Verilator needs a larger stack to simulate CORE-V Wally
limit stacksize unlimited
source $RISCV/site-setup.csh
echo "setup done"

59
setup.sh Executable file → Normal file
View file

@ -2,58 +2,35 @@
# setup.sh
# David_Harris@hmc.edu and kekim@hmc.edu 1 December 2021
# Set up tools for rvw
# Set up tools for cvw
# optionally have .bashrc or .bash_profile source this file with
#if [ -f ~/cvw/setup.sh ]; then
# source ~/cvw/setup.sh
#fi
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
echo "Executing Wally setup.sh"
# Path to RISC-V Tools
export RISCV=/opt/riscv # change this if you installed the tools in a different location
# Path to Wally repository
WALLY=$(dirname ${BASH_SOURCE[0]:-$0})
export WALLY=$(cd "$WALLY" && pwd)
echo \$WALLY set to ${WALLY}
# License servers and commercial CAD tool paths
# Must edit these based on your local environment. Ask your sysadmin.
export MGLS_LICENSE_FILE=27002@zircon.eng.hmc.edu # Change this to your Siemens license server
export SNPSLMD_LICENSE_FILE=27020@zircon.eng.hmc.edu # Change this to your Synopsys license server
export QUESTA_HOME=/cad/mentor/questa_sim-2023.4/questasim # Change this for your path to Questa, excluding bin
export SNPS_HOME=/cad/synopsys/SYN # Change this for your path to Design Compiler, excluding bin
# Path to RISC-V Tools
export RISCV=/opt/riscv # change this if you installed the tools in a different location
# Tools
# Questa and Synopsys
export PATH=$QUESTA_HOME/bin:$SNPS_HOME/bin:$PATH
# GCC
export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$RISCV/riscv-gnu-toolchain/lib:$RISCV/riscv-gnu-toolchain/riscv64-unknown-elf/lib
export PATH=$PATH:$RISCV/riscv-gnu-toolchain/bin:$RISCV/riscv-gnu-toolchain/riscv64-unknown-elf/bin # GCC tools
# Spike
export LD_LIBRARY_PATH=$RISCV/lib:$LD_LIBRARY_PATH
export PATH=$PATH:$RISCV/bin
# utility functions in Wally repository
export PATH=$WALLY/bin:$PATH
# Verilator
export PATH=/usr/local/bin/verilator:$PATH # Change this for your path to Verilator
# ModelSim/Questa (vsim)
# Note: 2022.1 complains on cache/sram1p1r1w about StoredData cannot be driven by multiple always_ff blocks. Ues 2021.2 for now
# Imperas; put this in if you are using it
#export PATH=$RISCV/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64:$PATH
#export LD_LIBRARY_PATH=$RISCV/imperas_riscv_tests/riscv-ovpsim-plus/bin/Linux64:$LD_LIBRARY_PATH # remove if no imperas
export IDV=$RISCV/ImperasDV-OpenHW
if [ -e "$IDV" ]; then
# echo "Imperas exists"
export IMPERAS_HOME=$IDV/Imperas
export IMPERAS_PERSONALITY=CPUMAN_DV_ASYNC
export ROOTDIR=~/
source ${IMPERAS_HOME}/bin/setup.sh
setupImperas ${IMPERAS_HOME}
export PATH=$IDV/scripts/cvw:$PATH
fi
# Verilator needs a larger stack to simulate CORE-V Wally
ulimit -s 100000
echo "setup done"
# load site licenses and tool locations
if [ -f ${RISCV}/site-setup.sh ]; then
source ${RISCV}/site-setup.sh
else
source ${WALLY}/site-setup.sh
fi
echo "setup done"

2
sim/Makefile
View file

@ -1,5 +1,5 @@
all: riscoftests memfiles coveragetests deriv benchmarks
all: riscoftests memfiles coveragetests deriv
# *** Build old tests/imperas-riscv-tests for now;
# Delete this part when the privileged tests transition over to tests/wally-riscv-arch-test
# DH: 2/27/22 temporarily commented out imperas-riscv-tests because license expired

12
sim/bp-results/branch-list-gshare-local8.txt Normal file
View file

@ -0,0 +1,12 @@
../logs/rv32gc_gshare6.log gshare 6
../logs/rv32gc_gshare8.log gshare 8
../logs/rv32gc_gshare10.log gshare 10
../logs/rv32gc_gshare12.log gshare 12
../logs/rv32gc_gshare14.log gshare 14
../logs/rv32gc_gshare16.log gshare 16
../logs/rv32gc_8local_basic6.log local 8 6
../logs/rv32gc_8local_basic8.log local 8 8
../logs/rv32gc_8local_basic10.log local 8 10
../logs/rv32gc_8local_basic12.log local 8 12
../logs/rv32gc_8local_basic14.log local 8 14
../logs/rv32gc_8local_basic16.log local 8 16

48
sim/bp-results/branch-list.txt
View file

@ -1,12 +1,36 @@
../logs/bpred_GSHARE_6_16_10_0_rv32gc_embench.log gshare 6
../logs/bpred_GSHARE_8_16_10_0_rv32gc_embench.log gshare 8
../logs/bpred_GSHARE_10_16_10_0_rv32gc_embench.log gshare 10
../logs/bpred_GSHARE_12_16_10_0_rv32gc_embench.log gshare 12
../logs/bpred_GSHARE_14_16_10_0_rv32gc_embench.log gshare 14
../logs/bpred_GSHARE_16_16_10_0_rv32gc_embench.log gshare 16
../logs/bpred_TWOBIT_6_16_10_0_rv32gc_embench.log twobit 6
../logs/bpred_TWOBIT_8_16_10_0_rv32gc_embench.log twobit 8
../logs/bpred_TWOBIT_10_16_10_0_rv32gc_embench.log twobit 10
../logs/bpred_TWOBIT_12_16_10_0_rv32gc_embench.log twobit 12
../logs/bpred_TWOBIT_14_16_10_0_rv32gc_embench.log twobit 14
../logs/bpred_TWOBIT_16_16_10_0_rv32gc_embench.log twobit 16
../logs/rv32gc_gshare6.log gshare 6
../logs/rv32gc_gshare8.log gshare 8
../logs/rv32gc_gshare10.log gshare 10
../logs/rv32gc_gshare12.log gshare 12
../logs/rv32gc_gshare14.log gshare 14
../logs/rv32gc_gshare16.log gshare 16
../logs/rv32gc_twobit6.log twobit 6
../logs/rv32gc_twobit8.log twobit 8
../logs/rv32gc_twobit10.log twobit 10
../logs/rv32gc_twobit12.log twobit 12
../logs/rv32gc_twobit14.log twobit 14
../logs/rv32gc_twobit16.log twobit 16
../logs/rv32gc_global6.log global 6
../logs/rv32gc_global8.log global 8
../logs/rv32gc_global10.log global 10
../logs/rv32gc_global12.log global 12
../logs/rv32gc_global14.log global 14
../logs/rv32gc_global16.log global 16
../logs/rv32gc_10local_basic6.log local 10 6
../logs/rv32gc_10local_basic8.log local 10 8
../logs/rv32gc_10local_basic10.log local 10 10
../logs/rv32gc_10local_basic12.log local 10 12
../logs/rv32gc_10local_basic14.log local 10 14
../logs/rv32gc_10local_basic16.log local 10 16
../logs/rv32gc_4local_basic6.log local 4 6
../logs/rv32gc_4local_basic8.log local 4 8
../logs/rv32gc_4local_basic10.log local 4 10
../logs/rv32gc_4local_basic12.log local 4 12
../logs/rv32gc_4local_basic14.log local 4 14
../logs/rv32gc_4local_basic16.log local 4 16
../logs/rv32gc_8local_basic6.log local 8 6
../logs/rv32gc_8local_basic8.log local 8 8
../logs/rv32gc_8local_basic10.log local 8 10
../logs/rv32gc_8local_basic12.log local 8 12
../logs/rv32gc_8local_basic14.log local 8 14
../logs/rv32gc_8local_basic16.log local 8 16

357
sim/linux-wave.do
View file

@ -1,357 +0,0 @@
onerror {resume}
quietly virtual function -install /testbench/dut/core/lsu -env /testbench/dut/core/lsu/bus { &{/testbench/dut/core/lsu/LSUHTRANS[1], /testbench/dut/core/lsu/LSUHADDR }} test
quietly WaveActivateNextPane {} 0
add wave -noupdate /testbench/clk
add wave -noupdate /testbench/reset
add wave -noupdate /testbench/dut/core/priv/priv/SATP_REGW
add wave -noupdate -group Testbench /testbench/reset_ext
add wave -noupdate -group Testbench -radix unsigned /testbench/InstrCountW
add wave -noupdate -group Testbench -radix unsigned /testbench/AttemptedInstructionCount
add wave -noupdate -group Testbench -radix decimal /testbench/interruptInstrCount
add wave -noupdate -group Testbench /testbench/interruptCauseVal
add wave -noupdate -group Testbench /testbench/interruptEpcVal
add wave -noupdate -group Testbench /testbench/interruptTVal
add wave -noupdate -group Testbench /testbench/interruptDesc
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/RetM
add wave -noupdate -expand -group HDU -expand -group hazards -color Pink /testbench/dut/core/hzu/TrapM
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/priv/priv/InterruptM
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/LoadStallD
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/LSUStallM
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/DivBusyE
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/ExceptionM
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM
add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushD
add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushE
add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushM
add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushW
add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallF
add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallD
add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallE
add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallM
add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallW
add wave -noupdate -group {instruction pipeline} /testbench/InstrFName
add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrD
add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrE
add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrM
add wave -noupdate -group {Decode Stage} /testbench/dut/core/ifu/PCD
add wave -noupdate -group {Decode Stage} /testbench/dut/core/ifu/InstrD
add wave -noupdate -group {Decode Stage} /testbench/InstrDName
add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/c/InstrValidD
add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/c/RegWriteD
add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/RdD
add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs1D
add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs2D
add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/PCE
add wave -noupdate -group {Execution Stage} /testbench/ExpectedPCE
add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/InstrE
add wave -noupdate -group {Execution Stage} /testbench/InstrEName
add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/c/InstrValidE
add wave -noupdate -group {Execution Stage} /testbench/textE
add wave -noupdate -group {Execution Stage} -color {Cornflower Blue} /testbench/FunctionName/FunctionName
add wave -noupdate -expand -group {Memory Stage} /testbench/checkInstrM
add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/PCM
add wave -noupdate -expand -group {Memory Stage} /testbench/ExpectedPCM
add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrM
add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName
add wave -noupdate -expand -group {Memory Stage} /testbench/textM
add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/lsu/IEUAdrM
add wave -noupdate -group {WriteBack stage} /testbench/checkInstrW
add wave -noupdate -group {WriteBack stage} /testbench/InstrValidW
add wave -noupdate -group {WriteBack stage} /testbench/PCW
add wave -noupdate -group {WriteBack stage} /testbench/ExpectedPCW
add wave -noupdate -group {WriteBack stage} /testbench/InstrW
add wave -noupdate -group {WriteBack stage} /testbench/InstrWName
add wave -noupdate -group {WriteBack stage} /testbench/textW
add wave -noupdate -group Bpred -group {branch update selection inputs} -divider {class check}
add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PCNextF
add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF
add wave -noupdate -group Bpred -expand -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE
add wave -noupdate -group Bpred -expand -group update -expand -group direction /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PCE
add wave -noupdate -group PCS /testbench/dut/core/ifu/PCNextF
add wave -noupdate -group PCS /testbench/dut/core/ifu/PCD
add wave -noupdate -group PCS /testbench/dut/core/PCE
add wave -noupdate -group PCS /testbench/dut/core/PCM
add wave -noupdate -group PCS /testbench/PCW
add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNextF
add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCF
add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCPlus2or4F
add wave -noupdate -group RegFile -expand /testbench/dut/core/ieu/dp/regf/rf
add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a1
add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a2
add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a3
add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/rd1
add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/rd2
add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/we3
add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/wd3
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/ReadDataW
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/CSRReadValW
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/ResultSrcW
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/ResultW
add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/A
add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/B
add wave -noupdate -group alu -divider internals
add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs1D
add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs2D
add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs1E
add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs2E
add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RdE
add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RdM
add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RdW
add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/MemReadE
add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RegWriteM
add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RegWriteW
add wave -noupdate -group Forward -color Thistle /testbench/dut/core/ieu/fw/ForwardAE
add wave -noupdate -group Forward -color Thistle /testbench/dut/core/ieu/fw/ForwardBE
add wave -noupdate -group Forward -color Thistle /testbench/dut/core/ieu/fw/LoadStallD
add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/ALUResultE
add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcAE
add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcBE
add wave -noupdate -group ifu -expand -group icache -color Gold /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CurrState
add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/ITLBMissF
add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/SelAdr
add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/PCNextF
add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/PCPF
add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/bus/icache/icache/HitWay
add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/ICacheStallF
add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/CacheBusAdr
add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CacheBusAck
add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/TLBWrite
add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/ITLBMissF
add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/PhysicalAddress
add wave -noupdate -group lsu /testbench/dut/core/lsu/IEUAdrM
add wave -noupdate -group lsu /testbench/dut/core/lsu/PAdrM
add wave -noupdate -group lsu /testbench/dut/core/lsu/SelHPTW
add wave -noupdate -group lsu /testbench/dut/core/lsu/LSUStallM
add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM
add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataM
add wave -noupdate -group lsu /testbench/dut/core/lsu/WriteDataM
add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/BusStall
add wave -noupdate -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrE
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrM
add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay}
add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/NextFlushAdr
add wave -noupdate -group lsu -expand -group dcache -expand -group flush -radix hexadecimal /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr
add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/LineDirty
add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty
add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr
add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/CacheableM
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/RAM}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/RAM}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/RAM}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/RAM}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/RAM}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/RAM}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/RAM}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/RAM}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/RAM}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/RAM}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/RAM}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/RAM}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/RAM}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/RAM}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/RAM}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/RAM[2]}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits[2]}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits[2]}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/RAM}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/RAM}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/RAM}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/RAM}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/RAM}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/RAM}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/RAM}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/RAM}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/RAM}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/SetValid
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
add wave -noupdate -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/FlushCache
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/ReadDataWordM
add wave -noupdate -group lsu -expand -group dcache -group status /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
add wave -noupdate -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit
add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBHit
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress
add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_D
add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_A
add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_U
add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_X
add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_W
add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_R
add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_V
add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/ImproperPrivilege
add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Misaligned
add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/dtlb/InvalidRead
add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/dtlb/InvalidWrite
add wave -noupdate -group lsu -group dtlb -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault
add wave -noupdate -group lsu -group dtlb -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM
add wave -noupdate -group lsu -group dtlb -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr
add wave -noupdate -group lsu -group dtlb -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
add wave -noupdate -group lsu -group dtlb -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal
add wave -noupdate -group lsu -group dtlb -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM
add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF
add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM
add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HCLK
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HRESETn
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HREADY
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HRESP
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HADDR
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HWDATA
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HWRITE
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HSIZE
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HBURST
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HPROT
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HTRANS
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HMASTLOCK
add wave -noupdate -group itlb /testbench/dut/core/ifu/immu/immu/TLBWrite
add wave -noupdate -group itlb /testbench/dut/core/ifu/ITLBMissF
add wave -noupdate -group itlb /testbench/dut/core/ifu/immu/immu/PhysicalAddress
add wave -noupdate -group itlb /testbench/dut/core/ifu/immu/immu/PMAInstrAccessFaultF
add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/UARTIntr
add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/GPIOIntr
add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOIntr
add wave -noupdate -group CLINT /testbench/dut/uncore/uncore/clint/clint/MTIME
add wave -noupdate -group CLINT /testbench/dut/uncore/uncore/clint/clint/MTIMECMP
add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/SIN
add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/DSRb
add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/DCDb
add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/CTSb
add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/RIb
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uncore/uart/uart/SOUT
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uncore/uart/uart/RTSb
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uncore/uart/uart/DTRb
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uncore/uart/uart/OUT1b
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uncore/uart/uart/OUT2b
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uncore/uart/uart/INTR
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uncore/uart/uart/TXRDYb
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uncore/uart/uart/RXRDYb
add wave -noupdate -group {debug trace} -expand -group mem -color Yellow /testbench/dut/core/FlushW
add wave -noupdate -group {debug trace} -expand -group mem /testbench/checkInstrM
add wave -noupdate -group {debug trace} -expand -group mem /testbench/dut/core/PCM
add wave -noupdate -group {debug trace} -expand -group mem /testbench/ExpectedPCM
add wave -noupdate -group {debug trace} -expand -group mem /testbench/textM
add wave -noupdate -group {debug trace} -expand -group mem -color Brown /testbench/dut/core/hzu/TrapM
add wave -noupdate -group {debug trace} -expand -group wb /testbench/checkInstrW
add wave -noupdate -group {debug trace} -expand -group wb /testbench/PCW
add wave -noupdate -group {debug trace} -expand -group wb /testbench/ExpectedPCW
add wave -noupdate -group {debug trace} -expand -group wb /testbench/TrapW
add wave -noupdate -group {debug trace} -expand -group wb /testbench/textW
add wave -noupdate -group {Performance Counters} -label MCYCLE -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[0]}
add wave -noupdate -group {Performance Counters} -label MINSTRET -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[2]}
add wave -noupdate -group {Performance Counters} -label {LOAD STORE HAZARD} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[3]}
add wave -noupdate -group {Performance Counters} -expand -group BRP -label {BP DIRECTION WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[4]}
add wave -noupdate -group {Performance Counters} -expand -group BRP -label {BP INSTRUCTION} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[5]}
add wave -noupdate -group {Performance Counters} -expand -group BRP -label {BTA/JTA WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[6]}
add wave -noupdate -group {Performance Counters} -expand -group BRP -label {JAL(R) INSTRUCTION} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[7]}
add wave -noupdate -group {Performance Counters} -expand -group BRP -label {RAS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[8]}
add wave -noupdate -group {Performance Counters} -expand -group BRP -label {RETURN INSTRUCTION} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[9]}
add wave -noupdate -group {Performance Counters} -expand -group BRP -label {BP CLASS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[10]}
add wave -noupdate -group {Performance Counters} -expand -group ICACHE -label {ICACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[13]}
add wave -noupdate -group {Performance Counters} -expand -group ICACHE -label {ICACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[14]}
add wave -noupdate -group {Performance Counters} -expand -group DCACHE -label {DCACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[11]}
add wave -noupdate -group {Performance Counters} -expand -group DCACHE -label {DCACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[12]}
add wave -noupdate /testbench/dut/core/lsu/test
add wave -noupdate {/testbench/dut/core/lsu/LSUHTRANS[1]}
add wave -noupdate /testbench/dut/core/lsu/LSUHADDR
add wave -noupdate /testbench/dut/core/lsu/LSUHTRANS
add wave -noupdate /testbench/dut/core/lsu/HRDATA
add wave -noupdate /testbench/dut/core/lsu/LSUHWDATA
add wave -noupdate /testbench/dut/core/lsu/LSUHWRITE
add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck
add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
add wave -noupdate /testbench/dut/core/priv/priv/PrivilegeModeW
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{invalid oad data} {15916799 ns} 1} {{original store} {4919493 ns} 1} {{correct load data} {165196425 ns} 0} {{Cursor 4} {165662196 ns} 1} {{Cursor 5} {165196436 ns} 1}
quietly wave cursor active 3
configure wave -namecolwidth 250
configure wave -valuecolwidth 314
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {165196205 ns} {165196487 ns}

0
sim/GetLineNum.do → sim/questa/GetLineNum.do
View file

2
sim/questa/coverage Executable file
View file

@ -0,0 +1,2 @@
# recompile coverage tests and run coverage including them
pushd $WALLY/tests/coverage; make; popd; ./regression-wally -coverage

282
sim/coverage-exclusions-rv64gc.do → sim/questa/coverage-exclusions-rv64gc.do
View file

@ -28,6 +28,10 @@
# This file should be a last resort. It's preferable to put
# // coverage off
# statements inline with the code whenever possible.
set WALLY $::env(WALLY)
set SRC ${WALLY}/src
# a hack to describe coverage exclusions without hardcoding linenumbers:
do GetLineNum.do
@ -44,13 +48,13 @@ coverage exclude -scope /dut/core/fpu/fpu/fdivsqrt/fdivsqrtfsm -ftrans state DON
# which won't happen while the divider is busy.
coverage exclude -scope /dut/core/fpu/fpu/fdivsqrt/fdivsqrtfsm -ftrans state BUSY->IDLE
# All Memory-stage stalls have resolved by time fdivsqrt finishes regular operation in this configuration, so can't test StallM
coverage exclude -scope /dut/core/fpu/fpu/fdivsqrt/fdivsqrtfsm -linerange [GetLineNum ../src/fpu/fdivsqrt/fdivsqrtfsm.sv "exclusion-tag: fdivsqrtfsm stallm"] -item b 1
coverage exclude -scope /dut/core/fpu/fpu/fdivsqrt/fdivsqrtfsm -linerange [GetLineNum ../src/fpu/fdivsqrt/fdivsqrtfsm.sv "exclusion-tag: fdivsqrtfsm stallm"] -item s 1
coverage exclude -scope /dut/core/fpu/fpu/fdivsqrt/fdivsqrtfsm -linerange [GetLineNum ${SRC}/fpu/fdivsqrt/fdivsqrtfsm.sv "exclusion-tag: fdivsqrtfsm stallm"] -item b 1
coverage exclude -scope /dut/core/fpu/fpu/fdivsqrt/fdivsqrtfsm -linerange [GetLineNum ${SRC}/fpu/fdivsqrt/fdivsqrtfsm.sv "exclusion-tag: fdivsqrtfsm stallm"] -item s 1
# Division by zero never sets sticky/guard/overflow/round to cause inexact or underflow result, but check out of paranoia
coverage exclude -scope /dut/core/fpu/fpu/postprocess/flags -linerange [GetLineNum ../src/fpu/postproc/flags.sv "assign FpInexact"] -item e 1 -fecexprrow 15
coverage exclude -scope /dut/core/fpu/fpu/postprocess/flags -linerange [GetLineNum ../src/fpu/postproc/flags.sv "assign Underflow"] -item e 1 -fecexprrow 22
coverage exclude -scope /dut/core/fpu/fpu/postprocess/flags -linerange [GetLineNum ${SRC}/fpu/postproc/flags.sv "assign FpInexact"] -item e 1 -fecexprrow 15
coverage exclude -scope /dut/core/fpu/fpu/postprocess/flags -linerange [GetLineNum ${SRC}/fpu/postproc/flags.sv "assign Underflow"] -item e 1 -fecexprrow 22
# Convert int to fp will never underflow
coverage exclude -scope /dut/core/fpu/fpu/postprocess/cvtshiftcalc -linerange [GetLineNum ../src/fpu/postproc/cvtshiftcalc.sv "assign CvtResUf"] -item e 1 -fecexprrow 4
coverage exclude -scope /dut/core/fpu/fpu/postprocess/cvtshiftcalc -linerange [GetLineNum ${SRC}/fpu/postproc/cvtshiftcalc.sv "assign CvtResUf"] -item e 1 -fecexprrow 4
##################
# Cache Exclusions
@ -62,89 +66,89 @@ coverage exclude -scope /dut/core/fpu/fpu/postprocess/cvtshiftcalc -linerange [G
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -fstate CurrState STATE_FLUSH STATE_FLUSH_WRITEBACK STATE_FLUSH_WRITEBACK STATE_WRITEBACK
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -ftrans CurrState STATE_WRITE_LINE->STATE_READY STATE_FETCH->STATE_READY
# exclude unused transitions from case statement. Unfortunately the whole branch needs to be excluded I think. Expression coverage should still work.
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache state-case"] -item b 1
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag: icache state-case"] -item b 1
# I$ does not flush
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache FlushCache"] -item e 1 -fecexprrow 2
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag: icache FlushCache"] -item e 1 -fecexprrow 2
# exclude branch/condition coverage: LineDirty if statement
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache FETCHStatement"] -item bc 1
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache FLUSHStatement"] -item bs 1
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag: icache FETCHStatement"] -item bc 1
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag: icache FLUSHStatement"] -item bs 1
# exclude the unreachable logic
set start [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag-start: icache case"]
set end [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag-end: icache case"]
set start [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag-start: icache case"]
set end [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag-end: icache case"]
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange $start-$end
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache WRITEBACKStatement"]
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag: icache WRITEBACKStatement"]
# exclude Atomic Operation logic
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: cache AnyMiss"] -item e 1 -fecexprrow 6
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache storeAMO1"] -item e 1 -fecexprrow 2-4
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache AnyUpdateHit"] -item e 1 -fecexprrow 2
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag: cache AnyMiss"] -item e 1 -fecexprrow 6
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag: icache storeAMO1"] -item e 1 -fecexprrow 2-4
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag: icache AnyUpdateHit"] -item e 1 -fecexprrow 2
# cache write logic
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache CacheW"] -item e 1 -fecexprrow 4
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag: icache CacheW"] -item e 1 -fecexprrow 4
# output signal logic
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache StallStates"] -item e 1 -fecexprrow 8 12 14
set start [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag-start: icache flushdirtycontrols"]
set end [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag-end: icache flushdirtycontrols"]
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag: icache StallStates"] -item e 1 -fecexprrow 8 12 14
set start [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag-start: icache flushdirtycontrols"]
set end [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag-end: icache flushdirtycontrols"]
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange $start-$end
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache CacheBusW"]
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache SelAdrCauses"] -item e 1 -fecexprrow 4 10
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache SelAdrTag"] -item e 1 -fecexprrow 8
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache CacheBusRCauses"] -item e 1 -fecexprrow 1-2 12
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag: icache CacheBusW"]
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag: icache SelAdrCauses"] -item e 1 -fecexprrow 4 10
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag: icache SelAdrTag"] -item e 1 -fecexprrow 8
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag: icache CacheBusRCauses"] -item e 1 -fecexprrow 1-2 12
# cache.sv AdrSelMuxData and AdrSelMuxTag and CacheBusAdrMux, excluding unhit Flush branch
coverage exclude -scope /dut/core/ifu/bus/icache/icache/AdrSelMuxData -linerange [GetLineNum ../src/generic/mux.sv "exclusion-tag: mux3"] -item b 1
coverage exclude -scope /dut/core/ifu/bus/icache/icache/AdrSelMuxTag -linerange [GetLineNum ../src/generic/mux.sv "exclusion-tag: mux3"] -item b 1
coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheBusAdrMux -linerange [GetLineNum ../src/generic/mux.sv "exclusion-tag: mux3"] -item b 1 3
coverage exclude -scope /dut/core/ifu/bus/icache/icache/AdrSelMuxData -linerange [GetLineNum ${SRC}/generic/mux.sv "exclusion-tag: mux3"] -item b 1
coverage exclude -scope /dut/core/ifu/bus/icache/icache/AdrSelMuxTag -linerange [GetLineNum ${SRC}/generic/mux.sv "exclusion-tag: mux3"] -item b 1
coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheBusAdrMux -linerange [GetLineNum ${SRC}/generic/mux.sv "exclusion-tag: mux3"] -item b 1 3
# CacheWay Dirty logic. -scope does not accept wildcards.
set numcacheways 4
for {set i 0} {$i < $numcacheways} {incr i} {
coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: icache SetDirtyWay"] -item e 1
coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: icache SelectedWiteWordEn"] -item e 1 -fecexprrow 4 6
coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ${SRC}/cache/cacheway.sv "exclusion-tag: icache SetDirtyWay"] -item e 1
coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ${SRC}/cache/cacheway.sv "exclusion-tag: icache SelectedWiteWordEn"] -item e 1 -fecexprrow 4 6
# below: flushD can't go high during an icache write b/c of pipeline stall
coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: cache SetValidEN"] -item e 1 -fecexprrow 4
coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: cache ClearValidEN"] -item e 1 -fecexprrow 4
coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ${SRC}/cache/cacheway.sv "exclusion-tag: cache SetValidEN"] -item e 1 -fecexprrow 4
coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ${SRC}/cache/cacheway.sv "exclusion-tag: cache ClearValidEN"] -item e 1 -fecexprrow 4
# No CMO to clear valid bits of I$
coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "// exclusion-tag: icache ClearValidBits"]
coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "// exclusion-tag: icache ClearValidWay"] -item e 1
coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ${SRC}/cache/cacheway.sv "// exclusion-tag: icache ClearValidBits"]
coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ${SRC}/cache/cacheway.sv "// exclusion-tag: icache ClearValidWay"] -item e 1
# No dirty ways in read-only I$
coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "// exclusion-tag: icache DirtyWay"] -item e 1
coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ${SRC}/cache/cacheway.sv "// exclusion-tag: icache DirtyWay"] -item e 1
}
# I$ buscachefsm does not perform atomics or write/writeback; HREADY is always 1
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm AtomicReadData"]
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm AtomicElse"] -item s 1
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm AtomicPhase"]
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm AtomicWait"] -item bs 1
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm FetchWriteback"] -item b 2
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm FetchWriteback"] -item s 1
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm WritebackWriteback"]
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm WritebackWriteback2"] -item bs 1
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY4"] -item bs 1
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY6"] -item bs 1
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADYread"] -item c 1 -feccondrow 1
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm FetchWriteback"] -item c 1 -feccondrow 1,2,3,4,6
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY4"] -item c 1
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY6"] -item c 1
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "assign HTRANS"] -item c 1 -feccondrow 5
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "assign BeatCntEn"] -item e 1 -fecexprrow 4
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "assign CacheAccess"] -item e 1 -fecexprrow 4
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "assign BusStall"] -item e 1 -fecexprrow 10,12,18
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "assign CacheBusAck"] -item e 1 -fecexprrow 3
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm AtomicReadData"]
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm AtomicElse"] -item s 1
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm AtomicPhase"]
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm AtomicWait"] -item bs 1
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm FetchWriteback"] -item b 2
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm FetchWriteback"] -item s 1
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm WritebackWriteback"]
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm WritebackWriteback2"] -item bs 1
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY4"] -item bs 1
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY6"] -item bs 1
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADYread"] -item c 1 -feccondrow 1
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm FetchWriteback"] -item c 1 -feccondrow 1,2,3,4,6
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY4"] -item c 1
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY6"] -item c 1
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "assign HTRANS"] -item c 1 -feccondrow 5
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "assign BeatCntEn"] -item e 1 -fecexprrow 4
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "assign CacheAccess"] -item e 1 -fecexprrow 4
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "assign BusStall"] -item e 1 -fecexprrow 10,12,18
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "assign CacheBusAck"] -item e 1 -fecexprrow 3
## D$ Exclusions.
# InvalidateCache is I$ only:
coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: dcache InvalidateCheck"] -item b 2
coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: dcache InvalidateCheck"] -item s 1
coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: dcache CacheEn"] -item e 1 -fecexprrow 12
coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: cache AnyMiss"] -item e 1 -fecexprrow 4
coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/cachefsm -linerange [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag: dcache InvalidateCheck"] -item b 2
coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/cachefsm -linerange [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag: dcache InvalidateCheck"] -item s 1
coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/cachefsm -linerange [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag: dcache CacheEn"] -item e 1 -fecexprrow 12
coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/cachefsm -linerange [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag: cache AnyMiss"] -item e 1 -fecexprrow 4
set numcacheways 4
for {set i 0} {$i < $numcacheways} {incr i} {
coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: dcache invalidateway"] -item bes 1 -fecexprrow 4
coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/CacheWays[$i] -linerange [GetLineNum ${SRC}/cache/cacheway.sv "exclusion-tag: dcache invalidateway"] -item bes 1 -fecexprrow 4
# InvalidateCacheDelay is always 0 for D$ because it is flushed, not invalidated
coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: dcache HitWay"] -item 3 1 -fecexprrow 2
coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/CacheWays[$i] -linerange [GetLineNum ${SRC}/cache/cacheway.sv "exclusion-tag: dcache HitWay"] -item 3 1 -fecexprrow 2
# FlushStage=1 will never happen when SetValidWay=1 since a pipeline stall is asserted by the cache in the fetch stage, which happens before
# going into the WRITE_LINE state (and asserting SetValidWay). No TrapM can fire and since StallW is high, a stallM caused by WFIStallM would not cause a flushW.
coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: cache SetValidEN"] -item e 1 -fecexprrow 4
coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: cache ClearValidEN"] -item e 1 -fecexprrow 4
# Not right; other ways can get flushed and dirtied simultaneously coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: cache UpdateDirty"] -item c 1 -feccondrow 6
coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/CacheWays[$i] -linerange [GetLineNum ${SRC}/cache/cacheway.sv "exclusion-tag: cache SetValidEN"] -item e 1 -fecexprrow 4
coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/CacheWays[$i] -linerange [GetLineNum ${SRC}/cache/cacheway.sv "exclusion-tag: cache ClearValidEN"] -item e 1 -fecexprrow 4
# Not right; other ways can get flushed and dirtied simultaneously coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/CacheWays[$i] -linerange [GetLineNum ${SRC}/cache/cacheway.sv "exclusion-tag: cache UpdateDirty"] -item c 1 -feccondrow 6
}
# D$ writeback, flush, write_line, or flush_writeback states can't be cancelled by a flush
coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/cachefsm -ftrans CurrState STATE_WRITEBACK->STATE_READY STATE_FLUSH->STATE_READY STATE_WRITE_LINE->STATE_READY STATE_FLUSH_WRITEBACK->STATE_READY
@ -164,16 +168,16 @@ coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/ddr4dec
coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/sdcdec
# PMA Regions 1, 2, and 3 (dtim, irom, ddr4) are never used in the rv64gc configuration, so exclude coverage
set line [GetLineNum ../src/mmu/pmachecker.sv "exclusion-tag: unused-atomic"]
set line [GetLineNum ${SRC}/mmu/pmachecker.sv "exclusion-tag: unused-atomic"]
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2,4
coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2,4
set line [GetLineNum ../src/mmu/pmachecker.sv "exclusion-tag: unused-tim"]
set line [GetLineNum ${SRC}/mmu/pmachecker.sv "exclusion-tag: unused-tim"]
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2,4
coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2,4
set line [GetLineNum ../src/mmu/pmachecker.sv "exclusion-tag: unused-cachable"]
set line [GetLineNum ${SRC}/mmu/pmachecker.sv "exclusion-tag: unused-cachable"]
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2
coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2
set line [GetLineNum ../src/mmu/pmachecker.sv "exclusion-tag: unused-idempotent"]
set line [GetLineNum ${SRC}/mmu/pmachecker.sv "exclusion-tag: unused-idempotent"]
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2,4,6
coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2,4,6,8
@ -183,7 +187,7 @@ coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/uncoreramdec
coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/spidec
# The following peripherals are always supported
set line [GetLineNum ../src/mmu/adrdec.sv "exclusion-tag: adrdecSel"]
set line [GetLineNum ${SRC}/mmu/adrdec.sv "exclusion-tag: adrdecSel"]
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/bootromdec -linerange $line-$line -item e 1 -fecexprrow 3,7
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/gpiodec -linerange $line-$line -item e 1 -fecexprrow 3
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/uartdec -linerange $line-$line -item e 1 -fecexprrow 3
@ -191,104 +195,104 @@ coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/plicdec -line
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/spidec -linerange $line-$line -item e 1 -fecexprrow 3
#Excluding signals in lsu: clintdec and uncoreram accept all sizes so 'SizeValid' will never be 0
set line [GetLineNum ../src/mmu/adrdec.sv "& SizeValid"]
set line [GetLineNum ${SRC}/mmu/adrdec.sv "& SizeValid"]
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/clintdec -linerange $line-$line -item e 1 -fecexprrow 5
set line [GetLineNum ../src/mmu/adrdec.sv "& SizeValid"]
set line [GetLineNum ${SRC}/mmu/adrdec.sv "& SizeValid"]
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/uncoreramdec -linerange $line-$line -item e 1 -fecexprrow 5
# set line [GetLineNum ../src/mmu/adrdec.sv "& Supported"]
# set line [GetLineNum ${SRC}/mmu/adrdec.sv "& Supported"]
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/dtimdec
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/iromdec
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/ddr4dec
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/sdcdec
# No DTIM or IROM
coverage exclude -scope /dut/core/ifu/bus/icache/UnCachedDataMux -linerange [GetLineNum ../src/generic/mux.sv "exclusion-tag: mux3"] -item b 1
coverage exclude -scope /dut/core/lsu/bus/dcache/UnCachedDataMux -linerange [GetLineNum ../src/generic/mux.sv "exclusion-tag: mux3"] -item b 1
coverage exclude -scope /dut/core/ifu/bus/icache/UnCachedDataMux -linerange [GetLineNum ${SRC}/generic/mux.sv "exclusion-tag: mux3"] -item b 1
coverage exclude -scope /dut/core/lsu/bus/dcache/UnCachedDataMux -linerange [GetLineNum ${SRC}/generic/mux.sv "exclusion-tag: mux3"] -item b 1
####################
# Unused access types due to sharing IFU and LSU logic
####################
## The lsu never executes instructions so 'ExecuteAccessF' will never be 1
set line [GetLineNum ../src/mmu/pmachecker.sv "AccessRWXC ="]
set line [GetLineNum ${SRC}/mmu/pmachecker.sv "AccessRWXC ="]
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 6
set line [GetLineNum ../src/mmu/pmachecker.sv "ReadAccessM \\| ExecuteAccessF"]
set line [GetLineNum ${SRC}/mmu/pmachecker.sv "ReadAccessM \\| ExecuteAccessF"]
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 4
set line [GetLineNum ../src/mmu/pmachecker.sv "ExecuteAccessF & PMAAccessFault"]
set line [GetLineNum ${SRC}/mmu/pmachecker.sv "ExecuteAccessF & PMAAccessFault"]
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2
set line [GetLineNum ../src/mmu/mmu.sv "ExecuteAccessF \\| ReadAccessM"]
set line [GetLineNum ${SRC}/mmu/mmu.sv "ExecuteAccessF \\| ReadAccessM"]
coverage exclude -scope /dut/core/lsu/dmmu/dmmu -linerange $line-$line -item e 1 -fecexprrow 2
set line [GetLineNum ../src/mmu/mmu.sv "TLBPageFault & ExecuteAccessF"]
set line [GetLineNum ${SRC}/mmu/mmu.sv "TLBPageFault & ExecuteAccessF"]
coverage exclude -scope /dut/core/lsu/dmmu/dmmu -linerange $line-$line -item e 1 -fecexprrow 1,2,4
set line [GetLineNum ../src/mmu/mmu.sv "PMAInstrAccessFaultF \\|"]
set line [GetLineNum ${SRC}/mmu/mmu.sv "PMAInstrAccessFaultF \\|"]
coverage exclude -scope /dut/core/lsu/dmmu/dmmu -linerange $line-$line -item e 1 -fecexprrow 2,4,5,6
set line [GetLineNum ../src/mmu/pmpchecker.sv "EnforcePMP & ExecuteAccessF"]
set line [GetLineNum ${SRC}/mmu/pmpchecker.sv "EnforcePMP & ExecuteAccessF"]
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmp/pmpchecker -linerange $line-$line -item e 1 -fecexprrow 1,2,4,5,6
set line [GetLineNum ../src/mmu/pmpchecker.sv "EnforcePMP & ExecuteAccessF"]
set line [GetLineNum ${SRC}/mmu/pmpchecker.sv "EnforcePMP & ExecuteAccessF"]
coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange $line-$line -item e 1 -fecexprrow 3
## The IFU has ReadAccess = WriteAccess = 0 and ExecuteAccess = 1 hardwired, so exclude alternatives
set line [GetLineNum ../src/mmu/pmachecker.sv "ReadAccessM \\| WriteAccessM"]
set line [GetLineNum ${SRC}/mmu/pmachecker.sv "ReadAccessM \\| WriteAccessM"]
coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2 4
set line [GetLineNum ../src/mmu/pmachecker.sv "WriteAccessM \\| ExecuteAccessF"]
set line [GetLineNum ${SRC}/mmu/pmachecker.sv "WriteAccessM \\| ExecuteAccessF"]
coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 1-5
set line [GetLineNum ../src/mmu/pmachecker.sv "ReadAccessM \\| ExecuteAccessF"]
set line [GetLineNum ${SRC}/mmu/pmachecker.sv "ReadAccessM \\| ExecuteAccessF"]
coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 1-3
set line [GetLineNum ../src/mmu/pmachecker.sv "ExecuteAccessF & PMAAccessFault"]
set line [GetLineNum ${SRC}/mmu/pmachecker.sv "ExecuteAccessF & PMAAccessFault"]
coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 1
set line [GetLineNum ../src/mmu/pmachecker.sv "ReadAccessM & PMAAccessFault"]
set line [GetLineNum ${SRC}/mmu/pmachecker.sv "ReadAccessM & PMAAccessFault"]
coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2-4
set line [GetLineNum ../src/mmu/pmachecker.sv "PMAStoreAmoAccessFaultM ="]
set line [GetLineNum ${SRC}/mmu/pmachecker.sv "PMAStoreAmoAccessFaultM ="]
coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line
set line [GetLineNum ../src/mmu/pmachecker.sv "AccessRWXC \\| AtomicAccessM"]
set line [GetLineNum ${SRC}/mmu/pmachecker.sv "AccessRWXC \\| AtomicAccessM"]
coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 3
set line [GetLineNum ../src/mmu/mmu.sv "ExecuteAccessF \\| ReadAccessM"]
set line [GetLineNum ${SRC}/mmu/mmu.sv "ExecuteAccessF \\| ReadAccessM"]
coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 1,3,4
set line [GetLineNum ../src/mmu/mmu.sv "ReadAccessM & ~WriteAccessM"]
set line [GetLineNum ${SRC}/mmu/mmu.sv "ReadAccessM & ~WriteAccessM"]
coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 2-4
set line [GetLineNum ../src/mmu/mmu.sv "assign AmoAccessM"]
set line [GetLineNum ${SRC}/mmu/mmu.sv "assign AmoAccessM"]
coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1
set line [GetLineNum ../src/mmu/mmu.sv "assign AmoMisalignedCausesAccessFaultM"]
set line [GetLineNum ${SRC}/mmu/mmu.sv "assign AmoMisalignedCausesAccessFaultM"]
coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1
set line [GetLineNum ../src/mmu/mmu.sv "DataMisalignedM & WriteAccessM"]
set line [GetLineNum ${SRC}/mmu/mmu.sv "DataMisalignedM & WriteAccessM"]
coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 1,2,4
set line [GetLineNum ../src/mmu/mmu.sv "TLBPageFault & ExecuteAccessF"]
set line [GetLineNum ${SRC}/mmu/mmu.sv "TLBPageFault & ExecuteAccessF"]
coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 3
set line [GetLineNum ../src/mmu/mmu.sv "TLBPageFault & ReadNoAmoAccessM"]
set line [GetLineNum ${SRC}/mmu/mmu.sv "TLBPageFault & ReadNoAmoAccessM"]
coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 1,2,4
set line [GetLineNum ../src/mmu/mmu.sv "StoreAmoPageFaultM \="]
set line [GetLineNum ${SRC}/mmu/mmu.sv "StoreAmoPageFaultM \="]
coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 1,2,4
set line [GetLineNum ../src/mmu/mmu.sv "DataMisalignedM & ReadNoAmoAccessM"]
set line [GetLineNum ${SRC}/mmu/mmu.sv "DataMisalignedM & ReadNoAmoAccessM"]
coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 1,2,4
set line [GetLineNum ../src/mmu/pmpchecker.sv "EnforcePMP & WriteAccessM"]
set line [GetLineNum ${SRC}/mmu/pmpchecker.sv "EnforcePMP & WriteAccessM"]
coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange $line-$line -item e 1 -fecexprrow 1,2,4,5,6
set line [GetLineNum ../src/mmu/pmpchecker.sv "EnforcePMP & ReadAccessM"]
set line [GetLineNum ${SRC}/mmu/pmpchecker.sv "EnforcePMP & ReadAccessM"]
coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange $line-$line -item e 1 -fecexprrow 1,2,4,5,6
set line [GetLineNum ../src/mmu/mmu.sv "LoadAccessFaultM \="]
set line [GetLineNum ${SRC}/mmu/mmu.sv "LoadAccessFaultM \="]
coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 2,4,5,6
set line [GetLineNum ../src/mmu/mmu.sv "StoreAmoAccessFaultM \="]
set line [GetLineNum ${SRC}/mmu/mmu.sv "StoreAmoAccessFaultM \="]
coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 2,4,5,6
set line [GetLineNum ../src/mmu/tlb/tlbcontrol.sv "ReadAccess \\| WriteAccess"]
set line [GetLineNum ${SRC}/mmu/tlb/tlbcontrol.sv "ReadAccess \\| WriteAccess"]
coverage exclude -scope /dut/core/ifu/immu/immu/tlb/tlb/tlbcontrol -linerange $line-$line -item e 1 -fecexprrow 1,3,4
set line [GetLineNum ../src/mmu/tlb/tlbcontrol.sv "CAMHit & TLBAccess"]
set line [GetLineNum ${SRC}/mmu/tlb/tlbcontrol.sv "CAMHit & TLBAccess"]
coverage exclude -scope /dut/core/ifu/immu/immu/tlb/tlb/tlbcontrol -linerange $line-$line -item e 1 -fecexprrow 3
set line [GetLineNum ../src/mmu/tlb/tlbcontrol.sv "~CAMHit & TLBAccess"]
set line [GetLineNum ${SRC}/mmu/tlb/tlbcontrol.sv "~CAMHit & TLBAccess"]
coverage exclude -scope /dut/core/ifu/immu/immu/tlb/tlb/tlbcontrol -linerange $line-$line -item e 1 -fecexprrow 3
# IMMU only makes word-sized accesses
set line [GetLineNum ../src/mmu/mmu.sv "exclusion-tag: immu-wordaccess"]
set line [GetLineNum ${SRC}/mmu/mmu.sv "exclusion-tag: immu-wordaccess"]
set line2 [expr $line + 6 ]
coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line2 -item e 1 -fecexprrow 4
coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line2 -item b 1
coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line2 -item s 1
# IMMU never disables translations
coverage exclude -scope /dut/core/ifu/ifu/immu/immu/tlb/tlb/tlbcontrol -linerange [GetLineNum ../src/mmu/tlb/tlbcontrol.sv "assign Translate"] -item e 1 -fecexprrow 2
coverage exclude -scope /dut/core/ifu/ifu/immu/immu/tlb/tlb/tlbcontrol -linerange [GetLineNum ../src/mmu/tlb/tlbcontrol.sv "assign UpdateDA"] -item e 1 -fecexprrow 5
coverage exclude -scope /dut/core/ifu/ifu/immu/immu/tlb/tlb/tlbcontrol -linerange [GetLineNum ${SRC}/mmu/tlb/tlbcontrol.sv "assign Translate"] -item e 1 -fecexprrow 2
coverage exclude -scope /dut/core/ifu/ifu/immu/immu/tlb/tlb/tlbcontrol -linerange [GetLineNum ${SRC}/mmu/tlb/tlbcontrol.sv "assign UpdateDA"] -item e 1 -fecexprrow 5
# never reaches this when ENVCFG_ADUE_1 because HPTW updates A bit first
coverage exclude -scope /dut/core/ifu/ifu/immu/immu/tlb/tlb/tlbcontrol -linerange [GetLineNum ../src/mmu/tlb/tlbcontrol.sv "assign PrePageFault"] -item e 1 -fecexprrow 18
coverage exclude -scope /dut/core/ifu/ifu/immu/immu/tlb/tlb/tlbcontrol -linerange [GetLineNum ${SRC}/mmu/tlb/tlbcontrol.sv "assign PrePageFault"] -item e 1 -fecexprrow 18
@ -298,19 +302,19 @@ coverage exclude -scope /dut/core/ifu/ifu/immu/immu/tlb/tlb/tlbcontrol -linerang
###############
# RV64GC HPTW never starts at L1_ADR
set line [GetLineNum ../src/mmu/hptw.sv "InitialWalkerState == L1_ADR"]
set line [GetLineNum ${SRC}/mmu/hptw.sv "InitialWalkerState == L1_ADR"]
coverage exclude -scope /dut/core/lsu/lsu/hptw/hptw -linerange $line-$line -item c 1 -feccondrow 2
# Never possible to get a page fault when neither reading nor writing
set line [GetLineNum ../src/mmu/hptw.sv "assign HPTWLoadPageFault"]
set line [GetLineNum ${SRC}/mmu/hptw.sv "assign HPTWLoadPageFault"]
coverage exclude -scope /dut/core/lsu/lsu/hptw/hptw -linerange $line-$line -item e 1 -fecexprrow 7
# Never possible to get a store page fault from an ITLB walk
set line [GetLineNum ../src/mmu/hptw.sv "assign HPTWStoreAmoPageFault"]
set line [GetLineNum ${SRC}/mmu/hptw.sv "assign HPTWStoreAmoPageFault"]
coverage exclude -scope /dut/core/lsu/lsu/hptw/hptw -linerange $line-$line -item e 1 -fecexprrow 3
# Never possible to get Access = 0 on a nonleaf PTE with no OtherPageFault (because InvalidRead/Write will be 1 on the nonleaf)
set line [GetLineNum ../src/mmu/hptw.sv "assign HPTWUpdateDA"]
set line [GetLineNum ${SRC}/mmu/hptw.sv "assign HPTWUpdateDA"]
coverage exclude -scope /dut/core/lsu/lsu/hptw/hptw -linerange $line-$line -item e 1 -fecexprrow 3
###############
@ -318,78 +322,78 @@ coverage exclude -scope /dut/core/lsu/lsu/hptw/hptw -linerange $line-$line -item
###############
# IMMU PMP does not support CBO instructions
coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange [GetLineNum ../src/mmu/pmpchecker.sv "exclusion-tag: immu-pmpcbom"]
coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange [GetLineNum ../src/mmu/pmpchecker.sv "exclusion-tag: immu-pmpcboz"]
coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange [GetLineNum ../src/mmu/pmpchecker.sv "exclusion-tag: immu-pmpcboaccess"]
coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange [GetLineNum ${SRC}/mmu/pmpchecker.sv "exclusion-tag: immu-pmpcbom"]
coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange [GetLineNum ${SRC}/mmu/pmpchecker.sv "exclusion-tag: immu-pmpcboz"]
coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange [GetLineNum ${SRC}/mmu/pmpchecker.sv "exclusion-tag: immu-pmpcboaccess"]
# No irom
set line [GetLineNum ../src/ifu/ifu.sv "~ITLBMissF & ~CacheableF & ~SelIROM"]
set line [GetLineNum ${SRC}/ifu/ifu.sv "~ITLBMissF & ~CacheableF & ~SelIROM"]
coverage exclude -scope /dut/core/ifu -linerange $line-$line -item c 1 -feccondrow 6
set line [GetLineNum ../src/ifu/ifu.sv "~ITLBMissF & CacheableF & ~SelIROM"]
set line [GetLineNum ${SRC}/ifu/ifu.sv "~ITLBMissF & CacheableF & ~SelIROM"]
coverage exclude -scope /dut/core/ifu -linerange $line-$line -item c 1 -feccondrow 4
# no DTIM
set line [GetLineNum ../src/lsu/lsu.sv "assign BusRW"]
set line [GetLineNum ${SRC}/lsu/lsu.sv "assign BusRW"]
coverage exclude -scope /dut/core/lsu -linerange $line-$line -item c 1 -feccondrow 4
set line [GetLineNum ../src/lsu/lsu.sv "assign CacheRWM"]
set line [GetLineNum ${SRC}/lsu/lsu.sv "assign CacheRWM"]
coverage exclude -scope /dut/core/lsu -linerange $line-$line -item c 1 -feccondrow 4
# Excluding reset and clear for impossible case in the wficountreg in privdec
set line [GetLineNum ../src/generic/flop/floprc.sv "reset \\| clear"]
coverage exclude -scope /dut/core/priv/priv/pmd/wfi/wficountreg -linerange $line-$line -item c 1 -feccondrow 2
#set line [GetLineNum ${SRC}/generic/flop/floprc.sv "reset \\| clear"]
#coverage exclude -scope /dut/core/priv/priv/pmd/wfi/wficountreg -linerange $line-$line -item c 1 -feccondrow 2
# Exclude system reset case in ebu
set line [GetLineNum ../src/ebu/ebufsmarb.sv "BeatCounter\\("]
set line [GetLineNum ${SRC}/ebu/ebufsmarb.sv "BeatCounter\\("]
coverage exclude -scope /dut/core/ebu/ebu/ebufsmarb -linerange $line-$line -item e 1 -fecexprrow 1
set line [GetLineNum ../src/ebu/ebufsmarb.sv "FinalBeatReg\\("]
set line [GetLineNum ${SRC}/ebu/ebufsmarb.sv "FinalBeatReg\\("]
coverage exclude -scope /dut/core/ebu/ebu/ebufsmarb -linerange $line-$line -item e 1 -fecexprrow 1
set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm AtomicElse"]
set line [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm AtomicElse"]
coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item bc 1
set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm AtomicWait"]
set line [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm AtomicWait"]
coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item bc 1
# The WritebackWriteback and FetchWriteback support back to back pipelined cache writebacks and fetch then
# writebacks. The cache never issues these type of requests.
set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm WritebackWriteback"]
set line [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm WritebackWriteback"]
coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item bc 2
set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm FetchWriteback"]
set line [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm FetchWriteback"]
coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item bc 2
# FetchWait never occurs because HREADY is never 0.
set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm FetchWait"]
set line [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm FetchWait"]
coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item bc 1
# all of these HREADY exclusions occur because HREADY is always 1. The ram_ahb module never stalls.
set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY0"]
set line [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY0"]
coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 1
#set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY1"]
#set line [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY1"]
#coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 1
#set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY2"]
#set line [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY2"]
#coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 1
set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY3"]
set line [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY3"]
coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 4
set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY4"]
set line [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY4"]
coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 1
coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 3
set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY5"]
set line [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY5"]
coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 1
set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY6"]
set line [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY6"]
coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 1
coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 5
coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "assign CacheBusAck"] -item e 1 -fecexprrow 5
coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "assign CacheBusAck"] -item e 1 -fecexprrow 5
coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm AtomicElse"] -item s 1
coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm AtomicWait"] -item s 1
coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm AtomicElse"] -item s 1
coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm AtomicWait"] -item s 1
# these transitions will not happen
coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -ftrans CurrState DATA_PHASE->ADR_PHASE ATOMIC_READ_DATA_PHASE->ADR_PHASE ATOMIC_PHASE->ADR_PHASE
@ -399,15 +403,15 @@ coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefs
coverage exclude -srcfile priorityonehot.sv
# Excluding pmpadrdecs[0] coverage case for PAgePMPAdrIn being hardwired to 1
coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker/pmp/pmpadrdecs[0] -linerange [GetLineNum ../src/mmu/pmpadrdec.sv "exclusion-tag: PAgePMPAdrIn"] -item e 1 -fecexprrow 1
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmp/pmpchecker/pmp/pmpadrdecs[0] -linerange [GetLineNum ../src/mmu/pmpadrdec.sv "exclusion-tag: PAgePMPAdrIn"] -item e 1 -fecexprrow 1
coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker/pmp/pmpadrdecs[0] -linerange [GetLineNum ${SRC}/mmu/pmpadrdec.sv "exclusion-tag: PAgePMPAdrIn"] -item e 1 -fecexprrow 1
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmp/pmpchecker/pmp/pmpadrdecs[0] -linerange [GetLineNum ${SRC}/mmu/pmpadrdec.sv "exclusion-tag: PAgePMPAdrIn"] -item e 1 -fecexprrow 1
####################
# Privileged
####################
# Instruction Misaligned never asserted because compresssed instructions are accepted
coverage exclude -scope /dut/core/priv/priv/trap -linerange [GetLineNum ../src/privileged/trap.sv "assign ExceptionM"] -item e 1 -fecexprrow 2
coverage exclude -scope /dut/core/priv/priv/trap -linerange [GetLineNum ${SRC}/privileged/trap.sv "assign ExceptionM"] -item e 1 -fecexprrow 2
####################
# EBU

0
sim/fpga-wave.do → sim/questa/fpga-wave.do
View file

0
sim/sim-imperas → sim/questa/sim-imperas
View file

4
sim/sim-testfloat → sim/questa/sim-testfloat
View file

@ -9,4 +9,6 @@
# sqrt - test square root
# all - test everything
vsim -do "do testfloat.do fdqh_ieee_rv64gc $1"
wsim fdqh_ieee_rv64gc $1 --tb testbench_fp --gui

6
sim/sim-testfloat-batch → sim/questa/sim-testfloat-batch
View file

@ -1,3 +1,4 @@
# Run TestFloat simulation
# cvtint - test integer conversion unit (fcvtint)
# cvtfp - test floating-point conversion unit (fcvtfp)
@ -10,4 +11,7 @@
# sqrt - test square root
# all - test everything
vsim -c -do "do testfloat.do fdqh_ieee_rv64gc $1"
#vsim -c -do "do testfloat.do fdqh_ieee_rv64gc $1"
wsim fdqh_ieee_rv64gc $1 --tb testbench_fp
#wsim fdqh_ieee_rv64gc $1 --tb testbench_fp --gui

27
sim/questa/sim-testfloat-verilator Executable file
View file

@ -0,0 +1,27 @@
#!/usr/bin/bash
# sim-testfloat-verilator
# David_Harris@hmc.edu 3 April 2024
# Run Testfloat simulations with Verilator
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
# cvtint - test integer conversion unit (fcvtint)
# cvtfp - test floating-point conversion unit (fcvtfp)
# cmp - test comparison unit's LT, LE, EQ opperations (fcmp)
# add - test addition
# fma - test fma
# mul - test mult with fma
# sub - test subtraction
# div - test division
# sqrt - test square root
# all - test everything
#vsim -c -do "do testfloat.do fdqh_ieee_rv64gc $1"
verilator -GTEST="\"all\"" -GTEST_SIZE="\"all\"" --timescale "1ns/1ns" --timing --binary --top-module testbenchfp "-I../config/shared" "-I../config/deriv/fdqh_ieee_rv64gc" ../src/cvw.sv ../testbench/testbench-fp.sv ../src/fpu/*.sv ../src/fpu/*/*.sv ../src/generic/*.sv ../src/generic/flop/*.sv --relative-includes
#vlog +incdir+../config/deriv/$1 +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench-fp.sv ../src/fpu/*.sv ../src/fpu/*/*.sv ../src/generic/*.sv ../src/generic/flop/*.sv -suppress 2583,7063,8607,2697
# Change TEST_SIZE to only test certain FP width
# values are QP, DP, SP, HP or all for all tests
#vsim -voptargs=+acc work.testbenchfp -GTEST=$2 -GTEST_SIZE="all"

2
sim/questa/sim-wally Executable file
View file

@ -0,0 +1,2 @@
wsim rv64gc arch64i --gui

1
sim/questa/sim-wally-batch Executable file
View file

@ -0,0 +1 @@
wsim rv64gc arch64i

14
sim/wally-imperas-cov.do → sim/questa/wally-imperas-cov.do
View file

@ -27,12 +27,14 @@ vlib work
vlog +incdir+../config/$1 \
+incdir+../config/shared \
+define+USE_IMPERAS_DV \
+define+IDV_INCLUDE_TRACE2COV \
+incdir+$env(IMPERAS_HOME)/ImpPublic/include/host \
+incdir+$env(IMPERAS_HOME)/ImpProprietary/include/host \
$env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvviApiPkg.sv \
$env(IMPERAS_HOME)/ImpProprietary/source/host/idv/idvApiPkg.sv \
$env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvviTrace.sv \
$env(IMPERAS_HOME)/ImpProprietary/source/host/idv/idvPkg.sv \
$env(IMPERAS_HOME)/ImpProprietary/source/host/idv/idvApiPkg.sv \
$env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2bin.sv \
$env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2api.sv \
$env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2log.sv \
\
@ -44,7 +46,7 @@ vlog +incdir+../config/$1 \
$env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2cov.sv \
\
../src/cvw.sv \
../testbench/testbench_imperas.sv \
../testbench/testbench-imperas.sv \
../testbench/common/*.sv \
../src/*/*.sv \
../src/*/*/*.sv \
@ -54,8 +56,10 @@ vlog +incdir+../config/$1 \
vopt +acc work.testbench -G DEBUG=1 -o workopt
eval vsim workopt +nowarn3829 -fatal 7 \
-sv_lib $env(IMPERAS_HOME)/lib/Linux64/ImperasLib/imperas.com/verification/riscv/1.0/model \
+testDir=$env(TESTDIR) $env(OTHERFLAGS) +TRACE2COV_ENABLE=1 \
-do "coverage save -onexit ./riscv.ucdb"
+testDir=$env(TESTDIR) $env(OTHERFLAGS) +TRACE2COV_ENABLE=1
coverage save -onexit ./riscv.ucdb
view wave
#-- display input and output signals as hexidecimal values
@ -64,7 +68,7 @@ view wave
run -all
noview ../testbench/testbench_imperas.sv
noview ../testbench/testbench-imperas.sv
view wave
quit -f

0
sim/wally-imperas-no-idv.do → sim/questa/wally-imperas-no-idv.do
View file

0
sim/wally-imperas.do → sim/questa/wally-imperas.do
View file

0
sim/wally-linux-imperas.do → sim/questa/wally-linux-imperas.do
View file

141
sim/questa/wally.do Normal file
View file

@ -0,0 +1,141 @@
# wally-batch.do
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
#
# Modification by Oklahoma State University & Harvey Mudd College
# Use with Testbench
# James Stine, 2008; David Harris 2021
# Go Cowboys!!!!!!
#
# Takes 1:10 to run RV64IC tests using gui
# Usage: do wally-batch.do <config> <testcases> <testbench> [-coverage] [+acc] [any number of +value] [any number of -G VAR=VAL]
# Example: do wally-batch.do rv64gc arch64i testbench
# Use this wally-batch.do file to run this example.
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
# do wally-batch.do
# or, to run from a shell, type the following at the shell prompt:
# vsim -do wally-batch.do -c
# (omit the "-c" to see the GUI while running from the shell)
onbreak {resume}
set CFG ${1}
set TESTSUITE ${2}
set TESTBENCH ${3}
set WKDIR wkdir/${CFG}_${TESTSUITE}
set WALLY $::env(WALLY)
set CONFIG ${WALLY}/config
set SRC ${WALLY}/src
set TB ${WALLY}/testbench
# create library
if [file exists ${WKDIR}] {
vdel -lib ${WKDIR} -all
}
vlib ${WKDIR}
# Create directory for coverage data
mkdir -p cov
set coverage 0
set CoverageVoptArg ""
set CoverageVsimArg ""
# Need to be able to pass arguments to vopt. Unforunately argv does not work because
# it takes on different values if vsim and the do file are called from the command line or
# if the do file isd called from questa sim directly. This chunk of code uses the $4 through $n
# variables and compacts into a single list for passing to vopt.
set tbArgs ""
set from 4
set step 1
set lst {}
set GUI 0
set PlusArgs {}
set ParamArgs {}
set accFlag ""
for {set i 0} true {incr i} {
set x [expr {$i*$step + $from}]
if {$x > $argc} break
set arg [expr "$$x"]
lappend lst $arg
}
if {$argc >= 3} {
if {[lindex $lst [expr { [llength $lst] -1 } ]] eq "+acc"} {
set GUI 1
set accFlag "+acc"
set tbArgs [lrange $lst 0 end-1]
} else {
set tbArgs $lst
}
set tbArgsLst [split $lst " "]
# separate the +args from the -G parameters
foreach otherArg $tbArgsLst {
if {[string index $otherArg 0] eq "+"} {
lappend PlusArgs $otherArg
} else {
lappend ParamArgs $otherArg
}
}
#echo "PlusArgs"
#echo $PlusArgs
#echo "ParamArgs"
#echo $ParamArgs
#echo "accFlag"
#echo $accFlag
#if {$3 eq "-coverage" || ($argc >= 7 && $7 eq "-coverage")} {
# set coverage 1
# set CoverageVoptArg "+cover=sbecf"
# set CoverageVsimArg "-coverage"
#} elseif {$3 eq "tbArgs"} {
# set tbArgs $lst
# puts $tbArgs
#}
}
# compile source files
# suppress spurious warnngs about
# "Extra checking for conflicts with always_comb done at vopt time"
# because vsim will run vopt
vlog -lint -work ${WKDIR} +incdir+${CONFIG}/$1 +incdir+${CONFIG}/deriv/$1 +incdir+${CONFIG}/shared ${SRC}/cvw.sv ${TB}/${TESTBENCH}.sv ${TB}/common/*.sv ${SRC}/*/*.sv ${SRC}/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286
# start and run simulation
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
vopt $accFlag wkdir/${CFG}_${TESTSUITE}.${TESTBENCH} -work ${WKDIR} ${tbArgs} -o testbenchopt ${CoverageVoptArg}
# *** tbArgs producees a warning that TEST not found in design when running sim-testfloat-batch. Need to separate -G and + arguments to pass separately to vopt and vsim
vsim -lib ${WKDIR} testbenchopt +TEST=${TESTSUITE} ${PlusArgs} -fatal 7 -suppress 3829 ${CoverageVsimArg}
# vsim -lib wkdir/work_${1}_${2} testbenchopt -fatal 7 -suppress 3829
# power add generates the logging necessary for said generation.
# power add -r /dut/core/*
if { ${GUI} } {
add log -recursive /*
if { ${TESTBENCH} eq "testbench_fp" } {
do wave-fpu.do
} else {
do wave.do
}
}
run -all
# power off -r /dut/core/*
if {$coverage} {
set UCDB cov/${CFG}_${TESTSUITE}.ucdb
echo "Saving coverage to ${UCDB}"
do coverage-exclusions-rv64gc.do # beware: this assumes testing the rv64gc configuration
coverage save -instance /testbench/dut/core ${UCDB}
}
# These aren't doing anything helpful
#profile report -calltree -file wally-calltree.rpt -cutoff 2
#power report -all -bsaif power.saif
# terminate simulation unless we need to keep the GUI running
if { ${GUI} == 0} {
quit
}

30
sim/questa/wave-fpu.do Normal file
View file

@ -0,0 +1,30 @@
add wave -noupdate /testbench_fp/clk
add wave -noupdate -radix decimal /testbench_fp/VectorNum
add wave -noupdate /testbench_fp/FrmNum
add wave -noupdate /testbench_fp/X
add wave -noupdate /testbench_fp/Y
add wave -noupdate /testbench_fp/Z
add wave -noupdate /testbench_fp/Res
add wave -noupdate /testbench_fp/Ans
add wave -noupdate /testbench_fp/reset
add wave -noupdate /testbench_fp/DivStart
add wave -noupdate /testbench_fp/FDivBusyE
add wave -noupdate /testbench_fp/CheckNow
add wave -noupdate /testbench_fp/DivDone
add wave -noupdate /testbench_fp/ResMatch
add wave -noupdate /testbench_fp/FlagMatch
add wave -noupdate /testbench_fp/CheckNow
add wave -noupdate /testbench_fp/NaNGood
add wave -group {PostProc} -noupdate /testbench_fp/postprocess/*
add wave -group {PostProc} -noupdate /testbench_fp/postprocess/specialcase/*
add wave -group {PostProc} -noupdate /testbench_fp/postprocess/flags/*
add wave -group {PostProc} -noupdate /testbench_fp/postprocess/normshift/*
add wave -group {PostProc} -noupdate /testbench_fp/postprocess/shiftcorrection/*
add wave -group {PostProc} -noupdate /testbench_fp/postprocess/resultsign/*
add wave -group {PostProc} -noupdate /testbench_fp/postprocess/round/*
add wave -group {PostProc} -noupdate /testbench_fp/postprocess/fmashiftcalc/*
add wave -group {PostProc} -noupdate /testbench_fp/postprocess/divshiftcalc/*
add wave -group {PostProc} -noupdate /testbench_fp/postprocess/cvtshiftcalc/*
add wave -group {Testbench} -noupdate /testbench_fp/*
add wave -group {Testbench} -noupdate /testbench_fp/readvectors/*

129
sim/wave.do → sim/questa/wave.do
View file

@ -6,43 +6,43 @@ add wave -noupdate /testbench/reset
add wave -noupdate /testbench/memfilename
add wave -noupdate /testbench/dut/core/SATP_REGW
add wave -noupdate /testbench/dut/core/InstrValidM
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/RetM
add wave -noupdate -expand -group HDU -expand -group hazards -color Pink /testbench/dut/core/hzu/TrapM
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/ieu/c/LoadStallD
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/ifu/IFUStallF
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/BPWrongE
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/LSUStallM
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/ieu/c/MDUStallD
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/DivBusyE
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/FDivBusyE
add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM
add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM
add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM
add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM
add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM
add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM
add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM
add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM
add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM
add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM
add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM
add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM
add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InterruptM
add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/HPTWInstrAccessFaultM
add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/pmd/WFITimeoutM
add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushD
add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushE
add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushM
add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushW
add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallF
add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallD
add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallE
add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallM
add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallW
add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/core/priv/priv/trap/PendingIntsM
add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/core/priv/priv/trap/InstrValidM
add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/core/priv/priv/trap/ValidIntsM
add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/core/hzu/WFIInterruptedM
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/RetM
add wave -noupdate -group HDU -expand -group hazards -color Pink /testbench/dut/core/hzu/TrapM
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/ieu/c/LoadStallD
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/ifu/IFUStallF
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/BPWrongE
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/LSUStallM
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/ieu/c/MDUStallD
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/DivBusyE
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/FDivBusyE
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InterruptM
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/HPTWInstrAccessFaultM
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/pmd/WFITimeoutM
add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushD
add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushE
add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushM
add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushW
add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallF
add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallD
add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallE
add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallM
add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallW
add wave -noupdate -group HDU -group interrupts /testbench/dut/core/priv/priv/trap/PendingIntsM
add wave -noupdate -group HDU -group interrupts /testbench/dut/core/priv/priv/trap/InstrValidM
add wave -noupdate -group HDU -group interrupts /testbench/dut/core/priv/priv/trap/ValidIntsM
add wave -noupdate -group HDU -group interrupts /testbench/dut/core/hzu/WFIInterruptedM
add wave -noupdate -group {instruction pipeline} /testbench/InstrFName
add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/PostSpillInstrRawF
add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrD
@ -205,7 +205,6 @@ add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/SrcAE
add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/SrcBE
add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/ALUResultE
add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/ResultW
add wave -noupdate -expand -group {Memory Stage} /testbench/FunctionName/FunctionName/FunctionName
add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrValidM
add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/PCM
add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrM
@ -256,7 +255,6 @@ add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-update-c
add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid
add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty
add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/SelWay
add wave -noupdate -expand -group lsu -expand -group dcache -group {requesting address} /testbench/dut/core/lsu/IEUAdrE
add wave -noupdate -expand -group lsu -expand -group dcache -group {requesting address} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr
add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLineWay
@ -265,7 +263,7 @@ add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs
add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/Tag
add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/ValidWay
add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs -color {Blue Violet} /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit
add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs -color {Blue Violet} /testbench/dut/core/lsu/bus/dcache/dcache/Hit
add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/DirtyWay
add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/HitDirtyWay
@ -294,7 +292,6 @@ add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM w
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/LineByteMask
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelData}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearValidWay}
@ -316,7 +313,6 @@ add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM w
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/bwe}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/RAM}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelNonHit}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelData}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ClearValidWay}
@ -410,30 +406,29 @@ add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dm
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/SelHPTW
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWStall
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/DTLBWalk
add wave -noupdate -expand -group lsu -expand -group ptwalker -color Gold /testbench/dut/core/lsu/hptw/hptw/WalkerState
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/NextWalkerState
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWAdr
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PTE
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/NextPageType
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PageType
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/ValidNonLeafPTE
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/ITLBMissF
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/DTLBMissM
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/ITLBWriteF
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/DTLBWriteM
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWFaultM
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUAccessFaultM
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/DCacheStallM
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFaultF
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSULoadAccessFaultM
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUStoreAmoAccessFaultM
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LoadAccessFaultM
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/StoreAmoAccessFaultM
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFault
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/PBMTFaultM
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/SelHPTW
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWStall
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/DTLBWalk
add wave -noupdate -expand -group lsu -group ptwalker -color Gold /testbench/dut/core/lsu/hptw/hptw/WalkerState
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/NextWalkerState
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWAdr
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PTE
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/NextPageType
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PageType
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/ValidNonLeafPTE
add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/ITLBMissF
add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/DTLBMissM
add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/ITLBWriteF
add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/DTLBWriteM
add wave -noupdate -expand -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWFaultM
add wave -noupdate -expand -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUAccessFaultM
add wave -noupdate -expand -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFaultF
add wave -noupdate -expand -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSULoadAccessFaultM
add wave -noupdate -expand -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUStoreAmoAccessFaultM
add wave -noupdate -expand -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LoadAccessFaultM
add wave -noupdate -expand -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/StoreAmoAccessFaultM
add wave -noupdate -expand -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFault
add wave -noupdate -expand -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/PBMTFaultM
add wave -noupdate -group {WriteBack stage} /testbench/InstrW
add wave -noupdate -group {WriteBack stage} /testbench/InstrWName
add wave -noupdate -group {WriteBack stage} /testbench/dut/core/priv/priv/pmd/wfiW
@ -682,4 +677,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {11566 ns} {11760 ns}
WaveRestoreZoom {0 ns} {284634 ns}

499
sim/regression-wally
View file

@ -1,499 +0,0 @@
#!/usr/bin/python3
##################################
#
# regression-wally
# David_Harris@Hmc.edu 25 January 2021
# Modified by Jarred Allen <jaallen@g.hmc.edu>
#
# Run a regression with multiple configurations in parallel and exit with
# non-zero status code if an error happened, as well as printing human-readable
# output.
#
##################################
import sys,os,shutil
import multiprocessing
class bcolors:
HEADER = '\033[95m'
OKBLUE = '\033[94m'
OKCYAN = '\033[96m'
OKGREEN = '\033[92m'
WARNING = '\033[93m'
FAIL = '\033[91m'
ENDC = '\033[0m'
BOLD = '\033[1m'
UNDERLINE = '\033[4m'
from collections import namedtuple
regressionDir = os.path.dirname(os.path.abspath(__file__))
os.chdir(regressionDir)
coverage = '-coverage' in sys.argv
fp = '-fp' in sys.argv
nightly = '-nightly' in sys.argv
softfloat = '-softfloat' in sys.argv
soc = '-soc' in sys.argv
TestCase = namedtuple("TestCase", ['name', 'variant', 'cmd', 'grepstr'])
# name: the name of this test configuration (used in printing human-readable
# output and picking logfile names)
# cmd: the command to run to test (should include the logfile as '{}', and
# the command needs to write to that file)
# grepstr: the string to grep through the log file for. The test succeeds iff
# grep finds that string in the logfile (is used by grep, so it may
# be any pattern grep accepts, see `man 1 grep` for more info).
# edit this list to add more test cases
if (nightly):
nightMode = "-nightly";
configs = []
else:
nightMode = "";
configs = [
TestCase(
name="lints",
variant="all",
cmd="./lint-wally " + nightMode + " | tee {}",
grepstr="lints run with no errors or warnings"
)
]
def getBuildrootTC(boot):
INSTR_LIMIT = 1000000 # multiple of 100000; 4M is interesting because it gets into the kernel and enabling VM
MAX_EXPECTED = 246000000 # *** TODO: replace this with a search for the login prompt.
if boot:
name="buildrootboot"
BRcmd="vsim > {} -c <<!\ndo wally.do buildroot buildroot-no-trace $RISCV 0 1 0\n!"
BRgrepstr="WallyHostname login:"
else:
name="buildroot"
if (coverage):
print( "buildroot coverage")
BRcmd="vsim > {} -c <<!\ndo wally-batch.do buildroot buildroot $RISCV "+str(INSTR_LIMIT)+" 1 0 -coverage\n!"
else:
print( "buildroot no coverage")
BRcmd="vsim > {} -c <<!\ndo wally-batch.do buildroot buildroot configOptions -GINSTR_LIMIT=" +str(INSTR_LIMIT) + " \n!"
BRgrepstr=str(INSTR_LIMIT)+" instructions"
return TestCase(name,variant="rv64gc",cmd=BRcmd,grepstr=BRgrepstr)
tests64gcimperas = ["imperas64i", "imperas64f", "imperas64d", "imperas64m", "imperas64c"] # unused
tests64i = ["arch64i"]
for test in tests64i:
tc = TestCase(
name=test,
variant="rv64i",
cmd="vsim > {} -c <<!\ndo wally-batch.do rv64i "+test+"\n!",
grepstr="All tests ran without failures")
configs.append(tc)
tests32gcimperas = ["imperas32i", "imperas32f", "imperas32m", "imperas32c"] # unused
tests32gc = ["arch32f", "arch32d", "arch32f_fma", "arch32d_fma", "arch32f_divsqrt", "arch32d_divsqrt", "arch32i", "arch32priv", "arch32c", "arch32m", "arch32a", "arch32zifencei", "arch32zicond", "arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "arch32zfh", "arch32zfh_fma", "arch32zfh_divsqrt", "arch32zfaf", "wally32a", "wally32priv", "wally32periph", "arch32zbkb", "arch32zbkc", "arch32zbkx", "arch32zknd", "arch32zkne", "arch32zknh"] # "arch32zbc", "arch32zfad",
#tests32gc = ["arch32f", "arch32d", "arch32f_fma", "arch32d_fma", "arch32i", "arch32priv", "arch32c", "arch32m", "arch32a", "arch32zifencei", "arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "arch32zicboz", "arch32zcb", "wally32a", "wally32priv", "wally32periph"]
for test in tests32gc:
tc = TestCase(
name=test,
variant="rv32gc",
cmd="vsim > {} -c <<!\ndo wally-batch.do rv32gc "+test+"\n!",
grepstr="All tests ran without failures")
configs.append(tc)
tests32imcimperas = ["imperas32i", "imperas32c"] # unused
tests32imc = ["arch32i", "arch32c", "arch32m", "wally32periph"]
for test in tests32imc:
tc = TestCase(
name=test,
variant="rv32imc",
cmd="vsim > {} -c <<!\ndo wally-batch.do rv32imc "+test+"\n!",
grepstr="All tests ran without failures")
configs.append(tc)
tests32i = ["arch32i"]
for test in tests32i:
tc = TestCase(
name=test,
variant="rv32i",
cmd="vsim > {} -c <<!\ndo wally-batch.do rv32i "+test+"\n!",
grepstr="All tests ran without failures")
configs.append(tc)
tests32e = ["arch32e"]
for test in tests32e:
tc = TestCase(
name=test,
variant="rv32e",
cmd="vsim > {} -c <<!\ndo wally-batch.do rv32e "+test+"\n!",
grepstr="All tests ran without failures")
configs.append(tc)
tests64gc = ["arch64f", "arch64d", "arch64f_fma", "arch64d_fma", "arch64f_divsqrt", "arch64d_divsqrt", "arch64i", "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs", "arch64zfh", "arch64zfh_divsqrt", "arch64zfh_fma", "arch64zfaf", "arch64zfad", "arch64zbkb", "arch64zbkc", "arch64zbkx", "arch64zknd", "arch64zkne", "arch64zknh",
"arch64priv", "arch64c", "arch64m", "arch64a", "arch64zifencei", "arch64zicond", "wally64a", "wally64periph", "wally64priv"] # add arch64zfh_fma when available; arch64zicobz, arch64zcb when working
#tests64gc = ["arch64f", "arch64d", "arch64f_fma", "arch64d_fma", "arch64i", "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs",
# "arch64priv", "arch64c", "arch64m", "arch64a", "arch64zifencei", "wally64a", "wally64periph", "wally64priv", "arch64zicboz", "arch64zcb"]
if (coverage): # delete all but 64gc tests when running coverage
configs = []
tests64gc = ["coverage64gc", "arch64i", "arch64priv", "arch64c", "arch64m",
"arch64zifencei", "arch64zicond", "arch64a", "wally64a", "wally64periph", "wally64priv",
"arch64zba", "arch64zbb", "arch64zbc", "arch64zbs"] # add when working: "arch64zcb", "arch64zicboz"
if (fp):
tests64gc.append("arch64f")
tests64gc.append("arch64d")
tests64gc.append("arch64zfh")
tests64gc.append("arch64f_fma")
tests64gc.append("arch64d_fma")
tests64gc.append("arch64zfh_fma")
tests64gc.append("arch64f_divsqrt")
tests64gc.append("arch64d_divsqrt")
tests64gc.append("arch64zfh_divsqrt")
tests64gc.append("arch64zfaf")
tests64gc.append("arch64zfad")
coverStr = '-coverage'
else:
coverStr = ''
for test in tests64gc:
tc = TestCase(
name=test,
variant="rv64gc",
cmd="vsim > {} -c <<!\ndo wally-batch.do rv64gc "+test+" " + coverStr + "\n!",
grepstr="All tests ran without failures")
configs.append(tc)
# run derivative configurations if requested
if (nightly):
derivconfigtests = [
["tlb2_rv32gc", ["wally32priv"]],
["tlb16_rv32gc", ["wally32priv"]],
["tlb2_rv64gc", ["wally64priv"]],
["tlb16_rv64gc", ["wally64priv"]],
["way_1_4096_512_rv32gc", ["arch32i"]],
["way_2_4096_512_rv32gc", ["arch32i"]],
["way_8_4096_512_rv32gc", ["arch32i"]],
["way_4_2048_512_rv32gc", ["arch32i"]],
["way_4_4096_256_rv32gc", ["arch32i"]],
["way_1_4096_512_rv64gc", ["arch64i"]],
["way_2_4096_512_rv64gc", ["arch64i"]],
["way_8_4096_512_rv64gc", ["arch64i"]],
["way_4_2048_512_rv64gc", ["arch64i"]],
["way_4_4096_256_rv64gc", ["arch64i"]],
["way_4_4096_1024_rv64gc", ["arch64i"]],
["ram_0_0_rv64gc", ["ahb64"]],
["ram_1_0_rv64gc", ["ahb64"]],
["ram_1_1_rv64gc", ["ahb64"]],
["ram_2_0_rv64gc", ["ahb64"]],
["ram_2_1_rv64gc", ["ahb64"]],
["noicache_rv32gc", ["ahb32"]],
# cacheless designs will not work until DTIM supports FLEN > XLEN
# ["nodcache_rv32gc", ["ahb32"]],
# ["nocache_rv32gc", ["ahb32"]],
["noicache_rv64gc", ["ahb64"]],
["nodcache_rv64gc", ["ahb64"]],
["nocache_rv64gc", ["ahb64"]],
### add misaligned tests
["div_2_1_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
["div_2_1i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
["div_2_2_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
["div_2_2i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
["div_2_4_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
["div_2_4i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
["div_4_1_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
["div_4_1i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
["div_4_2_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
["div_4_2i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
["div_4_4_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
["div_4_4i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
["div_2_1_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
["div_2_1i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
["div_2_2_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
["div_2_2i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
["div_2_4_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
["div_2_4i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
["div_4_1_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
["div_4_1i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
["div_4_2_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
["div_4_2i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
["div_4_4_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
["div_4_4i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
### branch predictor simulation
# ["bpred_TWOBIT_6_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
# ["bpred_TWOBIT_8_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
# ["bpred_TWOBIT_10_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
# ["bpred_TWOBIT_12_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
# ["bpred_TWOBIT_14_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
# ["bpred_TWOBIT_16_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
# ["bpred_TWOBIT_6_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
# ["bpred_TWOBIT_8_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
# ["bpred_TWOBIT_10_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
# ["bpred_TWOBIT_12_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
# ["bpred_TWOBIT_14_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
# ["bpred_TWOBIT_16_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
# ["bpred_GSHARE_6_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
# ["bpred_GSHARE_6_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
# ["bpred_GSHARE_8_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
# ["bpred_GSHARE_8_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
# ["bpred_GSHARE_10_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
# ["bpred_GSHARE_10_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
# ["bpred_GSHARE_12_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
# ["bpred_GSHARE_12_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
# ["bpred_GSHARE_14_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
# ["bpred_GSHARE_14_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
# ["bpred_GSHARE_16_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
# ["bpred_GSHARE_16_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
# # btb
# ["bpred_GSHARE_10_16_6_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
# ["bpred_GSHARE_10_16_6_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
# ["bpred_GSHARE_10_16_8_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
# ["bpred_GSHARE_10_16_8_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
# ["bpred_GSHARE_10_16_12_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
# ["bpred_GSHARE_10_16_12_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
# # ras
# ["bpred_GSHARE_10_2_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
# ["bpred_GSHARE_10_2_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
# ["bpred_GSHARE_10_3_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
# ["bpred_GSHARE_10_3_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
# ["bpred_GSHARE_10_4_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
# ["bpred_GSHARE_10_4_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
# ["bpred_GSHARE_10_6_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
# ["bpred_GSHARE_10_6_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
# ["bpred_GSHARE_10_10_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
# ["bpred_GSHARE_10_10_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
# enable floating-point tests when lint is fixed
["f_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma"]],
["fh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32zfh", "arch32zfh_divsqrt"]],
["fdh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32d", "arch32d_divsqrt", "arch32d_fma", "arch32zfh", "arch32zfh_divsqrt"]],
["fdq_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32d", "arch32d_divsqrt", "arch32d_fma", "arch32i"]],
["fdqh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32d", "arch32d_divsqrt", "arch32d_fma", "arch32zfh", "arch32zfh_divsqrt", "arch32i"]],
["f_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma"]],
["fh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64zfh", "arch64zfh_divsqrt"]], # hanging 1/31/24 dh; try again when lint is fixed
["fdh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64zfh", "arch64zfh_divsqrt"]],
["fdq_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64i"]],
["fdqh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64zfh", "arch64zfh_divsqrt", "arch64i", "wally64q"]],
]
for test in derivconfigtests:
config = test[0];
tests = test[1];
if(len(test) >= 4 and test[2] == "configOptions"):
configOptions = test[3]
cmdPrefix = "vsim > {} -c <<!\ndo wally-batch.do "+config
else:
configOptions = ""
cmdPrefix = "vsim > {} -c <<!\ndo wally-batch.do "+config
for t in tests:
tc = TestCase(
name=t,
variant=config,
cmd=cmdPrefix+" "+t+" configOptions "+configOptions+"\n!",
grepstr="All tests ran without failures")
configs.append(tc)
tests32e = ["arch32e"]
for test in tests32e:
tc = TestCase(
name=test,
variant="rv32e",
cmd="vsim > {} -c <<!\ndo wally-batch.do rv32e "+test+"\n!",
grepstr="All tests ran without failures")
configs.append(tc)
# softfloat tests
if (softfloat):
configs = []
softfloatconfigs = ['fdh_ieee_rv32gc', 'fdqh_ieee_rv32gc', 'fdq_ieee_rv32gc', \
'fh_ieee_v32gc', 'f_ieee_rv64gc', 'fdqh_ieee_rv64gc', \
'fdq_ieee_rv64gc', 'div_2_1_rv32gc', 'div_2_2_rv32gc', \
'div_2_4_rv32gc', 'div_4_1_rv32gc', 'div_4_2_rv32gc', \
'div_4_4_rv32gc', 'fd_ieee_rv32gc', 'fh_ieee_rv32gc', \
'div_2_1_rv64gc', 'div_2_2_rv64gc', 'div_2_4_rv64gc', \
'div_4_1_rv64gc', 'div_4_2_rv64gc', 'div_4_4_rv64gc', \
'fd_ieee_rv64gc', 'fh_ieee_rv64gc', 'f_ieee_rv32gc']
softfloatconfigs = ['fdh_ieee_div_2_1_rv32gc', 'fdh_ieee_div_2_1_rv64gc', \
'fdh_ieee_div_2_2_rv32gc', 'fdh_ieee_div_2_2_rv64gc', 'fdh_ieee_div_2_4_rv32gc', \
'fdh_ieee_div_2_4_rv64gc', 'fdh_ieee_div_4_1_rv32gc', 'fdh_ieee_div_4_1_rv64gc', \
'fdh_ieee_div_4_2_rv32gc', 'fdh_ieee_div_4_2_rv64gc', 'fdh_ieee_div_4_4_rv64gc', \
'fdh_ieee_rv32gc', 'fd_ieee_div_2_1_rv32gc', 'fd_ieee_div_2_1_rv64gc', \
'fd_ieee_div_2_2_rv32gc', 'fd_ieee_div_2_2_rv64gc', 'fd_ieee_div_2_4_rv32gc', \
'fd_ieee_div_2_4_rv64gc', 'fd_ieee_div_4_1_rv32gc', 'fd_ieee_div_4_1_rv64gc', \
'fd_ieee_div_4_2_rv32gc', 'fd_ieee_div_4_2_rv64gc', 'fd_ieee_div_4_4_rv64gc', \
'fd_ieee_rv32gc', 'fd_ieee_rv64gc', 'fdqh_ieee_div_2_1_rv32gc', \
'fdqh_ieee_div_2_1_rv64gc', 'fdqh_ieee_div_2_2_rv32gc', 'fdqh_ieee_div_2_2_rv64gc', \
'fdqh_ieee_div_2_4_rv32gc', 'fdqh_ieee_div_2_4_rv64gc', 'fdqh_ieee_div_4_1_rv32gc', \
'fdqh_ieee_div_4_1_rv64gc', 'fdqh_ieee_div_4_2_rv32gc', 'fdqh_ieee_div_4_2_rv64gc',\
'fdqh_ieee_div_4_4_rv64gc', 'fdqh_ieee_rv32gc', 'fdqh_ieee_rv64gc', \
'fdq_ieee_div_2_1_rv32gc', 'fdq_ieee_div_2_1_rv64gc', 'fdq_ieee_div_2_2_rv32gc',\
'fdq_ieee_div_2_2_rv64gc', 'fdq_ieee_div_2_4_rv32gc', 'fdq_ieee_div_2_4_rv64gc', \
'fdq_ieee_div_4_1_rv32gc', 'fdq_ieee_div_4_1_rv64gc', 'fdq_ieee_div_4_2_rv32gc', \
'fdq_ieee_div_4_2_rv64gc', 'fdq_ieee_div_4_4_rv64gc', 'fdq_ieee_rv32gc', \
'fdq_ieee_rv64gc', 'fh_ieee_div_2_1_rv32gc', 'fh_ieee_div_2_1_rv64gc', \
'fh_ieee_div_2_2_rv32gc', 'fh_ieee_div_2_2_rv64gc', 'fh_ieee_div_2_4_rv32gc',\
'fh_ieee_div_2_4_rv64gc', 'fh_ieee_div_4_1_rv32gc', 'fh_ieee_div_4_1_rv64gc',\
'fh_ieee_div_4_2_rv32gc', 'fh_ieee_div_4_2_rv64gc', 'fh_ieee_div_4_4_rv64gc', \
'fh_ieee_rv32gc', 'fh_ieee_rv64gc', 'fh_ieee_v32gc', 'f_ieee_div_2_1_rv32gc', \
'f_ieee_div_2_1_rv64gc', 'f_ieee_div_2_2_rv32gc', 'f_ieee_div_2_2_rv64gc', \
'f_ieee_div_2_4_rv32gc', 'f_ieee_div_2_4_rv64gc', 'f_ieee_div_4_1_rv32gc', \
'f_ieee_div_4_1_rv64gc', 'f_ieee_div_4_2_rv32gc', 'f_ieee_div_4_2_rv64gc', \
'f_ieee_div_4_4_rv64gc', 'f_ieee_rv32gc', 'f_ieee_rv64gc']
for config in softfloatconfigs:
# div test case
divtest = TestCase(
name="div",
variant=config,
cmd="vsim > {} -c <<!\ndo testfloat-batch.do " + config + " div \n!",
grepstr="All Tests completed with 0 errors"
)
configs.insert(0,divtest)
# sqrt test case
sqrttest = TestCase(
name="sqrt",
variant=config,
cmd="vsim > {} -c <<!\ndo testfloat-batch.do " + config + " sqrt \n!",
grepstr="All Tests completed with 0 errors"
)
#configs.append(sqrttest)
configs.insert(0,sqrttest)
# skip if divider variant config
if ("ieee" in config):
# cvtint test case
cvtinttest = TestCase(
name="cvtint",
variant=config,
cmd="vsim > {} -c <<!\ndo testfloat-batch.do " + config + " cvtint \n!",
grepstr="All Tests completed with 0 errors"
)
configs.append(cvtinttest)
# cvtfp test case
# WILL fail on F_only (refer to spec)
cvtfptest = TestCase(
name="cvtfp",
variant=config,
cmd="vsim > {} -c <<!\ndo testfloat-batch.do " + config + " cvtfp \n!",
grepstr="All Tests completed with 0 errors"
)
configs.append(cvtfptest)
if (soc):
print('Running soc coverage')
configs = [] # Delete all configs, just use test64gc
coverStr = '-coverage' # Include coverage report
for test in tests64gc:
if any(s in test for s in ['zfa', 'zfh', 'zbk', 'zkn']):
continue # Skip tests for extensions that aren't in riscv-arch-tests yet
tc = TestCase(
name=test,
variant="rv64gc",
cmd="vsim > {} -c <<!\ndo wally-soc.do rv64gc "+test+" " + coverStr + "\n!",
grepstr="All tests ran without failures")
configs.append(tc)
import os
from multiprocessing import Pool, TimeoutError
def search_log_for_text(text, logfile):
"""Search through the given log file for text, returning True if it is found or False if it is not"""
grepcmd = "grep -e '%s' '%s' > /dev/null" % (text, logfile)
return os.system(grepcmd) == 0
def run_test_case(config):
"""Run the given test case, and return 0 if the test suceeds and 1 if it fails"""
logname = "logs/"+config.variant+"_"+config.name+".log"
cmd = config.cmd.format(logname)
# print(cmd)
os.chdir(regressionDir)
os.system(cmd)
if search_log_for_text(config.grepstr, logname):
print(f"{bcolors.OKGREEN}%s_%s: Success{bcolors.ENDC}" % (config.variant, config.name))
return 0
else:
print(f"{bcolors.FAIL}%s_%s: Failures detected in output{bcolors.ENDC}" % (config.variant, config.name))
print(" Check %s" % logname)
return 1
def main():
"""Run the tests and count the failures"""
global configs, coverage
try:
os.chdir(regressionDir)
os.mkdir("logs")
except:
pass
try:
shutil.rmtree("wkdir")
except:
pass
finally:
os.mkdir("wkdir")
if '-makeTests' in sys.argv:
os.chdir(regressionDir)
os.system('./make-tests.sh | tee ./logs/make-tests.log')
if '-all' in sys.argv:
TIMEOUT_DUR = 30*7200 # seconds
configs.append(getBuildrootTC(boot=True))
elif '-buildroot' in sys.argv:
TIMEOUT_DUR = 30*7200 # seconds
configs=[getBuildrootTC(boot=True)]
elif '-coverage' in sys.argv:
TIMEOUT_DUR = 20*60 # seconds
# Presently don't run buildroot because it has a different config and can't be merged with the rv64gc coverage.
# Also it is slow to run.
# configs.append(getBuildrootTC(boot=False))
os.system('rm -f cov/*.ucdb')
elif '-nightly' in sys.argv:
TIMEOUT_DUR = 60*1440 # 1 day
configs.append(getBuildrootTC(boot=False))
elif '-softfloat' in sys.argv:
TIMEOUT_DUR = 60*60 # seconds
elif '-soc' in sys.argv:
TIMEOUT_DUR = 20*60 # seconds
# FIXME: Do we need to run buildroot?
else:
TIMEOUT_DUR = 10*60 # seconds
configs.append(getBuildrootTC(boot=False))
# Scale the number of concurrent processes to the number of test cases, but
# max out at a limited number of concurrent processes to not overwhelm the system
with Pool(processes=min(len(configs),multiprocessing.cpu_count())) as pool:
num_fail = 0
results = {}
for config in configs:
results[config] = pool.apply_async(run_test_case,(config,))
for (config,result) in results.items():
try:
num_fail+=result.get(timeout=TIMEOUT_DUR)
except TimeoutError:
num_fail+=1
print(f"{bcolors.FAIL}%s_%s: Timeout - runtime exceeded %d seconds{bcolors.ENDC}" % (config.variant, config.name, TIMEOUT_DUR))
# Coverage report
if coverage or soc:
os.system('make coverage')
# Count the number of failures
if num_fail:
print(f"{bcolors.FAIL}Regression failed with %s failed configurations{bcolors.ENDC}" % num_fail)
else:
print(f"{bcolors.OKGREEN}SUCCESS! All tests ran without failures{bcolors.ENDC}")
return num_fail
if __name__ == '__main__':
exit(main())

2
sim/run-imperas-linux.sh
View file

@ -7,4 +7,4 @@ export OTHERFLAGS="+TRACE2LOG_ENABLE=1 +TRACE2LOG_AFTER=100"
#export OTHERFLAGS="+TRACE2LOG_ENABLE=1 +TRACE2LOG_AFTER=10500000"
#export OTHERFLAGS=""
vsim -do "do wally-linux-imperas.do buildroot buildroot $::env(RISCV) 0 0 0"
vsim -c -do "do wally-linux-imperas.do buildroot buildroot $::env(RISCV) 0 0 0"

33
sim/sim-buildroot
View file

@ -1,33 +0,0 @@
#!/bin/bash
# Defaults
INSTR_LIMIT=0
INSTR_WAVEON=1
CHECKPOINT=0
# Arg Parsing
for i in "$@"; do
case $i in
--INSTR_LIMIT=*)
INSTR_LIMIT="${i#*=}"
shift # past argument=value
;;
--INSTR_WAVEON=*)
INSTR_WAVEON="${i#*=}"
shift # past argument=value
;;
--CHECKPOINT=*)
CHECKPOINT="${i#*=}"
shift # past argument=value
;;
*)
# unknown option
;;
esac
done
echo "INSTR_LIMIT = ${INSTR_LIMIT}"
echo "INSTR_WAVEON = ${INSTR_WAVEON}"
echo "CHECKPOINT = ${CHECKPOINT}"
vsim -do "do ./wally.do buildroot buildroot $RISCV $INSTR_LIMIT $INSTR_WAVEON $CHECKPOINT"

36
sim/sim-buildroot-batch
View file

@ -1,36 +0,0 @@
#!/bin/bash
# Defaults
INSTR_LIMIT=0
INSTR_WAVEON=1
CHECKPOINT=0
# Arg Parsing
for i in "$@"; do
case $i in
--INSTR_LIMIT=*)
INSTR_LIMIT="${i#*=}"
shift # past argument=value
;;
--INSTR_WAVEON=*)
INSTR_WAVEON="${i#*=}"
shift # past argument=value
;;
--CHECKPOINT=*)
CHECKPOINT="${i#*=}"
shift # past argument=value
;;
*)
# unknown option
;;
esac
done
echo "INSTR_LIMIT = ${INSTR_LIMIT}"
echo "INSTR_WAVEON = ${INSTR_WAVEON}"
echo "CHECKPOINT = ${CHECKPOINT}"
# *** change config from buildroot to rv64gc
vsim -c <<!
do wally-batch.do buildroot buildroot-no-trace $RISCV $INSTR_LIMIT $INSTR_WAVEON $CHECKPOINT
!

2
sim/sim-wally
View file

@ -1,2 +0,0 @@
vsim -do "do wally.do rv64gc wally64periph"

1
sim/sim-wally-batch
View file

@ -1 +0,0 @@
vsim -c -do "do wally-batch.do rv64gc wally64periph"

55
sim/testfloat-batch.do
View file

@ -1,55 +0,0 @@
# testfloat-batch.do
#
# Modification by Oklahoma State University & Harvey Mudd College
# Use with Testbench
# James Stine, 2008; David Harris 2021; Kevin Kim 2024
# Go Cowboys!!!!!!
#
# Takes 1:10 to run RV64IC tests using gui
# run with vsim -do "do wally.do rv64ic riscvarchtest-64m"
onbreak {resume}
# create library
if [file exists wkdir/work_${1}_${2}] {
vdel -lib wkdir/work_${1}_${2} -all
}
vlib wkdir/work_${1}_${2}
# c# compile source files
# suppress spurious warnngs about
# "Extra checking for conflicts with always_comb done at vopt time"
# because vsim will run vopt
# start and run simulation
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
# $num = the added words after the call
vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/deriv/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench-fp.sv ../src/fpu/*.sv ../src/fpu/*/*.sv ../src/generic/*.sv ../src/generic/flop/*.sv -suppress 2583,7063,8607,2697,7033
# Set WAV variable to avoid having any output to wave (to limit disk space)
quietly set WAV 0;
# Determine if nowave argument is provided this removes any output to
# a wlf or wave window to reduce disk space.
if {$WAV eq 0} {
puts "No wave output is selected"
} else {
puts "wave output is selected"
view wave
add log -recursive /*
do wave-fpu.do
}
# Change TEST_SIZE to only test certain FP width
# values are QP, DP, SP, HP or all for all tests
vopt +acc wkdir/work_${1}_${2}.testbenchfp -work wkdir/work_${1}_${2} -G TEST=$2 -G TEST_SIZE="all" -o testbenchopt
vsim -lib wkdir/work_${1}_${2} testbenchopt -fatal 7 -suppress 3829
#-- Run the Simulation
run -all

52
sim/testfloat.do
View file

@ -1,52 +0,0 @@
# testfloat.do
#
# Modification by Oklahoma State University & Harvey Mudd College
# Use with Testbench
# James Stine, 2008; David Harris 2021
# Go Cowboys!!!!!!
#
# Takes 1:10 to run RV64IC tests using gui
# run with vsim -do "do wally.do rv64ic riscvarchtest-64m"
onbreak {resume}
# create library
if [file exists work] {
vdel -all
}
vlib work
# compile source files
# suppress spurious warnngs about
# "Extra checking for conflicts with always_comb done at vopt time"
# because vsim will run vopt
# start and run simulation
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
# $num = the added words after the call
vlog +incdir+../config/deriv/$1 +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench-fp.sv ../src/fpu/*.sv ../src/fpu/*/*.sv ../src/generic/*.sv ../src/generic/flop/*.sv -suppress 2583,7063,8607,2697
# Change TEST_SIZE to only test certain FP width
# values are QP, DP, SP, HP or all for all tests
vsim -voptargs=+acc work.testbenchfp -GTEST=$2 -GTEST_SIZE="all"
# Set WAV variable to avoid having any output to wave (to limit disk space)
quietly set WAV 1;
# Determine if nowave argument is provided this removes any output to
# a wlf or wave window to reduce disk space.
if {$WAV eq 0} {
puts "No wave output is selected"
} else {
puts "wave output is selected"
view wave
add log -recursive /*
do wave-fpu.do
}
#-- Run the Simulation
run -all
noview testbench-fp.sv
view wave

25
sim/vcs/run_vcs.sh Executable file
View file

@ -0,0 +1,25 @@
#!/bin/bash
# Set CONFIG_VARIANT from the first script argument
#CONFIG_VARIANT=${1:-rv64i}
CONFIG_VARIANT=${1}
# Set TESTSUITE from the second script argument
TESTSUITE=$2
INCLUDE_DIRS=$(find ../src -type d | xargs -I {} echo -n "{} ")
SOURCE_PATH="+incdir+../config/${CONFIG_VARIANT} +incdir+../config/deriv/${CONFIG_VARIANT} +incdir+../config/shared +define+ +define+P.XLEN=64 +define+FPGA=0 +incdir+../testbench ../src/cvw.sv +incdir+../src"
SIMFILES="$INCLUDE_DIRS $(find ../src -name "*.sv" ! -path "../src/generic/clockgater.sv" ! -path "../src/generic/mem/rom1p1r_128x64.sv" ! -path "../src/generic/mem/ram2p1r1wbe_128x64.sv" ! -path "../src/generic/mem/rom1p1r_128x32.sv" ! -path "../src/generic/mem/ram2p1r1wbe_512x64.sv") ../testbench/testbench.sv $(find ../testbench/common -name "*.sv" ! -path "../testbench/common/wallyTracer.sv")"
OUTPUT="sim_out"
clean() {
rm -rf obj_dir work transcript vsim.wlf $OUTPUT *.vcd csrc ucli.key vc_hdrs.h program.out
rm -rf simv* *.daidir dve *.vpd *.dump DVEfiles/ verdi* novas* *fsdb* *.vg *.rep *.db *.chk *.log *.out profileReport* simprofile_dir*
}
# Clean and run simulation with VCS
clean
#vcs +lint=all,noGCWM -simprofile -sverilog +vc -Mupdate -line -full64 -kdb -lca -debug_access+all+reverse -v2k_generate ${SOURCE_PATH} +define+TEST=$TESTSUITE $SIMFILES -o $OUTPUT -error=NOODV
vcs +lint=all,noGCWM -simprofile -sverilog +vc -Mupdate -line -full64 -kdb -lca -debug_access+all+reverse -v2k_generate ${SOURCE_PATH} -pvalue+testbench.TEST=$TESTSUITE $SIMFILES -o $OUTPUT -error=NOODV
./$OUTPUT | tee program.out

0
sim/verilate → sim/verilator/verilate
View file

92
sim/wally-batch.do
View file

@ -1,92 +0,0 @@
# wally-batch.do
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
#
# Modification by Oklahoma State University & Harvey Mudd College
# Use with Testbench
# James Stine, 2008; David Harris 2021
# Go Cowboys!!!!!!
#
# Takes 1:10 to run RV64IC tests using gui
# Usage: do wally-batch.do <config> <testcases>
# Example: do wally-batch.do rv32imc imperas-32i
# Use this wally-batch.do file to run this example.
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
# do wally-batch.do
# or, to run from a shell, type the following at the shell prompt:
# vsim -do wally-batch.do -c
# (omit the "-c" to see the GUI while running from the shell)
onbreak {resume}
# create library
if [file exists wkdir/work_${1}_${2}] {
vdel -lib wkdir/work_${1}_${2} -all
}
vlib wkdir/work_${1}_${2}
# Create directory for coverage data
mkdir -p cov
set coverage 0
set CoverageVoptArg ""
set CoverageVsimArg ""
# Need to be able to pass arguments to vopt. Unforunately argv does not work because
# it takes on different values if vsim and the do file are called from the command line or
# if the do file isd called from questa sim directly. This chunk of code uses the $4 through $n
# variables and compacts into a single list for passing to vopt.
set configOptions ""
set from 4
set step 1
set lst {}
for {set i 0} true {incr i} {
set x [expr {$i*$step + $from}]
if {$x > $argc} break
set arg [expr "$$x"]
lappend lst $arg
}
if {$argc >= 3} {
if {$3 eq "-coverage" || ($argc >= 7 && $7 eq "-coverage")} {
set coverage 1
set CoverageVoptArg "+cover=sbecf"
set CoverageVsimArg "-coverage"
} elseif {$3 eq "configOptions"} {
set configOptions $lst
puts $configOptions
}
}
# compile source files
# suppress spurious warnngs about
# "Extra checking for conflicts with always_comb done at vopt time"
# because vsim will run vopt
# default to config/rv64ic, but allow this to be overridden at the command line. For example:
# do wally-pipelined-batch.do ../config/rv32imc rv32imc
vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/deriv/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286
# start and run simulation
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G TEST=$2 ${configOptions} -o testbenchopt ${CoverageVoptArg}
vsim -lib wkdir/work_${1}_${2} testbenchopt -fatal 7 -suppress 3829 ${CoverageVsimArg}
# vsim -lib wkdir/work_${1}_${2} testbenchopt -fatal 7 -suppress 3829
# power add generates the logging necessary for said generation.
# power add -r /dut/core/*
run -all
# power off -r /dut/core/*
if {$coverage} {
echo "Saving coverage to ${1}_${2}.ucdb"
do coverage-exclusions-rv64gc.do # beware: this assumes testing the rv64gc configuration
coverage save -instance /testbench/dut/core cov/${1}_${2}.ucdb
}
# These aren't doing anything helpful
#profile report -calltree -file wally-calltree.rpt -cutoff 2
#power report -all -bsaif power.saif
quit

120
sim/wally.do
View file

@ -1,120 +0,0 @@
# wally.do
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
#
# Modification by Oklahoma State University & Harvey Mudd College
# Use with Testbench
# James Stine, 2008; David Harris 2021
# Go Cowboys!!!!!!
#
# Takes 1:10 to run RV64IC tests using gui
# run with vsim -do "do wally-pipelined.do rv64ic riscvarchtest-64m"
# Use this wally-pipelined.do file to run this example.
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
# do wally.do
# or, to run from a shell, type the following at the shell prompt:
# vsim -do wally.do -c
# (omit the "-c" to see the GUI while running from the shell)
onbreak {resume}
# create library
if [file exists work] {
vdel -all
}
vlib work
# compile source files
# suppress spurious warnngs about
# "Extra checking for conflicts with always_comb done at vopt time"
# because vsim will run vopt
# start and run simulation
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
# start and run simulation
vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -G NO_SPOOFING=0 -o testbenchopt
vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829,13286 -fatal 7
#-- Run the Simulation
#run -all
add log -recursive /*
do linux-wave.do
run -all
exec ./slack-notifier/slack-notifier.py
} elseif {$2 eq "buildroot-no-trace"} {
vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
# start and run simulation
vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=0 -G INSTR_WAVEON=0 -G CHECKPOINT=0 -G NO_SPOOFING=1 -o testbenchopt
vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829,13286 -fatal 7
#-- Run the Simulation
echo "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!"
echo "Don't forget to change DEBUG_LEVEL = 0."
echo "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!"
#run 100 ns
#force -deposit testbench/dut/core/priv/priv/csr/csri/IE_REGW 16'h2aa
#force -deposit testbench/dut/uncore/uncore/clint/clint/MTIMECMP 64'h1000
run 14000 ms
#add log -recursive /*
#do linux-wave.do
#run -all
exec ./slack-notifier/slack-notifier.py
} elseif {$2 eq "fpga"} {
echo "hello"
vlog -work work +incdir+../config/fpga +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/sdc/*.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv ../../fpga/sim/*.sv -suppress 8852,12070,3084,3829,2583,7063,13286
vopt +acc work.testbench -G TEST=$2 -G DEBUG=0 -o workopt
vsim workopt +nowarn3829 -fatal 7
do fpga-wave.do
add log -r /*
run 20 ms
} else {
vlog +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583,13286 -suppress 7063
vopt +acc work.testbench -G TEST=$2 -G DEBUG=1 -o workopt
vsim workopt +nowarn3829 -fatal 7
view wave
#-- display input and output signals as hexidecimal values
#do ./wave-dos/peripheral-waves.do
add log -recursive /*
do wave.do
#do wave-bus.do
# power add generates the logging necessary for saif generation.
#power add -r /dut/core/*
#-- Run the Simulation
run -all
#power off -r /dut/core/*
#power report -all -bsaif power.saif
noview ../testbench/testbench.sv
view wave
}
#elseif {$2 eq "buildroot-no-trace""} {
# vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
# start and run simulation
# vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=470350800 -G INSTR_WAVEON=470350800 -G CHECKPOINT=470350800 -G DEBUG_TRACE=0 -o testbenchopt
# vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829
#-- Run the Simulation
# run 100 ns
# force -deposit testbench/dut/core/priv/priv/csr/csri/IE_REGW 16'h2aa
# force -deposit testbench/dut/uncore/uncore/clint/clint/MTIMECMP 64'h1000
# add log -recursive /*
# do linux-wave.do
# run -all
# exec ./slack-notifier/slack-notifier.py
#}

1606
sim/wave-all.do
View file

File diff suppressed because it is too large Load diff

100
sim/wave-dos/ahb-muldiv.do
View file

@ -1,100 +0,0 @@
restart -f
delete wave /*
view wave
add wave /testbench/clk
add wave /testbench/reset
add wave -divider
# new
#add wave /testbench/dut/core/ebu/ebu/IReadF
add wave /testbench/dut/core/DataStall
add wave /testbench/dut/core/ICacheStallF
add wave /testbench/dut/core/StallF
add wave /testbench/dut/core/StallD
add wave /testbench/dut/core/StallE
add wave /testbench/dut/core/StallM
add wave /testbench/dut/core/StallW
add wave /testbench/dut/core/FlushD
add wave /testbench/dut/core/FlushE
add wave /testbench/dut/core/FlushM
add wave /testbench/dut/core/FlushW
add wave -noupdate -divider -height 32 "MulDiv"
add wave -hex /testbench/dut/core/mdu/*
add wave -noupdate -divider -height 32 "Integer Divider"
add wave -hex /testbench/dut/core/mdu/genblk1/div/fsm1/CURRENT_STATE
add wave -hex /testbench/dut/core/mdu/genblk1/div/fsm1/NEXT_STATE
add wave -hex /testbench/dut/core/mdu/genblk1/div/*
add wave -noupdate -divider -height 32 "RF"
add wave -hex /testbench/dut/core/ieu/dp/regf/*
add wave -hex /testbench/dut/core/ieu/dp/regf/rf
add wave -divider
add wave -hex /testbench/dut/core/ifu/PCF
add wave -hex /testbench/dut/core/ifu/PCD
add wave -hex /testbench/dut/core/ifu/InstrD
add wave /testbench/InstrDName
add wave -divider
add wave -hex /testbench/dut/core/ifu/PCE
add wave -hex /testbench/dut/core/ifu/InstrE
add wave /testbench/InstrEName
add wave -hex /testbench/dut/core/ieu/dp/SrcAE
add wave -hex /testbench/dut/core/ieu/dp/SrcBE
add wave -hex /testbench/dut/core/ieu/dp/ALUResultE
#add wave /testbench/dut/core/ieu/dp/PCSrcE
add wave -divider
add wave -hex /testbench/dut/core/ifu/PCM
add wave -hex /testbench/dut/core/ifu/InstrM
add wave /testbench/InstrMName
add wave /testbench/dut/uncore/uncore/ram/memwrite
add wave -hex /testbench/dut/uncore/uncore/HADDR
add wave -hex /testbench/dut/uncore/uncore/HWDATA
add wave -divider
add wave -hex /testbench/dut/core/ebu/ebu/MemReadM
add wave -hex /testbench/dut/core/ebu/ebu/InstrReadF
add wave -hex /testbench/dut/core/ebu/ebu/BusState
add wave -hex /testbench/dut/core/ebu/ebu/NextBusState
add wave -hex /testbench/dut/core/ebu/ebu/HADDR
add wave -hex /testbench/dut/core/ebu/ebu/HREADY
add wave -hex /testbench/dut/core/ebu/ebu/HTRANS
add wave -hex /testbench/dut/core/ebu/ebu/HRDATA
add wave -hex /testbench/dut/core/ebu/ebu/HWRITE
add wave -hex /testbench/dut/core/ebu/ebu/HWDATA
add wave -hex /testbench/dut/core/ebu/ebu/HBURST
add wave -hex /testbench/dut/core/ebu/ebu/CaptureDataM
add wave -divider
add wave -hex /testbench/dut/uncore/uncore/ram/*
add wave -divider
add wave -hex /testbench/dut/core/ifu/PCW
add wave -hex /testbench/dut/core/ifu/InstrW
add wave /testbench/InstrWName
add wave /testbench/dut/core/ieu/dp/RegWriteW
add wave -hex /testbench/dut/core/ebu/ebu/ReadDataW
add wave -hex /testbench/dut/core/ieu/dp/ResultW
add wave -hex /testbench/dut/core/ieu/dp/RdW
add wave -divider
add wave -hex /testbench/dut/uncore/uncore/ram/*
add wave -divider
# appearance
TreeUpdate [SetDefaultTree]
WaveRestoreZoom {0 ps} {100 ps}
configure wave -namecolwidth 350
configure wave -valuecolwidth 250
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
set DefaultRadix hexadecimal

89
sim/wave-dos/ahb-waves.do
View file

@ -1,89 +0,0 @@
# ahb-waves.do
restart -f
delete wave /*
view wave
add wave /testbench/clk
add wave /testbench/reset
add wave -divider
#add wave /testbench/dut/core/ebu/ebu/IReadF
add wave /testbench/dut/core/DataStall
add wave /testbench/dut/core/ICacheStallF
add wave /testbench/dut/core/StallF
add wave /testbench/dut/core/StallD
add wave /testbench/dut/core/StallE
add wave /testbench/dut/core/StallM
add wave /testbench/dut/core/StallW
add wave /testbench/dut/core/FlushD
add wave /testbench/dut/core/FlushE
add wave /testbench/dut/core/FlushM
add wave /testbench/dut/core/FlushW
add wave -divider
add wave -hex /testbench/dut/core/ifu/PCF
add wave -hex /testbench/dut/core/ifu/PCD
add wave -hex /testbench/dut/core/ifu/InstrD
add wave /testbench/InstrDName
add wave -hex /testbench/dut/core/ifu/ic/InstrRawD
add wave -divider
add wave -hex /testbench/dut/core/ifu/PCE
add wave -hex /testbench/dut/core/ifu/InstrE
add wave /testbench/InstrEName
add wave -hex /testbench/dut/core/ieu/dp/SrcAE
add wave -hex /testbench/dut/core/ieu/dp/SrcBE
add wave -hex /testbench/dut/core/ieu/dp/ALUResultE
#add wave /testbench/dut/core/ieu/dp/PCSrcE
add wave -divider
add wave -hex /testbench/dut/core/ifu/PCM
add wave -hex /testbench/dut/core/ifu/InstrM
add wave /testbench/InstrMName
add wave /testbench/dut/uncore/uncore/ram/memwrite
add wave -hex /testbench/dut/uncore/uncore/HADDR
add wave -hex /testbench/dut/uncore/uncore/HWDATA
add wave -divider
add wave -hex /testbench/dut/core/ebu/ebu/MemReadM
add wave -hex /testbench/dut/core/ebu/ebu/InstrReadF
add wave -hex /testbench/dut/core/ebu/ebu/BusState
add wave -hex /testbench/dut/core/ebu/ebu/NextBusState
add wave -hex /testbench/dut/core/ebu/ebu/HADDR
add wave -hex /testbench/dut/core/ebu/ebu/HREADY
add wave -hex /testbench/dut/core/ebu/ebu/HTRANS
add wave -hex /testbench/dut/core/ebu/ebu/HRDATA
add wave -hex /testbench/dut/core/ebu/ebu/HWRITE
add wave -hex /testbench/dut/core/ebu/ebu/HWDATA
add wave -hex /testbench/dut/core/ebu/ebu/CaptureDataM
add wave -divider
add wave -hex /testbench/dut/uncore/uncore/ram/*
add wave -divider
add wave -hex /testbench/dut/core/ifu/PCW
add wave -hex /testbench/dut/core/ifu/InstrW
add wave /testbench/InstrWName
add wave /testbench/dut/core/ieu/dp/RegWriteW
add wave -hex /testbench/dut/core/ebu/ebu/ReadDataW
add wave -hex /testbench/dut/core/ieu/dp/ResultW
add wave -hex /testbench/dut/core/ieu/dp/RdW
add wave -divider
add wave -hex /testbench/dut/uncore/uncore/ram/*
add wave -divider
add wave -hex -r /testbench/*
# appearance
TreeUpdate [SetDefaultTree]
WaveRestoreZoom {0 ps} {100 ps}
configure wave -namecolwidth 250
configure wave -valuecolwidth 150
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
set DefaultRadix hexadecimal

76
sim/wave-dos/cache-waves.do
View file

@ -1,76 +0,0 @@
add wave /testbench/clk
add wave /testbench/reset
add wave -divider
#add wave /testbench/dut/core/ebu/ebu/IReadF
add wave /testbench/dut/core/DataStall
add wave /testbench/dut/core/ICacheStallF
add wave /testbench/dut/core/StallF
add wave /testbench/dut/core/StallD
add wave /testbench/dut/core/StallE
add wave /testbench/dut/core/StallM
add wave /testbench/dut/core/StallW
add wave /testbench/dut/core/FlushD
add wave /testbench/dut/core/FlushE
add wave /testbench/dut/core/FlushM
add wave /testbench/dut/core/FlushW
add wave -divider
add wave -hex /testbench/dut/core/ifu/PCF
add wave -hex /testbench/dut/core/ifu/PCD
add wave -hex /testbench/dut/core/ifu/InstrD
add wave /testbench/InstrDName
add wave -divider
add wave -hex /testbench/dut/core/ifu/PCE
add wave -hex /testbench/dut/core/ifu/InstrE
add wave /testbench/InstrEName
add wave -hex /testbench/dut/core/ieu/dp/SrcAE
add wave -hex /testbench/dut/core/ieu/dp/SrcBE
add wave -hex /testbench/dut/core/ieu/dp/ALUResultE
#add wave /testbench/dut/core/ieu/dp/PCSrcE
add wave -divider
add wave -hex /testbench/dut/core/ifu/PCM
add wave -hex /testbench/dut/core/ifu/InstrM
add wave /testbench/InstrMName
add wave /testbench/dut/uncore/uncore/ram/memwrite
add wave -hex /testbench/dut/uncore/uncore/HADDR
add wave -hex /testbench/dut/uncore/uncore/HWDATA
add wave -divider
add wave -hex /testbench/dut/core/ebu/ebu/MemReadM
add wave -hex /testbench/dut/core/ebu/ebu/InstrReadF
add wave -hex /testbench/dut/core/ebu/ebu/BusState
add wave -hex /testbench/dut/core/ebu/ebu/NextBusState
add wave -hex /testbench/dut/core/ebu/ebu/HADDR
add wave -hex /testbench/dut/core/ebu/ebu/HREADY
add wave -hex /testbench/dut/core/ebu/ebu/HTRANS
add wave -hex /testbench/dut/core/ebu/ebu/HRDATA
add wave -hex /testbench/dut/core/ebu/ebu/HWRITE
add wave -hex /testbench/dut/core/ebu/ebu/HWDATA
add wave -hex /testbench/dut/core/ebu/ebu/ReadDataM
add wave -divider
add wave /testbench/dut/core/ebu/ebu/CaptureDataM
add wave /testbench/dut/core/ebu/ebu/CapturedDataAvailable
add wave /testbench/dut/core/StallW
add wave -hex /testbench/dut/core/ebu/ebu/CapturedData
add wave -hex /testbench/dut/core/ebu/ebu/ReadDataWnext
add wave -hex /testbench/dut/core/ebu/ebu/ReadDataW
add wave -hex /testbench/dut/core/ifu/PCW
add wave -hex /testbench/dut/core/ifu/InstrW
add wave /testbench/InstrWName
add wave /testbench/dut/core/ieu/dp/RegWriteW
add wave -hex /testbench/dut/core/ebu/ebu/ReadDataW
add wave -hex /testbench/dut/core/ieu/dp/ResultW
add wave -hex /testbench/dut/core/ieu/dp/RdW
add wave -divider
add wave -hex /testbench/dut/core/dmem/*
add wave -hex /testbench/dut/core/dmem/genblk1/*
add wave -divider
add wave -hex -r /testbench/*

65
sim/wave-dos/default-waves.do
View file

@ -1,65 +0,0 @@
# default-waves.do
restart -f
delete wave /*
view wave
# Diplays All Signals recursively
add wave /testbench/clk
add wave /testbench/reset
add wave -divider
#add wave /testbench/dut/core/ebu/ebu/IReadF
#add wave /testbench/dut/core/DataStall
add wave /testbench/dut/core/ICacheStallF
add wave /testbench/dut/core/StallF
add wave /testbench/dut/core/StallD
add wave /testbench/dut/core/StallE
add wave /testbench/dut/core/StallM
add wave /testbench/dut/core/StallW
add wave /testbench/dut/core/FlushD
add wave /testbench/dut/core/FlushE
add wave /testbench/dut/core/FlushM
add wave /testbench/dut/core/FlushW
add wave -divider
add wave -hex /testbench/dut/core/ifu/PCF
add wave -hex /testbench/dut/core/ifu/PCD
add wave -hex /testbench/dut/core/ifu/InstrD
add wave /testbench/InstrDName
add wave -divider
add wave -hex /testbench/dut/core/ifu/PCE
add wave -hex /testbench/dut/core/ifu/InstrE
add wave /testbench/InstrEName
add wave -hex /testbench/dut/core/ieu/dp/SrcAE
add wave -hex /testbench/dut/core/ieu/dp/SrcBE
add wave -hex /testbench/dut/core/ieu/dp/ALUResultE
#add wave /testbench/dut/core/ieu/dp/PCSrcE
add wave -divider
add wave -hex /testbench/dut/core/ifu/PCM
add wave -hex /testbench/dut/core/ifu/InstrM
add wave /testbench/InstrMName
add wave /testbench/dut/uncore/uncore/ram/memwrite
add wave -hex /testbench/dut/uncore/uncore/HADDR
add wave -hex /testbench/dut/uncore/uncore/HWDATA
add wave -divider
add wave -hex /testbench/PCW
add wave -hex /testbench/InstrW
add wave /testbench/InstrWName
add wave /testbench/dut/core/ieu/dp/RegWriteW
add wave -hex /testbench/dut/core/ieu/dp/ResultW
add wave -hex /testbench/dut/core/ieu/dp/RdW
add wave -divider
add wave -hex -r /testbench/*
# appearance
TreeUpdate [SetDefaultTree]
WaveRestoreZoom {0 ps} {100 ps}
configure wave -namecolwidth 250
configure wave -valuecolwidth 150
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
set DefaultRadix hexadecimal

23
sim/wave-dos/generic.do
View file

@ -1,23 +0,0 @@
# default-waves.do
restart -f
delete wave /*
view wave
# Diplays All Signals recursively
add wave /testbench/clk
add wave /testbench/reset
add wave -divider
add wave -hex -r /testbench/*
# appearance
TreeUpdate [SetDefaultTree]
WaveRestoreZoom {0 ps} {300 ps}
configure wave -namecolwidth 350
configure wave -valuecolwidth 150
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
set DefaultRadix hexadecimal

207
sim/wave-dos/linux-waves.do
View file

@ -1,207 +0,0 @@
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -divider <NULL>
add wave -noupdate /testbench/clk
add wave -noupdate /testbench/reset
add wave -noupdate -radix decimal /testbench/errorCount
add wave -noupdate -radix decimal /testbench/InstrCountW
add wave -noupdate -divider Stalls_and_Flushes
add wave -noupdate /testbench/dut/core/StallF
add wave -noupdate /testbench/dut/core/StallD
add wave -noupdate /testbench/dut/core/StallE
add wave -noupdate /testbench/dut/core/StallM
add wave -noupdate /testbench/dut/core/StallW
add wave -noupdate /testbench/dut/core/FlushD
add wave -noupdate /testbench/dut/core/FlushE
add wave -noupdate /testbench/dut/core/FlushM
add wave -noupdate /testbench/dut/core/FlushW
add wave -noupdate -divider F
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCF
add wave -noupdate -divider D
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCD
add wave -noupdate /testbench/InstrDName
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrD
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/InstrValidD
add wave -noupdate -divider E
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCE
add wave -noupdate /testbench/InstrEName
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/InstrValidE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/SrcAE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/SrcBE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ALUResultE
add wave -noupdate -divider M
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCM
add wave -noupdate /testbench/InstrMName
add wave -noupdate /testbench/textM
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrM
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/InstrValidM
add wave -noupdate -radix hexadecimal /testbench/dut/core/lsu.bus.dcache/MemPAdrM
add wave -noupdate -radix hexadecimal /testbench/dut/core/lsu.bus.dcache/MemRWM
add wave -noupdate /testbench/dut/core/lsu.bus.dcache/WriteDataM
add wave -noupdate -radix hexadecimal /testbench/dut/core/lsu.bus.dcache/ReadDataM
add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/DTLBWalk
add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/BasePageTablePPN
add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/CurrentPPN
add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/MemWrite
add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/Executable
add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/Writable
add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/Readable
add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/Valid
add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/Misaligned
add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/MegapageMisaligned
add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/ValidPTE
add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/LeafPTE
add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/ValidLeafPTE
add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/ValidNonLeafPTE
add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/StartWalk
add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/TLBMiss
add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/PRegEn
add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/NextPageType
add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/SvMode
add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/TranslationVAdr
add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/WalkerState
add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/NextWalkerState
add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/InitialWalkerState
add wave -noupdate -group LSU -r /testbench/dut/core/lsu/*
add wave -noupdate -group DCache -r /testbench/dut/core/lsu.bus.dcache/*
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/clk
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/reset
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/StallW
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/UnsignedLoadM
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/AtomicMaskedM
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/Funct7M
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/InstrPAdrF
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/InstrReadF
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/InstrRData
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/InstrAckF
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/DCtoAHBPAdrM
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/DCtoAHBReadM
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/DCtoAHBWriteM
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/DCtoAHBWriteData
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/DCfromAHBReadData
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/MemSizeM
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/DCfromAHBAck
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HRDATA
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HREADY
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HRESP
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HCLK
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HRESETn
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HADDR
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HWDATA
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HWRITE
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HSIZE
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HBURST
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HPROT
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HTRANS
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HMASTLOCK
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HADDRD
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HSIZED
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HWRITED
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/GrantData
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/AccessAddress
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/ISize
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HRDATAMasked
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/ReadDataM
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HRDATANext
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/CapturedHRDATAMasked
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/WriteData
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/IReady
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/DReady
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/CaptureDataM
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/CapturedDataAvailable
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/BusState
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/NextBusState
add wave -noupdate -divider W
add wave -noupdate -radix hexadecimal /testbench/PCW
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/InstrValidW
add wave -noupdate /testbench/textM
add wave -noupdate /testbench/dut/core/ieu/dp/ReadDataW
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ResultW
add wave -noupdate -group RF /testbench/dut/core/ieu/dp/RegWriteW
add wave -noupdate -group RF -radix unsigned /testbench/dut/core/ieu/dp/RdW
add wave -noupdate -group RF /testbench/dut/core/ieu/dp/regf/wd3
add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[2]}
add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[3]}
add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[4]}
add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[5]}
add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[6]}
add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[7]}
add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[8]}
add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[9]}
add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[10]}
add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[11]}
add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[12]}
add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[13]}
add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[14]}
add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[15]}
add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[16]}
add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[17]}
add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[18]}
add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[19]}
add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[20]}
add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[21]}
add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[22]}
add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[23]}
add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[24]}
add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[25]}
add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[26]}
add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[27]}
add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[28]}
add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[29]}
add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[30]}
add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[31]}
add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/MSTATUS_REGW
add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/MCOUNTINHIBIT_REGW
add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/MCOUNTEREN_REGW
add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/MIDELEG_REGW
add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/MIP_REGW
add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/MIE_REGW
add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MEPC_REGW
add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MTVEC_REGW
add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MCOUNTEREN_REGW
add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MCOUNTINHIBIT_REGW
add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MEDELEG_REGW
add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MIDELEG_REGW
add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MSCRATCH_REGW
add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MCAUSE_REGW
add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MTVAL_REGW
add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/SSTATUS_REGW
add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/SCOUNTEREN_REGW
add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/SIP_REGW
add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/SIE_REGW
add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/SEPC_REGW
add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/STVEC_REGW
add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/SCOUNTEREN_REGW
add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/SEDELEG_REGW
add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/SIDELEG_REGW
add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/SATP_REGW
add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/USTATUS_REGW
add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/UEPC_REGW
add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/UTVEC_REGW
add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/UIP_REGW
add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/UIE_REGW
add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/PMPCFG_ARRAY_REGW
add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/PMPADDR_ARRAY_REGW
add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MISA_REGW
add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/FRM_REGW
add wave -noupdate -divider <NULL>
add wave -hex -r /testbench/*
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 8} {42752672 ns} 1} {{Cursor 2} {42752634 ns} 0}
quietly wave cursor active 2
configure wave -namecolwidth 250
configure wave -valuecolwidth 297
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {42752559 ns} {42752771 ns}

118
sim/wave-dos/peripheral-waves.do
View file

@ -1,118 +0,0 @@
# peripheral-waves.do
restart -f
delete wave /*
view wave
# general stuff
add wave /testbench/clk
add wave /testbench/reset
add wave -divider
#add wave /testbench/dut/core/DataStall
add wave /testbench/dut/core/StallF
add wave /testbench/dut/core/StallD
add wave /testbench/dut/core/StallE
add wave /testbench/dut/core/StallM
add wave /testbench/dut/core/StallW
add wave /testbench/dut/core/FlushD
add wave /testbench/dut/core/FlushE
add wave /testbench/dut/core/FlushM
add wave /testbench/dut/core/FlushW
add wave -divider
add wave -hex /testbench/dut/core/ifu/PCF
add wave -hex /testbench/dut/core/ifu/PCD
add wave -hex /testbench/dut/core/ifu/InstrD
add wave -hex /testbench/dut/core/ieu/c/InstrValidD
add wave /testbench/InstrDName
add wave -divider
add wave -hex /testbench/dut/core/ifu/PCE
add wave -hex /testbench/dut/core/ifu/InstrE
add wave -hex /testbench/dut/core/ieu/c/InstrValidE
add wave /testbench/InstrEName
add wave -hex /testbench/dut/core/ieu/dp/SrcAE
add wave -hex /testbench/dut/core/ieu/dp/SrcBE
add wave -hex /testbench/dut/core/ieu/dp/ALUResultE
#add wave /testbench/dut/core/ieu/dp/PCSrcE
add wave /testbench/dut/core/mdu/genblk1/div/DivStartE
add wave /testbench/dut/core/mdu/DivBusyE
add wave -hex /testbench/dut/core/mdu/genblk1/div/RemM
add wave -hex /testbench/dut/core/mdu/genblk1/div/QuotM
add wave -divider
add wave -hex /testbench/dut/core/ifu/PCM
add wave -hex /testbench/dut/core/ifu/InstrM
add wave -hex /testbench/dut/core/ieu/c/InstrValidM
add wave /testbench/InstrMName
add wave /testbench/dut/uncore/uncore/ram/memwrite
add wave -hex /testbench/dut/core/WriteDataM
add wave -hex /testbench/dut/core/lsu.bus.dcache/MemPAdrM
add wave -hex /testbench/dut/core/lsu.bus.dcache/WriteDataM
add wave -hex /testbench/dut/core/lsu.bus.dcache/ReadDataM
add wave -divider
add wave -hex /testbench/PCW
#add wave -hex /testbench/InstrW
#add wave -hex /testbench/dut/core/ieu/c/InstrValidW
#add wave /testbench/InstrWName
add wave -hex /testbench/dut/core/ReadDataW
add wave -hex /testbench/dut/core/ieu/dp/ResultW
add wave -hex /testbench/dut/core/ieu/dp/RegWriteW
add wave -hex /testbench/dut/core/ieu/dp/WriteDataW
add wave -hex /testbench/dut/core/ieu/dp/RdW
add wave -divider
add wave -hex /testbench/dut/core/priv/csr/TrapM
add wave -hex /testbench/dut/core/priv/csr/UnalignedNextEPCM
add wave -hex /testbench/dut/core/priv/csr/genblk1/csrm/WriteMEPCM
add wave -hex /testbench/dut/core/priv/csr/genblk1/csrm/MEPC_REGW
add wave -divider RegFile
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[1]
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[2]
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[3]
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[4]
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[5]
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[6]
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[7]
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[8]
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[9]
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[10]
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[11]
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[12]
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[13]
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[14]
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[15]
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[16]
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[17]
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[18]
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[19]
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[20]
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[21]
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[22]
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[23]
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[24]
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[25]
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[26]
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[27]
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[28]
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[29]
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[30]
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[31]
# peripherals
add wave -divider PLIC
add wave -hex /testbench/dut/core/priv/csr/TrapM
add wave -hex /testbench/dut/uncore/uncore/plic/plic/*
add wave -hex /testbench/dut/uncore/uncore/plic/plic/intPriority
add wave -hex /testbench/dut/uncore/uncore/plic/plic/pendingArray
add wave -divider UART
add wave -hex /testbench/dut/uncore/uncore/uart/uart/u/*
add wave -divider GPIO
add wave -hex /testbench/dut/uncore/uncore/gpio/gpio/*
#add wave -divider
#add wave -hex /testbench/dut/core/ebu/ebu/*
#add wave -divider
#add wave -divider
# everything else
add wave -hex -r /testbench/*

30
sim/wave-fpu.do
View file

@ -1,30 +0,0 @@
add wave -noupdate /testbenchfp/clk
add wave -noupdate -radix decimal /testbenchfp/VectorNum
add wave -noupdate /testbenchfp/FrmNum
add wave -noupdate /testbenchfp/X
add wave -noupdate /testbenchfp/Y
add wave -noupdate /testbenchfp/Z
add wave -noupdate /testbenchfp/Res
add wave -noupdate /testbenchfp/Ans
add wave -noupdate /testbenchfp/reset
add wave -noupdate /testbenchfp/DivStart
add wave -noupdate /testbenchfp/FDivBusyE
add wave -noupdate /testbenchfp/CheckNow
add wave -noupdate /testbenchfp/DivDone
add wave -noupdate /testbenchfp/ResMatch
add wave -noupdate /testbenchfp/FlagMatch
add wave -noupdate /testbenchfp/CheckNow
add wave -noupdate /testbenchfp/NaNGood
add wave -group {PostProc} -noupdate /testbenchfp/postprocess/*
add wave -group {PostProc} -noupdate /testbenchfp/postprocess/specialcase/*
add wave -group {PostProc} -noupdate /testbenchfp/postprocess/flags/*
add wave -group {PostProc} -noupdate /testbenchfp/postprocess/normshift/*
add wave -group {PostProc} -noupdate /testbenchfp/postprocess/shiftcorrection/*
add wave -group {PostProc} -noupdate /testbenchfp/postprocess/resultsign/*
add wave -group {PostProc} -noupdate /testbenchfp/postprocess/round/*
add wave -group {PostProc} -noupdate /testbenchfp/postprocess/fmashiftcalc/*
add wave -group {PostProc} -noupdate /testbenchfp/postprocess/divshiftcalc/*
add wave -group {PostProc} -noupdate /testbenchfp/postprocess/cvtshiftcalc/*
add wave -group {Testbench} -noupdate /testbenchfp/*
add wave -group {Testbench} -noupdate /testbenchfp/readvectors/*

0
sim/wally.xrun → sim/xcelium/wally.xrun
View file

46
site-setup.csh Normal file
View file

@ -0,0 +1,46 @@
#!/bin/csh
# site-setup.csh
# License servers and commercial CAD tool paths
# Must edit these based on your local environment. Ask your sysadmin.
setenv MGLS_LICENSE_FILE 27002@zircon.eng.hmc.edu # Change this to your Siemens license server
setenv SNPSLMD_LICENSE_FILE 27020@zircon.eng.hmc.edu # Change this to your Synopsys license server
setenv QUESTAPATH /cad/mentor/questa_sim-2022.4_2/questasim/bin # Change this for your path to Questa
setenv SNPSPATH /cad/synopsys/SYN/bin # Change this for your path to Design Compiler
# Tools
# Questa and Synopsys
extend PATH $QUESTAPATH
extend PATH $SNPSPATH
# GCC
prepend LD_LIBRARY_PATH $RISCV/riscv-gnu-toolchain/lib
prepend LD_LIBRARY_PATH $RISCV/riscv-gnu-toolchain/riscv64-unknown-elf/lib
extend PATH $RISCV/riscv-gnu-toolchain/bin # GCC tools
extend PATH $RISCV/riscv-gnu-toolchain/riscv64-unknown-elf/bin # GCC tools
# Spike
extend LD_LIBRARY_PATH $RISCV/lib
extend PATH $RISCV/bin
# Verilator
extend PATH /usr/local/bin/verilator # Change this for your path to Verilator
# Verilator needs a larger stack to simulate CORE-V Wally
limit stacksize unlimited
# Imperas; put this in if you are using it
#set path = ($RISCV/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64 $path)
#setenv LD_LIBRARY_PATH $RISCV/imperas_riscv_tests/riscv-ovpsim-plus/bin/Linux64:$LD_LIBRARY_PATH # remove if no imperas
setenv IDV $RISCV/ImperasDV-OpenHW
if ($?IDV) then
# echo "Imperas exists"
setenv IMPERAS_HOME $IDV/Imperas
setenv IMPERAS_PERSONALITY CPUMAN_DV_ASYNC
setenv ROOTDIR ~/
source ${IMPERAS_HOME}/bin/setup.sh
setupImperas ${IMPERAS_HOME}
extend PATH $IDV/scripts/cvw
endfi

47
site-setup.sh Executable file
View file

@ -0,0 +1,47 @@
#!/bin/bash
# site-setup.sh
# David_Harris@hmc.edu and kekim@hmc.edu 1 December 2021
# System Admin should install this into $RISCV/site-setup.sh
# $RISCV is typically /opt/riscv
# System Admin must update the licenses and paths for localization.
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
# license servers and commercial CAD tool paths
# Must edit these based on your local environment.
export MGLS_LICENSE_FILE=27002@zircon.eng.hmc.edu # Change this to your Siemens license server for Questa
export SNPSLMD_LICENSE_FILE=27020@zircon.eng.hmc.edu # Change this to your Synopsys license server for Design Compiler
export QUESTA_HOME=/cad/mentor/questa_sim-2023.4/questasim # Change this for your path to Questa, excluding bin
export DC_HOME=/cad/synopsys/SYN # Change this for your path to Synopsys Design Compiler, excluding bin
export VCS_HOME=/cad/synopsys/vcs/U-2023.03-SP2-4 # Change this for your path to Synopsys VCS, exccluding bin
# Tools
# Questa and Synopsys
export PATH=$QUESTA_HOME/bin:$DC_HOME/bin:$VCS_HOME/bin:$PATH
# GCC
export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$RISCV/riscv-gnu-toolchain/lib:$RISCV/riscv-gnu-toolchain/riscv64-unknown-elf/lib
export PATH=$PATH:$RISCV/riscv-gnu-toolchain/bin:$RISCV/riscv-gnu-toolchain/riscv64-unknown-elf/bin # GCC tools
# Spike
export LD_LIBRARY_PATH=$RISCV/lib:$LD_LIBRARY_PATH
export PATH=$PATH:$RISCV/bin
# Verilator
export PATH=/usr/local/bin/verilator:$PATH # Change this for your path to Verilator
# Imperas OVPsim; put this in if you are using it
#export PATH=$RISCV/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64:$PATH
#export LD_LIBRARY_PATH=$RISCV/imperas_riscv_tests/riscv-ovpsim-plus/bin/Linux64:$LD_LIBRARY_PATH
export IDV=$RISCV/ImperasDV-OpenHW
if [ -e "$IDV" ]; then
# echo "Imperas exists"
export IMPERAS_HOME=$IDV/Imperas
export IMPERAS_PERSONALITY=CPUMAN_DV_ASYNC
export ROOTDIR=~/
source ${IMPERAS_HOME}/bin/setup.sh
setupImperas ${IMPERAS_HOME}
export PATH=$IDV/scripts/cvw:$PATH
fi

4
src/cache/cacheLRU.sv vendored
View file

@ -149,8 +149,8 @@ module cacheLRU
for (int set = 0; set < NUMLINES; set++) LRUMemory[set] = 0; // exclusion-tag: initialize
else if(CacheEn) begin
// Because we are using blocking assignments, change to LRUMemory must occur after LRUMemory is used so we get the proper value
if(LRUWriteEn & (PAdr == CacheSetTag)) CurrLRU = #1 NextLRU;
else CurrLRU = #1 LRUMemory[CacheSetTag];
if(LRUWriteEn & (PAdr == CacheSetTag)) CurrLRU = NextLRU;
else CurrLRU = LRUMemory[CacheSetTag];
if(LRUWriteEn) LRUMemory[PAdr] = NextLRU;
end
end

4
src/cache/cachefsm.sv vendored
View file

@ -110,8 +110,8 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
flop #(1) resetDelayReg(.clk, .d(reset), .q(resetDelay));
always_ff @(posedge clk)
if (reset | FlushStage) CurrState <= #1 STATE_ACCESS;
else CurrState <= #1 NextState;
if (reset | FlushStage) CurrState <= STATE_ACCESS;
else CurrState <= NextState;
always_comb begin
NextState = STATE_ACCESS;

16
src/cache/cacheway.sv vendored
View file

@ -156,12 +156,12 @@ module cacheway import cvw::*; #(parameter cvw_t P,
/////////////////////////////////////////////////////////////////////////////////////////////
always_ff @(posedge clk) begin // Valid bit array,
if (reset) ValidBits <= #1 0;
if (reset) ValidBits <= 0;
if(CacheEn) begin
ValidWay <= #1 ValidBits[CacheSetTag];
if(InvalidateCache) ValidBits <= #1 0; // exclusion-tag: dcache invalidateway
else if (SetValidEN) ValidBits[CacheSetData] <= #1 SetValidWay;
else if (ClearValidEN) ValidBits[CacheSetData] <= #1 0; // exclusion-tag: icache ClearValidBits
ValidWay <= ValidBits[CacheSetTag];
if(InvalidateCache) ValidBits <= 0; // exclusion-tag: dcache invalidateway
else if (SetValidEN) ValidBits[CacheSetData] <= SetValidWay;
else if (ClearValidEN) ValidBits[CacheSetData] <= 0; // exclusion-tag: icache ClearValidBits
end
end
@ -173,10 +173,10 @@ module cacheway import cvw::*; #(parameter cvw_t P,
if (!READ_ONLY_CACHE) begin:dirty
always_ff @(posedge clk) begin
// reset is optional. Consider merging with TAG array in the future.
//if (reset) DirtyBits <= #1 {NUMLINES{1'b0}};
//if (reset) DirtyBits <= {NUMLINES{1'b0}};
if(CacheEn) begin
Dirty <= #1 DirtyBits[CacheSetTag];
if((SetDirtyWay | ClearDirtyWay) & ~FlushStage) DirtyBits[CacheSetData] <= #1 SetDirtyWay; // exclusion-tag: cache UpdateDirty
Dirty <= DirtyBits[CacheSetTag];
if((SetDirtyWay | ClearDirtyWay) & ~FlushStage) DirtyBits[CacheSetData] <= SetDirtyWay; // exclusion-tag: cache UpdateDirty
end
end
end else assign Dirty = 1'b0;

4
src/ebu/buscachefsm.sv
View file

@ -82,8 +82,8 @@ module buscachefsm #(
assign BusWrite = (CacheBusRW[0] | BusCMOZero) & ~READ_ONLY_CACHE;
always_ff @(posedge HCLK)
if (~HRESETn | Flush) CurrState <= #1 ADR_PHASE;
else CurrState <= #1 NextState;
if (~HRESETn | Flush) CurrState <= ADR_PHASE;
else CurrState <= NextState;
always_comb begin
case(CurrState)

4
src/ebu/busfsm.sv
View file

@ -55,8 +55,8 @@ module busfsm #(
busstatetype CurrState, NextState;
always_ff @(posedge HCLK)
if (~HRESETn | Flush) CurrState <= #1 ADR_PHASE;
else CurrState <= #1 NextState;
if (~HRESETn | Flush) CurrState <= ADR_PHASE;
else CurrState <= NextState;
always_comb begin
case(CurrState)

8
src/ebu/ebufsmarb.sv
View file

@ -51,7 +51,7 @@ module ebufsmarb (
statetype CurrState, NextState;
logic both; // Both the LSU and IFU request at the same time
logic IFUReqD; // 1 cycle delayed IFU request. Part of arbitration
logic IFUReqDelay; // 1 cycle delayed IFU request. Part of arbitration
logic FinalBeat, FinalBeatD; // Indicates the last beat of a burst
logic BeatCntEn;
logic [3:0] BeatCount; // Position within a burst transfer
@ -85,11 +85,11 @@ module ebufsmarb (
// Controller 1 (LSU)
// When both the IFU and LSU request at the same time, the FSM will go into the arbitrate state.
// Once the LSU request is done the fsm returns to IDLE. To prevent the LSU from regaining
// priority and re-issuing the same memory operation, the delayed IFUReqD squashes the LSU request.
// priority and re-issuing the same memory operation, the delayed IFUReqDelay squashes the LSU request.
// This is necessary because the pipeline is stalled for the entire duration of both transactions,
// and the LSU memory request will stil be active.
flopr #(1) ifureqreg(HCLK, ~HRESETn, IFUReq, IFUReqD);
assign LSUDisable = (CurrState == ARBITRATE) ? 1'b0 : (IFUReqD & ~(HREADY & FinalBeatD));
flopr #(1) ifureqreg(HCLK, ~HRESETn, IFUReq, IFUReqDelay);
assign LSUDisable = (CurrState == ARBITRATE) ? 1'b0 : (IFUReqDelay & ~(HREADY & FinalBeatD));
assign LSUSelect = (NextState == ARBITRATE) ? 1'b1: LSUReq;
////////////////////////////////////////////////////////////////////////////////////////////////////

2
src/fpu/fctrl.sv
View file

@ -250,7 +250,7 @@ module fctrl import cvw::*; #(parameter cvw_t P) (
/* verilator lint_on CASEINCOMPLETE */
// unswizzle control bits
assign #1 {FRegWriteD, FWriteIntD, FResSelD, PostProcSelD, OpCtrlD, FDivStartD, IllegalFPUInstrD, FCvtIntD, ZfaD} = ControlsD;
assign {FRegWriteD, FWriteIntD, FResSelD, PostProcSelD, OpCtrlD, FDivStartD, IllegalFPUInstrD, FCvtIntD, ZfaD} = ControlsD;
// rounding modes:
// 000 - round to nearest, ties to even

12
src/fpu/fdivsqrt/fdivsqrtfsm.sv
View file

@ -63,17 +63,17 @@ module fdivsqrtfsm import cvw::*; #(parameter cvw_t P) (
always_ff @(posedge clk) begin
if (reset | FlushE) begin
state <= #1 IDLE;
state <= IDLE;
end else if (IFDivStartE) begin // IFDivStartE implies stat is IDLE
step <= CyclesE;
if (SpecialCaseE) state <= #1 DONE;
else state <= #1 BUSY;
if (SpecialCaseE) state <= DONE;
else state <= BUSY;
end else if (state == BUSY) begin
if (step == 1 | WZeroE) state <= #1 DONE; // finished steps or terminate early on zero residual
if (step == 1 | WZeroE) state <= DONE; // finished steps or terminate early on zero residual
step <= step - 1;
end else if (state == DONE) begin // Can't still be stalled in configs tested, but keep this check for paranoia
if (StallM) state <= #1 DONE; // exclusion-tag: fdivsqrtfsm stallm
else state <= #1 IDLE;
if (StallM) state <= DONE; // exclusion-tag: fdivsqrtfsm stallm
else state <= IDLE;
end
end

6
src/fpu/fregfile.sv
View file

@ -47,8 +47,8 @@ module fregfile #(parameter FLEN) (
if (reset) for(i=0; i<32; i++) rf[i] <= 0;
else if (we4) rf[a4] <= wd4;
assign #2 rd1 = rf[a1];
assign #2 rd2 = rf[a2];
assign #2 rd3 = rf[a3];
assign rd1 = rf[a1];
assign rd2 = rf[a2];
assign rd3 = rf[a3];
endmodule // regfile

20
src/fpu/postproc/fmashiftcalc.sv
View file

@ -83,23 +83,23 @@ module fmashiftcalc import cvw::*; #(parameter cvw_t P) (
if (P.FPSIZES == 1) begin
logic Sum0LEZ, Sum0GEFL;
assign Sum0LEZ = PreNormSumExp[P.NE+1] | ~|PreNormSumExp;
assign Sum0GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF-2));
assign Sum0GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF-1)); // changed from -2 dh 4/3/24 for issue 655
assign FmaPreResultSubnorm = Sum0LEZ & Sum0GEFL & ~FmaSZero;
end else if (P.FPSIZES == 2) begin
logic Sum0LEZ, Sum0GEFL, Sum1LEZ, Sum1GEFL;
assign Sum0LEZ = PreNormSumExp[P.NE+1] | ~|PreNormSumExp;
assign Sum0GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF-2));
assign Sum0GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF-1)); // changed from -2 dh 4/3/24 for issue 655
assign Sum1LEZ = $signed(PreNormSumExp) <= $signed((P.NE+2)'(P.BIAS-P.BIAS1));
assign Sum1GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF1-2+P.BIAS-P.BIAS1)) | ~|PreNormSumExp;
assign Sum1GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF1-1+P.BIAS-P.BIAS1)) | ~|PreNormSumExp;
assign FmaPreResultSubnorm = (Fmt ? Sum0LEZ : Sum1LEZ) & (Fmt ? Sum0GEFL : Sum1GEFL) & ~FmaSZero;
end else if (P.FPSIZES == 3) begin
logic Sum0LEZ, Sum0GEFL, Sum1LEZ, Sum1GEFL, Sum2LEZ, Sum2GEFL;
assign Sum0LEZ = PreNormSumExp[P.NE+1] | ~|PreNormSumExp;
assign Sum0GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF-2));
assign Sum0GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF-1));
assign Sum1LEZ = $signed(PreNormSumExp) <= $signed((P.NE+2)'(P.BIAS-P.BIAS1));
assign Sum1GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF1-2+P.BIAS-P.BIAS1)) | ~|PreNormSumExp;
assign Sum1GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF1-1+P.BIAS-P.BIAS1)) | ~|PreNormSumExp;
assign Sum2LEZ = $signed(PreNormSumExp) <= $signed((P.NE+2)'(P.BIAS-P.BIAS2));
assign Sum2GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF2-2+P.BIAS-P.BIAS2)) | ~|PreNormSumExp;
assign Sum2GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF2-1+P.BIAS-P.BIAS2)) | ~|PreNormSumExp;
always_comb begin
case (Fmt)
P.FMT: FmaPreResultSubnorm = Sum0LEZ & Sum0GEFL; // & ~FmaSZero; // checking sum is not zero is harmless but turns out to be unnecessary
@ -111,13 +111,13 @@ module fmashiftcalc import cvw::*; #(parameter cvw_t P) (
end else if (P.FPSIZES == 4) begin
logic Sum0LEZ, Sum0GEFL, Sum1LEZ, Sum1GEFL, Sum2LEZ, Sum2GEFL, Sum3LEZ, Sum3GEFL;
assign Sum0LEZ = PreNormSumExp[P.NE+1] | ~|PreNormSumExp;
assign Sum0GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF-2));
assign Sum0GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF-1));
assign Sum1LEZ = $signed(PreNormSumExp) <= $signed((P.NE+2)'(P.BIAS-P.D_BIAS));
assign Sum1GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.D_NF-2+P.BIAS-P.D_BIAS)) | ~|PreNormSumExp;
assign Sum1GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.D_NF-1+P.BIAS-P.D_BIAS)) | ~|PreNormSumExp;
assign Sum2LEZ = $signed(PreNormSumExp) <= $signed((P.NE+2)'(P.BIAS-P.S_BIAS));
assign Sum2GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.S_NF-2+P.BIAS-P.S_BIAS)) | ~|PreNormSumExp;
assign Sum2GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.S_NF-1+P.BIAS-P.S_BIAS)) | ~|PreNormSumExp;
assign Sum3LEZ = $signed(PreNormSumExp) <= $signed((P.NE+2)'(P.BIAS-P.H_BIAS));
assign Sum3GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.H_NF-2+P.BIAS-P.H_BIAS)) | ~|PreNormSumExp;
assign Sum3GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.H_NF-1+P.BIAS-P.H_BIAS)) | ~|PreNormSumExp;
always_comb begin
case (Fmt)
2'h3: FmaPreResultSubnorm = Sum0LEZ & Sum0GEFL & ~FmaSZero;

4
src/fpu/postproc/specialcase.sv
View file

@ -305,7 +305,7 @@ module specialcase import cvw::*; #(parameter cvw_t P) (
// signed | 2^31-1 | 2^63-1 |
// unsigned | 2^32-1 | 2^64-1 |
//
// other: 32 bit unsinged res should be sign extended as if it were a signed number
// other: 32 bit unsigned res should be sign extended as if it were a signed number
if(P.IEEE754) begin
always_comb
@ -343,7 +343,7 @@ module specialcase import cvw::*; #(parameter cvw_t P) (
else OfIntRes2 = OfIntRes;
if (Zfa) Int64Res = {{(P.XLEN-32){CvtNegRes[P.XLEN-1]}}, CvtNegRes[31:0]};
else Int64Res = CvtNegRes[P.XLEN-1:0];
if (Zfa) SelCvtOfRes = InfIn | NaNIn | (CvtCe > 32 + 52); // fcvtmod.w.d only overflows to 0 on NaN or Infinity, or if the shift is so large that only zeros are left
if (Zfa) SelCvtOfRes = InfIn | NaNIn | (CvtCe > 32 + 52); // fcvtmod.w.d only overflows to 0 on NaN or Infinity, or if the shift is so large that only zeros are left
else SelCvtOfRes = IntInvalid; // regular fcvt gives an overflow if out of range
end
else

2
src/generic/flop/flop.sv
View file

@ -31,6 +31,6 @@ module flop #(parameter WIDTH = 8) (
output logic [WIDTH-1:0] q);
always_ff @(posedge clk)
q <= #1 d;
q <= d;
endmodule

2
src/generic/flop/flopen.sv
View file

@ -31,6 +31,6 @@ module flopen #(parameter WIDTH = 8) (
output logic [WIDTH-1:0] q);
always_ff @(posedge clk)
if (en) q <= #1 d;
if (en) q <= d;
endmodule

4
src/generic/flop/flopenl.sv
View file

@ -32,7 +32,7 @@ module flopenl #(parameter WIDTH = 8, parameter type TYPE=logic [WIDTH-1:0]) (
output TYPE q);
always_ff @(posedge clk)
if (load) q <= #1 val;
else if (en) q <= #1 d;
if (load) q <= val;
else if (en) q <= d;
endmodule

4
src/generic/flop/flopenr.sv
View file

@ -31,7 +31,7 @@ module flopenr #(parameter WIDTH = 8) (
output logic [WIDTH-1:0] q);
always_ff @(posedge clk)
if (reset) q <= #1 0;
else if (en) q <= #1 d;
if (reset) q <= 0;
else if (en) q <= d;
endmodule

6
src/generic/flop/flopenrc.sv
View file

@ -31,9 +31,9 @@ module flopenrc #(parameter WIDTH = 8) (
output logic [WIDTH-1:0] q);
always_ff @(posedge clk)
if (reset) q <= #1 0;
if (reset) q <= 0;
else if (en)
if (clear) q <= #1 0;
else q <= #1 d;
if (clear) q <= 0;
else q <= d;
endmodule

4
src/generic/flop/flopens.sv
View file

@ -31,8 +31,8 @@ module flopens #(parameter WIDTH = 8) (
output logic [WIDTH-1:0] q);
always_ff @(posedge clk)
if (set) q <= #1 1;
else if (en) q <= #1 d;
if (set) q <= 1;
else if (en) q <= d;
endmodule

4
src/generic/flop/flopr.sv
View file

@ -31,7 +31,7 @@ module flopr #(parameter WIDTH = 8) (
output logic [WIDTH-1:0] q);
always_ff @(posedge clk)
if (reset) q <= #1 0;
else q <= #1 d;
if (reset) q <= 0;
else q <= d;
endmodule

4
src/generic/flop/synchronizer.sv
View file

@ -33,8 +33,8 @@ module synchronizer (
logic mid;
always_ff @(posedge clk) begin
mid <= #1 d;
q <= #1 mid;
mid <= d;
q <= mid;
end
endmodule

6
src/generic/mem/ram1p1rwbe.sv
View file

@ -97,7 +97,7 @@ module ram1p1rwbe import cvw::*; #(parameter USE_SRAM=0, DEPTH=64, WIDTH=44, PRE
/* // Alternate read logic reads the old contents of mem[addr]. Increases setup time and adds dout reg, but reduces clk to q
always_ff @(posedge clk)
if(ce) dout <= #1 mem[addr]; */
if(ce) dout <= mem[addr]; */
// Write divided into part for bytes and part for extra msbs
// Questa sim version 2022.3_2 does not allow multiple drivers for RAM when using always_ff.
@ -106,12 +106,12 @@ module ram1p1rwbe import cvw::*; #(parameter USE_SRAM=0, DEPTH=64, WIDTH=44, PRE
always @(posedge clk)
if (ce & we)
for(i = 0; i < WIDTH/8; i++)
if(bwe[i]) RAM[addr][i*8 +: 8] <= #1 din[i*8 +: 8];
if(bwe[i]) RAM[addr][i*8 +: 8] <= din[i*8 +: 8];
if (WIDTH%8 != 0) // handle msbs if width not a multiple of 8
always @(posedge clk)
if (ce & we & bwe[WIDTH/8])
RAM[addr][WIDTH-1:WIDTH-WIDTH%8] <= #1 din[WIDTH-1:WIDTH-WIDTH%8];
RAM[addr][WIDTH-1:WIDTH-WIDTH%8] <= din[WIDTH-1:WIDTH-WIDTH%8];
end
endmodule

4
src/generic/mem/ram1p1rwe.sv
View file

@ -78,7 +78,7 @@ module ram1p1rwe import cvw::* ; #(parameter USE_SRAM=0, DEPTH=64, WIDTH=44) (
/* // Alternate read logic reads the old contents of mem[addr]. Increases setup time and adds dout reg, but reduces clk to q
always_ff @(posedge clk)
if(ce) dout <= #1 mem[addr]; */
if(ce) dout <= mem[addr]; */
// Write divided into part for bytes and part for extra msbs
// Questa sim version 2022.3_2 does not allow multiple drivers for RAM when using always_ff.
@ -90,6 +90,6 @@ module ram1p1rwe import cvw::* ; #(parameter USE_SRAM=0, DEPTH=64, WIDTH=44) (
// so we can never get we=1, ce=0 for I$.
if (ce & we)
// coverage on
RAM[addr] <= #1 din;
RAM[addr] <= din;
end
endmodule

4
src/generic/mem/ram2p1r1wbe.sv
View file

@ -130,13 +130,13 @@ module ram2p1r1wbe import cvw::*; #(parameter USE_SRAM=0, DEPTH=1024, WIDTH=68)
always @(posedge clk)
if (ce2 & we2)
for(i = 0; i < WIDTH/8; i++)
if(bwe2[i]) mem[wa2][i*8 +: 8] <= #1 wd2[i*8 +: 8];
if(bwe2[i]) mem[wa2][i*8 +: 8] <= wd2[i*8 +: 8];
// coverage on
if (WIDTH%8 != 0) // handle msbs if width not a multiple of 8
always @(posedge clk)
if (ce2 & we2 & bwe2[WIDTH/8])
mem[wa2][WIDTH-1:WIDTH-WIDTH%8] <= #1 wd2[WIDTH-1:WIDTH-WIDTH%8];
mem[wa2][WIDTH-1:WIDTH-WIDTH%8] <= wd2[WIDTH-1:WIDTH-WIDTH%8];
end
endmodule

18
src/hazard/hazard.sv
View file

@ -93,12 +93,12 @@ module hazard import cvw::*; #(parameter cvw_t P) (
// Stall each stage for cause or if the next stage is stalled
// coverage off: StallFCause is always 0
assign #1 StallF = StallFCause | StallD;
assign StallF = StallFCause | StallD;
// coverage on
assign #1 StallD = StallDCause | StallE;
assign #1 StallE = StallECause | StallM;
assign #1 StallM = StallMCause | StallW;
assign #1 StallW = StallWCause;
assign StallD = StallDCause | StallE;
assign StallE = StallECause | StallM;
assign StallM = StallMCause | StallW;
assign StallW = StallWCause;
// detect the first stage that is not stalled
assign LatestUnstalledD = ~StallD & StallF;
@ -107,8 +107,8 @@ module hazard import cvw::*; #(parameter cvw_t P) (
assign LatestUnstalledW = ~StallW & StallM;
// Each stage flushes if the previous stage is the last one stalled (for cause) or the system has reason to flush
assign #1 FlushD = LatestUnstalledD | FlushDCause;
assign #1 FlushE = LatestUnstalledE | FlushECause;
assign #1 FlushM = LatestUnstalledM | FlushMCause;
assign #1 FlushW = LatestUnstalledW | FlushWCause;
assign FlushD = LatestUnstalledD | FlushDCause;
assign FlushE = LatestUnstalledE | FlushECause;
assign FlushM = LatestUnstalledM | FlushMCause;
assign FlushW = LatestUnstalledW | FlushWCause;
endmodule

4
src/ieu/aes/aes32d.sv
View file

@ -34,8 +34,8 @@ module aes32d(
logic [7:0] SboxOut;
logic [31:0] so, mixed;
aesinvsbox inv_sbox(SboxIn, SboxOut); // Apply inverse sbox to si
aesinvsbox8 inv_sbox(SboxIn, SboxOut); // Apply inverse sbox to si
assign so = {24'h0, SboxOut}; // Pad output of inverse substitution box
aesinvmixcolumns mix(so, mixed); // Run so through the mixword AES function
aesinvmixcolumns32 mix(so, mixed); // Run so through the mixword AES function
mux2 #(32) rmux(mixed, so, finalround, result); // on final round, skip mixcolumns
endmodule

4
src/ieu/aes/aes32e.sv
View file

@ -34,8 +34,8 @@ module aes32e(
logic [7:0] SboxOut;
logic [31:0] so, mixed;
aessbox sbox(SboxIn, SboxOut); // Substitute
aessbox8 sbox(SboxIn, SboxOut); // Substitute
assign so = {24'h0, SboxOut}; // Pad sbox output
aesmixcolumns mwd(so, mixed); // Mix Word using aesmixword component
aesmixcolumns32 mwd(so, mixed); // Mix Word using aesmixword component
mux2 #(32) rmux(mixed, so, finalround, result); // on final round, skip mixcolumns
endmodule

14
src/ieu/aes/aes64d.sv
View file

@ -32,21 +32,19 @@ module aes64d(
output logic [63:0] result
);
logic [127:0] ShiftRowOut;
logic [63:0] SboxOut, MixcolIn, MixcolOut;
logic [63:0] ShiftRowOut, SboxOut, MixcolIn, MixcolOut;
// Apply inverse shiftrows to rs2 and rs1
aesinvshiftrow srow({rs2, rs1}, ShiftRowOut);
aesinvshiftrow64 srow({rs2, rs1}, ShiftRowOut);
// Apply full word inverse substitution to lower 2 words of shiftrow out
aesinvsboxword invsbox0(ShiftRowOut[31:0], SboxOut[31:0]);
aesinvsboxword invsbox1(ShiftRowOut[63:32], SboxOut[63:32]);
// Apply full word inverse substitution to lower doubleord of shiftrow out
aesinvsbox64 invsbox(ShiftRowOut, SboxOut);
mux2 #(64) mixcolmux(SboxOut, rs1, aes64im, MixcolIn);
// Apply inverse mixword to sbox outputs
aesinvmixcolumns invmw0(MixcolIn[31:0], MixcolOut[31:0]);
aesinvmixcolumns invmw1(MixcolIn[63:32], MixcolOut[63:32]);
aesinvmixcolumns32 invmw0(MixcolIn[31:0], MixcolOut[31:0]);
aesinvmixcolumns32 invmw1(MixcolIn[63:32], MixcolOut[63:32]);
// Final round skips mixcolumns.
mux2 #(64) resultmux(MixcolOut, SboxOut, finalround, result);

11
src/ieu/aes/aes64e.sv
View file

@ -34,22 +34,21 @@ module aes64e(
output logic [63:0] result
);
logic [127:0] ShiftRowOut;
logic [63:0] SboxOut, MixcolOut;
logic [63:0] ShiftRowOut, SboxOut, MixcolOut;
// AES shiftrow unit
aesshiftrow srow({rs2,rs1}, ShiftRowOut);
aesshiftrow64 srow({rs2,rs1}, ShiftRowOut);
// Apply substitution box to 2 lower words
// Use the shared sbox in zknde64.sv for the first sbox
assign SboxEIn = ShiftRowOut[31:0];
assign SboxOut[31:0] = Sbox0Out;
aessboxword sbox1(ShiftRowOut[63:32], SboxOut[63:32]); // instantiate second sbox
aessbox32 sbox1(ShiftRowOut[63:32], SboxOut[63:32]); // instantiate second sbox
// Apply mix columns operations
aesmixcolumns mw0(SboxOut[31:0], MixcolOut[31:0]);
aesmixcolumns mw1(SboxOut[63:32], MixcolOut[63:32]);
aesmixcolumns32 mw0(SboxOut[31:0], MixcolOut[31:0]);
aesmixcolumns32 mw1(SboxOut[63:32], MixcolOut[63:32]);
// Skip mixcolumns on last round
mux2 #(64) resultmux(MixcolOut, SboxOut, finalround, result);

8
src/ieu/aes/aes64ks1i.sv
View file

@ -34,19 +34,17 @@ module aes64ks1i(
);
logic finalround;
logic [7:0] rcon8;
logic [31:0] rcon, rs1Rotate;
rconlut128 rc(round, rcon8); // Get rcon value from lookup table
assign rcon = {24'b0, rcon8}; // Zero-pad RCON
rconlut32 rc(round, rcon); // Get rcon value from lookup table
assign rs1Rotate = {rs1[39:32], rs1[63:40]}; // Get rotated value fo ruse in tmp2
assign finalround = (round == 4'b1010); // round 10 is the last one
assign SboxKIn = finalround ? rs1[63:32] : rs1Rotate; // Don't rotate on the last round
assign SboxKIn = finalround ? rs1[63:32] : rs1Rotate; // Don't rotate on the last round
// Share sbox with encryption in zknde64. This module just sends value to shared sbox and gets result back
// send out value as SboxKIn, get back subsittuted result as Sbox0Out
assign result[31:0] = Sbox0Out ^ rcon;
assign result[31:0] = Sbox0Out ^ rcon;
assign result[63:32] = Sbox0Out ^ rcon;
endmodule

12
src/ieu/aes/aesinvmixcolumns.sv → src/ieu/aes/aesinvmixcolumns32.sv
View file

@ -1,5 +1,5 @@
///////////////////////////////////////////
// aesinvmixcolumns.sv
// aesinvmixcolumns32.sv
//
// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
// Created: 05 March 2024
@ -25,7 +25,7 @@
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module aesinvmixcolumns(
module aesinvmixcolumns32(
input logic [31:0] a,
output logic [31:0] y
);
@ -41,8 +41,8 @@ module aesinvmixcolumns(
assign xor2 = {temp, 3'b0} ^ {1'b0, a1^a3, 2'b0} ^ {2'b0, a1^a0, 1'b0} ^ {3'b0, temp} ^ {3'b0, a1};
assign xor3 = {temp, 3'b0} ^ {1'b0, a0^a2, 2'b0} ^ {2'b0, a0^a3, 1'b0} ^ {3'b0, temp} ^ {3'b0, a0};
galoismultinverse gm0 (xor0, y[7:0]);
galoismultinverse gm1 (xor1, y[15:8]);
galoismultinverse gm2 (xor2, y[23:16]);
galoismultinverse gm3 (xor3, y[31:24]);
galoismultinverse8 gm0 (xor0, y[7:0]);
galoismultinverse8 gm1 (xor1, y[15:8]);
galoismultinverse8 gm2 (xor2, y[23:16]);
galoismultinverse8 gm3 (xor3, y[31:24]);
endmodule

22
src/ieu/aes/aesinvsboxword.sv → src/ieu/aes/aesinvsbox64.sv
View file

@ -1,5 +1,5 @@
///////////////////////////////////////////
// aesinvsboxword.sv
// aesinvsbox64.sv
//
// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
@ -25,14 +25,18 @@
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module aesinvsboxword(
input logic [31:0] a,
output logic [31:0] y
module aesinvsbox64(
input logic [63:0] a,
output logic [63:0] y
);
// inverse substitutions boxes for each byte of the word
aesinvsbox sboxb0(a[7:0], y[7:0]);
aesinvsbox sboxb1(a[15:8], y[15:8]);
aesinvsbox sboxb2(a[23:16], y[23:16]);
aesinvsbox sboxb3(a[31:24], y[31:24]);
// inverse substitutions boxes for each byte of the 32-bit word
aesinvsbox8 sbox0(a[7:0], y[7:0]);
aesinvsbox8 sbox1(a[15:8], y[15:8]);
aesinvsbox8 sbox2(a[23:16], y[23:16]);
aesinvsbox8 sbox3(a[31:24], y[31:24]);
aesinvsbox8 sbox4(a[39:32], y[39:32]);
aesinvsbox8 sbox5(a[47:40], y[47:40]);
aesinvsbox8 sbox6(a[55:48], y[55:48]);
aesinvsbox8 sbox7(a[63:56], y[63:56]);
endmodule

4
src/ieu/aes/aesinvsbox.sv → src/ieu/aes/aesinvsbox8.sv
View file

@ -1,5 +1,5 @@
///////////////////////////////////////////
// aesinvsbox.sv
// aesinvsbox8.sv
//
// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
@ -25,7 +25,7 @@
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module aesinvsbox(
module aesinvsbox8(
input logic [7:0] a,
output logic [7:0] y
);

8
src/ieu/aes/aesinvshiftrow.sv → src/ieu/aes/aesinvshiftrow64.sv
View file

@ -25,13 +25,11 @@
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module aesinvshiftrow(
module aesinvshiftrow64(
input logic [127:0] a,
output logic [127:0] y
output logic [63:0] y
);
assign y = {a[31:24], a[55:48], a[79:72], a[103:96],
a[127:120], a[23:16], a[47:40], a[71:64],
a[95:88], a[119:112], a[15:8], a[39:32],
assign y = {a[95:88], a[119:112], a[15:8], a[39:32],
a[63:56], a[87:80], a[111:104], a[7:0]};
endmodule

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