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Moved lsuvirtmem muxes into hptw
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David Harris
parent
fd1ef82310
commit
9b20bf341e
3 changed files with 76 additions and 141 deletions
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@ -124,12 +124,12 @@ module lsu (
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assign LSUStallM = DCacheStallM | HPTWStall | BusStall;
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/////////////////////////////////////////////////////////////////////////////////////////////
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// HPTW and Interlock FSM (only needed if VM supported)
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// HPTW(only needed if VM supported)
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// MMU include PMP and is needed if any privileged supported
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/////////////////////////////////////////////////////////////////////////////////////////////
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if(`VIRTMEM_SUPPORTED) begin : VIRTMEM_SUPPORTED
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lsuvirtmem lsuvirtmem(.clk, .reset, .StallW, .MemRWM, .AtomicM, .ITLBMissF, .ITLBWriteF,
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hptw hptw(.clk, .reset, .StallW, .MemRWM, .AtomicM, .ITLBMissF, .ITLBWriteF,
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.DTLBMissM, .DTLBWriteM, .InstrDAPageFaultF, .DataDAPageFaultM,
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.TrapM, .DCacheStallM, .SATP_REGW, .PCF,
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.STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .PrivilegeModeW,
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@ -1,112 +0,0 @@
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///////////////////////////////////////////
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// lsuvirtmem.sv
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//
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// Written: Ross Thompson ross1728@gmail.com January 30, 2022
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// Modified:
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//
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// Purpose: Encapsulates the hptw and muxes required to support virtual memory.
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module lsuvirtmem(
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input logic clk, reset, StallW,
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input logic [1:0] MemRWM,
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input logic [1:0] AtomicM,
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input logic ITLBMissF,
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output logic ITLBWriteF,
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input logic DTLBMissM,
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output logic DTLBWriteM,
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input logic InstrDAPageFaultF,
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input logic DataDAPageFaultM,
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input logic TrapM,
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input logic DCacheStallM,
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input logic [`XLEN-1:0] SATP_REGW, // from csr
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input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV,
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input logic [1:0] STATUS_MPP,
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input logic [1:0] PrivilegeModeW,
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input logic [`XLEN-1:0] PCF,
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input logic [`XLEN-1:0] ReadDataM,
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input logic [`XLEN-1:0] WriteDataM,
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input logic [2:0] Funct3M,
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output logic [2:0] LSUFunct3M,
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input logic [6:0] Funct7M,
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output logic [6:0] LSUFunct7M,
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output logic [`XLEN-1:0] PTE,
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output logic [`XLEN-1:0] IMWriteDataM,
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output logic [1:0] PageType,
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output logic [1:0] PreLSURWM,
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output logic [1:0] LSUAtomicM,
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output logic [`XLEN+1:0] IHAdrM,
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input logic [`XLEN+1:0] IEUAdrExtM, // *** can move internally.
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output logic HPTWStall,
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output logic CPUBusy,
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output logic SelHPTW,
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output logic IgnoreRequestTLB);
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logic AnyCPUReqM;
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logic [`PA_BITS-1:0] HPTWAdr;
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logic [`XLEN+1:0] HPTWAdrExt;
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logic [1:0] HPTWRW;
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logic [2:0] HPTWSize;
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logic ITLBMissOrDAFaultF, ITLBMissOrDAFaultNoTrapF;
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logic DTLBMissOrDAFaultM, DTLBMissOrDAFaultNoTrapM;
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logic SelHPTWAdr;
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assign ITLBMissOrDAFaultF = ITLBMissF | (`HPTW_WRITES_SUPPORTED & InstrDAPageFaultF);
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assign DTLBMissOrDAFaultM = DTLBMissM | (`HPTW_WRITES_SUPPORTED & DataDAPageFaultM);
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assign ITLBMissOrDAFaultNoTrapF = ITLBMissOrDAFaultF & ~TrapM;
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assign DTLBMissOrDAFaultNoTrapM = DTLBMissOrDAFaultM & ~TrapM;
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hptw hptw(
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.clk, .reset, .SATP_REGW, .PCF, .IEUAdrExtM, .MemRWM, .AtomicM,
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.STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .PrivilegeModeW,
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.ITLBMissOrDAFaultNoTrapF, .DTLBMissOrDAFaultNoTrapM,
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.PTE, .PageType, .ITLBWriteF, .DTLBWriteM, .HPTWReadPTE(ReadDataM), // *** should it be HPTWReadDataM
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.DCacheStallM, .HPTWAdr, .HPTWRW, .HPTWSize, .IgnoreRequestTLB, .SelHPTW, .HPTWStall);
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// *** possible future optimization of simplifying page table entry with precomputed misalignment (Ross) low priority
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// Once the walk is done and it is time to update the TLB we need to switch back
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// to the orignal data virtual address.
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assign SelHPTWAdr = SelHPTW & ~(DTLBWriteM | ITLBWriteF);
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// multiplex the outputs to LSU
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if(`XLEN+2-`PA_BITS > 0) begin
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logic [(`XLEN+2-`PA_BITS)-1:0] zeros;
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assign zeros = '0;
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assign HPTWAdrExt = {zeros, HPTWAdr};
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end else assign HPTWAdrExt = HPTWAdr;
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mux2 #(2) rwmux(MemRWM, HPTWRW, SelHPTW, PreLSURWM);
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mux2 #(3) sizemux(Funct3M, HPTWSize, SelHPTW, LSUFunct3M);
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mux2 #(7) funct7mux(Funct7M, 7'b0, SelHPTW, LSUFunct7M);
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mux2 #(2) atomicmux(AtomicM, 2'b00, SelHPTW, LSUAtomicM);
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mux2 #(`XLEN+2) lsupadrmux(IEUAdrExtM, HPTWAdrExt, SelHPTWAdr, IHAdrM);
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if(`HPTW_WRITES_SUPPORTED)
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mux2 #(`XLEN) lsuwritedatamux(WriteDataM, PTE, SelHPTW, IMWriteDataM);
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else assign IMWriteDataM = WriteDataM;
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// always block interrupts when using the hardware page table walker.
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assign CPUBusy = StallW & ~SelHPTW;
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endmodule
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@ -30,9 +30,8 @@
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`include "wally-config.vh"
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module hptw
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(
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input logic clk, reset,
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module hptw (
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input logic clk, reset, StallW,
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input logic [`XLEN-1:0] SATP_REGW, // includes SATP.MODE to determine number of levels in page table
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input logic [`XLEN-1:0] PCF, // addresses to translate
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input logic [`XLEN+1:0] IEUAdrExtM, // addresses to translate
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@ -41,17 +40,28 @@ module hptw
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input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV,
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input logic [1:0] STATUS_MPP,
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input logic [1:0] PrivilegeModeW,
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(* mark_debug = "true" *) input logic ITLBMissOrDAFaultNoTrapF, DTLBMissOrDAFaultNoTrapM, // TLB Miss
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input logic [`XLEN-1:0] HPTWReadPTE, // page table entry from LSU *** change to ReadDataM
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input logic [`XLEN-1:0] ReadDataM, // page table entry from LSU
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input logic [`XLEN-1:0] WriteDataM,
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input logic DCacheStallM, // stall from LSU
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input logic [2:0] Funct3M,
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input logic [6:0] Funct7M,
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input logic ITLBMissF,
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input logic DTLBMissM,
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input logic TrapM,
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input logic InstrDAPageFaultF,
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input logic DataDAPageFaultM,
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output logic [`XLEN-1:0] PTE, // page table entry to TLBs
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output logic [1:0] PageType, // page type to TLBs
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(* mark_debug = "true" *) output logic ITLBWriteF, DTLBWriteM, // write TLB with new entry
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output logic [`PA_BITS-1:0] HPTWAdr,
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output logic [1:0] HPTWRW, // HPTW requesting to write or read memory
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output logic [2:0] HPTWSize, // 32 or 64 bit access.
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output logic [1:0] PreLSURWM,
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output logic [`XLEN+1:0] IHAdrM,
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output logic [`XLEN-1:0] IMWriteDataM,
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output logic [1:0] LSUAtomicM,
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output logic [2:0] LSUFunct3M,
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output logic [6:0] LSUFunct7M,
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output logic IgnoreRequestTLB,
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output logic SelHPTW,
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output logic CPUBusy,
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output logic HPTWStall
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);
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@ -77,6 +87,14 @@ module hptw
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logic UpdatePTE;
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logic DAPageFault;
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logic [`PA_BITS-1:0] HPTWReadAdr;
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logic SelHPTWAdr;
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logic [`XLEN+1:0] HPTWAdrExt;
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logic ITLBMissOrDAFaultF, ITLBMissOrDAFaultNoTrapF;
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logic DTLBMissOrDAFaultM, DTLBMissOrDAFaultNoTrapM;
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logic [`PA_BITS-1:0] HPTWAdr;
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logic [1:0] HPTWRW;
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logic [2:0] HPTWSize; // 32 or 64 bit access.
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(* mark_debug = "true" *) statetype WalkerState, NextWalkerState, InitialWalkerState;
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@ -119,7 +137,7 @@ module hptw
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logic [`XLEN-1:0] AccessedPTE;
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assign AccessedPTE = {PTE[`XLEN-1:8], (SetDirty | PTE[7]), 1'b1, PTE[5:0]}; // set accessed bit, conditionally set dirty bit
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mux2 #(`XLEN) NextPTEMux(HPTWReadPTE, AccessedPTE, UpdatePTE, NextPTE);
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mux2 #(`XLEN) NextPTEMux(ReadDataM, AccessedPTE, UpdatePTE, NextPTE);
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flopenr #(`PA_BITS) HPTWAdrWriteReg(clk, reset, SaveHPTWAdr, HPTWReadAdr, HPTWWriteAdr);
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assign SaveHPTWAdr = WalkerState == L0_ADR;
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@ -150,9 +168,9 @@ module hptw
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assign DAPageFault = ValidLeafPTE & (~Accessed | SetDirty) & ~OtherPageFault;
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assign HPTWRW[0] = (WalkerState == UPDATE_PTE);
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assign UpdatePTE = WalkerState == LEAF & DAPageFault;
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assign UpdatePTE = (WalkerState == LEAF) & DAPageFault;
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end else begin // block: hptwwrites
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assign NextPTE = HPTWReadPTE;
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assign NextPTE = ReadDataM;
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assign HPTWAdr = HPTWReadAdr;
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assign DAPageFault = '0;
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assign UpdatePTE = '0;
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@ -249,4 +267,33 @@ module hptw
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assign SelHPTW = WalkerState != IDLE;
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assign HPTWStall = (WalkerState != IDLE) | (WalkerState == IDLE & TLBMiss);
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assign ITLBMissOrDAFaultF = ITLBMissF | (`HPTW_WRITES_SUPPORTED & InstrDAPageFaultF);
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assign DTLBMissOrDAFaultM = DTLBMissM | (`HPTW_WRITES_SUPPORTED & DataDAPageFaultM);
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assign ITLBMissOrDAFaultNoTrapF = ITLBMissOrDAFaultF & ~TrapM;
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assign DTLBMissOrDAFaultNoTrapM = DTLBMissOrDAFaultM & ~TrapM;
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// HTPW address/data/control muxing
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// Once the walk is done and it is time to update the TLB we need to switch back
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// to the orignal data virtual address.
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assign SelHPTWAdr = SelHPTW & ~(DTLBWriteM | ITLBWriteF);
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// always block interrupts when using the hardware page table walker.
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assign CPUBusy = StallW & ~SelHPTW;
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// multiplex the outputs to LSU
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if(`XLEN+2-`PA_BITS > 0) begin // *** replace with XLEN=32
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logic [(`XLEN+2-`PA_BITS)-1:0] zeros;
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assign zeros = '0;
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assign HPTWAdrExt = {zeros, HPTWAdr};
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end else assign HPTWAdrExt = HPTWAdr;
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mux2 #(2) rwmux(MemRWM, HPTWRW, SelHPTW, PreLSURWM);
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mux2 #(3) sizemux(Funct3M, HPTWSize, SelHPTW, LSUFunct3M);
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mux2 #(7) funct7mux(Funct7M, 7'b0, SelHPTW, LSUFunct7M);
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mux2 #(2) atomicmux(AtomicM, 2'b00, SelHPTW, LSUAtomicM);
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mux2 #(`XLEN+2) lsupadrmux(IEUAdrExtM, HPTWAdrExt, SelHPTWAdr, IHAdrM);
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if(`HPTW_WRITES_SUPPORTED)
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mux2 #(`XLEN) lsuwritedatamux(WriteDataM, PTE, SelHPTW, IMWriteDataM);
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else assign IMWriteDataM = WriteDataM;
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endmodule
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