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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev

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This commit is contained in:
David Harris 2025-05-08 19:55:18 -07:00
commit 9c2090950b
3 changed files with 24 additions and 17 deletions
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19
bin/regression-wally
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@ -528,25 +528,18 @@ def selectTests(args, sims, coverStr):
if (args.performance or args.nightly): if (args.performance or args.nightly):
# RUNNING THE EMBENCH TEST # RUNNING THE EMBENCH TEST
actual_embench_directory = f"{WALLY}/benchmarks/embench/actual_embench_results/" embench_dir = f"{WALLY}/benchmarks/embench/"
expected_embench_directory = f"{WALLY}/benchmarks/embench/expected_embench_results/" actual_embench_directory = f"{embench_dir}/actual_embench_results/"
embench_logfile_path = os.path.expandvars("$WALLY/benchmarks/embench/run.log") expected_embench_directory = f"{embench_dir}/expected_embench_results/"
# Create the file if it doesn't exist embench_logfile_path = f"{embench_dir}/run.log"
with open(embench_logfile_path, 'w'):
pass
# Combine everything into the embench_test command
# finds any differences between the two embench directories and appends them to the log file # finds any differences between the two embench directories and appends them to the log file
embench_test = TestCase( embench_test = TestCase(
name="embench", name="embench",
variant="rv32gc", variant="rv32gc",
cmd=( cmd=(f"make -C {WALLY}/benchmarks/embench run > {embench_logfile_path}"),
f"cd $WALLY/benchmarks/embench && "
f"make run >> {embench_logfile_path} 2>&1"
),
grepstr=None, grepstr=None,
grepfile=embench_logfile_path, grepfile=embench_logfile_path,
altcommand=f"diff -ru {actual_embench_directory} {expected_embench_directory} >> {embench_logfile_path}" altcommand=f"diff -ru {actual_embench_directory} {expected_embench_directory} > {embench_logfile_path}"
) )
configs.append(embench_test) configs.append(embench_test)

7
testbench/testbench.sv
View file

@ -715,13 +715,16 @@ module testbench;
// 3. or PC is stuck at 0 // 3. or PC is stuck at 0
logic [P.XLEN-1:0] PCM;
// PCM is not valid for configurations without ZICSR or branch predictor
flopenr #(P.XLEN) PCMReg(clk, reset, ~dut.core.StallM, dut.core.PCE, PCM);
always @(posedge clk) begin always @(posedge clk) begin
TestComplete <= ((InstrM == 32'h6f) & dut.core.InstrValidM ) | TestComplete <= ((InstrM == 32'h6f) & dut.core.InstrValidM ) |
((dut.core.lsu.IEUAdrM == ProgramAddrLabelArray["tohost"] & dut.core.lsu.IEUAdrM != 0) & InstrMName == "SW"); // | ((dut.core.lsu.IEUAdrM == ProgramAddrLabelArray["tohost"] & dut.core.lsu.IEUAdrM != 0) & InstrMName == "SW"); // |
// (functionName.PCM == 0 & dut.core.ifu.InstrM == 0 & dut.core.InstrValidM & PrevPCZero)); // (functionName.PCM == 0 & dut.core.ifu.InstrM == 0 & dut.core.InstrValidM & PrevPCZero));
if (reset) PrevPCZero <= 0; if (reset) PrevPCZero <= 0;
else if (dut.core.InstrValidM) PrevPCZero <= (dut.core.PCM == 0 & dut.core.ifu.InstrM == 0); else if (dut.core.InstrValidM) PrevPCZero <= (PCM == 0 & dut.core.ifu.InstrM == 0);
if (dut.core.PCM == 0 & dut.core.ifu.InstrM == 0 & dut.core.InstrValidM & PrevPCZero) begin if (PCM == 0 & dut.core.ifu.InstrM == 0 & dut.core.InstrValidM & PrevPCZero) begin
$error("Program fetched illegal instruction 0x00000000 from address 0x00000000 twice in a row. Usually due to fault with no fault handler."); $error("Program fetched illegal instruction 0x00000000 from address 0x00000000 twice in a row. Usually due to fault with no fault handler.");
$fatal(1); $fatal(1);
end end

15
tests/coverage/tlbmisc.S
View file

@ -145,6 +145,13 @@ ConcurrentICacheMissDTLBMiss:
sw t1, 0(t0) # write to page sw t1, 0(t0) # write to page
jalr ra, t0 # jump to page jalr ra, t0 # jump to page
sfence.vma
li t0, 0x18000000000
lw t1, 0(t0) # read from page
sw t1, 0(t0) # write to page
jalr ra, t0 # jump to page
# jump to address for TLB miss to trigger HPTW to make access with DisableTranslation = 1, Translate = 0 # jump to address for TLB miss to trigger HPTW to make access with DisableTranslation = 1, Translate = 0
li t0, 0x80805000 li t0, 0x80805000
jalr ra, t0 jalr ra, t0
@ -264,6 +271,10 @@ ConcurrentICacheMissDTLBMiss:
cbo.zero (t0) cbo.zero (t0)
cbo.clean (t0) cbo.clean (t0)
# attempt read from read disabled, execute enabled PTE with MXR set
li t0, 0x81600000
lw t1, 0(t0) # read from page
# clear mstatus.MXR # clear mstatus.MXR
li a0, 3 li a0, 3
ecall ecall
@ -344,7 +355,7 @@ pagetable:
.8byte 0x20004401 # VA 0x00000000-0x7F_FFFFFFFF: PTE at 0x80011000 01 valid .8byte 0x20004401 # VA 0x00000000-0x7F_FFFFFFFF: PTE at 0x80011000 01 valid
.8byte 0x00000000000010CF # misaligned terapage at 0x80_00000000 .8byte 0x00000000000010CF # misaligned terapage at 0x80_00000000
.8byte 0x00000000000000CF # access fault terapage at 0x100_00000000 .8byte 0x00000000000000CF # access fault terapage at 0x100_00000000
.8byte 0x4000000020004401 # Bad PBMT at VA 0x180_0000000 .8byte 0x4000000020004401 # Bad PBMT at VA 0x180_00000000
# next page table at 0x80011000 # next page table at 0x80011000
.align 12 .align 12
@ -373,7 +384,7 @@ SpecialPage:
.8byte 0x0000000000004C01 # for VA starting at 81000000 (nonleaf pointing to unimplemented memory causes access fault) .8byte 0x0000000000004C01 # for VA starting at 81000000 (nonleaf pointing to unimplemented memory causes access fault)
.8byte 0x4000000020004C01 # for VA starting at 81200000 (nonleaf with PBMT nonzero causes page fault) .8byte 0x4000000020004C01 # for VA starting at 81200000 (nonleaf with PBMT nonzero causes page fault)
.8byte 0x00000000000000CF # for VA starting at 81400000 (megapage with access fault) .8byte 0x00000000000000CF # for VA starting at 81400000 (megapage with access fault)
.8byte 0x0000000020004CC1 .8byte 0x0000000020004C09 # for VA starting at 81600000 (executable and not readable)
.8byte 0x0000000020004CC1 .8byte 0x0000000020004CC1
.8byte 0x0000000020004CC1 .8byte 0x0000000020004CC1
.8byte 0x0000000020004CC1 .8byte 0x0000000020004CC1