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Merge branch 'main' of https://github.com/openhwgroup/cvw

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This commit is contained in:
Rose Thompson 2024-10-10 09:11:30 -05:00
commit 9ddbc8bc24
16 changed files with 78 additions and 5816 deletions
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1
bin/regression-wally
View file

@ -414,6 +414,7 @@ if (args.ccov): # only run RV64GC tests on Questa in code coverage mode
elif (args.fcov): # only run RV64GC tests on Questa in lockstep in functional coverage mode
addLockstepTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/rv32/", "rv32gc", coveragesim, 1)
addLockstepTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/rv64/", "rv64gc", coveragesim, 1)
addLockstepTestsByDir(WALLY+"/tests/riscof/work/wally-riscv-arch-test/rv64i_m/privilege/src/", "rv64gc", coveragesim, 0)
elif (args.fcovrvvi): # only run RV64GC tests on Questa in rvvi coverage mode
addTests(tests64gc_nofp, coveragesim)
if (args.fp):

2
bin/requirements.txt
View file

@ -3,7 +3,7 @@ lief>=0.14.1
Markdown>=3.6
matplotlib>=3.9.0
PyYAML>=5.2
riscv-isac @ git+https://github.com/riscv-software-src/riscv-isac@dev
riscv-isac @ git+https://github.com/riscv-non-isa/riscv-arch-test/#subdirectory=riscv-isac
riscof @ git+https://github.com/riscv/riscof.git
riscv-config>=3.18.3
riscv-isac>=0.18.0

48
bin/wally-tool-chain-install.sh
View file

@ -48,6 +48,7 @@ ENDC='\033[0m' # Reset to default color
error() {
echo -e "${FAIL_COLOR}Error: $STATUS installation failed"
echo -e "Error on line ${BASH_LINENO[0]} with command $BASH_COMMAND${ENDC}"
echo -e "Please check the log in $RISCV/logs/$STATUS.log for more information."
exit 1
}
@ -68,7 +69,7 @@ git_check() {
# Log output to a file and only print lines with keywords
logger() {
local log="$RISCV/logs/$1.log"
cat < /dev/stdin | tee -a "$log" | (grep -iE --color=never "(\bwarning|\berror|\bfail|\bsuccess|\bstamp)" || true) | (grep -viE --color=never "(_warning|warning_|_error|error_|-warning|warning-|-error|error-|Werror|error\.o|warning flags)" || true)
cat < /dev/stdin | tee -a "$log" | (grep -iE --color=never "(\bwarning|\berror|\bfail|\bsuccess|\bstamp|\bdoesn't work)" || true) | (grep -viE --color=never "(_warning|warning_|_error|error_|-warning|warning-|-error|error-|Werror|error\.o|warning flags)" || true)
}
set -e # break on error
@ -104,6 +105,13 @@ fi
export PATH=$PATH:$RISCV/bin:/usr/bin
export PKG_CONFIG_PATH=$RISCV/lib64/pkgconfig:$RISCV/lib/pkgconfig:$RISCV/share/pkgconfig:$RISCV/lib/x86_64-linux-gnu/pkgconfig:$PKG_CONFIG_PATH
# Check for incompatible PATH environment variable before proceeding with installation
if [[ ":$PATH:" == *::* || ":$PATH:" == *:.:* ]]; then
echo -e "${FAIL_COLOR}Error: You seem to have the current working directory in your \$PATH environment variable."
echo -e "This won't work. Please update your \$PATH and try again.${ENDC}"
exit 1
fi
# Create installation directory
mkdir -p "$RISCV"/logs
echo "Running as root: $ROOT"
@ -198,14 +206,14 @@ fi
# This configuration enables multilib to target many flavors of RISC-V.
# This book is tested with GCC 13.2.0
section_header "Installing/Updating RISC-V GNU Toolchain"
STATUS="RISC-V GNU Toolchain"
STATUS="riscv-gnu-toolchain"
cd "$RISCV"
# Temporarily pin riscv-gnu-toolchain to use GCC 13.2.0. GCC 14 does not work with the Q extension.
if git_check "riscv-gnu-toolchain" "https://github.com/riscv/riscv-gnu-toolchain" "$RISCV/riscv-gnu-toolchain/stamps/build-gcc-newlib-stage2" "b488ddb"; then
cd riscv-gnu-toolchain
git reset --hard && git clean -f && git checkout b488ddb #&& git pull
./configure --prefix="${RISCV}" --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;"
make -j "${NUM_THREADS}" 2>&1 | logger riscv-gnu-toolchain; [ "${PIPESTATUS[0]}" == 0 ]
make -j "${NUM_THREADS}" 2>&1 | logger $STATUS; [ "${PIPESTATUS[0]}" == 0 ]
if [ "$clean" ]; then
cd "$RISCV"
rm -rf riscv-gnu-toolchain
@ -232,8 +240,8 @@ if git_check "elf2hex" "https://github.com/sifive/elf2hex.git" "$RISCV/bin/riscv
git reset --hard && git clean -f && git checkout master && git pull
autoreconf -i
./configure --target=riscv64-unknown-elf --prefix="$RISCV"
make 2>&1 | logger elf2hex; [ "${PIPESTATUS[0]}" == 0 ]
make install 2>&1 | logger elf2hex; [ "${PIPESTATUS[0]}" == 0 ]
make 2>&1 | logger $STATUS; [ "${PIPESTATUS[0]}" == 0 ]
make install 2>&1 | logger $STATUS; [ "${PIPESTATUS[0]}" == 0 ]
if [ "$clean" ]; then
cd "$RISCV"
rm -rf elf2hex
@ -247,15 +255,15 @@ fi
# QEMU (https://www.qemu.org/docs/master/system/target-riscv.html)
# QEMU is an open source machine emulator and virtualizer capable of emulating RISC-V
section_header "Installing/Updating QEMU"
STATUS="QEMU"
STATUS="qemu"
cd "$RISCV"
if git_check "qemu" "https://github.com/qemu/qemu" "$RISCV/include/qemu-plugin.h"; then
cd qemu
git reset --hard && git clean -f && git checkout master && git pull --recurse-submodules -j "${NUM_THREADS}"
git submodule update --init --recursive
./configure --target-list=riscv64-softmmu --prefix="$RISCV"
make -j "${NUM_THREADS}" 2>&1 | logger qemu; [ "${PIPESTATUS[0]}" == 0 ]
make install 2>&1 | logger qemu; [ "${PIPESTATUS[0]}" == 0 ]
make -j "${NUM_THREADS}" 2>&1 | logger $STATUS; [ "${PIPESTATUS[0]}" == 0 ]
make install 2>&1 | logger $STATUS; [ "${PIPESTATUS[0]}" == 0 ]
if [ "$clean" ]; then
cd "$RISCV"
rm -rf qemu
@ -269,7 +277,7 @@ fi
# Spike (https://github.com/riscv-software-src/riscv-isa-sim)
# Spike is a reference model for RISC-V. It is a functional simulator that can be used to run RISC-V programs.
section_header "Installing/Updating SPIKE"
STATUS="SPIKE"
STATUS="spike"
cd "$RISCV"
if git_check "riscv-isa-sim" "https://github.com/riscv-software-src/riscv-isa-sim" "$RISCV/lib/pkgconfig/riscv-riscv.pc"; then
cd riscv-isa-sim
@ -277,8 +285,8 @@ if git_check "riscv-isa-sim" "https://github.com/riscv-software-src/riscv-isa-si
mkdir -p build
cd build
../configure --prefix="$RISCV"
make -j "${NUM_THREADS}" 2>&1 | logger spike; [ "${PIPESTATUS[0]}" == 0 ]
make install 2>&1 | logger spike; [ "${PIPESTATUS[0]}" == 0 ]
make -j "${NUM_THREADS}" 2>&1 | logger $STATUS; [ "${PIPESTATUS[0]}" == 0 ]
make install 2>&1 | logger $STATUS; [ "${PIPESTATUS[0]}" == 0 ]
if [ "$clean" ]; then
cd "$RISCV"
rm -rf riscv-isa-sim
@ -294,7 +302,7 @@ fi
# It is used for linting and simulation of Wally.
# Verilator needs to be built from source to get the latest version (Wally needs 5.021 or later).
section_header "Installing/Updating Verilator"
STATUS="Verilator"
STATUS="verilator"
cd "$RISCV"
if git_check "verilator" "https://github.com/verilator/verilator" "$RISCV/share/pkgconfig/verilator.pc"; then
unset VERILATOR_ROOT
@ -302,8 +310,8 @@ if git_check "verilator" "https://github.com/verilator/verilator" "$RISCV/share/
git reset --hard && git clean -f && git checkout master && git pull
autoconf
./configure --prefix="$RISCV"
make -j "${NUM_THREADS}" 2>&1 | logger verilator; [ "${PIPESTATUS[0]}" == 0 ]
make install 2>&1 | logger verilator; [ "${PIPESTATUS[0]}" == 0 ]
make -j "${NUM_THREADS}" 2>&1 | logger $STATUS; [ "${PIPESTATUS[0]}" == 0 ]
make install 2>&1 | logger $STATUS; [ "${PIPESTATUS[0]}" == 0 ]
if [ "$clean" ]; then
cd "$RISCV"
rm -rf verilator
@ -332,12 +340,12 @@ fi
# RISC-V Sail Model (https://github.com/riscv/sail-riscv)
# The RISC-V Sail Model is the golden reference model for RISC-V. It is written in Sail (described above)
section_header "Installing/Updating RISC-V Sail Model"
STATUS="RISC-V Sail Model"
STATUS="riscv-sail-model"
if git_check "sail-riscv" "https://github.com/riscv/sail-riscv.git" "$RISCV/bin/riscv_sim_RV32"; then
cd sail-riscv
git reset --hard && git clean -f && git checkout master && git pull
ARCH=RV64 make -j "${NUM_THREADS}" c_emulator/riscv_sim_RV64 2>&1 | logger sailModel; [ "${PIPESTATUS[0]}" == 0 ]
ARCH=RV32 make -j "${NUM_THREADS}" c_emulator/riscv_sim_RV32 2>&1 | logger sailModel; [ "${PIPESTATUS[0]}" == 0 ]
ARCH=RV64 make -j "${NUM_THREADS}" c_emulator/riscv_sim_RV64 2>&1 | logger $STATUS; [ "${PIPESTATUS[0]}" == 0 ]
ARCH=RV32 make -j "${NUM_THREADS}" c_emulator/riscv_sim_RV32 2>&1 | logger $STATUS; [ "${PIPESTATUS[0]}" == 0 ]
cp -f c_emulator/riscv_sim_RV64 "$RISCV"/bin/riscv_sim_RV64
cp -f c_emulator/riscv_sim_RV32 "$RISCV"/bin/riscv_sim_RV32
if [ "$clean" ]; then
@ -369,7 +377,7 @@ fi
# Buildroot is used to boot a minimal versio of Linux on Wally.
# Testvectors are generated using QEMU.
section_header "Installing Buildroot and Creating Linux testvectors"
STATUS="Buildroot"
STATUS="buildroot"
if [ -z "$LD_LIBRARY_PATH" ]; then
export LD_LIBRARY_PATH=$RISCV/lib:$RISCV/lib64:$RISCV/riscv64-unknown-elf/lib:$RISCV/lib/x86_64-linux-gnu/
else
@ -377,11 +385,11 @@ else
fi
cd "$dir"/../linux
if [ ! -e "$RISCV"/buildroot ]; then
make 2>&1 | logger buildroot; [ "${PIPESTATUS[0]}" == 0 ]
make 2>&1 | logger $STATUS; [ "${PIPESTATUS[0]}" == 0 ]
echo -e "${SUCCESS_COLOR}Buildroot successfully installed and Linux testvectors created!${ENDC}"
elif [ ! -e "$RISCV"/linux-testvectors ]; then
echo -e "${OK_COLOR}Buildroot already exists, but Linux testvectors are missing. Generating them now.${ENDC}"
make dumptvs 2>&1 | logger buildroot; [ "${PIPESTATUS[0]}" == 0 ]
make dumptvs 2>&1 | logger $STATUS; [ "${PIPESTATUS[0]}" == 0 ]
echo -e "${SUCCESS_COLOR}Linux testvectors successfully generated!${ENDC}"
else
echo -e "${OK_COLOR}Buildroot and Linux testvectors already exist.${ENDC}"

5
config/rv64gc/coverage.svh
View file

@ -8,5 +8,10 @@
`include "RV64I_coverage.svh"
`include "RV64M_coverage.svh"
`include "RV64F_coverage.svh"
// `include "RV64VM_coverage.svh"
// `include "RV64VM_PMP_coverage.svh"
// `include "RV64CBO_VM_coverage.svh"
// `include "RV64CBO_PMP_coverage.svh"
// `include "RV64Zicbom_coverage.svh"
`include "RV64Zicond_coverage.svh"
`include "RV64Zca_coverage.svh"

15
linux/Makefile
View file

@ -17,12 +17,6 @@ endif
WALLYBOARDSRC := $(WALLYLINUX)/buildroot-config-src/wally
WALLYBOARD := $(BUILDROOT)/board/wally
# Buildroot Package Stuff
PACKAGE_SOURCE := ${WALLYLINUX}/buildroot-packages/package-source
FPGA_AXI_SDC := ${WALLYLINUX}/buildroot-packages/fpga-axi-sdc
DRIVER := ${PACKAGE_SOURCE}/fpga-axi-sdc.c
PATCHFILE := $(BRPACKAGES)/package-2023.05.1.patch
# Device tree files
DTS ?= $(shell find devicetree -type f -regex ".*\.dts" | sort)
DTB := $(DTS:%.dts=%.dtb)
@ -114,15 +108,6 @@ $(WALLYBOARD): $(BUILDROOT)
cp $(BR2023)/main.config $(WALLYBOARD)/main.config
cp $(BR2023)/linux.config $(WALLYBOARD)/linux.config
# Buildroot Package ---------------------------------------------------
$(BUILDROOT)/package/fpga-axi-sdc: $(BUILDROOT) $(PATCHFILE) $(BRPACKAGES)/fpga-axi-sdc
cp -r $(BRPACKAGES)/fpga-axi-sdc $(BUILDROOT)/package
sed -i 's|FPGA_AXI_SDC_SITE =|FPGA_AXI_SDC_SITE = $(PACKAGE_SOURCE)|1' $(BUILDROOT)/package/fpga-axi-sdc/fpga-axi-sdc.mk
cd $(BUILDROOT); if git apply --check $(PATCHFILE) > /dev/null ; then git apply $(PATCHFILE); fi
$(PATCHFILE):
cd $(BUILDROOT); git apply $(PATCHFILE)
$(BUILDROOT):
git clone https://github.com/buildroot/buildroot.git $@
cd $@; git checkout 2023.05.x

3
linux/buildroot-config-src/buildroot-2023.05.1/main.config
View file

@ -1,6 +1,6 @@
#
# Automatically generated file; DO NOT EDIT.
# Buildroot 2023.05.3-dirty Configuration
# Buildroot 2023.05.3 Configuration
#
BR2_HAVE_DOT_CONFIG=y
BR2_HOST_GCC_AT_LEAST_4_9=y
@ -949,7 +949,6 @@ BR2_PACKAGE_SDL_FBCON=y
BR2_PACKAGE_FLASHROM_ARCH_SUPPORTS=y
# BR2_PACKAGE_FLASHROM is not set
# BR2_PACKAGE_FMTOOLS is not set
BR2_PACKAGE_FPGA_AXI_SDC=y
# BR2_PACKAGE_FREEIPMI is not set
# BR2_PACKAGE_FXLOAD is not set
# BR2_PACKAGE_GPM is not set

6
linux/buildroot-packages/fpga-axi-sdc/Config.in
View file

@ -1,6 +0,0 @@
config BR2_PACKAGE_FPGA_AXI_SDC
bool "FPGA AXI SDC"
help
The Vivado-RISC-V SDC Drivers.
https://www.github.com/eugene-tarassov/vivado-risc-v

10
linux/buildroot-packages/fpga-axi-sdc/fpga-axi-sdc.mk
View file

@ -1,10 +0,0 @@
FPGA_AXI_SDC_MODULE_VERSION = 1.0
# TODO This variable needs to change based on where the package
# contents are stored on each individual computer. Might parameterize
# this somehow.
FPGA_AXI_SDC_SITE =
FPGA_AXI_SDC_SITE_METHOD = local
FPGA_AXI_SDC_LICENSE = GPLv2
$(eval $(kernel-module))
$(eval $(generic-package))

1423
linux/buildroot-packages/linux.config
View file

File diff suppressed because it is too large Load diff

12
linux/buildroot-packages/package-2023.05.1.patch
View file

@ -1,12 +0,0 @@
diff --git a/package/Config.in b/package/Config.in
index ad438667d2..810bf0897e 100644
--- a/package/Config.in
+++ b/package/Config.in
@@ -503,6 +503,7 @@ endmenu
source "package/fconfig/Config.in"
source "package/flashrom/Config.in"
source "package/fmtools/Config.in"
+ source "package/fpga-axi-sdc/Config.in"
source "package/freeipmi/Config.in"
source "package/freescale-imx/Config.in"
source "package/fxload/Config.in"

9
linux/buildroot-packages/package-source/Makefile
View file

@ -1,9 +0,0 @@
.PHONY: all clean
obj-m += fpga-axi-sdc.o
all:
$(MAKE) -C '$(LINUX-DIR)' M='$(PWD)' modules
$(MAKE) -C '$(LINUX-DIR)' M='$(PWD)' modules_install
clean:
$(MAKE) -C '$(LINUX-DIR)' M='$(PWD)' clean

496
linux/buildroot-packages/package-source/fpga-axi-sdc.c
View file

@ -1,496 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/err.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/iopoll.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/consumer.h>
#include <linux/regulator/consumer.h>
#include <linux/reset.h>
#include <linux/mmc/card.h>
#include <linux/mmc/host.h>
#include <linux/mmc/mmc.h>
#include <linux/mmc/slot-gpio.h>
#include <linux/ktime.h>
/*
* AXI SD Card driver.
*
* AXI SD Card is open source Verilog implementation of high speed SD card controller.
* It is mainly used in FPGA designs.
*/
#ifdef CONFIG_DEBUG_INFO
#pragma GCC optimize("O0")
#endif
// Capability bits
#define SDC_CAPABILITY_SD_4BIT 0x0001
#define SDC_CAPABILITY_SD_RESET 0x0002
#define SDC_CAPABILITY_ADDR 0xff00
// Control bits
#define SDC_CONTROL_SD_4BIT 0x0001
#define SDC_CONTROL_SD_RESET 0x0002
// Card detect bits
#define SDC_CARD_INSERT_INT_EN 0x0001
#define SDC_CARD_INSERT_INT_REQ 0x0002
#define SDC_CARD_REMOVE_INT_EN 0x0004
#define SDC_CARD_REMOVE_INT_REQ 0x0008
// Command status bits
#define SDC_CMD_INT_STATUS_CC 0x0001 // Command complete
#define SDC_CMD_INT_STATUS_EI 0x0002 // Any error
#define SDC_CMD_INT_STATUS_CTE 0x0004 // Timeout
#define SDC_CMD_INT_STATUS_CCRC 0x0008 // CRC error
#define SDC_CMD_INT_STATUS_CIE 0x0010 // Command code check error
// Data status bits
#define SDC_DAT_INT_STATUS_TRS 0x0001 // Transfer complete
#define SDC_DAT_INT_STATUS_ERR 0x0002 // Any error
#define SDC_DAT_INT_STATUS_CTE 0x0004 // Timeout
#define SDC_DAT_INT_STATUS_CRC 0x0008 // CRC error
#define SDC_DAT_INT_STATUS_CFE 0x0010 // Data FIFO underrun or overrun
#define CMD_TIMEOUT_MS 1000
#define BUSY_TIMEOUT_MS 500
struct sdc_regs {
volatile uint32_t argument;
volatile uint32_t command;
volatile uint32_t response1;
volatile uint32_t response2;
volatile uint32_t response3;
volatile uint32_t response4;
volatile uint32_t data_timeout;
volatile uint32_t control;
volatile uint32_t cmd_timeout;
volatile uint32_t clock_divider;
volatile uint32_t software_reset;
volatile uint32_t power_control;
volatile uint32_t capability;
volatile uint32_t cmd_int_status;
volatile uint32_t cmd_int_enable;
volatile uint32_t dat_int_status;
volatile uint32_t dat_int_enable;
volatile uint32_t block_size;
volatile uint32_t block_count;
volatile uint32_t card_detect;
volatile uint32_t res_50;
volatile uint32_t res_54;
volatile uint32_t res_58;
volatile uint32_t res_5c;
volatile uint64_t dma_addres;
};
struct sdc_host {
struct platform_device * pdev;
struct sdc_regs __iomem * regs;
uint32_t clk_freq;
spinlock_t lock;
struct mmc_request * mrq;
struct mmc_data * data;
unsigned dma_addr_bits;
unsigned dma_count;
dma_addr_t dma_addr;
unsigned dma_size;
int irq;
};
static const struct of_device_id axi_sdc_of_match_table[] = {
{ .compatible = "riscv,axi-sd-card-1.0" },
{},
};
MODULE_DEVICE_TABLE(of, axi_sdc_of_match_table);
/* Set clock prescalar value based on the required clock in HZ */
static void sdc_set_clock(struct sdc_host * host, uint clock) {
unsigned clk_div;
/* Min clock frequency should be 400KHz */
if (clock < 400000) clock = 400000;
clk_div = host->clk_freq / (2 * clock);
if (clk_div > 0x100) clk_div = 0x100;
if (clk_div < 1) clk_div = 1;
if (host->regs->clock_divider != clk_div - 1) {
host->regs->clock_divider = clk_div - 1;
udelay(10000);
}
}
static void sdc_cmd_finish(struct sdc_host * host, struct mmc_command * cmd) {
while (1) {
unsigned status = host->regs->cmd_int_status;
if (status) {
// clear interrupts
host->regs->cmd_int_status = 0;
while (host->regs->software_reset != 0) {}
if (status == SDC_CMD_INT_STATUS_CC) {
// get response
cmd->resp[0] = host->regs->response1;
if (cmd->flags & MMC_RSP_136) {
cmd->resp[1] = host->regs->response2;
cmd->resp[2] = host->regs->response3;
cmd->resp[3] = host->regs->response4;
}
break;
}
cmd->error = (status & SDC_CMD_INT_STATUS_CTE) ? -ETIME : -EIO;
break;
}
}
}
static int sdc_setup_data_xfer(struct sdc_host * host, struct mmc_host * mmc, struct mmc_data * data) {
uint64_t timeout = 0;
data->bytes_xfered = 0;
if (host->dma_addr & 3) return -EINVAL;
if (data->blksz & 3) return -EINVAL;
if (data->blksz < 4) return -EINVAL;
if (data->blksz > 0x1000) return -EINVAL;
if (data->blocks > 0x10000) return -EINVAL;
if (host->dma_addr + data->blksz * data->blocks > ((uint64_t)1 << host->dma_addr_bits)) return -EINVAL;
if (data->sg->length < data->blksz * data->blocks) return -EINVAL;
// SD card data transfer time
timeout += data->blocks * data->blksz * 8 / (1 << mmc->ios.bus_width);
// SD card "busy" time
timeout += (uint64_t)mmc->ios.clock * BUSY_TIMEOUT_MS / 1000 * data->blocks;
host->regs->dma_addres = (uint64_t)host->dma_addr;
host->regs->block_size = data->blksz - 1;
host->regs->block_count = data->blocks - 1;
host->regs->data_timeout = (uint32_t)timeout;
if (host->regs->data_timeout != timeout) host->regs->data_timeout = 0;
return 0;
}
static int sdc_send_cmd(struct sdc_host * host, struct mmc_host * mmc, struct mmc_command * cmd, struct mmc_data * data) {
int command = cmd->opcode << 8;
uint64_t timeout = 0;
int xfer = 0;
if (cmd->flags & MMC_RSP_PRESENT) {
if (cmd->flags & MMC_RSP_136)
command |= 2;
else {
command |= 1;
}
}
if (cmd->flags & MMC_RSP_BUSY) command |= 1 << 2;
if (cmd->flags & MMC_RSP_CRC) command |= 1 << 3;
if (cmd->flags & MMC_RSP_OPCODE) command |= 1 << 4;
if (data && (data->flags & (MMC_DATA_READ | MMC_DATA_WRITE)) && data->blocks) {
host->dma_count = dma_map_sg(&host->pdev->dev, data->sg, data->sg_len, mmc_get_dma_dir(data));
if (host->dma_count != 1) {
dma_unmap_sg(&host->pdev->dev, data->sg, data->sg_len, mmc_get_dma_dir(data));
return data->error = -EIO;
}
host->dma_addr = sg_dma_address(data->sg);
host->dma_size = sg_dma_len(data->sg);
if (data->flags & MMC_DATA_READ) command |= 1 << 5;
if (data->flags & MMC_DATA_WRITE) command |= 1 << 6;
data->error = sdc_setup_data_xfer(host, mmc, data);
if (data->error < 0) {
dma_unmap_sg(&host->pdev->dev, data->sg, data->sg_len, mmc_get_dma_dir(data));
return data->error;
}
xfer = 1;
}
timeout = (uint64_t)mmc->ios.clock * CMD_TIMEOUT_MS / 1000;
host->regs->command = command;
host->regs->cmd_timeout = (uint32_t)timeout;
if (host->regs->cmd_timeout != timeout) host->regs->cmd_timeout = 0;
host->regs->argument = cmd->arg;
sdc_cmd_finish(host, cmd);
if (cmd->error < 0) {
if (xfer) dma_unmap_sg(&host->pdev->dev, data->sg, data->sg_len, mmc_get_dma_dir(data));
return cmd->error;
}
if (xfer) host->data = data;
return 0;
}
static void sdc_request(struct mmc_host * mmc, struct mmc_request * mrq) {
struct sdc_host * host = mmc_priv(mmc);
/* Clear the error statuses in case this is a retry */
if (mrq->sbc) mrq->sbc->error = 0;
if (mrq->cmd) mrq->cmd->error = 0;
if (mrq->data) mrq->data->error = 0;
if (mrq->stop) mrq->stop->error = 0;
spin_lock_irq(&host->lock);
host->data = NULL;
host->mrq = mrq;
if (!mrq->sbc || sdc_send_cmd(host, mmc, mrq->sbc, NULL) == 0) {
sdc_send_cmd(host, mmc, mrq->cmd, mrq->data);
}
if (host->data == NULL) {
mmc_request_done(mmc, mrq);
host->mrq = NULL;
}
else {
host->regs->dat_int_enable = SDC_DAT_INT_STATUS_TRS | SDC_DAT_INT_STATUS_ERR;
}
spin_unlock_irq(&host->lock);
}
static void sdc_set_ios(struct mmc_host * mmc, struct mmc_ios * ios) {
struct sdc_host * host = mmc_priv(mmc);
spin_lock_irq(&host->lock);
sdc_set_clock(host, ios->clock);
host->regs->control = ios->bus_width == MMC_BUS_WIDTH_4 ? SDC_CONTROL_SD_4BIT : 0;
spin_unlock_irq(&host->lock);
}
static void sdc_reset(struct mmc_host * mmc) {
struct sdc_host * host = mmc_priv(mmc);
uint32_t card_detect = 0;
spin_lock_init(&host->lock);
spin_lock_irq(&host->lock);
sdc_set_clock(host, 400000);
// software reset
host->regs->software_reset = 1;
while ((host->regs->software_reset & 1) == 0) {}
// clear software reset
host->regs->software_reset = 0;
while (host->regs->software_reset != 0) {}
udelay(10000);
// set bus width 1 bit
host->regs->control = 0;
// disable cmd/data interrupts
host->regs->cmd_int_enable = 0;
host->regs->dat_int_enable = 0;
// clear cmd/data interrupts
host->regs->cmd_int_status = 0;
host->regs->dat_int_status = 0;
// enable card detect interrupt
card_detect = host->regs->card_detect;
if (card_detect & SDC_CARD_INSERT_INT_REQ) {
host->regs->card_detect = SDC_CARD_REMOVE_INT_EN;
}
else if (card_detect & SDC_CARD_REMOVE_INT_REQ) {
host->regs->card_detect = SDC_CARD_INSERT_INT_EN;
}
while (host->regs->software_reset != 0) {}
spin_unlock_irq(&host->lock);
}
static void sdc_card_reset(struct mmc_host * mmc) {
struct sdc_host * host = mmc_priv(mmc);
uint32_t control = 0;
spin_lock_irq(&host->lock);
control = host->regs->control;
host->regs->control = control | SDC_CONTROL_SD_RESET;
udelay(10);
host->regs->control = control & ~(uint32_t)SDC_CONTROL_SD_RESET;
udelay(10);
spin_unlock_irq(&host->lock);
}
static int sdc_get_cd(struct mmc_host * mmc) {
struct sdc_host * host = mmc_priv(mmc);
uint32_t card_detect = host->regs->card_detect;
if (card_detect == 0) return 1; /* Card detect not supported */
return (card_detect & SDC_CARD_INSERT_INT_REQ) != 0;
}
static irqreturn_t sdc_isr(int irq, void * dev_id) {
struct mmc_host * mmc = (struct mmc_host *)dev_id;
struct sdc_host * host = mmc_priv(mmc);
uint32_t card_detect = 0;
uint32_t data_status = 0;
unsigned long flags;
spin_lock_irqsave(&host->lock, flags);
card_detect = host->regs->card_detect;
if (card_detect & SDC_CARD_INSERT_INT_REQ) {
if (card_detect & SDC_CARD_INSERT_INT_EN) {
host->regs->card_detect = SDC_CARD_REMOVE_INT_EN;
mmc_detect_change(mmc, 0);
}
}
else if (card_detect & SDC_CARD_REMOVE_INT_REQ) {
if (card_detect & SDC_CARD_REMOVE_INT_EN) {
host->regs->card_detect = SDC_CARD_INSERT_INT_EN;
mmc_detect_change(mmc, 0);
}
}
if ((data_status = host->regs->dat_int_status) != 0) {
host->regs->dat_int_enable = 0;
host->regs->dat_int_status = 0;
while (host->regs->software_reset != 0) {}
if (host->data) {
struct mmc_request * mrq = host->mrq;
struct mmc_data * data = host->data;
if (data_status == SDC_DAT_INT_STATUS_TRS) {
data->bytes_xfered = data->blksz * data->blocks;
}
else {
data->error = -EIO;
if (data_status & SDC_DAT_INT_STATUS_CTE) data->error = -ETIME;
}
if (mrq->stop) sdc_send_cmd(host, mmc, mrq->stop, NULL);
mmc_request_done(mmc, mrq);
dma_unmap_sg(&host->pdev->dev, data->sg, data->sg_len, mmc_get_dma_dir(data));
host->data = NULL;
host->mrq = NULL;
}
}
spin_unlock_irqrestore(&host->lock, flags);
return IRQ_HANDLED;
}
/*---------------------------------------------------------------------*/
static const struct mmc_host_ops axi_sdc_ops = {
.request = sdc_request,
.set_ios = sdc_set_ios,
.get_cd = sdc_get_cd,
.card_hw_reset = sdc_card_reset,
};
static int axi_sdc_probe(struct platform_device * pdev) {
struct device * dev = &pdev->dev;
struct resource * iomem;
struct sdc_host * host;
struct mmc_host * mmc;
void __iomem * ioaddr;
uint32_t capability;
int irq;
int ret;
iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
ioaddr = devm_ioremap_resource(dev, iomem);
if (IS_ERR(ioaddr)) return PTR_ERR(ioaddr);
irq = platform_get_irq(pdev, 0);
if (irq <= 0) return -ENXIO;
mmc = mmc_alloc_host(sizeof(*host), dev);
if (!mmc) return -ENOMEM;
mmc->ops = &axi_sdc_ops;
host = mmc_priv(mmc);
host->pdev = pdev;
host->regs = (struct sdc_regs __iomem *)ioaddr;
host->irq = irq;
ret = of_property_read_u32(dev->of_node, "clock", &host->clk_freq);
if (ret) host->clk_freq = 100000000;
ret = mmc_of_parse(mmc);
if (ret) {
mmc_free_host(mmc);
return ret;
}
if (mmc->f_min == 0) mmc->f_min = host->clk_freq / 0x200; /* maximum clock division 256 * 2 */
if (mmc->f_max == 0) mmc->f_max = host->clk_freq / 2; /* minimum clock division 2 */
if ((mmc->caps2 & MMC_CAP2_NO_SDIO) == 0) {
/* TODO: deprecated 10/19/2022, set in DTS */
mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
mmc->caps2 |= MMC_CAP2_NO_SDIO;
}
mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
mmc->max_segs = 1;
mmc->max_req_size = 0x2000000;
mmc->max_seg_size = 0x2000000;
mmc->max_blk_size = 0x1000;
mmc->max_blk_count = 0x10000;
ret = request_irq(host->irq, sdc_isr, IRQF_TRIGGER_HIGH, "fpga-axi-sdc", mmc);
if (ret) {
mmc_free_host(mmc);
return ret;
}
host->dma_addr_bits = 32;
capability = host->regs->capability;
if (capability & SDC_CAPABILITY_ADDR) {
host->dma_addr_bits = (capability & SDC_CAPABILITY_ADDR) >> __builtin_ctz(SDC_CAPABILITY_ADDR);
ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(host->dma_addr_bits));
if (ret) {
printk(KERN_ERR "AXI-SDC: Can't set DMA mask\n");
mmc_free_host(mmc);
return ret;
}
}
sdc_reset(mmc);
ret = mmc_add_host(mmc);
if (ret) {
printk(KERN_ERR "AXI-SDC: Can't register device\n");
mmc_free_host(mmc);
return ret;
}
//spin_lock_init(&host->lock);
platform_set_drvdata(pdev, host);
return 0;
}
static int axi_sdc_remove(struct platform_device * pdev) {
struct sdc_host * host = platform_get_drvdata(pdev);
struct mmc_host * mmc = mmc_from_priv(host);
free_irq(host->irq, mmc);
mmc_remove_host(mmc);
mmc_free_host(mmc);
return 0;
}
static struct platform_driver axi_sdc_driver = {
.driver = {
.name = "riscv-axi-sdc",
.of_match_table = axi_sdc_of_match_table,
},
.probe = axi_sdc_probe,
.remove = axi_sdc_remove,
};
module_platform_driver(axi_sdc_driver);
MODULE_DESCRIPTION("AXI SD Card driver");
MODULE_AUTHOR("Eugene Tarassov");
MODULE_LICENSE("GPL v2");

12
linux/buildroot-packages/package.patch
View file

@ -1,12 +0,0 @@
diff --git a/package/Config.in b/package/Config.in
index 82b28d2835..29e8bb66ac 100644
--- a/package/Config.in
+++ b/package/Config.in
@@ -469,6 +469,7 @@ endmenu
source "package/fconfig/Config.in"
source "package/flashrom/Config.in"
source "package/fmtools/Config.in"
+ source "package/fpga-axi-sdc/Config.in"
source "package/freescale-imx/Config.in"
source "package/fxload/Config.in"
source "package/gcnano-binaries/Config.in"

3808
linux/buildroot-packages/wally.config
View file

File diff suppressed because it is too large Load diff

4
sim/questa/wally.do
View file

@ -192,9 +192,9 @@ if {$DEBUG > 0} {
# suppress spurious warnngs about
# "Extra checking for conflicts with always_comb done at vopt time"
# because vsim will run vopt
set INC_DIRS "+incdir+${CONFIG}/${CFG} +incdir+${CONFIG}/deriv/${CFG} +incdir+${CONFIG}/shared +incdir+${FCRVVI} +incdir+${FCRVVI}/rv32 +incdir+${FCRVVI}/rv64 +incdir+${FCRVVI}/common +incdir+${FCRVVI}"
set INC_DIRS "+incdir+${CONFIG}/${CFG} +incdir+${CONFIG}/deriv/${CFG} +incdir+${CONFIG}/shared +incdir+${FCRVVI} +incdir+${FCRVVI}/rv32 +incdir+${FCRVVI}/rv64 +incdir+${FCRVVI}/rv64_priv +incdir+${FCRVVI}/common +incdir+${FCRVVI}"
set SOURCES "${SRC}/cvw.sv ${TB}/${TESTBENCH}.sv ${TB}/common/*.sv ${SRC}/*/*.sv ${SRC}/*/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*/*/*.sv"
vlog -lint +nowarnRDGN -work ${WKDIR} {*}${INC_DIRS} {*}${FCvlog} {*}${FCdefineCOVER_EXTS} {*}${lockstepvlog} ${FCdefineRVVI_COVERAGE} {*}${SOURCES} -suppress 2244 -suppress 2282 -suppress 2583 -suppress 7063,2596,13286
vlog -permissive -lint -work ${WKDIR} {*}${INC_DIRS} {*}${FCvlog} {*}${FCdefineCOVER_EXTS} {*}${lockstepvlog} ${FCdefineRVVI_COVERAGE} {*}${SOURCES} -suppress 2282,2583,7053,7063,2596,13286
# start and run simulation
# remove +acc flag for faster sim during regressions if there is no need to access internal signals

40
testbench/common/wallyTracer.sv
View file

@ -64,6 +64,16 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
logic wfiM;
logic InterruptM, InterruptW;
//For VM Verification
logic [(P.XLEN-1):0] VAdrIM,VAdrDM,VAdrIW,VAdrDW;
logic [(P.XLEN-1):0] PTE_iM,PTE_dM,PTE_iW,PTE_dW;
logic [(P.PA_BITS-1):0] PAIM,PADM,PAIW,PADW;
logic [(P.PPN_BITS-1):0] PPN_iM,PPN_dM,PPN_iW,PPN_dW;
logic ReadAccessM,WriteAccessM,ReadAccessW,WriteAccessW;
logic ExecuteAccessF,ExecuteAccessD,ExecuteAccessE,ExecuteAccessM,ExecuteAccessW;
assign clk = testbench.dut.clk;
// assign InstrValidF = testbench.dut.core.ieu.InstrValidF; // not needed yet
assign InstrValidD = testbench.dut.core.ieu.c.InstrValidD;
@ -93,6 +103,20 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
assign wfiM = testbench.dut.core.priv.priv.wfiM;
assign InterruptM = testbench.dut.core.priv.priv.InterruptM;
//FOr VM Verification
assign VAdrIM = testbench.dut.core.ifu.immu.immu.tlb.tlb.VAdr;
assign VAdrDM = testbench.dut.core.lsu.dmmu.dmmu.tlb.tlb.VAdr;
assign PAIM = testbench.dut.core.ifu.immu.immu.PhysicalAddress;
assign PADM = testbench.dut.core.lsu.dmmu.dmmu.PhysicalAddress;
assign ReadAccessM = testbench.dut.core.lsu.dmmu.dmmu.ReadAccessM;
assign WriteAccessM = testbench.dut.core.lsu.dmmu.dmmu.WriteAccessM;
assign ExecuteAccessF = testbench.dut.core.ifu.immu.immu.ExecuteAccessF;
assign PTE_iM = testbench.dut.core.ifu.immu.immu.PTE;
assign PTE_dM = testbench.dut.core.lsu.dmmu.dmmu.PTE;
assign PPN_iM = testbench.dut.core.ifu.immu.immu.tlb.tlb.PPN;
assign PPN_dM = testbench.dut.core.lsu.dmmu.dmmu.tlb.tlb.PPN;
logic valid;
int csrid;
@ -276,6 +300,22 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
flopenrc #(12) CSRAdrWReg (clk, reset, FlushW, ~StallW, CSRAdrM, CSRAdrW);
flopenrc #(1) CSRWriteWReg (clk, reset, FlushW, ~StallW, CSRWriteM, CSRWriteW);
//for VM Verification
flopenrc #(P.XLEN) VAdrIWReg (clk, reset, FlushW, ~StallW, VAdrIM, VAdrIW);
flopenrc #(P.XLEN) VAdrDWReg (clk, reset, FlushW, ~StallW, VAdrDM, VAdrDW);
flopenrc #(P.PA_BITS) PAIWReg (clk, reset, FlushW, ~StallW, PAIM, PAIW);
flopenrc #(P.PA_BITS) PADWReg (clk, reset, FlushW, ~StallW, PADM, PADW);
flopenrc #(P.XLEN) PTE_iWReg (clk, reset, FlushW, ~StallW, PTE_iM, PTE_iW);
flopenrc #(P.XLEN) PTE_dWReg (clk, reset, FlushW, ~StallW, PTE_dM, PTE_dW);
flopenrc #(P.PPN_BITS) PPN_iWReg (clk, reset, FlushW, ~StallW, PPN_iM, PPN_iW);
flopenrc #(P.PPN_BITS) PPN_dWReg (clk, reset, FlushW, ~StallW, PPN_dM, PPN_dW);
flopenrc #(1) ReadAccessWReg (clk, reset, FlushW, ~StallW, ReadAccessM, ReadAccessW);
flopenrc #(1) WriteAccessWReg (clk, reset, FlushW, ~StallW, WriteAccessM, WriteAccessW);
flopenrc #(1) ExecuteAccessDReg (clk, reset, FlushE, ~StallE, ExecuteAccessF, ExecuteAccessD);
flopenrc #(1) ExecuteAccessEReg (clk, reset, FlushE, ~StallE, ExecuteAccessD, ExecuteAccessE);
flopenrc #(1) ExecuteAccessMReg (clk, reset, FlushM, ~StallM, ExecuteAccessE, ExecuteAccessM);
flopenrc #(1) ExecuteAccessWReg (clk, reset, FlushW, ~StallW, ExecuteAccessM, ExecuteAccessW);
// Initially connecting the writeback stage signals, but may need to use M stage
// and gate on ~FlushW.