mirror of
https://github.com/openhwgroup/cvw.git
synced 2025-04-22 12:57:23 -04:00
Merge pull request #472 from ross144/main
Merge Zicclsm into main branch and removes the FPGA config. FPGA makefile now automatically creates the config when building
This commit is contained in:
David Harris
GitHub
commit
a77bea9954
44 changed files with 2144 additions and 752 deletions
3
.gitignore
vendored
3
.gitignore
vendored
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@ -172,3 +172,6 @@ tests/fp/combined_IF_vectors/IF_vectors/*.tv
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/sim/obj_dir/Vtestbench_tlbram__Pz1_T20__DepSet_hab70f5b0__0.cpp
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/sim/obj_dir/Vtestbench_tlbram__Pz1_T20__DepSet_hab70f5b0__0__Slow.cpp
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/sim/obj_dir/Vtestbench_tlbram__Pz1_T20__Slow.cpp
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sim/bp-results/*.log
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sim/branch*.log
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/tests/custom/fpga-test-sdc/bin/fpga-test-sdc
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@ -28,7 +28,6 @@
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// include shared configuration
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`include "BranchPredictorType.vh"
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localparam FPGA = 1;
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// RV32 or RV64: XLEN = 32 or 64
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localparam XLEN = 32'd64;
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@ -46,6 +45,7 @@ localparam SSTC_SUPPORTED = 1;
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localparam ZICBOM_SUPPORTED = 1;
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localparam ZICBOZ_SUPPORTED = 1;
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localparam ZICBOP_SUPPORTED = 1;
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localparam ZICCLSM_SUPPORTED = 0;
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localparam SVPBMT_SUPPORTED = 1;
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localparam SVNAPOT_SUPPORTED = 1;
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localparam SVINVAL_SUPPORTED = 1;
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@ -97,9 +97,11 @@ localparam logic [63:0] IROM_RANGE = 64'h00001FFF;
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localparam BOOTROM_SUPPORTED = 1'b1;
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localparam logic [63:0] BOOTROM_BASE = 64'h00001000 ;
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localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF;
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localparam BOOTROM_PRELOAD = 1'b1;
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localparam UNCORE_RAM_SUPPORTED = 1'b1;
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localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000;
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localparam logic [63:0] UNCORE_RAM_RANGE = 64'h07FFFFFF;
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localparam UNCORE_RAM_PRELOAD = 1'b1;
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localparam EXT_MEM_SUPPORTED = 1'b0;
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localparam logic [63:0] EXT_MEM_BASE = 64'h80000000;
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localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF;
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@ -1,189 +0,0 @@
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//////////////////////////////////////////
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// config.vh
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//
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// Written: David_Harris@hmc.edu 4 January 2021
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// Modified:
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//
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// Purpose: Specify which features are configured
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// Macros to determine which modes are supported based on MISA
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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// include shared configuration
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`include "BranchPredictorType.vh"
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localparam FPGA = 1;
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// RV32 or RV64: XLEN = 32 or 64
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localparam XLEN = 32'd64;
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// IEEE 754 compliance
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localparam IEEE754 = 0;
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// MISA RISC-V configuration per specification
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localparam MISA = (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0);
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localparam ZICSR_SUPPORTED = 1;
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localparam ZIFENCEI_SUPPORTED = 1;
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localparam COUNTERS = 12'd32;
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localparam ZICNTR_SUPPORTED = 1;
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localparam ZIHPM_SUPPORTED = 1;
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localparam ZFH_SUPPORTED = 0;
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localparam SSTC_SUPPORTED = 1;
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localparam ZICBOM_SUPPORTED = 1;
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localparam ZICBOZ_SUPPORTED = 1;
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localparam ZICBOP_SUPPORTED = 1;
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localparam SVPBMT_SUPPORTED = 1;
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localparam SVNAPOT_SUPPORTED = 1;
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localparam SVINVAL_SUPPORTED = 1;
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// LSU microarchitectural Features
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localparam BUS_SUPPORTED = 1;
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localparam DCACHE_SUPPORTED = 1;
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localparam ICACHE_SUPPORTED = 1;
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localparam VIRTMEM_SUPPORTED = 1;
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localparam VECTORED_INTERRUPTS_SUPPORTED = 1;
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localparam BIGENDIAN_SUPPORTED = 1;
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// TLB configuration. Entries should be a power of 2
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localparam ITLB_ENTRIES = 32'd32;
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localparam DTLB_ENTRIES = 32'd32;
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// Cache configuration. Sizes should be a power of two
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// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
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localparam DCACHE_NUMWAYS = 32'd4;
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localparam DCACHE_WAYSIZEINBYTES = 32'd4096;
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localparam DCACHE_LINELENINBITS = 32'd512;
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localparam ICACHE_NUMWAYS = 32'd4;
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localparam ICACHE_WAYSIZEINBYTES = 32'd4096;
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localparam ICACHE_LINELENINBITS = 32'd512;
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// Integer Divider Configuration
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// IDIV_BITSPERCYCLE must be 1, 2, or 4
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localparam IDIV_BITSPERCYCLE = 32'd4;
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localparam IDIV_ON_FPU = 1;
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// Legal number of PMP entries are 0, 16, or 64
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localparam PMP_ENTRIES = 32'd16;
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// Address space
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localparam logic [63:0] RESET_VECTOR = 64'h0000000000001000;
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// Bus Interface width
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localparam AHBW = 32'd64;
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// WFI Timeout Wait
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localparam WFI_TIMEOUT_BIT = 32'd16;
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// Peripheral Physical Addresses
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// Peripheral memory space extends from BASE to BASE+RANGE
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// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
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// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
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localparam DTIM_SUPPORTED = 1'b0;
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localparam logic [63:0] DTIM_BASE = 64'h80000000;
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localparam logic [63:0] DTIM_RANGE = 64'h00001FFF;
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localparam IROM_SUPPORTED = 1'b0;
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localparam logic [63:0] IROM_BASE = 64'h80000000;
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localparam logic [63:0] IROM_RANGE = 64'h00001FFF;
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localparam BOOTROM_SUPPORTED = 1'b1;
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localparam logic [63:0] BOOTROM_BASE = 64'h00001000;
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localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF;
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localparam UNCORE_RAM_SUPPORTED = 1'b1;
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localparam logic [63:0] UNCORE_RAM_BASE = 64'h00002000;
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localparam logic [63:0] UNCORE_RAM_RANGE = 64'h00000FFF;
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localparam EXT_MEM_SUPPORTED = 1'b1;
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localparam logic [63:0] EXT_MEM_BASE = 64'h80000000;
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localparam logic [63:0] EXT_MEM_RANGE = 64'h0FFFFFFF;
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localparam CLINT_SUPPORTED = 1'b1;
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localparam logic [63:0] CLINT_BASE = 64'h02000000;
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localparam logic [63:0] CLINT_RANGE = 64'h0000FFFF;
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localparam GPIO_SUPPORTED = 1'b1;
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localparam logic [63:0] GPIO_BASE = 64'h10060000;
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localparam logic [63:0] GPIO_RANGE = 64'h000000FF;
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localparam UART_SUPPORTED = 1'b1;
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localparam logic [63:0] UART_BASE = 64'h10000000;
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localparam logic [63:0] UART_RANGE = 64'h00000007;
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localparam PLIC_SUPPORTED = 1'b1;
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localparam logic [63:0] PLIC_BASE = 64'h0C000000;
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localparam logic [63:0] PLIC_RANGE = 64'h03FFFFFF;
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localparam SDC_SUPPORTED = 1'b1;
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localparam logic [63:0] SDC_BASE = 64'h00013000;
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localparam logic [63:0] SDC_RANGE = 64'h0000007F;
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localparam SPI_SUPPORTED = 1'b1;
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localparam logic [63:0] SPI_BASE = 64'h10040000;
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localparam logic [63:0] SPI_RANGE = 64'h00000FFF;
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// Test modes
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// Tie GPIO outputs back to inputs
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localparam GPIO_LOOPBACK_TEST = 0;
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localparam SPI_LOOPBACK_TEST = 0;
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// Hardware configuration
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localparam UART_PRESCALE = 32'd0;
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// Interrupt configuration
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localparam PLIC_NUM_SRC = 32'd53;
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// comment out the following if >=32 sources
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localparam PLIC_NUM_SRC_LT_32 = (PLIC_NUM_SRC < 32);
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localparam PLIC_GPIO_ID = 32'd3;
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localparam PLIC_UART_ID = 32'd10;
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localparam PLIC_SPI_ID = 32'd6;
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localparam PLIC_SDC_ID = 32'd20;
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localparam BPRED_SUPPORTED = 1;
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localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
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localparam BPRED_NUM_LHR = 32'd6;
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localparam BPRED_SIZE = 32'd12;
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localparam BTB_SIZE = 32'd10;
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localparam RAS_SIZE = 32'd16;
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localparam SVADU_SUPPORTED = 1;
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localparam ZMMUL_SUPPORTED = 0;
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// FPU division architecture
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localparam RADIX = 32'h4;
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localparam DIVCOPIES = 32'h4;
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// bit manipulation
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localparam ZBA_SUPPORTED = 1;
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localparam ZBB_SUPPORTED = 1;
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localparam ZBC_SUPPORTED = 1;
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localparam ZBS_SUPPORTED = 1;
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// New compressed instructions
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localparam ZCB_SUPPORTED = 1;
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localparam ZCA_SUPPORTED = 0;
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localparam ZCF_SUPPORTED = 0;
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localparam ZCD_SUPPORTED = 0;
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// Memory synthesis configuration
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localparam USE_SRAM = 0;
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`include "config-shared.vh"
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@ -27,8 +27,6 @@
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`include "BranchPredictorType.vh"
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localparam FPGA = 0;
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// RV32 or RV64: XLEN = 32 or 64
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localparam XLEN = 32'd32;
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@ -47,6 +45,7 @@ localparam SSTC_SUPPORTED = 0;
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localparam ZICBOM_SUPPORTED = 0;
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localparam ZICBOZ_SUPPORTED = 0;
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localparam ZICBOP_SUPPORTED = 0;
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localparam ZICCLSM_SUPPORTED = 0;
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localparam SVPBMT_SUPPORTED = 0;
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localparam SVNAPOT_SUPPORTED = 0;
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localparam SVINVAL_SUPPORTED = 0;
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@ -96,11 +95,13 @@ localparam IROM_SUPPORTED = 1'b0;
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localparam logic [63:0] IROM_BASE = 64'h80000000;
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localparam logic [63:0] IROM_RANGE = 64'h007FFFFF;
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localparam BOOTROM_SUPPORTED = 1'b1;
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localparam BOOTROM_PRELOAD = 1'b0;
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localparam logic [63:0] BOOTROM_BASE = 64'h00001000;
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localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF;
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localparam UNCORE_RAM_SUPPORTED = 1'b1;
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localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000;
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localparam logic [63:0] UNCORE_RAM_RANGE = 64'h07FFFFFF;
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localparam UNCORE_RAM_PRELOAD = 1'b0;
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localparam EXT_MEM_SUPPORTED = 1'b0;
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localparam logic [63:0] EXT_MEM_BASE = 64'h80000000;
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localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF;
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@ -29,8 +29,6 @@
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// `include "wally-shared.vh"
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`include "BranchPredictorType.vh"
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localparam FPGA = 0;
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// RV32 or RV64: XLEN = 32 or 64
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localparam XLEN = 32'd32;
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@ -48,6 +46,7 @@ localparam SSTC_SUPPORTED = 1;
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localparam ZICBOM_SUPPORTED = 1;
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localparam ZICBOZ_SUPPORTED = 1;
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localparam ZICBOP_SUPPORTED = 0;
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localparam ZICCLSM_SUPPORTED = 0;
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localparam SVPBMT_SUPPORTED = 0;
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localparam SVNAPOT_SUPPORTED = 0;
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localparam SVINVAL_SUPPORTED = 1;
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@ -99,9 +98,11 @@ localparam logic [63:0] IROM_RANGE = 64'h007FFFFF;
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localparam BOOTROM_SUPPORTED = 1'b1;
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localparam logic [63:0] BOOTROM_BASE = 64'h00001000;
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localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF;
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localparam BOOTROM_PRELOAD = 1'b0;
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localparam UNCORE_RAM_SUPPORTED = 1'b1;
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localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000;
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localparam logic [63:0] UNCORE_RAM_RANGE = 64'h07FFFFFF;
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localparam UNCORE_RAM_PRELOAD = 1'b0;
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localparam EXT_MEM_SUPPORTED = 1'b0;
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localparam logic [63:0] EXT_MEM_BASE = 64'h80000000;
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localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF;
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@ -27,8 +27,6 @@
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`include "BranchPredictorType.vh"
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localparam FPGA = 0;
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// RV32 or RV64: XLEN = 32 or 64
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localparam XLEN = 32'd32;
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@ -47,6 +45,7 @@ localparam SSTC_SUPPORTED = 0;
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localparam ZICBOM_SUPPORTED = 0;
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localparam ZICBOZ_SUPPORTED = 0;
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localparam ZICBOP_SUPPORTED = 0;
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localparam ZICCLSM_SUPPORTED = 0;
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localparam SVPBMT_SUPPORTED = 0;
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localparam SVNAPOT_SUPPORTED = 0;
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localparam SVINVAL_SUPPORTED = 0;
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@ -98,9 +97,11 @@ localparam logic [63:0] IROM_RANGE = 64'h007FFFFF;
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localparam BOOTROM_SUPPORTED = 1'b0;
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localparam logic [63:0] BOOTROM_BASE = 64'h00001000;
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localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF;
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localparam BOOTROM_PRELOAD = 1'b0;
|
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localparam UNCORE_RAM_SUPPORTED = 1'b0;
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localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000;
|
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localparam logic [63:0] UNCORE_RAM_RANGE = 64'h07FFFFFF;
|
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localparam UNCORE_RAM_PRELOAD = 1'b0;
|
||||
localparam EXT_MEM_SUPPORTED = 1'b0;
|
||||
localparam logic [63:0] EXT_MEM_BASE = 64'h80000000;
|
||||
localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF;
|
||||
|
|
|
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|
|
@ -27,8 +27,6 @@
|
|||
|
||||
`include "BranchPredictorType.vh"
|
||||
|
||||
localparam FPGA = 0;
|
||||
|
||||
// RV32 or RV64: XLEN = 32 or 64
|
||||
localparam XLEN = 32'd32;
|
||||
|
||||
|
|
@ -46,6 +44,7 @@ localparam SSTC_SUPPORTED = 0;
|
|||
localparam ZICBOM_SUPPORTED = 0;
|
||||
localparam ZICBOZ_SUPPORTED = 0;
|
||||
localparam ZICBOP_SUPPORTED = 0;
|
||||
localparam ZICCLSM_SUPPORTED = 0;
|
||||
localparam SVPBMT_SUPPORTED = 0;
|
||||
localparam SVNAPOT_SUPPORTED = 0;
|
||||
localparam SVINVAL_SUPPORTED = 0;
|
||||
|
|
@ -97,9 +96,11 @@ localparam logic [63:0] IROM_RANGE = 64'h007FFFFF;
|
|||
localparam BOOTROM_SUPPORTED = 1'b0;
|
||||
localparam logic [63:0] BOOTROM_BASE = 64'h00001000;
|
||||
localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF;
|
||||
localparam BOOTROM_PRELOAD = 1'b0;
|
||||
localparam UNCORE_RAM_SUPPORTED = 1'b0;
|
||||
localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000;
|
||||
localparam logic [63:0] UNCORE_RAM_RANGE = 64'h07FFFFFF;
|
||||
localparam UNCORE_RAM_PRELOAD = 1'b0;
|
||||
localparam EXT_MEM_SUPPORTED = 1'b0;
|
||||
localparam logic [63:0] EXT_MEM_BASE = 64'h80000000;
|
||||
localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF;
|
||||
|
|
|
|||
|
|
@ -27,8 +27,6 @@
|
|||
|
||||
`include "BranchPredictorType.vh"
|
||||
|
||||
localparam FPGA = 0;
|
||||
|
||||
// RV32 or RV64: XLEN = 32 or 64
|
||||
localparam XLEN = 32'd64;
|
||||
|
||||
|
|
@ -47,6 +45,7 @@ localparam SSTC_SUPPORTED = 0;
|
|||
localparam ZICBOM_SUPPORTED = 0;
|
||||
localparam ZICBOZ_SUPPORTED = 0;
|
||||
localparam ZICBOP_SUPPORTED = 0;
|
||||
localparam ZICCLSM_SUPPORTED = 0;
|
||||
localparam SVPBMT_SUPPORTED = 0;
|
||||
localparam SVNAPOT_SUPPORTED = 0;
|
||||
localparam SVINVAL_SUPPORTED = 1;
|
||||
|
|
@ -103,9 +102,11 @@ localparam logic [63:0] IROM_RANGE = 64'h007FFFFF;
|
|||
localparam BOOTROM_SUPPORTED = 1'b1;
|
||||
localparam logic [63:0] BOOTROM_BASE = 64'h00001000; // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
|
||||
localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF;
|
||||
localparam BOOTROM_PRELOAD = 1'b0;
|
||||
localparam UNCORE_RAM_SUPPORTED = 1'b1;
|
||||
localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000;
|
||||
localparam logic [63:0] UNCORE_RAM_RANGE = 64'h7FFFFFFF;
|
||||
localparam UNCORE_RAM_PRELOAD = 1'b0;
|
||||
localparam EXT_MEM_SUPPORTED = 1'b0;
|
||||
localparam logic [63:0] EXT_MEM_BASE = 64'h80000000;
|
||||
localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF;
|
||||
|
|
|
|||
|
|
@ -27,8 +27,6 @@
|
|||
|
||||
`include "BranchPredictorType.vh"
|
||||
|
||||
localparam FPGA = 0;
|
||||
|
||||
// RV32 or RV64: XLEN = 32 or 64
|
||||
localparam XLEN = 32'd64;
|
||||
|
||||
|
|
@ -47,6 +45,7 @@ localparam SSTC_SUPPORTED = 1;
|
|||
localparam ZICBOM_SUPPORTED = 1;
|
||||
localparam ZICBOZ_SUPPORTED = 1;
|
||||
localparam ZICBOP_SUPPORTED = 1;
|
||||
localparam ZICCLSM_SUPPORTED = 1;
|
||||
localparam SVPBMT_SUPPORTED = 1;
|
||||
localparam SVNAPOT_SUPPORTED = 1;
|
||||
localparam SVINVAL_SUPPORTED = 1;
|
||||
|
|
@ -103,9 +102,11 @@ localparam logic [63:0] IROM_RANGE = 64'h007FFFFF;
|
|||
localparam BOOTROM_SUPPORTED = 1'b1;
|
||||
localparam logic [63:0] BOOTROM_BASE = 64'h00001000; // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder;
|
||||
localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF;
|
||||
localparam BOOTROM_PRELOAD = 1'b0;
|
||||
localparam UNCORE_RAM_SUPPORTED = 1'b1;
|
||||
localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000;
|
||||
localparam logic [63:0] UNCORE_RAM_RANGE = 64'h7FFFFFFF;
|
||||
localparam UNCORE_RAM_PRELOAD = 1'b0;
|
||||
localparam EXT_MEM_SUPPORTED = 1'b0;
|
||||
localparam logic [63:0] EXT_MEM_BASE = 64'h80000000;
|
||||
localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF;
|
||||
|
|
|
|||
|
|
@ -27,8 +27,6 @@
|
|||
|
||||
`include "BranchPredictorType.vh"
|
||||
|
||||
localparam FPGA = 0;
|
||||
|
||||
// RV32 or RV64: XLEN = 32 or 64
|
||||
localparam XLEN = 32'd64;
|
||||
|
||||
|
|
@ -47,6 +45,7 @@ localparam SSTC_SUPPORTED = 0;
|
|||
localparam ZICBOM_SUPPORTED = 0;
|
||||
localparam ZICBOZ_SUPPORTED = 0;
|
||||
localparam ZICBOP_SUPPORTED = 0;
|
||||
localparam ZICCLSM_SUPPORTED = 0;
|
||||
localparam SVPBMT_SUPPORTED = 0;
|
||||
localparam SVNAPOT_SUPPORTED = 0;
|
||||
localparam SVINVAL_SUPPORTED = 0;
|
||||
|
|
@ -103,9 +102,11 @@ localparam logic [63:0] IROM_RANGE = 64'h007FFFFF;
|
|||
localparam BOOTROM_SUPPORTED = 1'b0;
|
||||
localparam logic [63:0] BOOTROM_BASE = 64'h00001000; // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
|
||||
localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF;
|
||||
localparam BOOTROM_PRELOAD = 1'b0;
|
||||
localparam UNCORE_RAM_SUPPORTED = 1'b0;
|
||||
localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000;
|
||||
localparam logic [63:0] UNCORE_RAM_RANGE = 64'h7FFFFFFF;
|
||||
localparam UNCORE_RAM_PRELOAD = 1'b0;
|
||||
localparam EXT_MEM_SUPPORTED = 1'b0;
|
||||
localparam logic [63:0] EXT_MEM_BASE = 64'h80000000;
|
||||
localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF;
|
||||
|
|
|
|||
|
|
@ -4,7 +4,6 @@
|
|||
`include "BranchPredictorType.vh"
|
||||
|
||||
localparam cvw_t P = '{
|
||||
FPGA : FPGA,
|
||||
XLEN : XLEN,
|
||||
IEEE754 : IEEE754,
|
||||
MISA : MISA,
|
||||
|
|
@ -24,6 +23,7 @@ localparam cvw_t P = '{
|
|||
ZICBOM_SUPPORTED : ZICBOM_SUPPORTED,
|
||||
ZICBOZ_SUPPORTED : ZICBOZ_SUPPORTED,
|
||||
ZICBOP_SUPPORTED : ZICBOP_SUPPORTED,
|
||||
ZICCLSM_SUPPORTED : ZICCLSM_SUPPORTED,
|
||||
SVPBMT_SUPPORTED : SVPBMT_SUPPORTED,
|
||||
SVNAPOT_SUPPORTED : SVNAPOT_SUPPORTED,
|
||||
SVINVAL_SUPPORTED : SVINVAL_SUPPORTED,
|
||||
|
|
@ -52,9 +52,11 @@ localparam cvw_t P = '{
|
|||
BOOTROM_SUPPORTED : BOOTROM_SUPPORTED,
|
||||
BOOTROM_BASE : BOOTROM_BASE,
|
||||
BOOTROM_RANGE : BOOTROM_RANGE,
|
||||
BOOTROM_PRELOAD : BOOTROM_PRELOAD,
|
||||
UNCORE_RAM_SUPPORTED : UNCORE_RAM_SUPPORTED,
|
||||
UNCORE_RAM_BASE : UNCORE_RAM_BASE,
|
||||
UNCORE_RAM_RANGE : UNCORE_RAM_RANGE,
|
||||
UNCORE_RAM_PRELOAD : UNCORE_RAM_PRELOAD,
|
||||
EXT_MEM_SUPPORTED : EXT_MEM_SUPPORTED,
|
||||
EXT_MEM_BASE : EXT_MEM_BASE,
|
||||
EXT_MEM_RANGE : EXT_MEM_RANGE,
|
||||
|
|
|
|||
|
|
@ -6,20 +6,20 @@ dst := IP
|
|||
#export board := vcu118
|
||||
|
||||
# vcu108
|
||||
export XILINX_PART := xcvu095-ffva2104-2-e
|
||||
export XILINX_BOARD := xilinx.com:vcu108:part0:1.2
|
||||
export board := vcu108
|
||||
#export XILINX_PART := xcvu095-ffva2104-2-e
|
||||
#export XILINX_BOARD := xilinx.com:vcu108:part0:1.2
|
||||
#export board := vcu108
|
||||
|
||||
# Arty A7
|
||||
# export XILINX_PART := xc7a100tcsg324-1
|
||||
# export XILINX_BOARD := digilentinc.com:arty-a7-100:part0:1.1
|
||||
# export board := ArtyA7
|
||||
export XILINX_PART := xc7a100tcsg324-1
|
||||
export XILINX_BOARD := digilentinc.com:arty-a7-100:part0:1.1
|
||||
export board := ArtyA7
|
||||
|
||||
# for Arty A7 and S7 boards
|
||||
# all: FPGA_Arty
|
||||
all: FPGA_Arty
|
||||
|
||||
# VCU 108 and VCU 118 boards
|
||||
all: FPGA_VCU
|
||||
#all: FPGA_VCU
|
||||
|
||||
FPGA_Arty: PreProcessFiles IP_Arty
|
||||
vivado -mode tcl -source wally.tcl 2>&1 | tee wally.log
|
||||
|
|
@ -50,7 +50,26 @@ IP_Arty: $(dst)/xlnx_proc_sys_reset.log \
|
|||
PreProcessFiles:
|
||||
rm -rf ../src/CopiedFiles_do_not_add_to_repo/
|
||||
cp -r ../../src/ ../src/CopiedFiles_do_not_add_to_repo/
|
||||
mkdir ../src/CopiedFiles_do_not_add_to_repo/config/
|
||||
cp ../../config/rv64gc/config.vh ../src/CopiedFiles_do_not_add_to_repo/config/
|
||||
./insert_debug_comment.sh
|
||||
# modify config *** RT: eventually setup for variably defined sized memory
|
||||
sed -i "s/ZICCLSM_SUPPORTED.*/ZICCLSM_SUPPORTED = 0;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
|
||||
sed -i "s/RESET_VECTOR.*/RESET_VECTOR = 64'h0000000000001000;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
|
||||
sed -i "s/BOOTROM_PRELOAD.*/BOOTROM_PRELOAD = 1'b1;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
|
||||
sed -i "s/UNCORE_RAM_BASE.*/UNCORE_RAM_BASE = 64'h00002000;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
|
||||
sed -i "s/UNCORE_RAM_RANGE.*/UNCORE_RAM_RANGE = 64'h00000FFF;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
|
||||
sed -i "s/UNCORE_RAM_PRELOAD.*/UNCORE_RAM_PRELOAD = 1'b1;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
|
||||
sed -i "s/EXT_MEM_SUPPORTED.*/EXT_MEM_SUPPORTED = 1'b1;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
|
||||
sed -i "s/EXT_MEM_RANGE.*/EXT_MEM_RANGE = 64'h0FFFFFFF;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
|
||||
sed -i "s/SDC_SUPPORTED.*/SDC_SUPPORTED = 1'b1;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
|
||||
sed -i "s/SPI_SUPPORTED.*/SPI_SUPPORTED = 1'b0;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh # *** RT: Add SPI when ready
|
||||
sed -i "s/GPIO_LOOPBACK_TEST.*/GPIO_LOOPBACK_TEST = 0;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
|
||||
sed -i "s/SPI_LOOPBACK_TEST.*/SPI_LOOPBACK_TEST = 0;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
|
||||
sed -i "s/UART_PRESCALE.*/UART_PRESCALE = 32'd0;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
|
||||
sed -i "s/PLIC_NUM_SRC = .*/PLIC_NUM_SRC = 32'd53;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
|
||||
sed -i "s/PLIC_SDC_ID.*/PLIC_SDC_ID = 32'd20;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
|
||||
sed -i "s/BPRED_SIZE.*/BPRED_SIZE = 32'd12;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
|
||||
|
||||
$(dst)/%.log: %.tcl
|
||||
mkdir -p IP
|
||||
|
|
|
|||
|
|
@ -48,7 +48,7 @@ read_verilog [glob -type f ../../addins/vivado-risc-v/sdc/sd_cmd_serial_host.v]
|
|||
read_verilog [glob -type f ../../addins/vivado-risc-v/sdc/sd_data_master.v]
|
||||
read_verilog [glob -type f ../../addins/vivado-risc-v/sdc/sd_data_serial_host.v]
|
||||
|
||||
set_property include_dirs {../../config/fpga ../../config/shared ../../addins/vivado-risc-v/sdc} [current_fileset]
|
||||
set_property include_dirs {../src/CopiedFiles_do_not_add_to_repo/config ../../config/shared ../../addins/vivado-risc-v/sdc} [current_fileset]
|
||||
|
||||
if {$board=="ArtyA7"} {
|
||||
add_files -fileset constrs_1 -norecurse ../constraints/constraints-$board.xdc
|
||||
|
|
|
|||
|
|
@ -15,7 +15,7 @@ set_property -dict [list CONFIG.PRIM_IN_FREQ {100.000} \
|
|||
CONFIG.CLKOUT4_USED {false} \
|
||||
CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {166.66667} \
|
||||
CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {200} \
|
||||
CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {23} \
|
||||
CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {20} \
|
||||
CONFIG.CLKIN1_JITTER_PS {10.0} \
|
||||
] [get_ips $ipName]
|
||||
|
||||
|
|
|
|||
|
|
@ -27,15 +27,6 @@ BINARIES := fw_jump.elf vmlinux busybox
|
|||
OBJDUMPS := $(foreach name, $(BINARIES), $(basename $(name) .elf))
|
||||
OBJDUMPS := $(foreach name, $(OBJDUMPS), $(DIS)/$(name).objdump)
|
||||
|
||||
# LINUXDIR := $(shell ls $(BUILDROOT)/output/build | grep -e '^linux-[0-9]\+\.[0-9]\+\.[0-9]\+$$' )
|
||||
# LINUXDIR := $(BUILDROOT)/output/build/$(LINUXDIR)
|
||||
# BUSYBOXDIR := $(shell ls $(BUILDROOT)/output/build | grep -e '^linux-[0-9]\+\.[0-9]\+\.[0-9]\+$$' )
|
||||
# BUSYBOXDIR := $(BUILDROOT)/output/build/$(BUSYBOXDIR)
|
||||
|
||||
# Gets Linux and Busybox output folders for objedect dumps
|
||||
# LINUXDIR ?= $(shell find $(BUILDROOT)/output/build -maxdepth 2 -type d -regex ".*/linux-[0-9]+\.[0-9]+\.[0-9]+$$")
|
||||
# BUSYBOXDIR ?= $(shell find $(BUILDROOT)/output/build -maxdepth 2 -type d -regex ".*/busybox-[0-9]+\.[0-9]+\.[0-9]+$$")
|
||||
|
||||
define linuxDir =
|
||||
$(shell find $(BUILDROOT)/output/build -maxdepth 2 -type d -regex ".*/linux-[0-9]+\.[0-9]+\.[0-9]+$$")
|
||||
endef
|
||||
|
|
@ -46,10 +37,6 @@ endef
|
|||
|
||||
.PHONY: all generate disassemble install clean cleanDTB cleanDriver test
|
||||
|
||||
# Generate all device trees -------------------------------------------
|
||||
# TODO: Add configuration for only generating device tree for specified
|
||||
# supported FPGA.
|
||||
|
||||
all:
|
||||
$(MAKE) install
|
||||
make -C $(BUILDROOT) --jobs
|
||||
|
|
@ -99,18 +86,6 @@ $(IMAGES)/busybox: $(call busyboxDir)/busybox
|
|||
install: $(BUILDROOT)/package/fpga-axi-sdc $(WALLYBOARD)
|
||||
cp $(WALLYBOARD)/main.config $(BUILDROOT)/.config
|
||||
|
||||
# CONFIG DEPENDENCIES 2021.05 -----------------------------------------
|
||||
# $(WALLYBOARD)/main.config: $(WALLYBOARD) $(BRPACKAGES)/wally.config
|
||||
# cp $(BRPACKAGES)/wally.config $@
|
||||
|
||||
# $(WALLYBOARD)/linux.config: $(BRPACKAGES)/linux.config $(WALLYBOARD)
|
||||
# cp $(BRPACKAGES)/linux.config $@
|
||||
|
||||
# $(WALLYBOARD): $(BUILDROOT)
|
||||
# cp -r $(WALLYBOARDSRC) $(BUILDROOT)/board
|
||||
# cp $(BRPACKAGES)/wally.config $(WALLYBOARD)/main.config
|
||||
# cp $(BRPACKAGES)/linux.config $(WALLYBOARD)/linux.config
|
||||
|
||||
# CONFIG DEPENDENCIES 2023.05.1 ---------------------------------------
|
||||
$(WALLYBOARD): $(BUILDROOT)
|
||||
cp -r $(WALLYBOARDSRC) $(BUILDROOT)/board
|
||||
|
|
@ -129,13 +104,6 @@ $(PATCHFILE):
|
|||
$(BUILDROOT):
|
||||
git clone https://github.com/buildroot/buildroot.git $@
|
||||
cd $@; git checkout 2023.05.x
|
||||
#cd $@; git checkout 2021.05
|
||||
|
||||
#$(DRIVER):
|
||||
# @ if [ -d "$(WALLY)/addins/vivado-risc-v" ] ; then git submodule update --init $(WALLY)/addins/vivado-risc-v; fi
|
||||
# cp ../addins/vivado-risc-v/patches/fpga-axi-sdc.c $@
|
||||
# For 2021.05
|
||||
#sed -i "s|card_hw_reset|hw_reset|1" $@
|
||||
|
||||
# ---------------------------------------------------------------------
|
||||
|
||||
|
|
|
|||
|
|
@ -1,8 +1,8 @@
|
|||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# Linux/riscv 6.3.12 Kernel Configuration
|
||||
# Linux/riscv 6.6.0 Kernel Configuration
|
||||
#
|
||||
CONFIG_CC_VERSION_TEXT="riscv64-buildroot-linux-gnu-gcc.br_real (Buildroot 2023.05.1-dirty) 12.3.0"
|
||||
CONFIG_CC_VERSION_TEXT="riscv64-buildroot-linux-gnu-gcc.br_real (Buildroot 2023.05.3) 12.3.0"
|
||||
CONFIG_CC_IS_GCC=y
|
||||
CONFIG_GCC_VERSION=120300
|
||||
CONFIG_CLANG_VERSION=0
|
||||
|
|
@ -85,6 +85,7 @@ CONFIG_PREEMPT_NONE=y
|
|||
# CONFIG_PREEMPT_VOLUNTARY is not set
|
||||
# CONFIG_PREEMPT is not set
|
||||
CONFIG_PREEMPT_COUNT=y
|
||||
# CONFIG_PREEMPT_DYNAMIC is not set
|
||||
|
||||
#
|
||||
# CPU/Task time and stats accounting
|
||||
|
|
@ -101,7 +102,6 @@ CONFIG_TICK_CPU_ACCOUNTING=y
|
|||
#
|
||||
CONFIG_TINY_RCU=y
|
||||
# CONFIG_RCU_EXPERT is not set
|
||||
CONFIG_SRCU=y
|
||||
CONFIG_TINY_SRCU=y
|
||||
# end of RCU Subsystem
|
||||
|
||||
|
|
@ -109,7 +109,6 @@ CONFIG_IKCONFIG=y
|
|||
CONFIG_IKCONFIG_PROC=y
|
||||
# CONFIG_IKHEADERS is not set
|
||||
CONFIG_LOG_BUF_SHIFT=17
|
||||
CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13
|
||||
# CONFIG_PRINTK_INDEX is not set
|
||||
CONFIG_GENERIC_SCHED_CLOCK=y
|
||||
|
||||
|
|
@ -127,7 +126,6 @@ CONFIG_ARCH_SUPPORTS_INT128=y
|
|||
# CONFIG_NAMESPACES is not set
|
||||
# CONFIG_CHECKPOINT_RESTORE is not set
|
||||
# CONFIG_SCHED_AUTOGROUP is not set
|
||||
# CONFIG_SYSFS_DEPRECATED is not set
|
||||
# CONFIG_RELAY is not set
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
CONFIG_INITRAMFS_SOURCE="${BR_BINARIES_DIR}/rootfs.cpio"
|
||||
|
|
@ -146,6 +144,8 @@ CONFIG_INITRAMFS_COMPRESSION_GZIP=y
|
|||
CONFIG_INITRAMFS_PRESERVE_MTIME=y
|
||||
CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
|
||||
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
|
||||
CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION=y
|
||||
# CONFIG_LD_DEAD_CODE_DATA_ELIMINATION is not set
|
||||
CONFIG_LD_ORPHAN_WARN=y
|
||||
CONFIG_LD_ORPHAN_WARN_LEVEL="warn"
|
||||
CONFIG_SYSCTL=y
|
||||
|
|
@ -177,8 +177,8 @@ CONFIG_KALLSYMS=y
|
|||
CONFIG_KALLSYMS_BASE_RELATIVE=y
|
||||
# CONFIG_KCMP is not set
|
||||
CONFIG_RSEQ=y
|
||||
CONFIG_CACHESTAT_SYSCALL=y
|
||||
# CONFIG_DEBUG_RSEQ is not set
|
||||
# CONFIG_EMBEDDED is not set
|
||||
CONFIG_HAVE_PERF_EVENTS=y
|
||||
# CONFIG_PC104 is not set
|
||||
|
||||
|
|
@ -189,10 +189,19 @@ CONFIG_HAVE_PERF_EVENTS=y
|
|||
# end of Kernel Performance Events And Counters
|
||||
|
||||
# CONFIG_PROFILING is not set
|
||||
|
||||
#
|
||||
# Kexec and crash features
|
||||
#
|
||||
# CONFIG_KEXEC is not set
|
||||
# CONFIG_KEXEC_FILE is not set
|
||||
# CONFIG_CRASH_DUMP is not set
|
||||
# end of Kexec and crash features
|
||||
# end of General setup
|
||||
|
||||
CONFIG_64BIT=y
|
||||
CONFIG_RISCV=y
|
||||
CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE=y
|
||||
CONFIG_ARCH_MMAP_RND_BITS_MIN=18
|
||||
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=8
|
||||
CONFIG_ARCH_MMAP_RND_BITS_MAX=24
|
||||
|
|
@ -213,7 +222,9 @@ CONFIG_GENERIC_HWEIGHT=y
|
|||
CONFIG_FIX_EARLYCON_MEM=y
|
||||
CONFIG_PGTABLE_LEVELS=5
|
||||
CONFIG_LOCKDEP_SUPPORT=y
|
||||
CONFIG_RISCV_DMA_NONCOHERENT=y
|
||||
CONFIG_AS_HAS_INSN=y
|
||||
CONFIG_AS_HAS_OPTION_ARCH=y
|
||||
|
||||
#
|
||||
# SoC selection
|
||||
|
|
@ -223,12 +234,14 @@ CONFIG_AS_HAS_INSN=y
|
|||
# CONFIG_SOC_SIFIVE is not set
|
||||
# CONFIG_SOC_STARFIVE is not set
|
||||
# CONFIG_ARCH_SUNXI is not set
|
||||
# CONFIG_ARCH_THEAD is not set
|
||||
# CONFIG_SOC_VIRT is not set
|
||||
# end of SoC selection
|
||||
|
||||
#
|
||||
# CPU errata selection
|
||||
#
|
||||
# CONFIG_ERRATA_ANDES is not set
|
||||
# CONFIG_ERRATA_SIFIVE is not set
|
||||
# CONFIG_ERRATA_THEAD is not set
|
||||
# end of CPU errata selection
|
||||
|
|
@ -245,11 +258,18 @@ CONFIG_MODULE_SECTIONS=y
|
|||
CONFIG_TUNE_GENERIC=y
|
||||
CONFIG_RISCV_ALTERNATIVE=y
|
||||
CONFIG_RISCV_ISA_C=y
|
||||
CONFIG_RISCV_ISA_SVNAPOT=y
|
||||
CONFIG_RISCV_ISA_SVPBMT=y
|
||||
# CONFIG_RISCV_ISA_ZICBOM is not set
|
||||
CONFIG_TOOLCHAIN_HAS_V=y
|
||||
CONFIG_RISCV_ISA_V=y
|
||||
CONFIG_RISCV_ISA_V_DEFAULT_ENABLE=y
|
||||
CONFIG_RISCV_ISA_ZICBOM=y
|
||||
CONFIG_RISCV_ISA_ZICBOZ=y
|
||||
CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE=y
|
||||
CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI=y
|
||||
CONFIG_FPU=y
|
||||
CONFIG_IRQ_STACKS=y
|
||||
CONFIG_THREAD_SIZE_ORDER=2
|
||||
# end of Platform type
|
||||
|
||||
#
|
||||
|
|
@ -261,10 +281,12 @@ CONFIG_HZ_250=y
|
|||
# CONFIG_HZ_1000 is not set
|
||||
CONFIG_HZ=250
|
||||
# CONFIG_RISCV_SBI_V01 is not set
|
||||
# CONFIG_KEXEC is not set
|
||||
# CONFIG_KEXEC_FILE is not set
|
||||
# CONFIG_CRASH_DUMP is not set
|
||||
CONFIG_ARCH_SUPPORTS_KEXEC=y
|
||||
CONFIG_ARCH_SUPPORTS_KEXEC_FILE=y
|
||||
CONFIG_ARCH_SUPPORTS_CRASH_DUMP=y
|
||||
CONFIG_COMPAT=y
|
||||
# CONFIG_RELOCATABLE is not set
|
||||
# CONFIG_RANDOMIZE_BASE is not set
|
||||
# end of Kernel features
|
||||
|
||||
#
|
||||
|
|
@ -275,6 +297,7 @@ CONFIG_EFI_STUB=y
|
|||
CONFIG_EFI=y
|
||||
CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y
|
||||
CONFIG_STACKPROTECTOR_PER_TASK=y
|
||||
CONFIG_RISCV_ISA_FALLBACK=y
|
||||
# end of Boot options
|
||||
|
||||
CONFIG_PORTABLE=y
|
||||
|
|
@ -282,7 +305,18 @@ CONFIG_PORTABLE=y
|
|||
#
|
||||
# Power management options
|
||||
#
|
||||
# CONFIG_PM is not set
|
||||
CONFIG_SUSPEND=y
|
||||
CONFIG_SUSPEND_FREEZER=y
|
||||
# CONFIG_SUSPEND_SKIP_SYNC is not set
|
||||
CONFIG_PM_SLEEP=y
|
||||
# CONFIG_PM_AUTOSLEEP is not set
|
||||
# CONFIG_PM_USERSPACE_AUTOSLEEP is not set
|
||||
# CONFIG_PM_WAKELOCKS is not set
|
||||
CONFIG_PM=y
|
||||
# CONFIG_PM_DEBUG is not set
|
||||
CONFIG_PM_CLK=y
|
||||
# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
|
||||
CONFIG_ARCH_SUSPEND_POSSIBLE=y
|
||||
# end of Power management options
|
||||
|
||||
#
|
||||
|
|
@ -303,10 +337,13 @@ CONFIG_PORTABLE=y
|
|||
# end of CPU Power Management
|
||||
|
||||
# CONFIG_VIRTUALIZATION is not set
|
||||
CONFIG_ARCH_SUPPORTS_ACPI=y
|
||||
# CONFIG_ACPI is not set
|
||||
|
||||
#
|
||||
# General architecture-dependent options
|
||||
#
|
||||
CONFIG_GENERIC_ENTRY=y
|
||||
# CONFIG_KPROBES is not set
|
||||
CONFIG_JUMP_LABEL=y
|
||||
# CONFIG_STATIC_KEYS_SELFTEST is not set
|
||||
|
|
@ -332,6 +369,7 @@ CONFIG_HAVE_PERF_REGS=y
|
|||
CONFIG_HAVE_PERF_USER_STACK_DUMP=y
|
||||
CONFIG_HAVE_ARCH_JUMP_LABEL=y
|
||||
CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y
|
||||
CONFIG_MMU_LAZY_TLB_REFCOUNT=y
|
||||
CONFIG_HAVE_ARCH_SECCOMP=y
|
||||
CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
|
||||
CONFIG_SECCOMP=y
|
||||
|
|
@ -339,6 +377,7 @@ CONFIG_HAVE_STACKPROTECTOR=y
|
|||
CONFIG_STACKPROTECTOR=y
|
||||
CONFIG_STACKPROTECTOR_STRONG=y
|
||||
CONFIG_LTO_NONE=y
|
||||
CONFIG_ARCH_SUPPORTS_CFI_CLANG=y
|
||||
CONFIG_HAVE_CONTEXT_TRACKING_USER=y
|
||||
CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
|
||||
CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
|
||||
|
|
@ -350,6 +389,9 @@ CONFIG_HAVE_ARCH_HUGE_VMALLOC=y
|
|||
CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
|
||||
CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
|
||||
CONFIG_MODULES_USE_ELF_RELA=y
|
||||
CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y
|
||||
CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK=y
|
||||
CONFIG_SOFTIRQ_ON_OWN_STACK=y
|
||||
CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
|
||||
CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
|
||||
CONFIG_ARCH_MMAP_RND_BITS=18
|
||||
|
|
@ -370,9 +412,13 @@ CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
|
|||
CONFIG_STRICT_MODULE_RWX=y
|
||||
CONFIG_ARCH_USE_MEMREMAP_PROT=y
|
||||
# CONFIG_LOCK_EVENT_COUNTS is not set
|
||||
CONFIG_ARCH_HAS_VDSO_DATA=y
|
||||
CONFIG_HAVE_PREEMPT_DYNAMIC=y
|
||||
CONFIG_HAVE_PREEMPT_DYNAMIC_KEY=y
|
||||
CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y
|
||||
CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
|
||||
CONFIG_ARCH_SUPPORTS_PAGE_TABLE_CHECK=y
|
||||
CONFIG_DYNAMIC_SIGFRAME=y
|
||||
|
||||
#
|
||||
# GCOV-based kernel profiling
|
||||
|
|
@ -389,6 +435,7 @@ CONFIG_FUNCTION_ALIGNMENT=0
|
|||
CONFIG_RT_MUTEXES=y
|
||||
CONFIG_BASE_SMALL=0
|
||||
CONFIG_MODULES=y
|
||||
# CONFIG_MODULE_DEBUG is not set
|
||||
# CONFIG_MODULE_FORCE_LOAD is not set
|
||||
# CONFIG_MODULE_UNLOAD is not set
|
||||
# CONFIG_MODVERSIONS is not set
|
||||
|
|
@ -409,7 +456,6 @@ CONFIG_BLK_ICQ=y
|
|||
# CONFIG_BLK_DEV_ZONED is not set
|
||||
# CONFIG_BLK_WBT is not set
|
||||
CONFIG_BLK_DEBUG_FS=y
|
||||
# CONFIG_BLK_SED_OPAL is not set
|
||||
# CONFIG_BLK_INLINE_ENCRYPTION is not set
|
||||
|
||||
#
|
||||
|
|
@ -421,6 +467,7 @@ CONFIG_EFI_PARTITION=y
|
|||
# end of Partition Types
|
||||
|
||||
CONFIG_BLK_MQ_VIRTIO=y
|
||||
CONFIG_BLK_PM=y
|
||||
|
||||
#
|
||||
# IO Schedulers
|
||||
|
|
@ -435,6 +482,8 @@ CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
|
|||
CONFIG_ARCH_USE_QUEUED_RWLOCKS=y
|
||||
CONFIG_ARCH_HAS_MMIOWB=y
|
||||
CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y
|
||||
CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y
|
||||
CONFIG_FREEZER=y
|
||||
|
||||
#
|
||||
# Executable file formats
|
||||
|
|
@ -459,14 +508,14 @@ CONFIG_SWAP=y
|
|||
#
|
||||
# SLAB allocator options
|
||||
#
|
||||
# CONFIG_SLAB is not set
|
||||
# CONFIG_SLAB_DEPRECATED is not set
|
||||
CONFIG_SLUB=y
|
||||
# CONFIG_SLOB_DEPRECATED is not set
|
||||
# CONFIG_SLUB_TINY is not set
|
||||
CONFIG_SLAB_MERGE_DEFAULT=y
|
||||
# CONFIG_SLAB_FREELIST_RANDOM is not set
|
||||
# CONFIG_SLAB_FREELIST_HARDENED is not set
|
||||
# CONFIG_SLUB_STATS is not set
|
||||
# CONFIG_RANDOM_KMALLOC_CACHES is not set
|
||||
# end of SLAB allocator options
|
||||
|
||||
# CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set
|
||||
|
|
@ -476,6 +525,7 @@ CONFIG_FLATMEM_MANUAL=y
|
|||
# CONFIG_SPARSEMEM_MANUAL is not set
|
||||
CONFIG_FLATMEM=y
|
||||
CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
|
||||
CONFIG_ARCH_WANT_OPTIMIZE_HUGETLB_VMEMMAP=y
|
||||
CONFIG_SPLIT_PTLOCK_CPUS=4
|
||||
CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y
|
||||
CONFIG_COMPACTION=y
|
||||
|
|
@ -485,7 +535,6 @@ CONFIG_MIGRATION=y
|
|||
CONFIG_PHYS_ADDR_T_64BIT=y
|
||||
# CONFIG_KSM is not set
|
||||
CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
|
||||
CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
|
||||
CONFIG_ARCH_WANTS_THP_SWAP=y
|
||||
# CONFIG_TRANSPARENT_HUGEPAGE is not set
|
||||
CONFIG_NEED_PER_CPU_KM=y
|
||||
|
|
@ -497,11 +546,14 @@ CONFIG_ZONE_DMA32=y
|
|||
# CONFIG_VM_EVENT_COUNTERS is not set
|
||||
# CONFIG_PERCPU_STATS is not set
|
||||
# CONFIG_GUP_TEST is not set
|
||||
# CONFIG_DMAPOOL_TEST is not set
|
||||
CONFIG_ARCH_HAS_PTE_SPECIAL=y
|
||||
CONFIG_MEMFD_CREATE=y
|
||||
CONFIG_SECRETMEM=y
|
||||
# CONFIG_ANON_VMA_NAME is not set
|
||||
# CONFIG_USERFAULTFD is not set
|
||||
# CONFIG_LRU_GEN is not set
|
||||
CONFIG_ARCH_SUPPORTS_PER_VMA_LOCK=y
|
||||
CONFIG_LOCK_MM_AND_FIND_VMA=y
|
||||
|
||||
#
|
||||
|
|
@ -537,6 +589,7 @@ CONFIG_FW_LOADER=y
|
|||
CONFIG_EXTRA_FIRMWARE=""
|
||||
# CONFIG_FW_LOADER_USER_HELPER is not set
|
||||
# CONFIG_FW_LOADER_COMPRESS is not set
|
||||
CONFIG_FW_CACHE=y
|
||||
# CONFIG_FW_UPLOAD is not set
|
||||
# end of Firmware loader
|
||||
|
||||
|
|
@ -548,6 +601,7 @@ CONFIG_ALLOW_DEV_COREDUMP=y
|
|||
CONFIG_REGMAP=y
|
||||
CONFIG_REGMAP_MMIO=y
|
||||
CONFIG_GENERIC_ARCH_TOPOLOGY=y
|
||||
# CONFIG_FW_DEVLINK_SYNC_STATE_TIMEOUT is not set
|
||||
# end of Generic Driver Options
|
||||
|
||||
#
|
||||
|
|
@ -557,6 +611,12 @@ CONFIG_GENERIC_ARCH_TOPOLOGY=y
|
|||
# CONFIG_MHI_BUS_EP is not set
|
||||
# end of Bus devices
|
||||
|
||||
#
|
||||
# Cache Drivers
|
||||
#
|
||||
# CONFIG_AX45MP_L2_CACHE is not set
|
||||
# end of Cache Drivers
|
||||
|
||||
#
|
||||
# Firmware Drivers
|
||||
#
|
||||
|
|
@ -606,7 +666,6 @@ CONFIG_OF_ADDRESS=y
|
|||
CONFIG_OF_IRQ=y
|
||||
CONFIG_OF_RESERVED_MEM=y
|
||||
# CONFIG_OF_OVERLAY is not set
|
||||
CONFIG_OF_DMA_DEFAULT_COHERENT=y
|
||||
# CONFIG_PARPORT is not set
|
||||
CONFIG_BLK_DEV=y
|
||||
# CONFIG_BLK_DEV_NULL_BLK is not set
|
||||
|
|
@ -708,6 +767,7 @@ CONFIG_TTY=y
|
|||
CONFIG_VT=y
|
||||
CONFIG_CONSOLE_TRANSLATIONS=y
|
||||
CONFIG_VT_CONSOLE=y
|
||||
CONFIG_VT_CONSOLE_SLEEP=y
|
||||
CONFIG_HW_CONSOLE=y
|
||||
CONFIG_VT_HW_CONSOLE_BINDING=y
|
||||
CONFIG_UNIX98_PTYS=y
|
||||
|
|
@ -767,6 +827,7 @@ CONFIG_HW_RANDOM_VIRTIO=y
|
|||
# CONFIG_HW_RANDOM_CCTRNG is not set
|
||||
# CONFIG_HW_RANDOM_XIPHERA is not set
|
||||
CONFIG_DEVMEM=y
|
||||
CONFIG_DEVPORT=y
|
||||
# CONFIG_TCG_TPM is not set
|
||||
# CONFIG_XILLYBUS is not set
|
||||
# end of Character devices
|
||||
|
|
@ -876,14 +937,10 @@ CONFIG_BCMA_POSSIBLE=y
|
|||
#
|
||||
# Graphics support
|
||||
#
|
||||
# CONFIG_AUXDISPLAY is not set
|
||||
# CONFIG_DRM is not set
|
||||
# CONFIG_DRM_DEBUG_MODESET_LOCK is not set
|
||||
|
||||
#
|
||||
# ARM devices
|
||||
#
|
||||
# end of ARM devices
|
||||
|
||||
#
|
||||
# Frame buffer Devices
|
||||
#
|
||||
|
|
@ -944,7 +1001,6 @@ CONFIG_EDAC_SUPPORT=y
|
|||
# CONFIG_DMABUF_HEAPS is not set
|
||||
# end of DMABUF options
|
||||
|
||||
# CONFIG_AUXDISPLAY is not set
|
||||
# CONFIG_UIO is not set
|
||||
# CONFIG_VFIO is not set
|
||||
# CONFIG_VIRT_DRIVERS is not set
|
||||
|
|
@ -1121,6 +1177,7 @@ CONFIG_SIFIVE_PLIC=y
|
|||
#
|
||||
# CONFIG_VALIDATE_FS_PARSER is not set
|
||||
CONFIG_FS_IOMAP=y
|
||||
CONFIG_BUFFER_HEAD=y
|
||||
# CONFIG_EXT2_FS is not set
|
||||
# CONFIG_EXT3_FS is not set
|
||||
CONFIG_EXT4_FS=y
|
||||
|
|
@ -1149,7 +1206,6 @@ CONFIG_DNOTIFY=y
|
|||
CONFIG_INOTIFY_USER=y
|
||||
# CONFIG_FANOTIFY is not set
|
||||
# CONFIG_QUOTA is not set
|
||||
# CONFIG_AUTOFS4_FS is not set
|
||||
CONFIG_AUTOFS_FS=y
|
||||
# CONFIG_FUSE_FS is not set
|
||||
# CONFIG_OVERLAY_FS is not set
|
||||
|
|
@ -1191,10 +1247,9 @@ CONFIG_TMPFS=y
|
|||
CONFIG_TMPFS_POSIX_ACL=y
|
||||
CONFIG_TMPFS_XATTR=y
|
||||
# CONFIG_TMPFS_INODE64 is not set
|
||||
# CONFIG_TMPFS_QUOTA is not set
|
||||
CONFIG_ARCH_SUPPORTS_HUGETLBFS=y
|
||||
# CONFIG_HUGETLBFS is not set
|
||||
CONFIG_ARCH_WANT_HUGETLB_PAGE_OPTIMIZE_VMEMMAP=y
|
||||
CONFIG_MEMFD_CREATE=y
|
||||
CONFIG_ARCH_HAS_GIGANTIC_PAGE=y
|
||||
# CONFIG_CONFIGFS_FS is not set
|
||||
CONFIG_EFIVAR_FS=y
|
||||
|
|
@ -1213,7 +1268,6 @@ CONFIG_IO_WQ=y
|
|||
# CONFIG_SECURITY_DMESG_RESTRICT is not set
|
||||
# CONFIG_SECURITY is not set
|
||||
# CONFIG_SECURITYFS is not set
|
||||
CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
|
||||
# CONFIG_HARDENED_USERCOPY is not set
|
||||
# CONFIG_FORTIFY_SOURCE is not set
|
||||
# CONFIG_STATIC_USERMODEHELPER is not set
|
||||
|
|
@ -1239,6 +1293,13 @@ CONFIG_CC_HAS_ZERO_CALL_USED_REGS=y
|
|||
# CONFIG_ZERO_CALL_USED_REGS is not set
|
||||
# end of Memory initialization
|
||||
|
||||
#
|
||||
# Hardening of kernel data structures
|
||||
#
|
||||
CONFIG_LIST_HARDENED=y
|
||||
# CONFIG_BUG_ON_DATA_CORRUPTION is not set
|
||||
# end of Hardening of kernel data structures
|
||||
|
||||
CONFIG_RANDSTRUCT_NONE=y
|
||||
# end of Kernel hardening options
|
||||
# end of Security options
|
||||
|
|
@ -1426,14 +1487,26 @@ CONFIG_CRC32_SLICEBY8=y
|
|||
CONFIG_ZLIB_INFLATE=y
|
||||
# CONFIG_XZ_DEC is not set
|
||||
CONFIG_DECOMPRESS_GZIP=y
|
||||
CONFIG_GENERIC_ALLOCATOR=y
|
||||
CONFIG_HAS_IOMEM=y
|
||||
CONFIG_HAS_IOPORT=y
|
||||
CONFIG_HAS_IOPORT_MAP=y
|
||||
CONFIG_HAS_DMA=y
|
||||
CONFIG_NEED_DMA_MAP_STATE=y
|
||||
CONFIG_ARCH_DMA_ADDR_T_64BIT=y
|
||||
CONFIG_DMA_DECLARE_COHERENT=y
|
||||
CONFIG_ARCH_HAS_SETUP_DMA_OPS=y
|
||||
CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y
|
||||
CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y
|
||||
CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y
|
||||
CONFIG_ARCH_DMA_DEFAULT_COHERENT=y
|
||||
CONFIG_SWIOTLB=y
|
||||
# CONFIG_SWIOTLB_DYNAMIC is not set
|
||||
CONFIG_DMA_BOUNCE_UNALIGNED_KMALLOC=y
|
||||
# CONFIG_DMA_RESTRICTED_POOL is not set
|
||||
CONFIG_DMA_NONCOHERENT_MMAP=y
|
||||
CONFIG_DMA_COHERENT_POOL=y
|
||||
CONFIG_DMA_DIRECT_REMAP=y
|
||||
# CONFIG_DMA_API_DEBUG is not set
|
||||
# CONFIG_DMA_MAP_BENCHMARK is not set
|
||||
# CONFIG_IRQ_POLL is not set
|
||||
|
|
@ -1489,6 +1562,7 @@ CONFIG_READABLE_ASM=y
|
|||
# CONFIG_HEADERS_INSTALL is not set
|
||||
# CONFIG_DEBUG_SECTION_MISMATCH is not set
|
||||
CONFIG_SECTION_MISMATCH_WARN_ONLY=y
|
||||
# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_64B is not set
|
||||
CONFIG_ARCH_WANT_FRAME_POINTERS=y
|
||||
CONFIG_FRAME_POINTER=y
|
||||
# CONFIG_VMLINUX_MAP is not set
|
||||
|
|
@ -1570,6 +1644,7 @@ CONFIG_DETECT_HUNG_TASK=y
|
|||
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120
|
||||
# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
|
||||
CONFIG_WQ_WATCHDOG=y
|
||||
# CONFIG_WQ_CPU_INTENSIVE_REPORT is not set
|
||||
# CONFIG_TEST_LOCKUP is not set
|
||||
# end of Debug Oops, Lockups and Hangs
|
||||
|
||||
|
|
@ -1614,7 +1689,6 @@ CONFIG_DEBUG_LIST=y
|
|||
CONFIG_DEBUG_PLIST=y
|
||||
CONFIG_DEBUG_SG=y
|
||||
# CONFIG_DEBUG_NOTIFIERS is not set
|
||||
# CONFIG_BUG_ON_DATA_CORRUPTION is not set
|
||||
# CONFIG_DEBUG_MAPLE_TREE is not set
|
||||
# end of Debug kernel data structures
|
||||
|
||||
|
|
@ -1635,6 +1709,7 @@ CONFIG_RCU_EQS_DEBUG=y
|
|||
CONFIG_HAVE_RETHOOK=y
|
||||
CONFIG_HAVE_FUNCTION_TRACER=y
|
||||
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
|
||||
CONFIG_HAVE_FUNCTION_GRAPH_RETVAL=y
|
||||
CONFIG_HAVE_DYNAMIC_FTRACE=y
|
||||
CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
|
||||
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# Buildroot 2023.05.2-166-gb362115b25 Configuration
|
||||
# Buildroot 2023.05.3-dirty Configuration
|
||||
#
|
||||
BR2_HAVE_DOT_CONFIG=y
|
||||
BR2_HOST_GCC_AT_LEAST_4_9=y
|
||||
|
|
@ -399,15 +399,16 @@ BR2_ROOTFS_POST_IMAGE_SCRIPT=""
|
|||
# Kernel
|
||||
#
|
||||
BR2_LINUX_KERNEL=y
|
||||
BR2_LINUX_KERNEL_LATEST_VERSION=y
|
||||
# BR2_LINUX_KERNEL_LATEST_VERSION is not set
|
||||
# BR2_LINUX_KERNEL_LATEST_CIP_VERSION is not set
|
||||
# BR2_LINUX_KERNEL_LATEST_CIP_RT_VERSION is not set
|
||||
# BR2_LINUX_KERNEL_CUSTOM_VERSION is not set
|
||||
BR2_LINUX_KERNEL_CUSTOM_VERSION=y
|
||||
# BR2_LINUX_KERNEL_CUSTOM_TARBALL is not set
|
||||
# BR2_LINUX_KERNEL_CUSTOM_GIT is not set
|
||||
# BR2_LINUX_KERNEL_CUSTOM_HG is not set
|
||||
# BR2_LINUX_KERNEL_CUSTOM_SVN is not set
|
||||
BR2_LINUX_KERNEL_VERSION="6.3.13"
|
||||
BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="6.6"
|
||||
BR2_LINUX_KERNEL_VERSION="6.6"
|
||||
BR2_LINUX_KERNEL_PATCH=""
|
||||
# BR2_LINUX_KERNEL_USE_DEFCONFIG is not set
|
||||
# BR2_LINUX_KERNEL_USE_ARCH_DEFAULT_CONFIG is not set
|
||||
|
|
@ -433,6 +434,7 @@ BR2_LINUX_KERNEL_GZIP=y
|
|||
#
|
||||
# Linux Kernel Extensions
|
||||
#
|
||||
# BR2_LINUX_KERNEL_EXT_RTAI is not set
|
||||
# BR2_LINUX_KERNEL_EXT_EV3DEV_LINUX_DRIVERS is not set
|
||||
# BR2_LINUX_KERNEL_EXT_FBTFT is not set
|
||||
# BR2_LINUX_KERNEL_EXT_AUFS is not set
|
||||
|
|
@ -939,6 +941,7 @@ BR2_PACKAGE_NETSURF_ARCH_SUPPORTS=y
|
|||
BR2_PACKAGE_FLASHROM_ARCH_SUPPORTS=y
|
||||
# BR2_PACKAGE_FLASHROM is not set
|
||||
# BR2_PACKAGE_FMTOOLS is not set
|
||||
BR2_PACKAGE_FPGA_AXI_SDC=y
|
||||
# BR2_PACKAGE_FREEIPMI is not set
|
||||
# BR2_PACKAGE_FXLOAD is not set
|
||||
# BR2_PACKAGE_GPM is not set
|
||||
|
|
|
|||
|
|
@ -21,8 +21,8 @@
|
|||
cpus {
|
||||
#address-cells = <0x01>;
|
||||
#size-cells = <0x00>;
|
||||
clock-frequency = <0x15EF3C0>;
|
||||
timebase-frequency = <0x15EF3C0>;
|
||||
clock-frequency = <0x1312D00>;
|
||||
timebase-frequency = <0x1312D00>;
|
||||
|
||||
cpu@0 {
|
||||
phandle = <0x01>;
|
||||
|
|
@ -51,7 +51,7 @@
|
|||
uart@10000000 {
|
||||
interrupts = <0x0a>;
|
||||
interrupt-parent = <0x03>;
|
||||
clock-frequency = <0x15EF3C0>;
|
||||
clock-frequency = <0x1312D00>;
|
||||
reg = <0x00 0x10000000 0x00 0x100>;
|
||||
compatible = "ns16550a";
|
||||
};
|
||||
|
|
@ -74,8 +74,8 @@
|
|||
fifo-depth = <256>;
|
||||
bus-width = <4>;
|
||||
interrupt-parent = <0x03>;
|
||||
clock = <0x15EF3C0>;
|
||||
max-frequency = <0x15EF3C0>;
|
||||
clock = <0x1312D00>;
|
||||
max-frequency = <0x1312D00>;
|
||||
cap-sd-highspeed;
|
||||
cap-mmc-highspeed;
|
||||
no-sdio;
|
||||
|
|
|
|||
|
|
@ -15,7 +15,7 @@
|
|||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x00 0x80000000 0x00 0x08000000>;
|
||||
reg = <0x00 0x80000000 0x00 0x10000000>;
|
||||
};
|
||||
|
||||
cpus {
|
||||
|
|
|
|||
49
linux/testvector-generation/EmulateLinux.sh
Executable file
49
linux/testvector-generation/EmulateLinux.sh
Executable file
|
|
@ -0,0 +1,49 @@
|
|||
#!/bin/bash
|
||||
|
||||
usage() { echo "Usage: $0 [-h] [-b <path/to/buildroot>] [-d <path/to/device tree>]" 1>&2; exit 1; }
|
||||
|
||||
help() {
|
||||
echo "Usage: $0 [OPTIONS] <device>"
|
||||
echo " -b <path/to/buildroot> get images from given buildroot"
|
||||
echo " -d <device tree name> specify device tree to use"
|
||||
exit 0;
|
||||
}
|
||||
|
||||
# defaults
|
||||
imageDir=$RISCV/buildroot/output/images
|
||||
DEVICE_TREE=../devicetree/wally-virt.dtb
|
||||
|
||||
# Process options and arguments. The following code grabs the single
|
||||
# sdcard device argument no matter where it is in the positional
|
||||
# parameters list.
|
||||
ARGS=()
|
||||
while [ $OPTIND -le "$#" ] ; do
|
||||
if getopts "hb:d:" arg ; then
|
||||
case "${arg}" in
|
||||
h) help
|
||||
;;
|
||||
b) BUILDROOT=${OPTARG}
|
||||
;;
|
||||
d) DEVICE_TREE=${OPTARG}
|
||||
;;
|
||||
esac
|
||||
else
|
||||
ARGS+=("${!OPTIND}")
|
||||
((OPTIND++))
|
||||
fi
|
||||
done
|
||||
|
||||
# File location variables
|
||||
imageDir=$BUILDROOT/output/images
|
||||
|
||||
#imageDir=$RISCV/buildroot/output/images
|
||||
imageDir=~/repos/buildroot-sept2023/output/images
|
||||
tvDir=$RISCV/linux-testvectors
|
||||
tcpPort=1239
|
||||
|
||||
# QEMU Simulation
|
||||
qemu-system-riscv64 \
|
||||
-M virt -m 256M -dtb $DEVICE_TREE \
|
||||
-nographic \
|
||||
-bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro"
|
||||
-singlestep -rtc clock=vm -icount shift=0,align=off,sleep=on
|
||||
573
sim/wave.do
573
sim/wave.do
|
|
@ -34,6 +34,7 @@ add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/Lo
|
|||
add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM
|
||||
add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/InterruptM
|
||||
add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/HPTWInstrAccessFaultM
|
||||
add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/pmd/WFITimeoutM
|
||||
add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushD
|
||||
add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushE
|
||||
add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushM
|
||||
|
|
@ -43,6 +44,10 @@ add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/Sta
|
|||
add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallE
|
||||
add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallM
|
||||
add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallW
|
||||
add wave -noupdate /testbench/dut/core/hzu/WFIInterruptedM
|
||||
add wave -noupdate /testbench/dut/core/priv/priv/trap/PendingIntsM
|
||||
add wave -noupdate /testbench/dut/core/priv/priv/trap/InstrValidM
|
||||
add wave -noupdate /testbench/dut/core/priv/priv/trap/ValidIntsM
|
||||
add wave -noupdate -group {instruction pipeline} /testbench/InstrFName
|
||||
add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/PostSpillInstrRawF
|
||||
add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrD
|
||||
|
|
@ -75,257 +80,295 @@ add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/PCM
|
|||
add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrM
|
||||
add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName
|
||||
add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/lsu/IEUAdrM
|
||||
add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataM
|
||||
add wave -noupdate -group lsu /testbench/dut/core/lsu/WriteDataM
|
||||
add wave -noupdate -group lsu /testbench/dut/core/lsu/SelHPTW
|
||||
add wave -noupdate -group lsu /testbench/dut/core/lsu/LSUStallM
|
||||
add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM
|
||||
add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataM
|
||||
add wave -noupdate -group lsu -radix hexadecimal /testbench/dut/core/lsu/WriteDataM
|
||||
add wave -noupdate -group lsu /testbench/dut/core/lsu/FWriteDataM
|
||||
add wave -noupdate -group lsu /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall
|
||||
add wave -noupdate -group lsu /testbench/dut/core/lsu/IgnoreRequestTLB
|
||||
add wave -noupdate -group lsu /testbench/dut/core/lsu/SelHPTW
|
||||
add wave -noupdate -group lsu -group bus /testbench/dut/core/ebu/ebu/HCLK
|
||||
add wave -noupdate -group lsu -group bus -color Gold /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/CurrState
|
||||
add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/HREADY
|
||||
add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/BusStall
|
||||
add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HTRANS
|
||||
add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/FetchBuffer
|
||||
add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HRDATA
|
||||
add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUHWDATA
|
||||
add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/BusStall
|
||||
add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusRW
|
||||
add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusAck
|
||||
add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr
|
||||
add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit
|
||||
add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheRW
|
||||
add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CMOp
|
||||
add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CMOZeroHit
|
||||
add wave -noupdate -group lsu -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState
|
||||
add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
|
||||
add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid
|
||||
add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid
|
||||
add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty
|
||||
add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
|
||||
add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr
|
||||
add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/IEUAdrE
|
||||
add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheSet
|
||||
add wave -noupdate -group lsu -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay}
|
||||
add wave -noupdate -group lsu -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
|
||||
add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelFlush
|
||||
add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelWriteback
|
||||
add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/TagWay
|
||||
add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/Tag
|
||||
add wave -noupdate -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay
|
||||
add wave -noupdate -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn
|
||||
add wave -noupdate -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CacheSet
|
||||
add wave -noupdate -group lsu -group dcache -group {replacement policy} -color {Orange Red} {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]}
|
||||
add wave -noupdate -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU
|
||||
add wave -noupdate -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU
|
||||
add wave -noupdate -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/VictimWay
|
||||
add wave -noupdate -group lsu -group dcache -group {replacement policy} -expand -group DETAILS -expand /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/Intermediate
|
||||
add wave -noupdate -group lsu -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUUpdate
|
||||
add wave -noupdate -group lsu -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/WayExpanded
|
||||
add wave -noupdate -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/LineDirty
|
||||
add wave -noupdate -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
|
||||
add wave -noupdate -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/NextFlushAdr
|
||||
add wave -noupdate -group lsu -group dcache -group flush -radix hexadecimal /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr
|
||||
add wave -noupdate -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushWayFlag
|
||||
add wave -noupdate -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWayCntEn
|
||||
add wave -noupdate -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushAdrCntEn
|
||||
add wave -noupdate -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdrFlag
|
||||
add wave -noupdate -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/SelFlush
|
||||
add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay
|
||||
add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr
|
||||
add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/PAdr
|
||||
add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/CacheSet
|
||||
add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU
|
||||
add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU
|
||||
add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn
|
||||
add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLine
|
||||
add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/WordOffsetAddr
|
||||
add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay
|
||||
add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/ValidWay
|
||||
add wave -noupdate -group lsu -group dcache -group Victim {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]}
|
||||
add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/SetValid
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelData}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearValidWay}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/RAM[62]}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelNotHit2}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelNonHit}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelData}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ClearValidWay}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ClearValidWay}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ClearValidWay}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/CacheSet
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidWay}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/TagWay}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidWay}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/TagWay}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidWay}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/TagWay}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidWay}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/TagWay}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
|
||||
add wave -noupdate -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/NextSet
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusRW
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataWord
|
||||
add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBHit
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress
|
||||
add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault
|
||||
add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM
|
||||
add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr
|
||||
add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
|
||||
add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal
|
||||
add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM
|
||||
add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF
|
||||
add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM
|
||||
add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM
|
||||
add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/SelHPTW
|
||||
add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWStall
|
||||
add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/DTLBWalk
|
||||
add wave -noupdate -group lsu -group ptwalker -color Gold /testbench/dut/core/lsu/hptw/hptw/WalkerState
|
||||
add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWAdr
|
||||
add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PTE
|
||||
add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/NextPageType
|
||||
add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PageType
|
||||
add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/ValidNonLeafPTE
|
||||
add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/ITLBMissF
|
||||
add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/DTLBMissM
|
||||
add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/ITLBWriteF
|
||||
add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/DTLBWriteM
|
||||
add wave -noupdate -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUAccessFaultM
|
||||
add wave -noupdate -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/DCacheStallM
|
||||
add wave -noupdate -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFaultF
|
||||
add wave -noupdate -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSULoadAccessFaultM
|
||||
add wave -noupdate -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUStoreAmoAccessFaultM
|
||||
add wave -noupdate -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LoadAccessFaultM
|
||||
add wave -noupdate -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/StoreAmoAccessFaultM
|
||||
add wave -noupdate -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFault
|
||||
add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataM
|
||||
add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/WriteDataM
|
||||
add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/SelHPTW
|
||||
add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/LSUStallM
|
||||
add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM
|
||||
add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataM
|
||||
add wave -noupdate -expand -group lsu -radix hexadecimal /testbench/dut/core/lsu/WriteDataM
|
||||
add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/FWriteDataM
|
||||
add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall
|
||||
add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/IgnoreRequestTLB
|
||||
add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/SelHPTW
|
||||
add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/ebu/ebu/HCLK
|
||||
add wave -noupdate -expand -group lsu -expand -group bus -color Gold /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/CurrState
|
||||
add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/HREADY
|
||||
add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/BusStall
|
||||
add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HTRANS
|
||||
add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/FetchBuffer
|
||||
add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HRDATA
|
||||
add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/LSUHWDATA
|
||||
add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/BusStall
|
||||
add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusRW
|
||||
add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusAck
|
||||
add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr
|
||||
add wave -noupdate -expand -group lsu -group alignment -color Gold /testbench/dut/core/lsu/ziccslm_align/align/CurrState
|
||||
add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/ziccslm_align/align/MemRWM
|
||||
add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/ziccslm_align/align/DTLBMissM
|
||||
add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/ziccslm_align/align/CacheableM
|
||||
add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/ziccslm_align/align/HalfSpillM
|
||||
add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/ziccslm_align/align/WordSpillM
|
||||
add wave -noupdate -expand -group lsu -group alignment -color Orange /testbench/dut/core/lsu/ziccslm_align/align/SpillM
|
||||
add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/ziccslm_align/align/IEUAdrSpillM
|
||||
add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/ziccslm_align/align/SaveByteMask
|
||||
add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/ziccslm_align/align/ByteMaskSaveM
|
||||
add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/ByteMaskM
|
||||
add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/ByteMaskExtendedM
|
||||
add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/ziccslm_align/align/SelSpillE
|
||||
add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/ziccslm_align/align/SelSpillM
|
||||
add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/ziccslm_align/align/ByteMaskMuxM
|
||||
add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/ByteMaskSpillM
|
||||
add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/LSUWriteDataM
|
||||
add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/ziccslm_align/align/LSUWriteDataShiftedM
|
||||
add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/LSUWriteDataSpillM
|
||||
add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/CacheWriteData
|
||||
add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/ByteMask
|
||||
add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/WriteSelLogic/BlankByteMask
|
||||
add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/WriteSelLogic/DemuxedByteMask
|
||||
add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/WriteSelLogic/FetchBufferByteSel
|
||||
add wave -noupdate -expand -group lsu -group alignment {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/LineWriteData}
|
||||
add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/ziccslm_align/align/IncrementAmount
|
||||
add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/IEUAdrExtE
|
||||
add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/IEUAdrExtM
|
||||
add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/bus/dcache/dcache/NextSet
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheRW
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CMOp
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CMOZeroHit
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrE
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -radix unsigned /testbench/dut/core/lsu/bus/dcache/dcache/CacheSet
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/PAdr
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelFlush
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelWriteback
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/TagWay
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/Tag
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLineCache
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataWord
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CacheSet
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} -color {Orange Red} {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/VictimWay
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} -expand -group DETAILS -expand /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/Intermediate
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUUpdate
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/WayExpanded
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/LineDirty
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/NextFlushAdr
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group flush -radix hexadecimal /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushWayFlag
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWayCntEn
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushAdrCntEn
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdrFlag
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/SelFlush
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/PAdr
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/CacheSet
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLine
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/WordOffsetAddr
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/ValidWay
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/SetValid
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/LineByteMask
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearValidWay}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/bwe}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/bwe}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/bwe}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/ce}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/bwe}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelNotHit2}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelNonHit}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ClearValidWay}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ClearValidWay}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ClearValidWay}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/CacheSet
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidWay}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/TagWay}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidWay}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/TagWay}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidWay}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/TagWay}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidWay}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/TagWay}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/NextSet
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusRW
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataWord
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBHit
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress
|
||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault
|
||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr
|
||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
|
||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal
|
||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite
|
||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress
|
||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions
|
||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable
|
||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent
|
||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault
|
||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF
|
||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/SelHPTW
|
||||
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWStall
|
||||
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/DTLBWalk
|
||||
add wave -noupdate -expand -group lsu -group ptwalker -color Gold /testbench/dut/core/lsu/hptw/hptw/WalkerState
|
||||
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWAdr
|
||||
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PTE
|
||||
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/NextPageType
|
||||
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PageType
|
||||
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/ValidNonLeafPTE
|
||||
add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/ITLBMissF
|
||||
add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/DTLBMissM
|
||||
add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/ITLBWriteF
|
||||
add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/DTLBWriteM
|
||||
add wave -noupdate -expand -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/DCacheStallM
|
||||
add wave -noupdate -expand -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFaultF
|
||||
add wave -noupdate -expand -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSULoadAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUStoreAmoAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LoadAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/StoreAmoAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFault
|
||||
add wave -noupdate -group {WriteBack stage} /testbench/InstrW
|
||||
add wave -noupdate -group {WriteBack stage} /testbench/InstrWName
|
||||
add wave -noupdate -expand -group Bpred -expand -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRM
|
||||
add wave -noupdate -expand -group Bpred -expand -group {branch update selection inputs} -label PHT /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHT/mem
|
||||
add wave -noupdate -expand -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[5]}
|
||||
add wave -noupdate -expand -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[4]}
|
||||
add wave -noupdate -expand -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[3]}
|
||||
add wave -noupdate -expand -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[2]}
|
||||
add wave -noupdate -expand -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[1]}
|
||||
add wave -noupdate -expand -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[0]}
|
||||
add wave -noupdate -expand -group Bpred -expand -group RAS -expand /testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory
|
||||
add wave -noupdate -expand -group Bpred -expand -group RAS /testbench/dut/core/ifu/bpred/bpred/RASPredictor/Ptr
|
||||
add wave -noupdate -expand -group Bpred -divider {class check}
|
||||
add wave -noupdate -expand -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF
|
||||
add wave -noupdate -expand -group Bpred -expand -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE
|
||||
add wave -noupdate -group {WriteBack stage} /testbench/dut/core/priv/priv/pmd/wfiW
|
||||
add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRM
|
||||
add wave -noupdate -group Bpred -expand -group {branch update selection inputs} -label PHT /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHT/mem
|
||||
add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[5]}
|
||||
add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[4]}
|
||||
add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[3]}
|
||||
add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[2]}
|
||||
add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[1]}
|
||||
add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[0]}
|
||||
add wave -noupdate -group Bpred -expand -group RAS -expand /testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory
|
||||
add wave -noupdate -group Bpred -expand -group RAS /testbench/dut/core/ifu/bpred/bpred/RASPredictor/Ptr
|
||||
add wave -noupdate -group Bpred -divider {class check}
|
||||
add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF
|
||||
add wave -noupdate -group Bpred -expand -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE
|
||||
add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNextF
|
||||
add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/bpred/bpred/NextValidPCE
|
||||
add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCF
|
||||
add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCPlus2or4F
|
||||
add wave -noupdate -group RegFile -expand /testbench/dut/core/ieu/dp/regf/rf
|
||||
add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a1
|
||||
add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a2
|
||||
add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a3
|
||||
add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/rd1
|
||||
add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/rd2
|
||||
add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/we3
|
||||
add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/wd3
|
||||
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/ReadDataW
|
||||
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/CSRReadValW
|
||||
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/ResultSrcW
|
||||
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/ResultW
|
||||
add wave -noupdate -expand -group RegFile -expand /testbench/dut/core/ieu/dp/regf/rf
|
||||
add wave -noupdate -expand -group RegFile /testbench/dut/core/ieu/dp/regf/a1
|
||||
add wave -noupdate -expand -group RegFile /testbench/dut/core/ieu/dp/regf/a2
|
||||
add wave -noupdate -expand -group RegFile /testbench/dut/core/ieu/dp/regf/a3
|
||||
add wave -noupdate -expand -group RegFile /testbench/dut/core/ieu/dp/regf/rd1
|
||||
add wave -noupdate -expand -group RegFile /testbench/dut/core/ieu/dp/regf/rd2
|
||||
add wave -noupdate -expand -group RegFile /testbench/dut/core/ieu/dp/regf/we3
|
||||
add wave -noupdate -expand -group RegFile /testbench/dut/core/ieu/dp/regf/wd3
|
||||
add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/ReadDataW
|
||||
add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/CSRReadValW
|
||||
add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/ResultSrcW
|
||||
add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/ResultW
|
||||
add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/csrm/MISA_REGW
|
||||
add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/csrm/MCAUSE_REGW
|
||||
add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MCOUNTEREN_REGW
|
||||
|
|
@ -489,14 +532,14 @@ add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/d
|
|||
add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/IFUCacheBusStallF
|
||||
add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/ITLBMissF
|
||||
add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/TakeSpillF
|
||||
add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HSIZE
|
||||
add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HBURST
|
||||
add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HTRANS
|
||||
add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HWRITE
|
||||
add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HADDR
|
||||
add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/Flush
|
||||
add wave -noupdate -group ifu -group bus -color Gold /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/CurrState
|
||||
add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HRDATA
|
||||
add wave -noupdate -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HSIZE
|
||||
add wave -noupdate -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HBURST
|
||||
add wave -noupdate -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HTRANS
|
||||
add wave -noupdate -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HWRITE
|
||||
add wave -noupdate -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HADDR
|
||||
add wave -noupdate -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/Flush
|
||||
add wave -noupdate -group ifu -expand -group bus -color Gold /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/CurrState
|
||||
add wave -noupdate -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HRDATA
|
||||
add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/Stall
|
||||
add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/FlushStage
|
||||
add wave -noupdate -group ifu -expand -group icache -color Gold /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CurrState
|
||||
|
|
@ -666,27 +709,9 @@ add wave -noupdate -group wfi /testbench/dut/core/priv/priv/pmd/STATUS_TW
|
|||
add wave -noupdate -group wfi /testbench/dut/core/priv/priv/pmd/PrivilegeModeW
|
||||
add wave -noupdate -group wfi /testbench/dut/core/priv/priv/pmd/wfi/WFICount
|
||||
add wave -noupdate -group wfi /testbench/dut/core/priv/priv/pmd/WFITimeoutM
|
||||
add wave -noupdate /testbench/loggers/clk
|
||||
add wave -noupdate /testbench/dut/core/ifu/bus/icache/icache/LRUWriteEn
|
||||
add wave -noupdate /testbench/dut/core/ifu/bus/icache/icache/FlushStage
|
||||
add wave -noupdate /testbench/dut/core/ifu/bus/icache/icache/Stall
|
||||
add wave -noupdate /testbench/loggers/ICacheLogger/Enable
|
||||
add wave -noupdate /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CurrState
|
||||
add wave -noupdate /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/CacheEn
|
||||
add wave -noupdate /testbench/dut/core/ifu/bus/icache/icache/LRUWriteEn
|
||||
add wave -noupdate /testbench/dut/core/ifu/bus/icache/icache/FlushStage
|
||||
add wave -noupdate /testbench/dut/core/ifu/bus/icache/icache/CacheEn
|
||||
add wave -noupdate /testbench/dut/core/ifu/CacheableF
|
||||
add wave -noupdate /testbench/loggers/BeginSample
|
||||
add wave -noupdate /testbench/loggers/StartSample
|
||||
add wave -noupdate /testbench/loggers/reset
|
||||
add wave -noupdate -radix ascii /testbench/loggers/TEST
|
||||
add wave -noupdate /testbench/dut/core/fpu/fpu/fctrl/IllegalFPUInstrD
|
||||
add wave -noupdate /testbench/dut/core/fpu/fpu/fctrl/STATUS_FS
|
||||
add wave -noupdate /testbench/dut/core/priv/priv/csr/csrsr/STATUS_FS_INT
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 4} {172636 ns} 1} {{Cursor 4} {111958 ns} 0} {{Cursor 3} {152766 ns} 1}
|
||||
quietly wave cursor active 2
|
||||
WaveRestoreCursors {{Cursor 4} {39144 ns} 1} {{Cursor 4} {33684 ns} 1} {{Cursor 3} {39145 ns} 0}
|
||||
quietly wave cursor active 3
|
||||
configure wave -namecolwidth 250
|
||||
configure wave -valuecolwidth 194
|
||||
configure wave -justifyvalue left
|
||||
|
|
@ -701,4 +726,4 @@ configure wave -griddelta 40
|
|||
configure wave -timeline 0
|
||||
configure wave -timelineunits ns
|
||||
update
|
||||
WaveRestoreZoom {37879604 ns} {38203328 ns}
|
||||
WaveRestoreZoom {39053 ns} {39217 ns}
|
||||
|
|
|
|||
14
src/cache/cache.sv
vendored
14
src/cache/cache.sv
vendored
|
|
@ -175,10 +175,16 @@ module cache import cvw::*; #(parameter cvw_t P,
|
|||
logic [LINELEN/8-1:0] DemuxedByteMask, FetchBufferByteSel;
|
||||
|
||||
// Adjust byte mask from word to cache line
|
||||
onehotdecoder #(LOGCWPL) adrdec(.bin(PAdr[LOGCWPL+LOGLLENBYTES-1:LOGLLENBYTES]), .decoded(MemPAdrDecoded));
|
||||
for(index = 0; index < 2**LOGCWPL; index++) begin
|
||||
assign DemuxedByteMask[(index+1)*(WORDLEN/8)-1:index*(WORDLEN/8)] = MemPAdrDecoded[index] ? ByteMask : '0;
|
||||
end
|
||||
|
||||
localparam CACHEMUXINVERALPERLINE = LINELEN/MUXINTERVAL;// Number of words in cache line
|
||||
localparam LOGMIPL = $clog2(CACHEMUXINVERALPERLINE);// Log2 of ^
|
||||
|
||||
logic [LINELEN/8-1:0] BlankByteMask;
|
||||
assign BlankByteMask[WORDLEN/8-1:0] = ByteMask;
|
||||
assign BlankByteMask[LINELEN/8-1:WORDLEN/8] = '0;
|
||||
|
||||
assign DemuxedByteMask = BlankByteMask << ((MUXINTERVAL/8) * WordOffsetAddr);
|
||||
|
||||
assign FetchBufferByteSel = SetValid & ~SetDirty ? '1 : ~DemuxedByteMask; // If load miss set all muxes to 1.
|
||||
|
||||
// Merge write data into fetched cache line for store miss
|
||||
|
|
|
|||
|
|
@ -37,7 +37,6 @@ package cvw;
|
|||
`include "BranchPredictorType.vh"
|
||||
|
||||
typedef struct packed {
|
||||
logic FPGA; // Modifications to tare
|
||||
int XLEN; // Machine width (32 or 64)
|
||||
logic IEEE754; // IEEE754 NaN handling (0 = use RISC-V NaN propagation instead)
|
||||
int MISA; // Machine Instruction Set Architecture
|
||||
|
|
@ -59,6 +58,7 @@ typedef struct packed {
|
|||
logic ZICBOM_SUPPORTED;
|
||||
logic ZICBOZ_SUPPORTED;
|
||||
logic ZICBOP_SUPPORTED;
|
||||
logic ZICCLSM_SUPPORTED;
|
||||
logic SVPBMT_SUPPORTED;
|
||||
logic SVNAPOT_SUPPORTED;
|
||||
logic SVINVAL_SUPPORTED;
|
||||
|
|
@ -107,9 +107,11 @@ typedef struct packed {
|
|||
logic BOOTROM_SUPPORTED;
|
||||
logic [63:0] BOOTROM_BASE;
|
||||
logic [63:0] BOOTROM_RANGE;
|
||||
logic BOOTROM_PRELOAD;
|
||||
logic UNCORE_RAM_SUPPORTED;
|
||||
logic [63:0] UNCORE_RAM_BASE;
|
||||
logic [63:0] UNCORE_RAM_RANGE;
|
||||
logic UNCORE_RAM_PRELOAD;
|
||||
logic EXT_MEM_SUPPORTED;
|
||||
logic [63:0] EXT_MEM_BASE;
|
||||
logic [63:0] EXT_MEM_RANGE;
|
||||
|
|
|
|||
|
|
@ -113,7 +113,7 @@ module ahbcacheinterface #(
|
|||
|
||||
// *** bummer need a second byte mask for bus as it is AHBW rather than LLEN.
|
||||
// probably can merge by muxing PAdrM's LLEN/8-1 index bit based on HTRANS being != 0.
|
||||
swbytemask #(AHBW) busswbytemask(.Size(HSIZE), .Adr(HADDR[$clog2(AHBW/8)-1:0]), .ByteMask(BusByteMaskM));
|
||||
swbytemask #(AHBW) busswbytemask(.Size(HSIZE), .Adr(HADDR[$clog2(AHBW/8)-1:0]), .ByteMask(BusByteMaskM), .ByteMaskExtended());
|
||||
|
||||
flopen #(AHBW/8) HWSTRBReg(HCLK, HREADY, BusByteMaskM[AHBW/8-1:0], HWSTRB);
|
||||
|
||||
|
|
|
|||
190
src/lsu/align.sv
Normal file
190
src/lsu/align.sv
Normal file
|
|
@ -0,0 +1,190 @@
|
|||
///////////////////////////////////////////
|
||||
// spill.sv
|
||||
//
|
||||
// Written: Rose Thompson ross1728@gmail.com
|
||||
// Created: 26 October 2023
|
||||
// Modified: 26 October 2023
|
||||
//
|
||||
// Purpose: This module implements native alignment support for the Zicclsm extension
|
||||
// It is simlar to the IFU's spill module and probably could be merged together with
|
||||
// some effort.
|
||||
//
|
||||
// Documentation: RISC-V System on Chip Design Chapter 11 (Figure 11.5)
|
||||
//
|
||||
// A component of the CORE-V-WALLY configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
module align import cvw::*; #(parameter cvw_t P) (
|
||||
input logic clk,
|
||||
input logic reset,
|
||||
input logic StallM, FlushM,
|
||||
input logic [P.XLEN-1:0] IEUAdrM, // 2 byte aligned PC in Fetch stage
|
||||
input logic [P.XLEN-1:0] IEUAdrE, // The next IEUAdrM
|
||||
input logic [2:0] Funct3M, // Size of memory operation
|
||||
input logic [1:0] MemRWM,
|
||||
input logic CacheableM,
|
||||
input logic [P.LLEN*2-1:0]DCacheReadDataWordM, // Instruction from the IROM, I$, or bus. Used to check if the instruction if compressed
|
||||
input logic CacheBusHPWTStall, // I$ or bus are stalled. Transition to second fetch of spill after the first is fetched
|
||||
input logic DTLBMissM, // ITLB miss, ignore memory request
|
||||
input logic DataUpdateDAM, // ITLB miss, ignore memory request
|
||||
|
||||
input logic [(P.LLEN-1)/8:0] ByteMaskM,
|
||||
input logic [(P.LLEN-1)/8:0] ByteMaskExtendedM,
|
||||
input logic [P.LLEN-1:0] LSUWriteDataM,
|
||||
|
||||
output logic [(P.LLEN*2-1)/8:0] ByteMaskSpillM,
|
||||
output logic [P.LLEN*2-1:0] LSUWriteDataSpillM,
|
||||
|
||||
output logic [P.XLEN-1:0] IEUAdrSpillE, // The next PCF for one of the two memory addresses of the spill
|
||||
output logic [P.XLEN-1:0] IEUAdrSpillM, // IEUAdrM for one of the two memory addresses of the spill
|
||||
output logic SelSpillE, // During the transition between the two spill operations, the IFU should stall the pipeline
|
||||
output logic [1:0] MemRWSpillM,
|
||||
output logic SelStoreDelay, //*** this is bad. really don't like moving this outside
|
||||
output logic [P.LLEN-1:0] DCacheReadDataWordSpillM, // The final 32 bit instruction after merging the two spilled fetches into 1 instruction
|
||||
output logic SpillStallM);
|
||||
|
||||
localparam LLENINBYTES = P.LLEN/8;
|
||||
localparam OFFSET_BIT_POS = $clog2(P.DCACHE_LINELENINBITS/8);
|
||||
// Spill threshold occurs when all the cache offset PC bits are 1 (except [0]). Without a cache this is just PCF[1]
|
||||
typedef enum logic [1:0] {STATE_READY, STATE_SPILL, STATE_STORE_DELAY} statetype;
|
||||
|
||||
statetype CurrState, NextState;
|
||||
logic TakeSpillM;
|
||||
logic SpillM;
|
||||
logic SelSpillM;
|
||||
logic SpillSaveM;
|
||||
logic [P.LLEN-1:0] ReadDataWordFirstHalfM;
|
||||
logic MisalignedM;
|
||||
logic [P.LLEN*2-1:0] ReadDataWordSpillAllM;
|
||||
logic [P.LLEN*2-1:0] ReadDataWordSpillShiftedM;
|
||||
|
||||
logic [P.XLEN-1:0] IEUAdrIncrementM;
|
||||
|
||||
logic [(P.LLEN-1)*2/8:0] ByteMaskSaveM;
|
||||
logic [(P.LLEN-1)*2/8:0] ByteMaskMuxM;
|
||||
logic SaveByteMask;
|
||||
logic HalfMisalignedM, WordMisalignedM;
|
||||
logic [OFFSET_BIT_POS-1:$clog2(LLENINBYTES)] WordOffsetM;
|
||||
logic [$clog2(LLENINBYTES)-1:0] ByteOffsetM;
|
||||
logic HalfSpillM, WordSpillM;
|
||||
logic [$clog2(LLENINBYTES)-1:0] AccessByteOffsetM;
|
||||
|
||||
/* verilator lint_off WIDTHEXPAND */
|
||||
assign IEUAdrIncrementM = IEUAdrM + LLENINBYTES;
|
||||
/* verilator lint_on WIDTHEXPAND */
|
||||
mux2 #(P.XLEN) ieuadrspillemux(.d0(IEUAdrE), .d1(IEUAdrIncrementM), .s(SelSpillE), .y(IEUAdrSpillE));
|
||||
mux2 #(P.XLEN) ieuadrspillmmux(.d0(IEUAdrM), .d1(IEUAdrIncrementM), .s(SelSpillM), .y(IEUAdrSpillM));
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
// Detect spill
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// spill detection in lsu is more complex than ifu, depends on 3 factors
|
||||
// 1) operation size
|
||||
// 2) offset
|
||||
// 3) access location within the cacheline
|
||||
|
||||
assign {WordOffsetM, ByteOffsetM} = IEUAdrM[OFFSET_BIT_POS-1:0];
|
||||
|
||||
always_comb begin
|
||||
case (Funct3M[1:0])
|
||||
2'b00: AccessByteOffsetM = '0; // byte access
|
||||
2'b01: AccessByteOffsetM = {2'b00, ByteOffsetM[0]}; // half access
|
||||
2'b10: AccessByteOffsetM = {1'b0, ByteOffsetM[1:0]}; // word access
|
||||
2'b11: AccessByteOffsetM = ByteOffsetM; // double access
|
||||
default: AccessByteOffsetM = ByteOffsetM;
|
||||
endcase
|
||||
end
|
||||
|
||||
// compute misalignement
|
||||
assign HalfMisalignedM = (ByteOffsetM[0] != '0) & Funct3M[1:0] == 2'b01;
|
||||
assign WordMisalignedM = (ByteOffsetM[1:0] != '0) & Funct3M[1:0] == 2'b10;
|
||||
assign HalfSpillM = (IEUAdrM[OFFSET_BIT_POS-1:1] == '1) & HalfMisalignedM;
|
||||
assign WordSpillM = (IEUAdrM[OFFSET_BIT_POS-1:2] == '1) & WordMisalignedM;
|
||||
|
||||
if(P.LLEN == 64) begin
|
||||
logic DoubleSpillM;
|
||||
logic DoubleMisalignedM;
|
||||
assign DoubleMisalignedM = (ByteOffsetM[2:0] != '0) & Funct3M[1:0] == 2'b11;
|
||||
assign DoubleSpillM = (IEUAdrM[OFFSET_BIT_POS-1:3] == '1) & DoubleMisalignedM;
|
||||
assign MisalignedM = HalfMisalignedM | WordMisalignedM | DoubleMisalignedM;
|
||||
assign SpillM = (|MemRWM) & CacheableM & (HalfSpillM | WordSpillM | DoubleSpillM);
|
||||
end else begin
|
||||
assign SpillM = (|MemRWM) & CacheableM & (HalfSpillM | WordSpillM);
|
||||
assign MisalignedM = HalfMisalignedM | WordMisalignedM;
|
||||
end
|
||||
|
||||
// align by shifting
|
||||
// Don't take the spill if there is a stall, TLB miss, or hardware update to the D/A bits
|
||||
assign TakeSpillM = SpillM & ~CacheBusHPWTStall & ~(DTLBMissM | (P.SVADU_SUPPORTED & DataUpdateDAM));
|
||||
|
||||
always_ff @(posedge clk)
|
||||
if (reset | FlushM) CurrState <= #1 STATE_READY;
|
||||
else CurrState <= #1 NextState;
|
||||
|
||||
always_comb begin
|
||||
case (CurrState)
|
||||
STATE_READY: if (TakeSpillM & ~MemRWM[0]) NextState = STATE_SPILL;
|
||||
else if(TakeSpillM & MemRWM[0])NextState = STATE_STORE_DELAY;
|
||||
else NextState = STATE_READY;
|
||||
STATE_SPILL: if(StallM) NextState = STATE_SPILL;
|
||||
else NextState = STATE_READY;
|
||||
STATE_STORE_DELAY: NextState = STATE_SPILL;
|
||||
default: NextState = STATE_READY;
|
||||
endcase
|
||||
end
|
||||
|
||||
assign SelSpillM = (CurrState == STATE_SPILL | CurrState == STATE_STORE_DELAY);
|
||||
assign SelSpillE = (CurrState == STATE_READY & TakeSpillM) | (CurrState == STATE_SPILL & CacheBusHPWTStall) | (CurrState == STATE_STORE_DELAY);
|
||||
assign SaveByteMask = (CurrState == STATE_READY & TakeSpillM);
|
||||
assign SpillSaveM = (CurrState == STATE_READY) & TakeSpillM & ~FlushM;
|
||||
assign SelStoreDelay = (CurrState == STATE_STORE_DELAY); // *** Can this be merged into the PreLSURWM logic?
|
||||
assign SpillStallM = SelSpillE | CurrState == STATE_STORE_DELAY;
|
||||
mux2 #(2) memrwmux(MemRWM, 2'b00, SelStoreDelay, MemRWSpillM);
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
// Merge spilled data
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// save the first native word
|
||||
flopenr #(P.LLEN) SpillDataReg(clk, reset, SpillSaveM, DCacheReadDataWordM[P.LLEN-1:0], ReadDataWordFirstHalfM);
|
||||
|
||||
// merge together
|
||||
mux2 #(2*P.LLEN) postspillmux(DCacheReadDataWordM, {DCacheReadDataWordM[P.LLEN-1:0], ReadDataWordFirstHalfM}, SelSpillM, ReadDataWordSpillAllM);
|
||||
|
||||
|
||||
// shifter (4:1 mux for 32 bit, 8:1 mux for 64 bit)
|
||||
// 8 * is for shifting by bytes not bits
|
||||
assign ReadDataWordSpillShiftedM = ReadDataWordSpillAllM >> (MisalignedM ? 8 * AccessByteOffsetM : '0);
|
||||
assign DCacheReadDataWordSpillM = ReadDataWordSpillShiftedM[P.LLEN-1:0];
|
||||
|
||||
// write path. Also has the 8:1 shifter muxing for the byteoffset
|
||||
// then it also has the mux to select when a spill occurs
|
||||
logic [P.LLEN*3-1:0] LSUWriteDataShiftedExtM; // *** RT: Find a better way. I've extending in both directions so we don't shift in zeros. The cache expects the writedata to not have any zero data, but instead replicated data.
|
||||
|
||||
assign LSUWriteDataShiftedExtM = {LSUWriteDataM, LSUWriteDataM, LSUWriteDataM} << (MisalignedM ? 8 * AccessByteOffsetM : '0);
|
||||
assign LSUWriteDataSpillM = LSUWriteDataShiftedExtM[P.LLEN*3-1:P.LLEN];
|
||||
|
||||
mux3 #(2*P.LLEN/8) bytemaskspillmux(ByteMaskMuxM, // no spill
|
||||
{{{P.LLEN/8}{1'b0}}, ByteMaskM}, // spill, first half
|
||||
{{{P.LLEN/8}{1'b0}}, ByteMaskMuxM[P.LLEN*2/8-1:P.LLEN/8]}, // spill, second half
|
||||
{SelSpillM, SelSpillE}, ByteMaskSpillM);
|
||||
|
||||
flopenr #(P.LLEN*2/8) bytemaskreg(clk, reset, SaveByteMask, {ByteMaskExtendedM, ByteMaskM}, ByteMaskSaveM);
|
||||
mux2 #(P.LLEN*2/8) bytemasksavemux({ByteMaskExtendedM, ByteMaskM}, ByteMaskSaveM, SelSpillM, ByteMaskMuxM);
|
||||
endmodule
|
||||
|
|
@ -92,6 +92,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
|
|||
input var logic [7:0] PMPCFG_ARRAY_REGW[P.PMP_ENTRIES-1:0], // PMP configuration from privileged unit
|
||||
input var logic [P.PA_BITS-3:0] PMPADDR_ARRAY_REGW[P.PMP_ENTRIES-1:0] // PMP address from privileged unit
|
||||
);
|
||||
localparam MISALIGN_SUPPORT = P.ZICCLSM_SUPPORTED & P.DCACHE_SUPPORTED;
|
||||
|
||||
logic [P.XLEN+1:0] IEUAdrExtM; // Memory stage address zero-extended to PA_BITS or XLEN whichever is longer
|
||||
logic [P.XLEN+1:0] IEUAdrExtE; // Execution stage address zero-extended to PA_BITS or XLEN whichever is longer
|
||||
|
|
@ -108,13 +109,20 @@ module lsu import cvw::*; #(parameter cvw_t P) (
|
|||
|
||||
logic BusStall; // Bus interface busy with multicycle operation
|
||||
logic HPTWStall; // HPTW busy with multicycle operation
|
||||
logic CacheBusHPWTStall; // Cache, bus, or hptw is requesting a stall
|
||||
logic SelSpillE; // Align logic detected a spill and needs to stall
|
||||
|
||||
logic CacheableM; // PMA indicates memory address is cacheable
|
||||
logic BusCommittedM; // Bus memory operation in flight, delay interrupts
|
||||
logic DCacheCommittedM; // D$ memory operation started, delay interrupts
|
||||
|
||||
logic [P.LLEN-1:0] DTIMReadDataWordM; // DTIM read data
|
||||
logic [P.LLEN-1:0] DCacheReadDataWordM; // D$ read data
|
||||
/* verilator lint_off WIDTHEXPAND */
|
||||
logic [(MISALIGN_SUPPORT+1)*P.LLEN-1:0] DCacheReadDataWordM; // D$ read data
|
||||
logic [(MISALIGN_SUPPORT+1)*P.LLEN-1:0] LSUWriteDataSpillM; // Final write data
|
||||
logic [((MISALIGN_SUPPORT+1)*P.LLEN-1)/8:0] ByteMaskSpillM; // Selects which bytes within a word to write
|
||||
/* verilator lint_on WIDTHEXPAND */
|
||||
logic [P.LLEN-1:0] DCacheReadDataWordSpillM; // D$ read data
|
||||
logic [P.LLEN-1:0] ReadDataWordMuxM; // DTIM or D$ read data
|
||||
logic [P.LLEN-1:0] LittleEndianReadDataWordM; // Endian-swapped read data
|
||||
logic [P.LLEN-1:0] ReadDataWordM; // Read data before subword selection
|
||||
|
|
@ -126,7 +134,11 @@ module lsu import cvw::*; #(parameter cvw_t P) (
|
|||
logic [P.LLEN-1:0] LittleEndianWriteDataM; // Ending-swapped write data
|
||||
logic [P.LLEN-1:0] LSUWriteDataM; // Final write data
|
||||
logic [(P.LLEN-1)/8:0] ByteMaskM; // Selects which bytes within a word to write
|
||||
|
||||
logic [(P.LLEN-1)/8:0] ByteMaskExtendedM; // Selects which bytes within a word to write
|
||||
logic [1:0] MemRWSpillM;
|
||||
logic SpillStallM;
|
||||
logic SelStoreDelay;
|
||||
|
||||
logic DTLBMissM; // DTLB miss causes HPTW walk
|
||||
logic DTLBWriteM; // Writes PTE and PageType to DTLB
|
||||
logic DataUpdateDAM; // DTLB hit needs to update dirty or access bits
|
||||
|
|
@ -142,8 +154,26 @@ module lsu import cvw::*; #(parameter cvw_t P) (
|
|||
/////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
flopenrc #(P.XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, IEUAdrM);
|
||||
assign IEUAdrExtM = {2'b00, IEUAdrM};
|
||||
assign IEUAdrExtE = {2'b00, IEUAdrE};
|
||||
if(MISALIGN_SUPPORT) begin : ziccslm_align
|
||||
logic [P.XLEN-1:0] IEUAdrSpillE, IEUAdrSpillM;
|
||||
align #(P) align(.clk, .reset, .StallM, .FlushM, .IEUAdrE, .IEUAdrM, .Funct3M,
|
||||
.MemRWM, .CacheableM,
|
||||
.DCacheReadDataWordM, .CacheBusHPWTStall, .DTLBMissM, .DataUpdateDAM,
|
||||
.ByteMaskM, .ByteMaskExtendedM, .LSUWriteDataM, .ByteMaskSpillM, .LSUWriteDataSpillM,
|
||||
.IEUAdrSpillE, .IEUAdrSpillM, .SelSpillE, .MemRWSpillM, .DCacheReadDataWordSpillM, .SpillStallM,
|
||||
.SelStoreDelay);
|
||||
assign IEUAdrExtM = {2'b00, IEUAdrSpillM};
|
||||
assign IEUAdrExtE = {2'b00, IEUAdrSpillE};
|
||||
end else begin : no_ziccslm_align
|
||||
assign IEUAdrExtM = {2'b00, IEUAdrM};
|
||||
assign IEUAdrExtE = {2'b00, IEUAdrE};
|
||||
assign SelSpillE = '0;
|
||||
assign DCacheReadDataWordSpillM = DCacheReadDataWordM;
|
||||
assign ByteMaskSpillM = ByteMaskM;
|
||||
assign LSUWriteDataSpillM = LSUWriteDataM;
|
||||
assign MemRWSpillM = MemRWM;
|
||||
assign {SpillStallM, SelStoreDelay} = '0;
|
||||
end
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////////////////
|
||||
// HPTW (only needed if VM supported)
|
||||
|
|
@ -180,7 +210,8 @@ module lsu import cvw::*; #(parameter cvw_t P) (
|
|||
// the trap module.
|
||||
assign CommittedM = SelHPTW | DCacheCommittedM | BusCommittedM;
|
||||
assign GatedStallW = StallW & ~SelHPTW;
|
||||
assign LSUStallM = DCacheStallM | HPTWStall | BusStall;
|
||||
assign CacheBusHPWTStall = DCacheStallM | HPTWStall | BusStall;
|
||||
assign LSUStallM = CacheBusHPWTStall | SpillStallM;
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////////////////
|
||||
// MMU and misalignment fault logic required if privileged unit exists
|
||||
|
|
@ -234,9 +265,10 @@ module lsu import cvw::*; #(parameter cvw_t P) (
|
|||
assign DTIMMemRWM = SelDTIM & ~IgnoreRequestTLB ? LSURWM : '0;
|
||||
// **** fix ReadDataWordM to be LLEN. ByteMask is wrong length.
|
||||
// **** create config to support DTIM with floating point.
|
||||
// Add support for cboz
|
||||
dtim #(P) dtim(.clk, .ce(~GatedStallW), .MemRWM(DTIMMemRWM),
|
||||
.DTIMAdr, .FlushW, .WriteDataM(LSUWriteDataM),
|
||||
.ReadDataWordM(DTIMReadDataWordM[P.LLEN-1:0]), .ByteMaskM(ByteMaskM[P.LLEN/8-1:0]));
|
||||
.ReadDataWordM(DTIMReadDataWordM[P.LLEN-1:0]), .ByteMaskM(ByteMaskM));
|
||||
end else begin
|
||||
end
|
||||
if (P.BUS_SUPPORTED) begin : bus
|
||||
|
|
@ -247,6 +279,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
|
|||
localparam AHBWLOGBWPL = $clog2(BEATSPERLINE); // Log2 of ^
|
||||
localparam LINELEN = P.DCACHE_LINELENINBITS; // Number of bits in cacheline
|
||||
localparam LLENPOVERAHBW = P.LLEN / P.AHBW; // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation)
|
||||
localparam CACHEWORDLEN = P.ZICCLSM_SUPPORTED ? 2*P.LLEN : P.LLEN; // Width of the cache's input and output data buses. Misaligned doubles width for fast access
|
||||
|
||||
logic [LINELEN-1:0] FetchBuffer; // Temporary buffer to hold partially fetched cacheline
|
||||
logic [P.PA_BITS-1:0] DCacheBusAdr; // Cacheline address to fetch or writeback.
|
||||
|
|
@ -268,14 +301,12 @@ module lsu import cvw::*; #(parameter cvw_t P) (
|
|||
assign CacheAtomicM = CacheableM & ~SelDTIM ? LSUAtomicM : '0;
|
||||
assign FlushDCache = FlushDCacheM & ~(SelHPTW);
|
||||
|
||||
// *** need RT to add support for CMOpM and LSUPrefetchM (DH 7/2/23)
|
||||
// *** prefetch can just act as a read operation
|
||||
cache #(.P(P), .PA_BITS(P.PA_BITS), .XLEN(P.XLEN), .LINELEN(P.DCACHE_LINELENINBITS), .NUMLINES(P.DCACHE_WAYSIZEINBYTES*8/LINELEN),
|
||||
.NUMWAYS(P.DCACHE_NUMWAYS), .LOGBWPL(LLENLOGBWPL), .WORDLEN(P.LLEN), .MUXINTERVAL(P.LLEN), .READ_ONLY_CACHE(0)) dcache(
|
||||
.clk, .reset, .Stall(GatedStallW), .SelBusBeat, .FlushStage(FlushW | IgnoreRequestTLB), .CacheRW(CacheRWM), .CacheAtomic(CacheAtomicM),
|
||||
.FlushCache(FlushDCache), .NextSet(IEUAdrE[11:0]), .PAdr(PAdrM),
|
||||
.ByteMask(ByteMaskM), .BeatCount(BeatCount[AHBWLOGBWPL-1:AHBWLOGBWPL-LLENLOGBWPL]),
|
||||
.CacheWriteData(LSUWriteDataM), .SelHPTW,
|
||||
.NUMWAYS(P.DCACHE_NUMWAYS), .LOGBWPL(LLENLOGBWPL), .WORDLEN(CACHEWORDLEN), .MUXINTERVAL(P.LLEN), .READ_ONLY_CACHE(0)) dcache(
|
||||
.clk, .reset, .Stall(GatedStallW & ~SelSpillE), .SelBusBeat, .FlushStage(FlushW | IgnoreRequestTLB), .CacheRW(SelStoreDelay ? 2'b00 : CacheRWM), .CacheAtomic(CacheAtomicM),
|
||||
.FlushCache(FlushDCache), .NextSet(IEUAdrExtE[11:0]), .PAdr(PAdrM),
|
||||
.ByteMask(ByteMaskSpillM), .BeatCount(BeatCount[AHBWLOGBWPL-1:AHBWLOGBWPL-LLENLOGBWPL]),
|
||||
.CacheWriteData(LSUWriteDataSpillM), .SelHPTW,
|
||||
.CacheStall, .CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess),
|
||||
.CacheCommitted(DCacheCommittedM),
|
||||
.CacheBusAdr(DCacheBusAdr), .ReadDataWord(DCacheReadDataWordM),
|
||||
|
|
@ -285,11 +316,12 @@ module lsu import cvw::*; #(parameter cvw_t P) (
|
|||
assign DCacheStallM = CacheStall & ~IgnoreRequestTLB;
|
||||
assign CacheBusRW = CacheBusRWTemp;
|
||||
|
||||
// *** add support for cboz
|
||||
ahbcacheinterface #(.AHBW(P.AHBW), .LLEN(P.LLEN), .PA_BITS(P.PA_BITS), .BEATSPERLINE(BEATSPERLINE), .AHBWLOGBWPL(AHBWLOGBWPL), .LINELEN(LINELEN), .LLENPOVERAHBW(LLENPOVERAHBW), .READ_ONLY_CACHE(0)) ahbcacheinterface(
|
||||
.HCLK(clk), .HRESETn(~reset), .Flush(FlushW | IgnoreRequestTLB),
|
||||
.HRDATA, .HWDATA(LSUHWDATA), .HWSTRB(LSUHWSTRB),
|
||||
.HSIZE(LSUHSIZE), .HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HREADY(LSUHREADY),
|
||||
.BeatCount, .SelBusBeat, .CacheReadDataWordM(DCacheReadDataWordM), .WriteDataM(LSUWriteDataM),
|
||||
.BeatCount, .SelBusBeat, .CacheReadDataWordM(DCacheReadDataWordM[P.LLEN-1:0]), .WriteDataM(LSUWriteDataM),
|
||||
.Funct3(LSUFunct3M), .HADDR(LSUHADDR), .CacheBusAdr(DCacheBusAdr), .CacheBusRW, .CacheableOrFlushCacheM,
|
||||
.CacheBusAck(DCacheBusAck), .FetchBuffer, .PAdr(PAdrM),
|
||||
.Cacheable(CacheableOrFlushCacheM), .BusRW, .Stall(GatedStallW),
|
||||
|
|
@ -299,7 +331,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
|
|||
// Uncache bus access may be smaller width than LLEN. Duplicate LLENPOVERAHBW times.
|
||||
// *** DTIMReadDataWordM should be increased to LLEN.
|
||||
// pma should generate exception for LLEN read to periph.
|
||||
mux3 #(P.LLEN) UnCachedDataMux(.d0(DCacheReadDataWordM), .d1({LLENPOVERAHBW{FetchBuffer[P.XLEN-1:0]}}),
|
||||
mux3 #(P.LLEN) UnCachedDataMux(.d0(DCacheReadDataWordSpillM), .d1({LLENPOVERAHBW{FetchBuffer[P.XLEN-1:0]}}),
|
||||
.d2({{P.LLEN-P.XLEN{1'b0}}, DTIMReadDataWordM[P.XLEN-1:0]}),
|
||||
.s({SelDTIM, ~(CacheableOrFlushCacheM)}), .y(ReadDataWordMuxM));
|
||||
end else begin : passthrough // No Cache, use simple ahbinterface instad of ahbcacheinterface
|
||||
|
|
@ -312,7 +344,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
|
|||
|
||||
ahbinterface #(P.XLEN, 1) ahbinterface(.HCLK(clk), .HRESETn(~reset), .Flush(FlushW), .HREADY(LSUHREADY),
|
||||
.HRDATA(HRDATA), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HWDATA(LSUHWDATA),
|
||||
.HWSTRB(LSUHWSTRB), .BusRW, .ByteMask(ByteMaskM[P.XLEN/8-1:0]), .WriteData(LSUWriteDataM[P.XLEN-1:0]),
|
||||
.HWSTRB(LSUHWSTRB), .BusRW, .ByteMask(ByteMaskM), .WriteData(LSUWriteDataM[P.XLEN-1:0]),
|
||||
.Stall(GatedStallW), .BusStall, .BusCommitted(BusCommittedM), .FetchBuffer(FetchBuffer));
|
||||
|
||||
// Mux between the 2 sources of read data, 0: Bus, 1: DTIM
|
||||
|
|
@ -354,7 +386,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
|
|||
subwordwrite #(P.LLEN) subwordwrite(.LSUFunct3M, .IMAFWriteDataM, .LittleEndianWriteDataM);
|
||||
|
||||
// Compute byte masks
|
||||
swbytemask #(P.LLEN) swbytemask(.Size(LSUFunct3M), .Adr(PAdrM[$clog2(P.LLEN/8)-1:0]), .ByteMask(ByteMaskM));
|
||||
swbytemask #(P.LLEN, P.ZICCLSM_SUPPORTED) swbytemask(.Size(LSUFunct3M), .Adr(PAdrM[$clog2(P.LLEN/8)-1:0]), .ByteMask(ByteMaskM), .ByteMaskExtended(ByteMaskExtendedM));
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////////////////
|
||||
// MW Pipeline Register
|
||||
|
|
|
|||
|
|
@ -27,13 +27,22 @@
|
|||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
module swbytemask #(parameter WORDLEN)(
|
||||
module swbytemask #(parameter WORDLEN, EXTEND = 0)(
|
||||
input logic [2:0] Size,
|
||||
input logic [$clog2(WORDLEN/8)-1:0] Adr,
|
||||
output logic [WORDLEN/8-1:0] ByteMask
|
||||
output logic [WORDLEN/8-1:0] ByteMask,
|
||||
output logic [WORDLEN/8-1:0] ByteMaskExtended
|
||||
);
|
||||
|
||||
assign ByteMask =(('d2**('d2**Size))-'d1) << Adr; // 'd2 means 2, but stops Design Compiler from complaining about signed to unsigned conversion
|
||||
if(EXTEND) begin
|
||||
logic [WORDLEN*2/8-1:0] ExtendedByteMask;
|
||||
// 'd2 means 2, but stops Design Compiler from complaining about signed to unsigned conversion
|
||||
assign ExtendedByteMask = (('d2**('d2**Size))-'d1) << Adr;
|
||||
assign ByteMask = ExtendedByteMask[WORDLEN/8-1:0];
|
||||
assign ByteMaskExtended = ExtendedByteMask[WORDLEN*2/8-1:WORDLEN/8];
|
||||
end else begin
|
||||
assign ByteMask = (('d2**('d2**Size))-'d1) << Adr;
|
||||
assign ByteMaskExtended = '0;
|
||||
end
|
||||
|
||||
/* Equivalent to the following
|
||||
|
||||
|
|
|
|||
|
|
@ -138,8 +138,8 @@ module mmu import cvw::*; #(parameter cvw_t P,
|
|||
2'b10: DataMisalignedM = VAdr[1] | VAdr[0]; // lw, sw, flw, fsw, lwu
|
||||
2'b11: DataMisalignedM = |VAdr[2:0]; // ld, sd, fld, fsd
|
||||
endcase
|
||||
assign LoadMisalignedFaultM = DataMisalignedM & ReadNoAmoAccessM;
|
||||
assign StoreAmoMisalignedFaultM = DataMisalignedM & WriteAccessM;
|
||||
assign LoadMisalignedFaultM = DataMisalignedM & ReadNoAmoAccessM & ~(P.ZICCLSM_SUPPORTED & Cacheable);
|
||||
assign StoreAmoMisalignedFaultM = DataMisalignedM & WriteAccessM & ~(P.ZICCLSM_SUPPORTED & Cacheable);
|
||||
|
||||
// Specify which type of page fault is occurring
|
||||
assign InstrPageFaultF = TLBPageFault & ExecuteAccessF;
|
||||
|
|
|
|||
|
|
@ -29,7 +29,7 @@
|
|||
`define RAM_LATENCY 0
|
||||
|
||||
module ram_ahb import cvw::*; #(parameter cvw_t P,
|
||||
parameter BASE=0, RANGE = 65535) (
|
||||
parameter BASE=0, RANGE = 65535, PRELOAD = 0) (
|
||||
input logic HCLK, HRESETn,
|
||||
input logic HSELRam,
|
||||
input logic [P.PA_BITS-1:0] HADDR,
|
||||
|
|
@ -71,7 +71,7 @@ module ram_ahb import cvw::*; #(parameter cvw_t P,
|
|||
mux2 #(P.PA_BITS) adrmux(HADDR, HADDRD, memwriteD | ~HREADY, RamAddr);
|
||||
|
||||
// single-ported RAM
|
||||
ram1p1rwbe #(.USE_SRAM(P.USE_SRAM), .DEPTH(RANGE/8), .WIDTH(P.XLEN), .PRELOAD_ENABLED(P.FPGA)) memory(.clk(HCLK), .ce(1'b1),
|
||||
ram1p1rwbe #(P.USE_SRAM, RANGE/8, P.XLEN, PRELOAD) memory(.clk(HCLK), .ce(1'b1),
|
||||
.addr(RamAddr[ADDR_WIDTH+OFFSET-1:OFFSET]), .we(memwriteD), .din(HWDATA), .bwe(HWSTRB), .dout(HREADRam));
|
||||
|
||||
// use this to add arbitrary latency to ram. Helps test AHB controller correctness
|
||||
|
|
|
|||
|
|
@ -27,7 +27,7 @@
|
|||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
module rom_ahb import cvw::*; #(parameter cvw_t P,
|
||||
parameter BASE=0, RANGE = 65535) (
|
||||
parameter BASE=0, RANGE = 65535, PRELOAD = 0) (
|
||||
input logic HCLK, HRESETn,
|
||||
input logic HSELRom,
|
||||
input logic [P.PA_BITS-1:0] HADDR,
|
||||
|
|
@ -45,6 +45,6 @@ module rom_ahb import cvw::*; #(parameter cvw_t P,
|
|||
assign HRESPRom = 0; // OK
|
||||
|
||||
// single-ported ROM
|
||||
rom1p1r #(ADDR_WIDTH, P.XLEN, P.FPGA)
|
||||
rom1p1r #(ADDR_WIDTH, P.XLEN, PRELOAD)
|
||||
memory(.clk(HCLK), .ce(1'b1), .addr(HADDR[ADDR_WIDTH+OFFSET-1:OFFSET]), .dout(HREADRom));
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -63,7 +63,7 @@ module uncore import cvw::*; #(parameter cvw_t P)(
|
|||
logic [P.XLEN-1:0] HREADRam, HREADSDC;
|
||||
|
||||
logic [11:0] HSELRegions;
|
||||
logic HSELDTIM, HSELIROM, HSELRam, HSELCLINT, HSELPLIC, HSELGPIO, HSELUART, HSELSDC, HSELSPI;
|
||||
logic HSELDTIM, HSELIROM, HSELRam, HSELCLINT, HSELPLIC, HSELGPIO, HSELUART, HSELSPI;
|
||||
logic HSELDTIMD, HSELIROMD, HSELEXTD, HSELRamD, HSELCLINTD, HSELPLICD, HSELGPIOD, HSELUARTD, HSELSDCD, HSELSPID;
|
||||
logic HRESPRam, HRESPSDC;
|
||||
logic HREADYRam, HRESPSDCD;
|
||||
|
|
@ -91,7 +91,7 @@ module uncore import cvw::*; #(parameter cvw_t P)(
|
|||
adrdecs #(P) adrdecs(HADDR, 1'b1, 1'b1, 1'b1, HSIZE[1:0], HSELRegions);
|
||||
|
||||
// unswizzle HSEL signals
|
||||
assign {HSELDTIM, HSELIROM, HSELEXT, HSELBootRom, HSELRam, HSELCLINT, HSELGPIO, HSELUART, HSELPLIC, HSELSDC, HSELSPI} = HSELRegions[11:1];
|
||||
assign {HSELDTIM, HSELIROM, HSELEXT, HSELBootRom, HSELRam, HSELCLINT, HSELGPIO, HSELUART, HSELPLIC, HSELEXTSDC, HSELSPI} = HSELRegions[11:1];
|
||||
|
||||
// AHB -> APB bridge
|
||||
ahbapbbridge #(P, 5) ahbapbbridge (
|
||||
|
|
@ -102,13 +102,13 @@ module uncore import cvw::*; #(parameter cvw_t P)(
|
|||
|
||||
// on-chip RAM
|
||||
if (P.UNCORE_RAM_SUPPORTED) begin : ram
|
||||
ram_ahb #(.P(P), .BASE(P.UNCORE_RAM_BASE), .RANGE(P.UNCORE_RAM_RANGE)) ram (
|
||||
ram_ahb #(.P(P), .BASE(P.UNCORE_RAM_BASE), .RANGE(P.UNCORE_RAM_RANGE), .PRELOAD(P.UNCORE_RAM_PRELOAD)) ram (
|
||||
.HCLK, .HRESETn, .HSELRam, .HADDR, .HWRITE, .HREADY,
|
||||
.HTRANS, .HWDATA, .HWSTRB, .HREADRam, .HRESPRam, .HREADYRam);
|
||||
end
|
||||
|
||||
if (P.BOOTROM_SUPPORTED) begin : bootrom
|
||||
rom_ahb #(.P(P), .BASE(P.BOOTROM_BASE), .RANGE(P.BOOTROM_RANGE))
|
||||
rom_ahb #(.P(P), .BASE(P.BOOTROM_BASE), .RANGE(P.BOOTROM_RANGE), .PRELOAD(P.BOOTROM_PRELOAD))
|
||||
bootrom(.HCLK, .HRESETn, .HSELRom(HSELBootRom), .HADDR, .HREADY, .HTRANS,
|
||||
.HREADRom(HREADBootRom), .HRESPRom(HRESPBootRom), .HREADYRom(HREADYBootRom));
|
||||
end
|
||||
|
|
|
|||
|
|
@ -267,6 +267,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
|
|||
flopenrc #(1) TrapWReg (clk, reset, 1'b0, ~StallW, TrapM, TrapW);
|
||||
flopenrc #(1) HaltWReg (clk, reset, 1'b0, ~StallW, HaltM, HaltW);
|
||||
|
||||
// **** remove? are these used?
|
||||
flopenrc #(1) IntrFReg (clk, reset, 1'b0, ~StallF, TrapM, IntrF);
|
||||
flopenrc #(1) IntrDReg (clk, reset, FlushD, ~StallD, IntrF, IntrD);
|
||||
flopenrc #(1) IntrEReg (clk, reset, FlushE, ~StallE, IntrD, IntrE);
|
||||
|
|
@ -285,9 +286,9 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
|
|||
assign rvvi.order[0][0] = CSRArray[12'hB02]; // TODO: IMPERAS Should be event order
|
||||
assign rvvi.insn[0][0] = InstrRawW;
|
||||
assign rvvi.pc_rdata[0][0] = PCW;
|
||||
assign rvvi.trap[0][0] = 0; // TODO: IMPERAS TrapW;
|
||||
assign rvvi.trap[0][0] = 0;
|
||||
assign rvvi.halt[0][0] = HaltW;
|
||||
assign rvvi.intr[0][0] = IntrW;
|
||||
assign rvvi.intr[0][0] = 0;
|
||||
assign rvvi.mode[0][0] = PrivilegeModeW;
|
||||
assign rvvi.ixl[0][0] = PrivilegeModeW == 2'b11 ? 2'b10 :
|
||||
PrivilegeModeW == 2'b01 ? STATUS_SXL : STATUS_UXL;
|
||||
|
|
|
|||
|
|
@ -1,132 +0,0 @@
|
|||
///////////////////////////////////////////
|
||||
// sd_top_tb.sv
|
||||
//
|
||||
// Written: Ross Thompson September 20, 2021
|
||||
// Modified:
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// MIT LICENSE
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this
|
||||
// software and associated documentation files (the "Software"), to deal in the Software
|
||||
// without restriction, including without limitation the rights to use, copy, modify, merge,
|
||||
// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
|
||||
// to whom the Software is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or
|
||||
// substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
|
||||
// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
|
||||
// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
|
||||
// OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "wconfig.vh"
|
||||
|
||||
|
||||
module sd_top_tb();
|
||||
|
||||
|
||||
localparam g_COUNT_WIDTH = 8;
|
||||
|
||||
logic a_RST;
|
||||
logic i_SD_CMD;
|
||||
logic o_SD_CMD;
|
||||
logic o_SD_CMD_OE;
|
||||
wire [3:0] i_SD_DAT;
|
||||
logic o_SD_CLK;
|
||||
logic [32:9] i_BLOCK_ADDR;
|
||||
logic [g_COUNT_WIDTH-1:0] i_COUNT_IN_MAX;
|
||||
|
||||
logic o_READY_FOR_READ;
|
||||
logic i_READ_REQUEST;
|
||||
logic [3:0] o_DATA_TO_CORE;
|
||||
logic o_DATA_VALID;
|
||||
logic o_LAST_NIBBLE;
|
||||
logic [4095:0] ReadData;
|
||||
logic o_SD_RESTARTING;
|
||||
logic [2:0] o_ERROR_CODE_Q;
|
||||
logic o_FATAL_ERROR;
|
||||
|
||||
|
||||
|
||||
// Driver
|
||||
wire PAD;
|
||||
|
||||
logic r_CLK;
|
||||
|
||||
|
||||
// clock
|
||||
|
||||
sd_top #(g_COUNT_WIDTH) DUT
|
||||
(.CLK(r_CLK),
|
||||
.a_RST(a_RST),
|
||||
.i_SD_CMD(i_SD_CMD),
|
||||
.o_SD_CMD(o_SD_CMD),
|
||||
.o_SD_CMD_OE(o_SD_CMD_OE),
|
||||
.i_SD_DAT(i_SD_DAT),
|
||||
.o_SD_CLK(o_SD_CLK),
|
||||
.i_BLOCK_ADDR(i_BLOCK_ADDR),
|
||||
.o_READY_FOR_READ(o_READY_FOR_READ),
|
||||
.o_SD_RESTARTING(o_SD_RESTARTING),
|
||||
.o_ERROR_CODE_Q(o_ERROR_CODE_Q),
|
||||
.o_FATAL_ERROR(o_FATAL_ERROR),
|
||||
.i_READ_REQUEST(i_READ_REQUEST),
|
||||
.o_DATA_TO_CORE(o_DATA_TO_CORE),
|
||||
.ReadData(ReadData),
|
||||
.o_DATA_VALID(o_DATA_VALID),
|
||||
.o_LAST_NIBBLE(o_LAST_NIBBLE),
|
||||
.i_COUNT_IN_MAX(i_COUNT_IN_MAX),
|
||||
.LIMIT_SD_TIMERS(1'b1));
|
||||
|
||||
sdModel sdcard
|
||||
(.sdClk(o_SD_CLK),
|
||||
.cmd(PAD),
|
||||
.dat(i_SD_DAT));
|
||||
|
||||
// tri state pad
|
||||
// replace with I/O standard cell or FPGA gate.
|
||||
assign PAD = o_SD_CMD_OE ? o_SD_CMD : 1'bz;
|
||||
assign i_SD_CMD = PAD;
|
||||
|
||||
|
||||
always
|
||||
begin
|
||||
r_CLK = 1; # 5; r_CLK = 0; # 5;
|
||||
end
|
||||
|
||||
|
||||
initial $readmemh("ramdisk2.hex", sdcard.FLASHmem);
|
||||
|
||||
initial begin
|
||||
|
||||
a_RST = 1'b0;
|
||||
i_BLOCK_ADDR = 24'h100000;
|
||||
i_COUNT_IN_MAX = '0;
|
||||
i_READ_REQUEST = 1'b0;
|
||||
|
||||
# 5;
|
||||
i_COUNT_IN_MAX = -62;
|
||||
|
||||
# 10;
|
||||
a_RST = 1'b1;
|
||||
|
||||
# 4800;
|
||||
|
||||
a_RST = 1'b0;
|
||||
|
||||
# 2000000;
|
||||
i_READ_REQUEST = 1'b0;
|
||||
# 10000;
|
||||
i_READ_REQUEST = 1'b1;
|
||||
# 10000;
|
||||
i_READ_REQUEST = 1'b0;
|
||||
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -36,10 +36,10 @@ module testbench;
|
|||
/* verilator lint_off WIDTHEXPAND */
|
||||
parameter DEBUG=0;
|
||||
parameter TEST="none";
|
||||
parameter PrintHPMCounters=1;
|
||||
parameter BPRED_LOGGER=1;
|
||||
parameter I_CACHE_ADDR_LOGGER=1;
|
||||
parameter D_CACHE_ADDR_LOGGER=1;
|
||||
parameter PrintHPMCounters=0;
|
||||
parameter BPRED_LOGGER=0;
|
||||
parameter I_CACHE_ADDR_LOGGER=0;
|
||||
parameter D_CACHE_ADDR_LOGGER=0;
|
||||
|
||||
`include "parameter-defs.vh"
|
||||
|
||||
|
|
|
|||
|
|
@ -884,7 +884,9 @@ string imperas32f[] = '{
|
|||
"rv64i_m/privilege/src/misalign-blt-01.S",
|
||||
"rv64i_m/privilege/src/misalign-bltu-01.S",
|
||||
"rv64i_m/privilege/src/misalign-bne-01.S",
|
||||
"rv64i_m/privilege/src/misalign-jal-01.S",
|
||||
"rv64i_m/privilege/src/misalign-jal-01.S"
|
||||
// removed because rv64gc supports Zicclsm
|
||||
/* -----\/----- EXCLUDED -----\/-----
|
||||
"rv64i_m/privilege/src/misalign-ld-01.S",
|
||||
"rv64i_m/privilege/src/misalign-lh-01.S",
|
||||
"rv64i_m/privilege/src/misalign-lhu-01.S",
|
||||
|
|
@ -893,6 +895,7 @@ string imperas32f[] = '{
|
|||
"rv64i_m/privilege/src/misalign-sd-01.S",
|
||||
"rv64i_m/privilege/src/misalign-sh-01.S",
|
||||
"rv64i_m/privilege/src/misalign-sw-01.S"
|
||||
-----/\----- EXCLUDED -----/\----- */
|
||||
};
|
||||
|
||||
string arch64zi[] = '{
|
||||
|
|
@ -1971,6 +1974,7 @@ string arch64zbs[] = '{
|
|||
string wally64priv[] = '{
|
||||
`WALLYTEST,
|
||||
"rv64i_m/privilege/src/WALLY-minfo-01.S",
|
||||
"rv64i_m/privilege/src/WALLY-misaligned-access-01.S",
|
||||
"rv64i_m/privilege/src/WALLY-csr-permission-s-01.S",
|
||||
"rv64i_m/privilege/src/WALLY-cboz-01.S",
|
||||
"rv64i_m/privilege/src/WALLY-cbom-01.S",
|
||||
|
|
|
|||
|
|
@ -30,7 +30,7 @@ LINKER :=$(ROOT)/linker1000.x
|
|||
AFLAGS =$(MARCH) $(MABI) -W
|
||||
# Override directive allows us to prepend other options on the command line
|
||||
# e.g. $ make CFLAGS=-g
|
||||
override CFLAGS +=$(MARCH) $(MABI) -mcmodel=medany -O2
|
||||
override CFLAGS +=$(MARCH) $(MABI) -mcmodel=medany -O2 -g
|
||||
AS=riscv64-unknown-elf-as
|
||||
CC=riscv64-unknown-elf-gcc
|
||||
AR=riscv64-unknown-elf-ar
|
||||
|
|
|
|||
|
|
@ -28,11 +28,11 @@
|
|||
# Description: Makefrag for RV64I architectural tests
|
||||
|
||||
rv64i_sc_tests = \
|
||||
WALLY-ADD \
|
||||
WALLY-ADD \
|
||||
WALLY-SUB \
|
||||
WALLY-SLT \
|
||||
WALLY-SLTU \
|
||||
WALLY-XOR
|
||||
WALLY-SLTU \
|
||||
WALLY-XOR \
|
||||
|
||||
|
||||
rv64i_tests = $(addsuffix .elf, $(rv64i_sc_tests))
|
||||
|
|
|
|||
|
|
@ -60,6 +60,7 @@ target_tests_nosim = \
|
|||
WALLY-wfi-01 \
|
||||
WALLY-cbom-01 \
|
||||
WALLY-cboz-01 \
|
||||
WALLY-misaligned-access-01 \
|
||||
|
||||
|
||||
# unclear why status-fp-enabled and wfi aren't simulating ok
|
||||
|
|
|
|||
|
|
@ -0,0 +1,560 @@
|
|||
03020100 # ByteDstData
|
||||
07060504
|
||||
0b0a0908
|
||||
0f0e0d0c
|
||||
13021110
|
||||
17161514
|
||||
1b1a1918
|
||||
1f1e1d1c
|
||||
23222120
|
||||
27262524
|
||||
2b2a2928
|
||||
2f2e2d2c
|
||||
33023130
|
||||
37363534
|
||||
3b3a3938
|
||||
3f3e3d3c
|
||||
43424140
|
||||
47464544
|
||||
4b4a4948
|
||||
4f4e4d4c
|
||||
53025150
|
||||
57565554
|
||||
5b5a5958
|
||||
5f5e5d5c
|
||||
63626160
|
||||
67666564
|
||||
6b6a6968
|
||||
6f6e6d6c
|
||||
73027170
|
||||
77767574
|
||||
7b7a7978
|
||||
7f7e7d7c
|
||||
03020100 # Half0DstData
|
||||
07060504
|
||||
0b0a0908
|
||||
0f0e0d0c
|
||||
13021110
|
||||
17161514
|
||||
1b1a1918
|
||||
1f1e1d1c
|
||||
23222120
|
||||
27262524
|
||||
2b2a2928
|
||||
2f2e2d2c
|
||||
33023130
|
||||
37363534
|
||||
3b3a3938
|
||||
3f3e3d3c
|
||||
43424140
|
||||
47464544
|
||||
4b4a4948
|
||||
4f4e4d4c
|
||||
53025150
|
||||
57565554
|
||||
5b5a5958
|
||||
5f5e5d5c
|
||||
63626160
|
||||
67666564
|
||||
6b6a6968
|
||||
6f6e6d6c
|
||||
73027170
|
||||
77767574
|
||||
7b7a7978
|
||||
7f7e7d7c
|
||||
020100ef # Half1DstData
|
||||
06050403
|
||||
0a090807
|
||||
0e0d0c0b
|
||||
0211100f
|
||||
16151413
|
||||
1a191817
|
||||
1e1d1c1b
|
||||
2221201f
|
||||
26252423
|
||||
2a292827
|
||||
2e2d2c2b
|
||||
0231302f
|
||||
36353433
|
||||
3a393837
|
||||
3e3d3c3b
|
||||
4241403f
|
||||
46454443
|
||||
4a494847
|
||||
4e4d4c4b
|
||||
0251504f
|
||||
56555453
|
||||
5a595857
|
||||
5e5d5c5b
|
||||
6261605f
|
||||
66656463
|
||||
6a696867
|
||||
6e6d6c6b
|
||||
0271706f
|
||||
76757473
|
||||
7a797877
|
||||
7e7d7c7b
|
||||
deadbe7f
|
||||
deadbeef
|
||||
03020100 # Word0DstData
|
||||
07060504
|
||||
0b0a0908
|
||||
0f0e0d0c
|
||||
13021110
|
||||
17161514
|
||||
1b1a1918
|
||||
1f1e1d1c
|
||||
23222120
|
||||
27262524
|
||||
2b2a2928
|
||||
2f2e2d2c
|
||||
33023130
|
||||
37363534
|
||||
3b3a3938
|
||||
3f3e3d3c
|
||||
43424140
|
||||
47464544
|
||||
4b4a4948
|
||||
4f4e4d4c
|
||||
53025150
|
||||
57565554
|
||||
5b5a5958
|
||||
5f5e5d5c
|
||||
63626160
|
||||
67666564
|
||||
6b6a6968
|
||||
6f6e6d6c
|
||||
73027170
|
||||
77767574
|
||||
7b7a7978
|
||||
7f7e7d7c
|
||||
020100ef # Word1DstData
|
||||
06050403
|
||||
0a090807
|
||||
0e0d0c0b
|
||||
0211100f
|
||||
16151413
|
||||
1a191817
|
||||
1e1d1c1b
|
||||
2221201f
|
||||
26252423
|
||||
2a292827
|
||||
2e2d2c2b
|
||||
0231302f
|
||||
36353433
|
||||
3a393837
|
||||
3e3d3c3b
|
||||
4241403f
|
||||
46454443
|
||||
4a494847
|
||||
4e4d4c4b
|
||||
0251504f
|
||||
56555453
|
||||
5a595857
|
||||
5e5d5c5b
|
||||
6261605f
|
||||
66656463
|
||||
6a696867
|
||||
6e6d6c6b
|
||||
0271706f
|
||||
76757473
|
||||
7a797877
|
||||
7e7d7c7b
|
||||
deadbe7f
|
||||
deadbeef
|
||||
0100beef # Word2DstData
|
||||
05040302
|
||||
09080706
|
||||
0d0c0b0a
|
||||
11100f0e
|
||||
15141302
|
||||
19181716
|
||||
1d1c1b1a
|
||||
21201f1e
|
||||
25242322
|
||||
29282726
|
||||
2d2c2b2a
|
||||
31302f2e
|
||||
35343302
|
||||
39383736
|
||||
3d3c3b3a
|
||||
41403f3e
|
||||
45444342
|
||||
49484746
|
||||
4d4c4b4a
|
||||
51504f4e
|
||||
55545302
|
||||
59585756
|
||||
5d5c5b5a
|
||||
61605f5e
|
||||
65646362
|
||||
69686766
|
||||
6d6c6b6a
|
||||
71706f6e
|
||||
75747302
|
||||
79787776
|
||||
7d7c7b7a
|
||||
dead7f7e
|
||||
deadbeef
|
||||
00adbeef # Word3DstData
|
||||
04030201
|
||||
08070605
|
||||
0c0b0a09
|
||||
100f0e0d
|
||||
14130211
|
||||
18171615
|
||||
1c1b1a19
|
||||
201f1e1d
|
||||
24232221
|
||||
28272625
|
||||
2c2b2a29
|
||||
302f2e2d
|
||||
34330231
|
||||
38373635
|
||||
3c3b3a39
|
||||
403f3e3d
|
||||
44434241
|
||||
48474645
|
||||
4c4b4a49
|
||||
504f4e4d
|
||||
54530251
|
||||
58575655
|
||||
5c5b5a59
|
||||
605f5e5d
|
||||
64636261
|
||||
68676665
|
||||
6c6b6a69
|
||||
706f6e6d
|
||||
74730271
|
||||
78777675
|
||||
7c7b7a79
|
||||
de7f7e7d
|
||||
deadbeef
|
||||
03020100 # Double0DstData
|
||||
07060504
|
||||
0b0a0908
|
||||
0f0e0d0c
|
||||
13021110
|
||||
17161514
|
||||
1b1a1918
|
||||
1f1e1d1c
|
||||
23222120
|
||||
27262524
|
||||
2b2a2928
|
||||
2f2e2d2c
|
||||
33023130
|
||||
37363534
|
||||
3b3a3938
|
||||
3f3e3d3c
|
||||
43424140
|
||||
47464544
|
||||
4b4a4948
|
||||
4f4e4d4c
|
||||
53025150
|
||||
57565554
|
||||
5b5a5958
|
||||
5f5e5d5c
|
||||
63626160
|
||||
67666564
|
||||
6b6a6968
|
||||
6f6e6d6c
|
||||
73027170
|
||||
77767574
|
||||
7b7a7978
|
||||
7f7e7d7c
|
||||
020100ef # Double1DstData
|
||||
06050403
|
||||
0a090807
|
||||
0e0d0c0b
|
||||
0211100f
|
||||
16151413
|
||||
1a191817
|
||||
1e1d1c1b
|
||||
2221201f
|
||||
26252423
|
||||
2a292827
|
||||
2e2d2c2b
|
||||
0231302f
|
||||
36353433
|
||||
3a393837
|
||||
3e3d3c3b
|
||||
4241403f
|
||||
46454443
|
||||
4a494847
|
||||
4e4d4c4b
|
||||
0251504f
|
||||
56555453
|
||||
5a595857
|
||||
5e5d5c5b
|
||||
6261605f
|
||||
66656463
|
||||
6a696867
|
||||
6e6d6c6b
|
||||
0271706f
|
||||
76757473
|
||||
7a797877
|
||||
7e7d7c7b
|
||||
deadbe7f
|
||||
deadbeef
|
||||
0100beef # Double2DstData
|
||||
05040302
|
||||
09080706
|
||||
0d0c0b0a
|
||||
11100f0e
|
||||
15141302
|
||||
19181716
|
||||
1d1c1b1a
|
||||
21201f1e
|
||||
25242322
|
||||
29282726
|
||||
2d2c2b2a
|
||||
31302f2e
|
||||
35343302
|
||||
39383736
|
||||
3d3c3b3a
|
||||
41403f3e
|
||||
45444342
|
||||
49484746
|
||||
4d4c4b4a
|
||||
51504f4e
|
||||
55545302
|
||||
59585756
|
||||
5d5c5b5a
|
||||
61605f5e
|
||||
65646362
|
||||
69686766
|
||||
6d6c6b6a
|
||||
71706f6e
|
||||
75747302
|
||||
79787776
|
||||
7d7c7b7a
|
||||
dead7f7e
|
||||
deadbeef
|
||||
00adbeef # Double3DstData
|
||||
04030201
|
||||
08070605
|
||||
0c0b0a09
|
||||
100f0e0d
|
||||
14130211
|
||||
18171615
|
||||
1c1b1a19
|
||||
201f1e1d
|
||||
24232221
|
||||
28272625
|
||||
2c2b2a29
|
||||
302f2e2d
|
||||
34330231
|
||||
38373635
|
||||
3c3b3a39
|
||||
403f3e3d
|
||||
44434241
|
||||
48474645
|
||||
4c4b4a49
|
||||
504f4e4d
|
||||
54530251
|
||||
58575655
|
||||
5c5b5a59
|
||||
605f5e5d
|
||||
64636261
|
||||
68676665
|
||||
6c6b6a69
|
||||
706f6e6d
|
||||
74730271
|
||||
78777675
|
||||
7c7b7a79
|
||||
de7f7e7d
|
||||
deadbeef
|
||||
deadbeef # Double4DstData
|
||||
03020100
|
||||
07060504
|
||||
0b0a0908
|
||||
0f0e0d0c
|
||||
13021110
|
||||
17161514
|
||||
1b1a1918
|
||||
1f1e1d1c
|
||||
23222120
|
||||
27262524
|
||||
2b2a2928
|
||||
2f2e2d2c
|
||||
33023130
|
||||
37363534
|
||||
3b3a3938
|
||||
3f3e3d3c
|
||||
43424140
|
||||
47464544
|
||||
4b4a4948
|
||||
4f4e4d4c
|
||||
53025150
|
||||
57565554
|
||||
5b5a5958
|
||||
5f5e5d5c
|
||||
63626160
|
||||
67666564
|
||||
6b6a6968
|
||||
6f6e6d6c
|
||||
73027170
|
||||
77767574
|
||||
7b7a7978
|
||||
7f7e7d7c
|
||||
deadbeef
|
||||
deadbeef # Double5DstData
|
||||
020100ef
|
||||
06050403
|
||||
0a090807
|
||||
0e0d0c0b
|
||||
0211100f
|
||||
16151413
|
||||
1a191817
|
||||
1e1d1c1b
|
||||
2221201f
|
||||
26252423
|
||||
2a292827
|
||||
2e2d2c2b
|
||||
0231302f
|
||||
36353433
|
||||
3a393837
|
||||
3e3d3c3b
|
||||
4241403f
|
||||
46454443
|
||||
4a494847
|
||||
4e4d4c4b
|
||||
0251504f
|
||||
56555453
|
||||
5a595857
|
||||
5e5d5c5b
|
||||
6261605f
|
||||
66656463
|
||||
6a696867
|
||||
6e6d6c6b
|
||||
0271706f
|
||||
76757473
|
||||
7a797877
|
||||
7e7d7c7b
|
||||
deadbe7f
|
||||
deadbeef # Double6DstData
|
||||
0100beef
|
||||
05040302
|
||||
09080706
|
||||
0d0c0b0a
|
||||
11100f0e
|
||||
15141302
|
||||
19181716
|
||||
1d1c1b1a
|
||||
21201f1e
|
||||
25242322
|
||||
29282726
|
||||
2d2c2b2a
|
||||
31302f2e
|
||||
35343302
|
||||
39383736
|
||||
3d3c3b3a
|
||||
41403f3e
|
||||
45444342
|
||||
49484746
|
||||
4d4c4b4a
|
||||
51504f4e
|
||||
55545302
|
||||
59585756
|
||||
5d5c5b5a
|
||||
61605f5e
|
||||
65646362
|
||||
69686766
|
||||
6d6c6b6a
|
||||
71706f6e
|
||||
75747302
|
||||
79787776
|
||||
7d7c7b7a
|
||||
dead7f7e
|
||||
deadbeef # Double7DstData
|
||||
00adbeef
|
||||
04030201
|
||||
08070605
|
||||
0c0b0a09
|
||||
100f0e0d
|
||||
14130211
|
||||
18171615
|
||||
1c1b1a19
|
||||
201f1e1d
|
||||
24232221
|
||||
28272625
|
||||
2c2b2a29
|
||||
302f2e2d
|
||||
34330231
|
||||
38373635
|
||||
3c3b3a39
|
||||
403f3e3d
|
||||
44434241
|
||||
48474645
|
||||
4c4b4a49
|
||||
504f4e4d
|
||||
54530251
|
||||
58575655
|
||||
5c5b5a59
|
||||
605f5e5d
|
||||
64636261
|
||||
68676665
|
||||
6c6b6a69
|
||||
706f6e6d
|
||||
74730271
|
||||
78777675
|
||||
7c7b7a79
|
||||
de7f7e7d
|
||||
ffffffff #signature
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
000000ff
|
||||
00000000
|
||||
|
|
@ -1,3 +1,4 @@
|
|||
|
||||
FFFFFFFF # stimecmp low bits
|
||||
00000000 # stimecmp high bits
|
||||
00000000 # menvcfg low bits
|
||||
|
|
@ -24,7 +25,7 @@ FFFFFFFF # stimecmp low bits
|
|||
00000000
|
||||
00000004 # mcause from load address misaligned
|
||||
00000000
|
||||
80000411 # mtval of misaligned address (0x80000409)
|
||||
02000001 # mtval of misaligned address
|
||||
00000000
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
00000000
|
||||
|
|
@ -36,7 +37,7 @@ FFFFFFFF # stimecmp low bits
|
|||
00000000
|
||||
00000006 # mcause from store misaligned
|
||||
00000000
|
||||
80000429 # mtval of address with misaligned store instr (0x80000421)
|
||||
02000001 # mtval of misaligned address
|
||||
00000000
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
00000000
|
||||
|
|
@ -136,7 +137,7 @@ FFFFFFFF # stimecmp low bits
|
|||
00000000
|
||||
00000004 # mcause from load address misaligned
|
||||
00000000
|
||||
80000411 # mtval of misaligned address (0x80000409)
|
||||
02000001 # mtval of misaligned address
|
||||
00000000
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
00000000
|
||||
|
|
@ -148,7 +149,7 @@ FFFFFFFF # stimecmp low bits
|
|||
00000000
|
||||
00000006 # mcause from store misaligned
|
||||
00000000
|
||||
80000429 # mtval of address with misaligned store instr (0x80000421)
|
||||
02000001 # mtval of misaligned address
|
||||
00000000
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
00000000
|
||||
|
|
|
|||
|
|
@ -26,7 +26,7 @@
|
|||
00000000
|
||||
00000004 # scause from load address misaligned
|
||||
00000000
|
||||
80000411 # stval of misaligned address (0x80000409)
|
||||
02000001 # mtval of misaligned address
|
||||
00000000
|
||||
00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
|
||||
00000000
|
||||
|
|
@ -38,7 +38,7 @@
|
|||
00000000
|
||||
00000006 # scause from store misaligned
|
||||
00000000
|
||||
80000429 # stval of address with misaligned store instr (0x80000421)
|
||||
02000001 # mtval of misaligned address
|
||||
00000000
|
||||
00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
|
||||
00000000
|
||||
|
|
@ -128,7 +128,7 @@
|
|||
00000000
|
||||
00000004 # scause from load address misaligned
|
||||
00000000
|
||||
80000411 # stval of misaligned address (0x80000409)
|
||||
02000001 # mtval of misaligned address
|
||||
00000000
|
||||
00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
|
||||
00000000
|
||||
|
|
@ -140,7 +140,7 @@
|
|||
00000000
|
||||
00000006 # scause from store misaligned
|
||||
00000000
|
||||
80000429 # stval of address with misaligned store instr (0x80000421)
|
||||
02000001 # mtval of misaligned address
|
||||
00000000
|
||||
00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
|
||||
00000000
|
||||
|
|
|
|||
|
|
@ -26,7 +26,7 @@
|
|||
00000000
|
||||
00000004 # scause from load address misaligned
|
||||
00000000
|
||||
80000411 # stval of misaligned address (0x80000409)
|
||||
02000001 # mtval of misaligned address
|
||||
00000000
|
||||
00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
|
||||
00000000
|
||||
|
|
@ -38,7 +38,7 @@
|
|||
00000000
|
||||
00000006 # scause from store misaligned
|
||||
00000000
|
||||
80000429 # stval of address with misaligned store instr (0x80000421)
|
||||
02000001 # mtval of misaligned address
|
||||
00000000
|
||||
00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
|
||||
00000000
|
||||
|
|
@ -122,7 +122,7 @@
|
|||
00000000
|
||||
00000004 # scause from load address misaligned
|
||||
00000000
|
||||
80000411 # stval of misaligned address (0x80000409)
|
||||
02000001 # mtval of misaligned address
|
||||
00000000
|
||||
00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
|
||||
00000000
|
||||
|
|
@ -134,7 +134,7 @@
|
|||
00000000
|
||||
00000006 # scause from store misaligned
|
||||
00000000
|
||||
80000429 # stval of address with misaligned store instr (0x80000421)
|
||||
02000001 # mtval of misaligned address
|
||||
00000000
|
||||
00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
|
||||
00000000
|
||||
|
|
|
|||
|
|
@ -98,7 +98,8 @@ cause_breakpnt:
|
|||
ret
|
||||
|
||||
cause_load_addr_misaligned:
|
||||
auipc t3, 0 // get current PC, which is aligned
|
||||
li t3, 0x02000000 // base address of clint, because with zicclsm misaligned cached access won't trap
|
||||
//auipc t3, 0 // get current PC, which is aligned
|
||||
addi t3, t3, 1
|
||||
lw t4, 0(t3) // load from a misaligned address
|
||||
ret
|
||||
|
|
@ -108,7 +109,8 @@ cause_load_acc:
|
|||
ret
|
||||
|
||||
cause_store_addr_misaligned:
|
||||
auipc t3, 0 // get current PC, which is aligned
|
||||
li t3, 0x02000000 // base address of clint, because with zicclsm misaligned cached access won't trap
|
||||
//auipc t3, 0 // get current PC, which is aligned
|
||||
addi t3, t3, 1
|
||||
sw t4, 0(t3) // store to a misaligned address
|
||||
ret
|
||||
|
|
|
|||
|
|
@ -0,0 +1,752 @@
|
|||
///////////////////////////////////////////
|
||||
// ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SLT.S
|
||||
// David_Harris@hmc.edu & Katherine Parry
|
||||
// Created 2022-06-17 22:58:09.916813//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
// is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
RVTEST_ISA("RV64I")
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
rvtest_entry_point:
|
||||
RVMODEL_BOOT
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",ld)
|
||||
|
||||
# This test checks the misaligned load and stores work correctly and across D$ line spills.
|
||||
# The general approach is to
|
||||
# 1. load a region of memory using load doubles equal to two cache lines. And copy to a new
|
||||
# region but using stores of bytes, half, word, or doubles. Each are repeated for all possible
|
||||
# misaligned access. Bytes are always aligned, halves are 0, and 1, words are 0, 1, 2, and 3, and
|
||||
# doubles are 0 through 7. Then the new region is compared against the reference region. Because
|
||||
# of the misalignment the last few bytes will not be written so they will be some portion of deadbeef.
|
||||
# The comparison is done using using same abyte, half, word, and double misaligned approach.
|
||||
|
||||
la a3, signature # does not get overwritten by any functions
|
||||
|
||||
TEST_BYTE:
|
||||
# byte copy region. always naturally aligned
|
||||
la a0, SourceData
|
||||
la a1, ByteDstData
|
||||
li a2, 16
|
||||
jal ra, memcpy8_1
|
||||
|
||||
# check if the values are write for all sizes and offsets of misaligned loads.
|
||||
la a0, SourceData
|
||||
la a1, ByteDstData
|
||||
li a2, 16
|
||||
jal ra, CheckAllWriteSignature
|
||||
|
||||
TEST_HALF0:
|
||||
la a0, SourceData
|
||||
la a1, Half0DstData
|
||||
li a2, 16
|
||||
jal ra, memcpy8_2
|
||||
|
||||
# check if the values are write for all sizes and offsets of misaligned loads.
|
||||
la a0, SourceData
|
||||
la a1, Half0DstData
|
||||
li a2, 16
|
||||
jal ra, CheckAllWriteSignature
|
||||
|
||||
TEST_HALF1:
|
||||
la a0, SourceData
|
||||
la a1, Half1DstData+1
|
||||
li a2, 16
|
||||
jal ra, memcpy8_2
|
||||
|
||||
# check if the values are write for all sizes and offsets of misaligned loads.
|
||||
la a0, SourceData
|
||||
la a1, Half1DstData+1
|
||||
li a2, 16
|
||||
jal ra, CheckAllWriteSignature
|
||||
|
||||
TEST_WORD0:
|
||||
la a0, SourceData
|
||||
la a1, Word0DstData
|
||||
li a2, 16
|
||||
jal ra, memcpy8_4
|
||||
|
||||
# check if the values are write for all sizes and offsets of misaligned loads.
|
||||
la a0, SourceData
|
||||
la a1, Word0DstData
|
||||
li a2, 16
|
||||
jal ra, CheckAllWriteSignature
|
||||
|
||||
TEST_WORD1:
|
||||
la a0, SourceData
|
||||
la a1, Word1DstData+1
|
||||
li a2, 16
|
||||
jal ra, memcpy8_4
|
||||
|
||||
# check if the values are write for all sizes and offsets of misaligned loads.
|
||||
la a0, SourceData
|
||||
la a1, Word1DstData+1
|
||||
li a2, 16
|
||||
jal ra, CheckAllWriteSignature
|
||||
|
||||
TEST_WORD2:
|
||||
la a0, SourceData
|
||||
la a1, Word2DstData+2
|
||||
li a2, 16
|
||||
jal ra, memcpy8_4
|
||||
|
||||
# check if the values are write for all sizes and offsets of misaligned loads.
|
||||
la a0, SourceData
|
||||
la a1, Word2DstData+2
|
||||
li a2, 16
|
||||
jal ra, CheckAllWriteSignature
|
||||
|
||||
TEST_WORD3:
|
||||
la a0, SourceData
|
||||
la a1, Word3DstData+3
|
||||
li a2, 16
|
||||
jal ra, memcpy8_4
|
||||
|
||||
# check if the values are write for all sizes and offsets of misaligned loads.
|
||||
la a0, SourceData
|
||||
la a1, Word3DstData+3
|
||||
li a2, 16
|
||||
jal ra, CheckAllWriteSignature
|
||||
|
||||
TEST_DOUBLE0:
|
||||
la a0, SourceData
|
||||
la a1, Double0DstData
|
||||
li a2, 16
|
||||
jal ra, memcpy8_8
|
||||
|
||||
# check if the values are write for all sizes and offsets of misaligned loads.
|
||||
la a0, SourceData
|
||||
la a1, Double0DstData
|
||||
li a2, 16
|
||||
jal ra, CheckAllWriteSignature
|
||||
|
||||
TEST_DOUBLE1:
|
||||
la a0, SourceData
|
||||
la a1, Double1DstData+1
|
||||
li a2, 16
|
||||
jal ra, memcpy8_8
|
||||
|
||||
# check if the values are write for all sizes and offsets of misaligned loads.
|
||||
la a0, SourceData
|
||||
la a1, Double1DstData+1
|
||||
li a2, 16
|
||||
jal ra, CheckAllWriteSignature
|
||||
|
||||
TEST_DOUBLE2:
|
||||
la a0, SourceData
|
||||
la a1, Double2DstData+2
|
||||
li a2, 16
|
||||
jal ra, memcpy8_8
|
||||
|
||||
# check if the values are write for all sizes and offsets of misaligned loads.
|
||||
la a0, SourceData
|
||||
la a1, Double2DstData+2
|
||||
li a2, 16
|
||||
jal ra, CheckAllWriteSignature
|
||||
|
||||
TEST_DOUBLE3:
|
||||
la a0, SourceData
|
||||
la a1, Double3DstData+3
|
||||
li a2, 16
|
||||
jal ra, memcpy8_8
|
||||
|
||||
# check if the values are write for all sizes and offsets of misaligned loads.
|
||||
la a0, SourceData
|
||||
la a1, Double3DstData+3
|
||||
li a2, 16
|
||||
jal ra, CheckAllWriteSignature
|
||||
|
||||
TEST_DOUBLE4:
|
||||
la a0, SourceData
|
||||
la a1, Double4DstData+4
|
||||
li a2, 16
|
||||
jal ra, memcpy8_8
|
||||
|
||||
# check if the values are write for all sizes and offsets of misaligned loads.
|
||||
la a0, SourceData
|
||||
la a1, Double4DstData+4
|
||||
li a2, 16
|
||||
jal ra, CheckAllWriteSignature
|
||||
|
||||
TEST_DOUBLE5:
|
||||
la a0, SourceData
|
||||
la a1, Double5DstData+5
|
||||
li a2, 16
|
||||
jal ra, memcpy8_8
|
||||
|
||||
# check if the values are write for all sizes and offsets of misaligned loads.
|
||||
la a0, SourceData
|
||||
la a1, Double5DstData+5
|
||||
li a2, 16
|
||||
jal ra, CheckAllWriteSignature
|
||||
|
||||
TEST_DOUBLE6:
|
||||
la a0, SourceData
|
||||
la a1, Double6DstData+6
|
||||
li a2, 16
|
||||
jal ra, memcpy8_8
|
||||
|
||||
# check if the values are write for all sizes and offsets of misaligned loads.
|
||||
la a0, SourceData
|
||||
la a1, Double6DstData+6
|
||||
li a2, 16
|
||||
jal ra, CheckAllWriteSignature
|
||||
|
||||
TEST_DOUBLE7:
|
||||
la a0, SourceData
|
||||
la a1, Double7DstData+7
|
||||
li a2, 16
|
||||
jal ra, memcpy8_8
|
||||
|
||||
# check if the values are write for all sizes and offsets of misaligned loads.
|
||||
la a0, SourceData
|
||||
la a1, Double7DstData+7
|
||||
li a2, 16
|
||||
jal ra, CheckAllWriteSignature
|
||||
|
||||
RVMODEL_HALT
|
||||
|
||||
.type CheckAll, @function
|
||||
# a0 is the SourceData, (golden), a1 is the data to be checked.
|
||||
# a2 is the number of doubles
|
||||
# a3 is the signature pointer
|
||||
# returns a0 as 0 for no mismatch, 1 for mismatch,
|
||||
# returns a3 as incremented signature pointer
|
||||
CheckAllWriteSignature:
|
||||
mv s0, a0
|
||||
mv s1, a1
|
||||
mv s2, a2
|
||||
mv s3, a3
|
||||
# there is no stack so I'm saving ra into s5
|
||||
mv s5, ra
|
||||
|
||||
# check values byte by byte
|
||||
mv a0, s0 # SourceData
|
||||
mv a1, s1 # ie: ByteDstData
|
||||
slli a2, s2, 3 # * 8
|
||||
jal ra, memcmp1
|
||||
sb a0, 0(s3)
|
||||
mv s4, a0
|
||||
|
||||
# check values half by half
|
||||
mv a0, s0 # SourceData
|
||||
mv a1, s1 # ie: ByteDstData
|
||||
slli a2, s2, 2 # * 4
|
||||
jal ra, memcmp2
|
||||
sb a0, 1(s3)
|
||||
or s4, s4, a0
|
||||
|
||||
# check values half by half
|
||||
addi a0, s0, 1 # SourceData+1
|
||||
addi a1, s1, 1 # ie: ByteDstData+1
|
||||
slli a2, s2, 2 # * 4 -1
|
||||
addi a2, a2, -1
|
||||
jal ra, memcmp2
|
||||
sb a0, 2(s3)
|
||||
or s4, s4, a0
|
||||
|
||||
# check values word by word
|
||||
addi a0, s0, 0 # SourceData
|
||||
mv a1, s1 # ie: ByteDstData
|
||||
slli a2, s2, 1 # * 2
|
||||
jal ra, memcmp4
|
||||
sb a0, 3(s3)
|
||||
or s4, s4, a0
|
||||
|
||||
# check values word by word
|
||||
addi a0, s0, 1 # SourceData+1
|
||||
addi a1, s1, 1 # ie: ByteDstData+1
|
||||
slli a2, s2, 1 # * 2 -1
|
||||
addi a2, a2, -1
|
||||
jal ra, memcmp4
|
||||
sb a0, 4(s3)
|
||||
or s4, s4, a0
|
||||
|
||||
# check values word by word
|
||||
addi a0, s0, 2 # SourceData+2
|
||||
addi a1, s1, 2 # ie: ByteDstData+2
|
||||
slli a2, s2, 1 # * 2 -1
|
||||
addi a2, a2, -1
|
||||
jal ra, memcmp4
|
||||
sb a0, 5(s3)
|
||||
or s4, s4, a0
|
||||
|
||||
# check values word by word
|
||||
addi a0, s0, 3 # SourceData+3
|
||||
addi a1, s1, 3 # ie: ByteDstData+3
|
||||
slli a2, s2, 1 # * 2 -1
|
||||
addi a2, a2, -1
|
||||
jal ra, memcmp4
|
||||
sb a0, 6(s3)
|
||||
or s4, s4, a0
|
||||
|
||||
# check values double by double
|
||||
mv a0, s0 # SourceData
|
||||
mv a1, s1 # ie: ByteDstData
|
||||
slli a2, s2, 0 # * 1
|
||||
jal ra, memcmp8
|
||||
sb a0, 7(s3)
|
||||
|
||||
# check values double by double
|
||||
addi a0, s0, 1 # SourceData+1
|
||||
addi a1, s1, 1 # ie: ByteDstData+1
|
||||
slli a2, s2, 0 # * 1 -1
|
||||
addi a2, a2, -1
|
||||
jal ra, memcmp8
|
||||
sb a0, 8(s3)
|
||||
|
||||
# check values double by double
|
||||
addi a0, s0, 2 # SourceData+2
|
||||
addi a1, s1, 2 # ie: ByteDstData+2
|
||||
slli a2, s2, 0 # * 1 -1
|
||||
addi a2, a2, -1
|
||||
jal ra, memcmp8
|
||||
sb a0, 9(s3)
|
||||
|
||||
# check values double by double
|
||||
addi a0, s0, 3 # SourceData+3
|
||||
addi a1, s1, 3 # ie: ByteDstData+3
|
||||
slli a2, s2, 0 # * 1 -1
|
||||
addi a2, a2, -1
|
||||
jal ra, memcmp8
|
||||
sb a0, 10(s3)
|
||||
|
||||
# check values double by double
|
||||
addi a0, s0, 4 # SourceData+4
|
||||
addi a1, s1, 4 # ie: ByteDstData+4
|
||||
slli a2, s2, 0 # * 1 -1
|
||||
addi a2, a2, -1
|
||||
jal ra, memcmp8
|
||||
sb a0, 11(s3)
|
||||
|
||||
# check values double by double
|
||||
addi a0, s0, 5 # SourceData+5
|
||||
addi a1, s1, 5 # ie: ByteDstData+5
|
||||
slli a2, s2, 0 # * 1 -1
|
||||
addi a2, a2, -1
|
||||
jal ra, memcmp8
|
||||
sb a0, 12(s3)
|
||||
|
||||
# check values double by double
|
||||
addi a0, s0, 6 # SourceData+6
|
||||
addi a1, s1, 6 # ie: ByteDstData+6
|
||||
slli a2, s2, 0 # * 1 -1
|
||||
addi a2, a2, -1
|
||||
jal ra, memcmp8
|
||||
sb a0, 13(s3)
|
||||
|
||||
# check values double by double
|
||||
addi a0, s0, 7 # SourceData+7
|
||||
addi a1, s1, 7 # ie: ByteDstData+7
|
||||
slli a2, s2, 0 # * 1
|
||||
addi a2, a2, -1
|
||||
jal ra, memcmp8
|
||||
sb a0, 14(s3)
|
||||
|
||||
addi s3, s3, 15
|
||||
mv a3, s3
|
||||
or a0, s4, a0
|
||||
mv ra, s5
|
||||
ret
|
||||
|
||||
|
||||
.type memcmp1, @function
|
||||
# returns which index mismatch, -1 if none
|
||||
memcmp1:
|
||||
# a0 is the source1
|
||||
# a1 is the source2
|
||||
# a2 is the number of 1 byte words
|
||||
mv t0, a0
|
||||
mv t1, a1
|
||||
li t2, 0
|
||||
memcmp1_loop:
|
||||
lbu t3, 0(t0)
|
||||
lbu t4, 0(t1)
|
||||
bne t3, t4, memcmp1_ne
|
||||
addi t0, t0, 1
|
||||
addi t1, t1, 1
|
||||
addi t2, t2, 1
|
||||
blt t2, a2, memcmp1_loop
|
||||
li a0, -1
|
||||
ret
|
||||
memcmp1_ne:
|
||||
mv a0, t2
|
||||
ret
|
||||
|
||||
.type memcmp2, @function
|
||||
# returns which index mismatch, -1 if none
|
||||
memcmp2:
|
||||
# a0 is the source1
|
||||
# a1 is the source2
|
||||
# a2 is the number of 2 byte words
|
||||
mv t0, a0
|
||||
mv t1, a1
|
||||
li t2, 0
|
||||
memcmp2_loop:
|
||||
lhu t3, 0(t0)
|
||||
lhu t4, 0(t1)
|
||||
bne t3, t4, memcmp2_ne
|
||||
addi t0, t0, 2
|
||||
addi t1, t1, 2
|
||||
addi t2, t2, 1
|
||||
blt t2, a2, memcmp2_loop
|
||||
li a0, -1
|
||||
ret
|
||||
memcmp2_ne:
|
||||
mv a0, t2
|
||||
ret
|
||||
|
||||
.type memcmp4, @function
|
||||
# returns which index mismatch, -1 if none
|
||||
memcmp4:
|
||||
# a0 is the source1
|
||||
# a1 is the source2
|
||||
# a2 is the number of 4 byte words
|
||||
mv t0, a0
|
||||
mv t1, a1
|
||||
li t2, 0
|
||||
memcmp4_loop:
|
||||
lwu t3, 0(t0)
|
||||
lwu t4, 0(t1)
|
||||
bne t3, t4, memcmp4_ne
|
||||
addi t0, t0, 4
|
||||
addi t1, t1, 4
|
||||
addi t2, t2, 1
|
||||
blt t2, a2, memcmp4_loop
|
||||
li a0, -1
|
||||
ret
|
||||
memcmp4_ne:
|
||||
mv a0, t2
|
||||
ret
|
||||
|
||||
.type memcmp8, @function
|
||||
# returns which index mismatch, -1 if none
|
||||
memcmp8:
|
||||
# a0 is the source1
|
||||
# a1 is the source2
|
||||
# a2 is the number of 8 byte words
|
||||
mv t0, a0
|
||||
mv t1, a1
|
||||
li t2, 0
|
||||
memcmp8_loop:
|
||||
ld t3, 0(t0)
|
||||
ld t4, 0(t1)
|
||||
bne t3, t4, memcmp8_ne
|
||||
addi t0, t0, 8
|
||||
addi t1, t1, 8
|
||||
addi t2, t2, 1
|
||||
blt t2, a2, memcmp8_loop
|
||||
li a0, -1
|
||||
ret
|
||||
memcmp8_ne:
|
||||
mv a0, t2
|
||||
ret
|
||||
|
||||
|
||||
RVTEST_CODE_END
|
||||
|
||||
.type memcpy8_1, @function
|
||||
# load 8 bytes using load double then store using 8 sb
|
||||
memcpy8_1:
|
||||
# a0 is the source
|
||||
# a1 is the dst
|
||||
# a2 is the number of 8 byte words
|
||||
mv t0, a0
|
||||
mv t1, a1
|
||||
li t2, 0
|
||||
memcpy8_1_loop:
|
||||
ld t3, 0(t0)
|
||||
andi t4, t3, 0xff
|
||||
sb t4, 0(t1)
|
||||
srli t4, t3, 8
|
||||
andi t4, t4, 0xff
|
||||
sb t4, 1(t1)
|
||||
|
||||
srli t4, t3, 16
|
||||
andi t4, t4, 0xff
|
||||
sb t4, 2(t1)
|
||||
|
||||
srli t4, t3, 24
|
||||
andi t4, t4, 0xff
|
||||
sb t4, 3(t1)
|
||||
|
||||
srli t4, t3, 32
|
||||
andi t4, t4, 0xff
|
||||
sb t4, 4(t1)
|
||||
|
||||
srli t4, t3, 40
|
||||
andi t4, t4, 0xff
|
||||
sb t4, 5(t1)
|
||||
|
||||
srli t4, t3, 48
|
||||
andi t4, t4, 0xff
|
||||
sb t4, 6(t1)
|
||||
|
||||
srli t4, t3, 56
|
||||
andi t4, t4, 0xff
|
||||
sb t4, 7(t1)
|
||||
|
||||
addi t0, t0, 8
|
||||
addi t1, t1, 8
|
||||
addi t2, t2, 1
|
||||
blt t2, a2, memcpy8_1_loop
|
||||
ret
|
||||
|
||||
.type memcpy8_2, @function
|
||||
# load 8 bytes using load double then store using 4 sh
|
||||
memcpy8_2:
|
||||
# a0 is the source
|
||||
# a1 is the dst
|
||||
# a2 is the number of 8 byte words
|
||||
mv t0, a0
|
||||
mv t1, a1
|
||||
li t2, 0
|
||||
|
||||
# 16 bit mask
|
||||
lui t4, 0xf
|
||||
li t3, 0xfff
|
||||
or t5, t4, t3
|
||||
|
||||
memcpy8_2_loop:
|
||||
ld t3, 0(t0)
|
||||
and t4, t3, t5
|
||||
sh t4, 0(t1)
|
||||
|
||||
srli t4, t3, 16
|
||||
and t4, t4, t5
|
||||
sh t4, 2(t1)
|
||||
|
||||
srli t4, t3, 32
|
||||
and t4, t4, t5
|
||||
sh t4, 4(t1)
|
||||
|
||||
srli t4, t3, 48
|
||||
and t4, t4, t5
|
||||
sh t4, 6(t1)
|
||||
|
||||
|
||||
addi t0, t0, 8
|
||||
addi t1, t1, 8
|
||||
addi t2, t2, 1
|
||||
blt t2, a2, memcpy8_2_loop
|
||||
ret
|
||||
|
||||
.type memcpy8_4, @function
|
||||
# load 8 bytes using load double then store using 2 sw
|
||||
memcpy8_4:
|
||||
# a0 is the source
|
||||
# a1 is the dst
|
||||
# a2 is the number of 8 byte words
|
||||
mv t0, a0
|
||||
mv t1, a1
|
||||
li t2, 0
|
||||
|
||||
# 32 bit mask
|
||||
addi t4, x0, -1
|
||||
srli t5, t4, 32
|
||||
|
||||
memcpy8_4_loop:
|
||||
ld t3, 0(t0)
|
||||
and t4, t3, t5
|
||||
sw t4, 0(t1)
|
||||
|
||||
srli t4, t3, 32
|
||||
and t4, t4, t5
|
||||
sw t4, 4(t1)
|
||||
|
||||
addi t0, t0, 8
|
||||
addi t1, t1, 8
|
||||
addi t2, t2, 1
|
||||
blt t2, a2, memcpy8_4_loop
|
||||
ret
|
||||
|
||||
.type memcpy8_8, @function
|
||||
# load 8 bytes using load double then store using 1 sd
|
||||
memcpy8_8:
|
||||
# a0 is the source
|
||||
# a1 is the dst
|
||||
# a2 is the number of 8 byte words
|
||||
mv t0, a0
|
||||
mv t1, a1
|
||||
li t2, 0
|
||||
|
||||
memcpy8_8_loop:
|
||||
ld t3, 0(t0)
|
||||
sd t3, 0(t1)
|
||||
|
||||
addi t0, t0, 8
|
||||
addi t1, t1, 8
|
||||
addi t2, t2, 1
|
||||
blt t2, a2, memcpy8_8_loop
|
||||
ret
|
||||
|
||||
|
||||
RVTEST_DATA_BEGIN
|
||||
.align 3
|
||||
rvtest_data:
|
||||
SourceData:
|
||||
.8byte 0x0706050403020100, 0x0f0e0d0c0b0a0908, 0x1716151413021110, 0x1f1e1d1c1b1a1918
|
||||
.8byte 0x2726252423222120, 0x2f2e2d2c2b2a2928, 0x3736353433023130, 0x3f3e3d3c3b3a3938
|
||||
.8byte 0x4746454443424140, 0x4f4e4d4c4b4a4948, 0x5756555453025150, 0x5f5e5d5c5b5a5958
|
||||
.8byte 0x6766656463626160, 0x6f6e6d6c6b6a6968, 0x7776757473027170, 0x7f7e7d7c7b7a7978
|
||||
.8byte 0xdeadbeefdeadbeef
|
||||
|
||||
Response1ByteOffsetData:
|
||||
.8byte 0x0807060504030201, 0x100f0e0d0c0b0a09, 0x1817161514130211, 0x201f1e1d1c1b1a19
|
||||
.8byte 0x2827262524232221, 0x302f2e2d2c2b2a29, 0x3837363534330231, 0x403f3e3d3c3b3a39
|
||||
.8byte 0x4847464544434241, 0x504f4e4d4c4b4a49, 0x5857565554530251, 0x605f5e5d5c5b5a59
|
||||
.8byte 0x6867666564636261, 0x706f6e6d6c6b6a69, 0x7877767574730271, 0xde7f7e7d7c7b7a79
|
||||
|
||||
Response2ByteOffsetData:
|
||||
.8byte 0x0908070605040302, 0x11100f0e0d0c0b0a, 0x1918171615141302, 0x21201f1e1d1c1b1a
|
||||
.8byte 0x2928272625242322, 0x31302f2e2d2c2b2a, 0x3938373635343302, 0x41403f3e3d3c3b3a
|
||||
.8byte 0x4948474645444342, 0x51504f4e4d4c4b4a, 0x5958575655545302, 0x61605f5e5d5c5b5a
|
||||
.8byte 0x6968676665646362, 0x71706f6e6d6c6b6a, 0x7978777675747302, 0xdead7f7e7d7c7b7a
|
||||
|
||||
Response3ByteOffsetData:
|
||||
.8byte 0x0a09080706050403, 0x0211100f0e0d0c0b, 0x1a19181716151413, 0x2221201f1e1d1c1b
|
||||
.8byte 0x2a29282726252423, 0x0231302f2e2d2c2b, 0x3a39383736353433, 0x4241403f3e3d3c3b
|
||||
.8byte 0x4a49484746454443, 0x0251504f4e4d4c4b, 0x5a59585756555453, 0x6261605f5e5d5c5b
|
||||
.8byte 0x6a69686766656463, 0x0271706f6e6d6c6b, 0x7a79787776757473, 0xdeadbe7f7e7d7c7b
|
||||
|
||||
Response4ByteOffsetData:
|
||||
.8byte 0x0b0a090807060504, 0x130211100f0e0d0c, 0x1b1a191817161514, 0x232221201f1e1d1c
|
||||
.8byte 0x2b2a292827262524, 0x330231302f2e2d2c, 0x3b3a393837363534, 0x434241403f3e3d3c
|
||||
.8byte 0x4b4a494847464544, 0x530251504f4e4d4c, 0x5b5a595857565554, 0x636261605f5e5d5c
|
||||
.8byte 0x6b6a696867666564, 0x730271706f6e6d6c, 0x7b7a797877767574, 0xdeadbeef7f7e7d7c
|
||||
|
||||
Response5ByteOffsetData:
|
||||
.8byte 0x0c0b0a0908070605, 0x14130211100f0e0d, 0x1c1b1a1918171615, 0x24232221201f1e1d
|
||||
.8byte 0x2c2b2a2928272625, 0x34330231302f2e2d, 0x3c3b3a3938373635, 0x44434241403f3e3d
|
||||
.8byte 0x4c4b4a4948474645, 0x54530251504f4e4d, 0x5c5b5a5958575655, 0x64636261605f5e5d
|
||||
.8byte 0x6c6b6a6968676665, 0x74730271706f6e6d, 0x7c7b7a7978777675, 0xdeadbeefde7f7e7d
|
||||
|
||||
Response6ByteOffsetData:
|
||||
.8byte 0x0d0c0b0a09080706, 0x1514130211100f0e, 0x1d1c1b1a19181716, 0x2524232221201f1e
|
||||
.8byte 0x2d2c2b2a29282726, 0x3534330231302f2e, 0x3d3c3b3a39383736, 0x4544434241403f3e
|
||||
.8byte 0x4d4c4b4a49484746, 0x5554530251504f4e, 0x5d5c5b5a59585756, 0x6564636261605f5e
|
||||
.8byte 0x6d6c6b6a69686766, 0x7574730271706f6e, 0x7d7c7b7a79787776, 0xdeadbeefdead7f7e
|
||||
|
||||
Response7ByteOffsetData:
|
||||
.8byte 0x0e0d0c0b0a090807, 0x161514130211100f, 0x1e1d1c1b1a191817, 0x262524232221201f
|
||||
.8byte 0x2e2d2c2b2a292827, 0x363534330231302f, 0x3e3d3c3b3a393837, 0x464544434241403f
|
||||
.8byte 0x4e4d4c4b4a494847, 0x565554530251504f, 0x5e5d5c5b5a595857, 0x666564636261605f
|
||||
.8byte 0x6e6d6c6b6a696867, 0x767574730271706f, 0x7e7d7c7b7a797877, 0xdeadbeefdeadbe7f
|
||||
|
||||
RVTEST_DATA_END
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
|
||||
ByteDstData:
|
||||
.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
|
||||
.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
|
||||
.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
|
||||
.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
|
||||
|
||||
Half0DstData:
|
||||
.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
|
||||
.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
|
||||
.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
|
||||
.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
|
||||
|
||||
Half1DstData:
|
||||
.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
|
||||
.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
|
||||
.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
|
||||
.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
|
||||
.8byte 0xdeadbeefdeadbeef
|
||||
Word0DstData:
|
||||
.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
|
||||
.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
|
||||
.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
|
||||
.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
|
||||
|
||||
Word1DstData:
|
||||
.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
|
||||
.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
|
||||
.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
|
||||
.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
|
||||
.8byte 0xdeadbeefdeadbeef
|
||||
Word2DstData:
|
||||
.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
|
||||
.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
|
||||
.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
|
||||
.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
|
||||
.8byte 0xdeadbeefdeadbeef
|
||||
Word3DstData:
|
||||
.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
|
||||
.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
|
||||
.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
|
||||
.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
|
||||
.8byte 0xdeadbeefdeadbeef
|
||||
Double0DstData:
|
||||
.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
|
||||
.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
|
||||
.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
|
||||
.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
|
||||
|
||||
Double1DstData:
|
||||
.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
|
||||
.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
|
||||
.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
|
||||
.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
|
||||
.8byte 0xdeadbeefdeadbeef
|
||||
Double2DstData:
|
||||
.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
|
||||
.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
|
||||
.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
|
||||
.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
|
||||
.8byte 0xdeadbeefdeadbeef
|
||||
Double3DstData:
|
||||
.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
|
||||
.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
|
||||
.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
|
||||
.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
|
||||
.8byte 0xdeadbeefdeadbeef
|
||||
Double4DstData:
|
||||
.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
|
||||
.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
|
||||
.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
|
||||
.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
|
||||
.8byte 0xdeadbeefdeadbeef
|
||||
Double5DstData:
|
||||
.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
|
||||
.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
|
||||
.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
|
||||
.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
|
||||
.8byte 0xdeadbeefdeadbeef
|
||||
Double6DstData:
|
||||
.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
|
||||
.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
|
||||
.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
|
||||
.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
|
||||
.8byte 0xdeadbeefdeadbeef
|
||||
Double7DstData:
|
||||
.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
|
||||
.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
|
||||
.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
|
||||
.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
|
||||
.8byte 0xdeadbeefdeadbeef
|
||||
signature:
|
||||
.fill 225, 1, 0x00
|
||||
|
||||
RVMODEL_DATA_END
|
||||
// ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SLT.S
|
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// David_Harris@hmc.edu & Katherine Parry
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