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At least it simulates and gets through fpga elaboration.

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This commit is contained in:
Ross Thompson 2023-07-21 18:35:27 -05:00
parent a89a1e675c
commit ab6ef5bb58
4 changed files with 12 additions and 13 deletions
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4
fpga/constraints/constraints-ArtyA7.xdc
View file

@ -80,6 +80,8 @@ set_property PACKAGE_PIN E2 [get_ports {SDCDat[1]}]
set_property PACKAGE_PIN F4 [get_ports {SDCDat[0]}]
set_property PACKAGE_PIN F3 [get_ports SDCCLK]
set_property PACKAGE_PIN D3 [get_ports {SDCCmd}]
set_property PACKAGE_PIN H2 [get_ports {SDCCD}]
set_property IOSTANDARD LVCMOS33 [get_ports {SDCDat[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SDCDat[2]}]
@ -87,11 +89,13 @@ set_property IOSTANDARD LVCMOS33 [get_ports {SDCDat[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SDCDat[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports SDCCLK]
set_property IOSTANDARD LVCMOS33 [get_ports {SDCCmd}]
set_property IOSTANDARD LVCMOS33 [get_ports {SDCCD}]
set_property PULLUP true [get_ports {SDCDat[3]}]
set_property PULLUP true [get_ports {SDCDat[2]}]
set_property PULLUP true [get_ports {SDCDat[1]}]
set_property PULLUP true [get_ports {SDCDat[0]}]
set_property PULLUP true [get_ports {SDCCmd}]
set_property PULLUP true [get_ports {SDCCD}]
set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -min -add_delay 2.500 [get_ports {SDCDat[*]}]

7
fpga/generator/Makefile
View file

@ -21,7 +21,7 @@ all: FPGA_Arty
# VCU 108 and VCU 118 boards
#all: FPGA_VCU
FPGA_Arty: PreProcessFiles IP_Arty SDC
FPGA_Arty: PreProcessFiles IP_Arty
vivado -mode tcl -source wally.tcl 2>&1 | tee wally.log
FPGA_VCU: PreProcessFiles IP_VCU SDC
@ -40,15 +40,12 @@ IP_Arty: $(dst)/xlnx_proc_sys_reset.log \
$(dst)/xlnx_ddr3-$(board).log \
$(dst)/xlnx_mmcm.log \
$(dst)/xlnx_axi_clock_converter.log \
$(dst)/xlnx_ahblite_axi_bridge.log
$(dst)/xlnx_ahblite_axi_bridge.log \
$(dst)/xlnx_axi_crossbar.log \
$(dst)/xlnx_axi_dwidth_conv_32to64.log \
$(dst)/xlnx_axi_dwidth_conv_64to32.log \
$(dst)/xlnx_axi_prtcl_conv.log
SDC:
cp $(sdc_src) ../src/
tar xzf ../src/sdc.tar.gz -C ../src
PreProcessFiles:
rm -rf ../src/CopiedFiles_do_not_add_to_repo/

8
fpga/src/fpgaTopArtyA7.v
View file

@ -35,9 +35,10 @@ module fpgaTop
input UARTSin,
output UARTSout,
input [3:0] SDCDat,
inout [3:0] SDCDat,
output SDCCLK,
inout SDCCmd,
input SDCCD,
inout [15:0] ddr3_dq,
inout [1:0] ddr3_dqs_n,
@ -999,7 +1000,7 @@ module fpgaTop
.s_axi_rready(s00_axi_rready),
.m_axi_aclk(BUSCLK),
.m_axi_aresetn(~reset),
.m_axi_aresetn(resetn),
.m_axi_awid(BUS_axi_awid),
.m_axi_awlen(BUS_axi_awlen),
.m_axi_awsize(BUS_axi_awsize),
@ -1040,9 +1041,6 @@ module fpgaTop
.m_axi_rlast(BUS_axi_rlast),
.m_axi_rready(BUS_axi_rready));
assign CPUCLK = CLK208;
xlnx_ddr3 xlnx_ddr3_c0
(
// ddr3 I/O

6
linux/sdcard/flash-sd.sh
View file

@ -11,10 +11,10 @@ NAME="$GREEN"${0:2}"$NC"
# File location variables
RISCV=/opt/riscv
IMAGES=$RISCV/buildroot/output/images
IMAGES=/home/ross/repos/buildroot/output/images/
FW_JUMP=$IMAGES/fw_jump.bin
LINUX_KERNEL=$IMAGES/Image
DEVICE_TREE=$IMAGES/wally-vcu108.dtb
DEVICE_TREE=$IMAGES/wally-artya7.dtb
# Mount Directory
MNT_DIR=wallyimg
@ -117,4 +117,4 @@ fi
echo
echo "GPT Information for $1 ==================================="
sgdisk -p $1
sudo sgdisk -p $1