mirror of
https://github.com/openhwgroup/cvw.git
synced 2025-04-23 13:27:16 -04:00
Pass TEST to testbench with +TEST=<name> rather than -G TEST=<name> so that we don't have to recompile for every new test
This commit is contained in:
David Harris
parent
347df26713
commit
ac9a21873d
5 changed files with 121 additions and 209 deletions
8
bin/wsim
8
bin/wsim
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@ -40,10 +40,14 @@ if (args.coverage):
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# Launch selected simulator
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cd = "cd $WALLY/sim/" +args.sim
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if (args.sim == "questa"):
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cmd = "do wally-batch.do " + args.config + " " + args.testsuite + " " + args.tb + " " + args.arg
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cmd = "do wally.do " + args.config + " " + args.testsuite + " " + args.tb + " " + args.arg
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if (args.coverage):
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cmd += " -coverage"
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os.system(cd + "; vsim -c -do \"" + cmd + "\"")
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if (args.gui): # launch Questa with GUI; add +acc to keep variables accessible
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cmd = cd + "; vsim -do \"" + cmd + " +acc\""
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else: # launch Questa in batch mode
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cmd = cd + "; vsim -c -do \"" + cmd + "\""
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os.system(cmd)
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elif (args.sim == "verilator"):
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print("Running Verilator on %s %s", args.config, args.testsuite)
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elif (args.sim == "vcs"):
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@ -1,99 +0,0 @@
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# wally-batch.do
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# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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#
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# Modification by Oklahoma State University & Harvey Mudd College
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# Use with Testbench
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# James Stine, 2008; David Harris 2021
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# Go Cowboys!!!!!!
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#
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# Takes 1:10 to run RV64IC tests using gui
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# Usage: do wally-batch.do <config> <testcases> <testbench>
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# Example: do wally-batch.do rv64gc arch64i testbench
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# Use this wally-batch.do file to run this example.
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# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
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# do wally-batch.do
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# or, to run from a shell, type the following at the shell prompt:
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# vsim -do wally-batch.do -c
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# (omit the "-c" to see the GUI while running from the shell)
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onbreak {resume}
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set CFG ${1}
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set TESTSUITE ${2}
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set TESTBENCH ${3}
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set WKDIR wkdir/${CFG}_${TESTSUITE}
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set WALLY $::env(WALLY)
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set CONFIG ${WALLY}/config
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set SRC ${WALLY}/src
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set TB ${WALLY}/testbench
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# create library
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if [file exists ${WKDIR}] {
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vdel -lib ${WKDIR} -all
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}
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vlib ${WKDIR}
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# Create directory for coverage data
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mkdir -p cov
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set coverage 0
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set CoverageVoptArg ""
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set CoverageVsimArg ""
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# Need to be able to pass arguments to vopt. Unforunately argv does not work because
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# it takes on different values if vsim and the do file are called from the command line or
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# if the do file isd called from questa sim directly. This chunk of code uses the $4 through $n
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# variables and compacts into a single list for passing to vopt.
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set configOptions ""
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set from 4
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set step 1
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set lst {}
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for {set i 0} true {incr i} {
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set x [expr {$i*$step + $from}]
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if {$x > $argc} break
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set arg [expr "$$x"]
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lappend lst $arg
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}
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if {$argc >= 3} {
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if {$3 eq "-coverage" || ($argc >= 7 && $7 eq "-coverage")} {
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set coverage 1
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set CoverageVoptArg "+cover=sbecf"
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set CoverageVsimArg "-coverage"
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} elseif {$3 eq "configOptions"} {
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set configOptions $lst
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puts $configOptions
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}
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}
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# compile source files
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# suppress spurious warnngs about
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# "Extra checking for conflicts with always_comb done at vopt time"
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# because vsim will run vopt
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vlog -lint -work ${WKDIR} +incdir+${CONFIG}/$1 +incdir+${CONFIG}/deriv/$1 +incdir+${CONFIG}/shared ${SRC}/cvw.sv ${TB}/${TESTBENCH}.sv ${TB}/common/*.sv ${SRC}/*/*.sv ${SRC}/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286
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# start and run simulation
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# remove +acc flag for faster sim during regressions if there is no need to access internal signals
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vopt wkdir/${CFG}_${TESTSUITE}.${TESTBENCH} -work ${WKDIR} -G TEST=$2 ${configOptions} -o testbenchopt ${CoverageVoptArg}
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vsim -lib ${WKDIR} testbenchopt -fatal 7 -suppress 3829 ${CoverageVsimArg}
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# vsim -lib wkdir/work_${1}_${2} testbenchopt -fatal 7 -suppress 3829
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# power add generates the logging necessary for said generation.
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# power add -r /dut/core/*
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run -all
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# power off -r /dut/core/*
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if {$coverage} {
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set UCDB cov/${CFG}_${TESTSUITE}.ucdb
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echo "Saving coverage to ${UCDB}"
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do coverage-exclusions-rv64gc.do # beware: this assumes testing the rv64gc configuration
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coverage save -instance /testbench/dut/core ${UCDB}
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}
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# These aren't doing anything helpful
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#profile report -calltree -file wally-calltree.rpt -cutoff 2
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#power report -all -bsaif power.saif
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quit
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@ -1,4 +1,4 @@
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# wally.do
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# wally-batch.do
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# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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#
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# Modification by Oklahoma State University & Harvey Mudd College
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@ -8,113 +8,93 @@
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#
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# Takes 1:10 to run RV64IC tests using gui
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# run with vsim -do "do wally-pipelined.do rv64ic riscvarchtest-64m"
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# Usage: do wally-batch.do <config> <testcases> <testbench> [-coverage] [+acc] [any number of +value] [any number of -G VAR=VAL]
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# Example: do wally-batch.do rv64gc arch64i testbench
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# Use this wally-pipelined.do file to run this example.
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# Use this wally-batch.do file to run this example.
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# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
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# do wally.do
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# do wally-batch.do
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# or, to run from a shell, type the following at the shell prompt:
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# vsim -do wally.do -c
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# vsim -do wally-batch.do -c
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# (omit the "-c" to see the GUI while running from the shell)
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onbreak {resume}
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set CFG ${1}
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set TESTSUITE ${2}
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set TESTBENCH ${3}
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set WKDIR wkdir/${CFG}_${TESTSUITE}
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set WALLY $::env(WALLY)
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set CONFIG ${WALLY}/config
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set SRC ${WALLY}/src
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set TB ${WALLY}/testbench
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# create library
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if [file exists work] {
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vdel -all
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if [file exists ${WKDIR}] {
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vdel -lib ${WKDIR} -all
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}
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vlib ${WKDIR}
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# Create directory for coverage data
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mkdir -p cov
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set coverage 0
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set CoverageVoptArg ""
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set CoverageVsimArg ""
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# Need to be able to pass arguments to vopt. Unforunately argv does not work because
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# it takes on different values if vsim and the do file are called from the command line or
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# if the do file isd called from questa sim directly. This chunk of code uses the $4 through $n
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# variables and compacts into a single list for passing to vopt.
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set configOptions ""
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set from 4
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set step 1
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set lst {}
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for {set i 0} true {incr i} {
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set x [expr {$i*$step + $from}]
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if {$x > $argc} break
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set arg [expr "$$x"]
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lappend lst $arg
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}
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if {$argc >= 3} {
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if {$3 eq "-coverage" || ($argc >= 7 && $7 eq "-coverage")} {
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set coverage 1
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set CoverageVoptArg "+cover=sbecf"
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set CoverageVsimArg "-coverage"
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} elseif {$3 eq "configOptions"} {
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set configOptions $lst
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puts $configOptions
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}
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}
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vlib work
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# compile source files
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# suppress spurious warnngs about
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# "Extra checking for conflicts with always_comb done at vopt time"
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# because vsim will run vopt
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vlog -lint -work ${WKDIR} +incdir+${CONFIG}/$1 +incdir+${CONFIG}/deriv/$1 +incdir+${CONFIG}/shared ${SRC}/cvw.sv ${TB}/${TESTBENCH}.sv ${TB}/common/*.sv ${SRC}/*/*.sv ${SRC}/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286
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# start and run simulation
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# remove +acc flag for faster sim during regressions if there is no need to access internal signals
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if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
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vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/deriv/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
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# start and run simulation
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vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -G NO_SPOOFING=0 -o testbenchopt
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vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829,13286 -fatal 7
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#vopt wkdir/${CFG}_${TESTSUITE}.${TESTBENCH} -work ${WKDIR} -G TEST=$2 ${configOptions} -o testbenchopt ${CoverageVoptArg}
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vopt wkdir/${CFG}_${TESTSUITE}.${TESTBENCH} -work ${WKDIR} ${configOptions} -o testbenchopt ${CoverageVoptArg}
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vsim -lib ${WKDIR} testbenchopt +TEST=${TESTSUITE} -fatal 7 -suppress 3829 ${CoverageVsimArg}
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#-- Run the Simulation
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#run -all
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add log -recursive /*
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do linux-wave.do
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run -all
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# vsim -lib wkdir/work_${1}_${2} testbenchopt -fatal 7 -suppress 3829
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# power add generates the logging necessary for said generation.
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# power add -r /dut/core/*
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run -all
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# power off -r /dut/core/*
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exec ./slack-notifier/slack-notifier.py
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} elseif {$2 eq "buildroot-no-trace"} {
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vlog -lint -work work_${1}_${2} +incdir+../config/deriv/$1 +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
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# start and run simulation
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vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=0 -G INSTR_WAVEON=0 -G CHECKPOINT=0 -G NO_SPOOFING=1 -o testbenchopt
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vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829,13286 -fatal 7
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#-- Run the Simulation
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echo "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!"
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echo "Don't forget to change DEBUG_LEVEL = 0."
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echo "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!"
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#run 100 ns
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#force -deposit testbench/dut/core/priv/priv/csr/csri/IE_REGW 16'h2aa
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#force -deposit testbench/dut/uncore/uncore/clint/clint/MTIMECMP 64'h1000
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run 14000 ms
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#add log -recursive /*
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#do linux-wave.do
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#run -all
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exec ./slack-notifier/slack-notifier.py
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} elseif {$2 eq "fpga"} {
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echo "hello"
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vlog -work work +incdir+../config/fpga +incdir+../config/deriv/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/sdc/*.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv ../../fpga/sim/*.sv -suppress 8852,12070,3084,3829,2583,7063,13286
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vopt +acc work.testbench -G TEST=$2 -G DEBUG=0 -o workopt
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vsim workopt +nowarn3829 -fatal 7
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do fpga-wave.do
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add log -r /*
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run 20 ms
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} else {
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vlog +incdir+../config/$1 +incdir+../config/deriv/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583,13286 -suppress 7063
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vopt +acc work.testbench -G TEST=$2 -G DEBUG=1 -o workopt
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vsim workopt +nowarn3829 -fatal 7
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view wave
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#-- display input and output signals as hexidecimal values
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#do ./wave-dos/peripheral-waves.do
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add log -recursive /*
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do wave.do
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#do wave-bus.do
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# power add generates the logging necessary for saif generation.
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#power add -r /dut/core/*
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#-- Run the Simulation
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run -all
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#power off -r /dut/core/*
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#power report -all -bsaif power.saif
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noview ../testbench/testbench.sv
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view wave
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if {$coverage} {
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set UCDB cov/${CFG}_${TESTSUITE}.ucdb
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echo "Saving coverage to ${UCDB}"
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do coverage-exclusions-rv64gc.do # beware: this assumes testing the rv64gc configuration
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coverage save -instance /testbench/dut/core ${UCDB}
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}
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#elseif {$2 eq "buildroot-no-trace""} {
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# vlog -lint -work work_${1}_${2} +incdir+../config/deriv/$1 +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
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# start and run simulation
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# vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=470350800 -G INSTR_WAVEON=470350800 -G CHECKPOINT=470350800 -G DEBUG_TRACE=0 -o testbenchopt
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# vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829
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#-- Run the Simulation
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# run 100 ns
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# force -deposit testbench/dut/core/priv/priv/csr/csri/IE_REGW 16'h2aa
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# force -deposit testbench/dut/uncore/uncore/clint/clint/MTIMECMP 64'h1000
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# add log -recursive /*
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# do linux-wave.do
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# run -all
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# exec ./slack-notifier/slack-notifier.py
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#}
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# These aren't doing anything helpful
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#profile report -calltree -file wally-calltree.rpt -cutoff 2
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#power report -all -bsaif power.saif
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quit
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@ -27,7 +27,7 @@
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////////////////////////////////////////////////////////////////////////////////////////////////
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module loggers import cvw::*; #(parameter cvw_t P,
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parameter string TEST,
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parameter PrintHPMCounters,
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parameter I_CACHE_ADDR_LOGGER,
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parameter D_CACHE_ADDR_LOGGER,
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@ -39,7 +39,8 @@ module loggers import cvw::*; #(parameter cvw_t P,
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// input logic BeginSample,
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// input logic StartSample,
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// input logic EndSample,
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input string memfilename
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input string memfilename,
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input string TEST
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);
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// performance counter logging
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@ -79,40 +80,64 @@ module loggers import cvw::*; #(parameter cvw_t P,
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"Divide Cycles"
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};
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always_comb
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if (TEST == "embench") begin
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StartSampleFirst = FunctionName.FunctionName.FunctionName == "start_trigger";
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EndSampleFirst = FunctionName.FunctionName.FunctionName == "stop_trigger";
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end else if (TEST == "coremark") begin
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StartSampleFirst = FunctionName.FunctionName.FunctionName == "start_time";
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EndSampleFirst = FunctionName.FunctionName.FunctionName == "stop_time";
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end else begin
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StartSampleFirst = reset;
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EndSample = DCacheFlushStart & ~DCacheFlushDone;
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end
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/*
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if(TEST == "embench") begin
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// embench runs warmup then runs start_trigger
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// embench end with stop_trigger.
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assign StartSampleFirst = FunctionName.FunctionName.FunctionName == "start_trigger";
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flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed);
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assign StartSample = StartSampleFirst & ~ StartSampleDelayed;
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//assign StartSampleFirst = FunctionName.FunctionName.FunctionName == "start_trigger";
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//flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed);
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//assign StartSample = StartSampleFirst & ~ StartSampleDelayed;
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assign EndSampleFirst = FunctionName.FunctionName.FunctionName == "stop_trigger";
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//assign EndSampleFirst = FunctionName.FunctionName.FunctionName == "stop_trigger";
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flopr #(1) EndSampleReg(clk, reset, EndSampleFirst, EndSampleDelayed);
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assign EndSample = EndSampleFirst & ~ EndSampleDelayed;
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end else if(TEST == "coremark") begin
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// embench runs warmup then runs start_trigger
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// embench end with stop_trigger.
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assign StartSampleFirst = FunctionName.FunctionName.FunctionName == "start_time";
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flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed);
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assign StartSample = StartSampleFirst & ~ StartSampleDelayed;
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//assign StartSampleFirst = FunctionName.FunctionName.FunctionName == "start_time";
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//flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed);
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//assign StartSample = StartSampleFirst & ~ StartSampleDelayed;
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assign EndSampleFirst = FunctionName.FunctionName.FunctionName == "stop_time";
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//assign EndSampleFirst = FunctionName.FunctionName.FunctionName == "stop_time";
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flopr #(1) EndSampleReg(clk, reset, EndSampleFirst, EndSampleDelayed);
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assign EndSample = EndSampleFirst & ~ EndSampleDelayed;
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end else begin
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// default start condiction is reset
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// default end condiction is end of test (DCacheFlushDone)
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assign StartSampleFirst = reset;
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flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed);
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assign StartSample = StartSampleFirst & ~ StartSampleDelayed;
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assign EndSample = DCacheFlushStart & ~DCacheFlushDone;
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//assign StartSampleFirst = reset;
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//flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed);
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//assign StartSample = StartSampleFirst & ~ StartSampleDelayed;
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//assign EndSample = DCacheFlushStart & ~DCacheFlushDone;
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flop #(1) BeginReg(clk, StartSampleFirst, BeginDelayed);
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assign BeginSample = StartSampleFirst & ~BeginDelayed;
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end
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*/
|
||||
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||||
flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed);
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||||
assign StartSample = StartSampleFirst & ~StartSampleDelayed;
|
||||
flopr #(1) EndSampleReg(clk, reset, EndSampleFirst, EndSampleDelayed);
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||||
assign EndSample = EndSampleFirst & ~ EndSampleDelayed;
|
||||
flop #(1) BeginReg(clk, StartSampleFirst, BeginDelayed); // ** is this redundant with StartSampleReg?
|
||||
assign BeginSample = StartSampleFirst & ~BeginDelayed;
|
||||
|
||||
|
||||
always @(negedge clk) begin
|
||||
if(StartSample) begin
|
||||
for(HPMCindex = 0; HPMCindex < 32; HPMCindex += 1) begin
|
||||
|
|
|
|||
|
|
@ -39,7 +39,6 @@ module testbench;
|
|||
/* verilator lint_off WIDTHTRUNC */
|
||||
/* verilator lint_off WIDTHEXPAND */
|
||||
parameter DEBUG=0;
|
||||
parameter string TEST="arch64m";
|
||||
parameter PrintHPMCounters=0;
|
||||
parameter BPRED_LOGGER=0;
|
||||
parameter I_CACHE_ADDR_LOGGER=0;
|
||||
|
|
@ -58,6 +57,7 @@ module testbench;
|
|||
logic clk;
|
||||
logic reset_ext, reset;
|
||||
logic ResetMem;
|
||||
string TEST;
|
||||
|
||||
// DUT signals
|
||||
logic [P.AHBW-1:0] HRDATAEXT;
|
||||
|
|
@ -101,7 +101,9 @@ module testbench;
|
|||
|
||||
// pick tests based on modes supported
|
||||
initial begin
|
||||
$display("TEST is %s", TEST);
|
||||
TEST = "none";
|
||||
if ($value$plusargs("TEST=%s", TEST))
|
||||
$display("TEST is %s", TEST);
|
||||
//tests = '{};
|
||||
if (P.XLEN == 64) begin // RV64
|
||||
case (TEST)
|
||||
|
|
@ -309,7 +311,7 @@ module testbench;
|
|||
// Verify the test ran correctly by checking the memory against a known signature.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
if(TestBenchReset) test = 1;
|
||||
if (TEST == "coremark")
|
||||
if (P.ZICSR_SUPPORTED & TEST == "coremark")
|
||||
if (dut.core.priv.priv.EcallFaultM) begin
|
||||
$display("Benchmark: coremark is done.");
|
||||
$stop;
|
||||
|
|
@ -559,8 +561,8 @@ module testbench;
|
|||
ramxdetector #(P.XLEN, P.LLEN) ramxdetector(clk, dut.core.lsu.MemRWM[1], dut.core.lsu.LSULoadAccessFaultM, dut.core.lsu.ReadDataM,
|
||||
dut.core.ifu.PCM, InstrM, dut.core.lsu.IEUAdrM, InstrMName);
|
||||
riscvassertions #(P) riscvassertions(); // check assertions for a legal configuration
|
||||
loggers #(P, TEST, PrintHPMCounters, I_CACHE_ADDR_LOGGER, D_CACHE_ADDR_LOGGER, BPRED_LOGGER)
|
||||
loggers (clk, reset, DCacheFlushStart, DCacheFlushDone, memfilename);
|
||||
loggers #(P, PrintHPMCounters, I_CACHE_ADDR_LOGGER, D_CACHE_ADDR_LOGGER, BPRED_LOGGER)
|
||||
loggers (clk, reset, DCacheFlushStart, DCacheFlushDone, memfilename, TEST);
|
||||
|
||||
// track the current function or global label
|
||||
if (DEBUG == 1 | ((PrintHPMCounters | BPRED_LOGGER) & P.ZICNTR_SUPPORTED)) begin : FunctionName
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue