mirror of
https://github.com/openhwgroup/cvw.git
synced 2025-04-22 21:08:08 -04:00
Merge branch 'main' of https://github.com/openhwgroup/cvw into imperas_verbose
This commit is contained in:
Jordan Carlin
commit
ae593ed81d
40 changed files with 694 additions and 800 deletions
|
|
@ -1,6 +1,6 @@
|
|||
# core-v-wally
|
||||
|
||||
Wally is a 5-stage pipelined processor configurable to support all the standard RISC-V options, including RV32/64, A, B, C, D, F, M, Q, and Zk* extensions, virtual memory, PMP, and the various privileged modes and CSRs. It provides optional caches, branch prediction, and standard RISC-V peripherals (CLINT, PLIC, UART, GPIO). Wally is written in SystemVerilog. It passes the [RISC-V Arch Tests](https://github.com/riscv-non-isa/riscv-arch-test) and boots Linux on an FPGA. Configurations range from a minimal RV32E core to a fully featured RV64GC application processor.
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||||
Wally is a 5-stage pipelined processor configurable to support all the standard RISC-V options, including RV32/64, A, B, C, D, F, M, Q, and Zk* extensions, virtual memory, PMP, and the various privileged modes and CSRs. It provides optional caches, branch prediction, and standard RISC-V peripherals (CLINT, PLIC, UART, GPIO). Wally is written in SystemVerilog. It passes the [RISC-V Arch Tests](https://github.com/riscv-non-isa/riscv-arch-test) and boots Linux on an FPGA. Configurations range from a minimal RV32E core to a fully featured RV64GC application processor with all of the RVA22S64 profile extensions. Wally is part of the OpenHWGroup family of robust open RISC-V cores.
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|
||||
|
||||
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@ -222,3 +222,4 @@ Run lockstep against ImperasDV with directory file.
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|||
Run lockstep against ImperasDV with directory file and specify specific extension.
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||||
wsim rv64gc ../../tests/riscof/work/riscv-arch-test/rv64i_m/I/src/ --lockstep --elfext ref.elf
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||||
|
|
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|||
|
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@ -1 +1 @@
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|||
Subproject commit 9d54f3f8e902bb85db74305993d2fc03796b57bc
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||||
Subproject commit 80cdee231f924b3045054594d4a7769e6eddcdcc
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||||
|
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@ -1,50 +0,0 @@
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|||
#!/bin/bash
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||||
# Alessandro Maiuolo 2022
|
||||
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
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|
||||
configFile=config/shared/wally-shared.vh
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||||
|
||||
searchRadix="define RADIX 32'"..
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||||
searchCopies="define DIVCOPIES 32'"..
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||||
|
||||
currRadix="define RADIX 32'h2"
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||||
currCopies="define DIVCOPIES 32'h1"
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||||
sed -i "s/$searchRadix/$currRadix/" $configFile
|
||||
sed -i "s/$searchCopies/$currCopies/" $configFile
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||||
echo regression on Radix :$currRadix: and Copies :$currCopies:
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||||
./sim/regression-wally
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|
||||
currRadix="define RADIX 32'h2"
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currCopies="define DIVCOPIES 32'h2"
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||||
sed -i "s/$searchRadix/$currRadix/" $configFile
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||||
sed -i "s/$searchCopies/$currCopies/" $configFile
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||||
echo regression on Radix :$currRadix: and Copies :$currCopies:
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||||
./sim/regression-wally
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||||
|
||||
currRadix="define RADIX 32'h2"
|
||||
currCopies="define DIVCOPIES 32'h4"
|
||||
sed -i "s/$searchRadix/$currRadix/" $configFile
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||||
sed -i "s/$searchCopies/$currCopies/" $configFile
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||||
echo regression on Radix :$currRadix: and Copies :$currCopies:
|
||||
./sim/regression-wally
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||||
|
||||
currRadix="define RADIX 32'h4"
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||||
currCopies="define DIVCOPIES 32'h1"
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||||
sed -i "s/$searchRadix/$currRadix/" $configFile
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||||
sed -i "s/$searchCopies/$currCopies/" $configFile
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||||
echo regression on Radix :$currRadix: and Copies :$currCopies:
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||||
./sim/regression-wally
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||||
|
||||
currRadix="define RADIX 32'h4"
|
||||
currCopies="define DIVCOPIES 32'h2"
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sed -i "s/$searchRadix/$currRadix/" $configFile
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||||
sed -i "s/$searchCopies/$currCopies/" $configFile
|
||||
echo regression on Radix :$currRadix: and Copies :$currCopies:
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./sim/regression-wally
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||||
|
||||
currRadix="define RADIX 32'h4"
|
||||
currCopies="define DIVCOPIES 32'h4"
|
||||
sed -i "s/$searchRadix/$currRadix/" $configFile
|
||||
sed -i "s/$searchCopies/$currCopies/" $configFile
|
||||
echo regression on Radix :$currRadix: and Copies :$currCopies:
|
||||
./sim/regression-wally
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|
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@ -232,8 +232,8 @@ bpredtests = [
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# list of tests not supported by ImperasDV yet that should be waived during lockstep testing
|
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lockstepwaivers = [
|
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"WALLY-q-01.S_ref.elf", # Q extension is not supported by ImperasDV
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||||
"WALLY-cbom-01.S_ref.elf", # cbom extension is not supported by ImperasDV because there is no cache model in ImperasDV
|
||||
"coverage_ieu.elf" # Issue 881: ImperasDV misinterprets 0x6BF05013 as a grevi rather than an illegal instruction
|
||||
"WALLY-cbom-01.S_ref.elf" #, # cbom extension is not supported by ImperasDV because there is no cache model in ImperasDV
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# "coverage_ieu.elf" # Issue 881: ImperasDV misinterprets 0x6BF05013 as a grevi rather than an illegal instruction
|
||||
]
|
||||
|
||||
##################################
|
||||
|
|
@ -292,7 +292,10 @@ def addTests(tests, sim):
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|
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def addLockstepTestsByDir(dir, config, sim):
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sim_logdir = WALLY+ "/sim/" + sim + "/logs/"
|
||||
cmdPrefix="wsim --lockstep --sim " + sim + " " + coverStr + " " + config
|
||||
if (coverStr != ""): # use --fcov in place of --lockstep
|
||||
cmdPrefix="wsim --sim " + sim + " " + coverStr + " " + config
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||||
else:
|
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cmdPrefix="wsim --lockstep --sim " + sim + " " + config
|
||||
if (os.path.isdir(dir)):
|
||||
for dirpath, dirnames, filenames in os.walk(os.path.abspath(dir)):
|
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for file in filenames:
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||||
|
|
@ -408,7 +411,8 @@ if (args.ccov): # only run RV64GC tests on Questa in code coverage mode
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if (args.fp):
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addTests(tests64gc_fp, coveragesim)
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elif (args.fcov): # only run RV64GC tests on Questa in lockstep in functional coverage mode
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addLockstepTestsByDir(WALLY+"/tests/functcov/rv64/I", "rv64gc", coveragesim)
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addLockstepTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/rv32/I", "rv32gc", coveragesim)
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# addLockstepTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/rv64/I", "rv64gc", coveragesim)
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elif (args.fcovrvvi): # only run RV64GC tests on Questa in rvvi coverage mode
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addTests(tests64gc_nofp, coveragesim)
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if (args.fp):
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|
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@ -545,7 +549,8 @@ def main():
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if args.ccov:
|
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os.system('make QuestaCodeCoverage')
|
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if args.fcov:
|
||||
os.system('make QuestaFunctCoverage')
|
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#os.system('make QuestaFunctCoverage')
|
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os.system('make -f '+WALLY+'/addins/cvw-arch-verif/Makefile merge')
|
||||
if args.fcovrvvi:
|
||||
os.system('make QuestaFunctCoverageRvvi')
|
||||
# Count the number of failures
|
||||
|
|
|
|||
16
bin/wsim
16
bin/wsim
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|
@ -27,8 +27,8 @@ parser.add_argument("--sim", "-s", help="Simulator", choices=["questa", "verilat
|
|||
parser.add_argument("--tb", "-t", help="Testbench", choices=["testbench", "testbench_fp"], default="testbench")
|
||||
parser.add_argument("--gui", "-g", help="Simulate with GUI", action="store_true")
|
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parser.add_argument("--ccov", "-c", help="Code Coverage", action="store_true")
|
||||
parser.add_argument("--fcov", "-f", help="Functional Coverage, implies lockstep", action="store_true")
|
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parser.add_argument("--fcov2", "-f2", help="Functional Coverage, implies lockstep", action="store_true")
|
||||
parser.add_argument("--fcovimp", "-f2", help="Functional Coverage with Imperas licensed riscvISACOV, implies lockstep", action="store_true")
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||||
parser.add_argument("--fcov", "-f", help="Functional Coverage with cvw-arch-verif, implies lockstep", action="store_true")
|
||||
parser.add_argument("--fcovrvvi", "-fr", help="Functional Coverage RVVI", action="store_true")
|
||||
parser.add_argument("--args", "-a", help="Optional arguments passed to simulator via $value$plusargs", default="")
|
||||
parser.add_argument("--params", "-p", help="Optional top-level parameter overrides of the form param=value", default="")
|
||||
|
|
@ -69,7 +69,7 @@ if(args.testsuite.endswith('.elf') and args.elf == ""): # No --elf argument; che
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|||
|
||||
|
||||
# Validate arguments
|
||||
if (args.gui or args.ccov or args.fcov or args.fcov2 or args.fcovrvvi or args.lockstep or args.lockstepverbose):
|
||||
if (args.gui or args.ccov or args.fcov or args.fcovimp or args.fcovrvvi or args.lockstep or args.lockstepverbose):
|
||||
if args.sim not in ["questa", "vcs"]:
|
||||
print("Option only supported for Questa and VCS")
|
||||
exit(1)
|
||||
|
|
@ -86,7 +86,7 @@ if (args.tb == "testbench_fp"):
|
|||
# if lockstep is enabled, then we need to pass the Imperas lockstep arguments
|
||||
if(int(args.locksteplog) >= 1): EnableLog = 1
|
||||
else: EnableLog = 0
|
||||
if((args.lockstep or args.lockstepverbose or args.fcov or args.fcov2) and args.sim == "questa"):
|
||||
if((args.lockstep or args.lockstepverbose or args.fcov or args.fcovimp) and args.sim == "questa"):
|
||||
prefix = "IMPERAS_TOOLS=" + WALLY + "/config/"+args.config+"/imperas.ic"
|
||||
prefix = "MTI_VCO_MODE=64 " + prefix
|
||||
else:
|
||||
|
|
@ -95,13 +95,13 @@ else:
|
|||
if (args.lockstep or args.lockstepverbose):
|
||||
if(args.locksteplog != 0): ImperasPlusArgs = " +IDV_TRACE2LOG=" + str(EnableLog) + " +IDV_TRACE2LOG_AFTER=" + str(args.locksteplog)
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||||
else: ImperasPlusArgs = ""
|
||||
if(args.fcov):
|
||||
if(args.fcovimp):
|
||||
CovEnableStr = "1" if int(args.covlog) > 0 else "0"
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||||
if(args.covlog >= 1): EnableLog = 1
|
||||
else: EnableLog = 0
|
||||
ImperasPlusArgs = " +IDV_TRACE2COV=" + str(EnableLog) + " +TRACE2LOG_AFTER=" + str(args.covlog) + " +TRACE2COV_ENABLE=" + CovEnableStr
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||||
suffix = ""
|
||||
if(args.fcov2):
|
||||
if(args.fcov):
|
||||
CovEnableStr = "1" if int(args.covlog) > 0 else "0";
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||||
if(args.covlog >= 1): EnableLog = 1
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else: EnableLog = 0
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||||
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|
@ -124,8 +124,8 @@ if (args.ccov):
|
|||
flags += " --ccov"
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||||
if (args.fcov):
|
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flags += " --fcov"
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||||
if (args.fcov2):
|
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flags += " --fcov2"
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||||
if (args.fcovimp):
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flags += " --fcovimp"
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if (args.fcovrvvi):
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flags += "--fcovrvvi"
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||||
|
||||
|
|
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|||
|
|
@ -54,7 +54,23 @@ UNCORE_RAM_RANGE 64'h1FFF
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|||
BOOTROM_RANGE 64'hFFF
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EXT_MEM_SUPPORTED 1
|
||||
EXT_MEM_BASE 64'h80000000
|
||||
EXT_MEM_RANGE 64'h7FFFFFFF
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||||
SDC_SUPPORTED 1
|
||||
PLIC_SDC_ID 32'd20
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BPRED_SIZE 32'd12
|
||||
|
||||
deriv fpgaArtyA7 fpga
|
||||
EXT_MEM_RANGE 64'h0FFFFFFF
|
||||
|
||||
deriv fpgavcu108 fpga
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||||
EXT_MEM_RANGE 64'h7FFFFFFF
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||||
|
||||
# temporary spitest configuration
|
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deriv spitest rv64gc
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UNCORE_RAM_RANGE 64'h0FFFFFFF
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||||
SPI_LOOPBACK_TEST 1
|
||||
UART_PRESCALE 32'd0
|
||||
PLIC_NUM_SRC 32'd53
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||||
SDC_SUPPORTED 1
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||||
PLIC_SDC_ID 32'd20
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BPRED_SIZE 32'd12
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||||
|
|
|
|||
13
config/rv32gc/coverage.svh
Normal file
13
config/rv32gc/coverage.svh
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
// coverage.svh
|
||||
// David_Harris@hmc.edu 7 September 2024
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
|
||||
// This file is needed in the config subdirectory for each config supporting coverage.
|
||||
// It defines which extensions are enabled for that config.
|
||||
|
||||
`define COVER_RV32I
|
||||
`define COVER_RV32M
|
||||
`define COVER_RV32F
|
||||
`include "coverage/RV32I_coverage.svh"
|
||||
`include "coverage/RV32M_coverage.svh"
|
||||
`include "coverage/RV32F_coverage.svh"
|
||||
13
config/rv64gc/coverage.svh
Normal file
13
config/rv64gc/coverage.svh
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
// coverage.svh
|
||||
// David_Harris@hmc.edu 7 September 2024
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
|
||||
// This file is needed in the config subdirectory for each config supporting coverage.
|
||||
// It defines which extensions are enabled for that config.
|
||||
|
||||
`define COVER_RV64I
|
||||
`define COVER_RV64M
|
||||
`define COVER_RV64F
|
||||
`include "coverage/RV64I_coverage.svh"
|
||||
`include "coverage/RV64M_coverage.svh"
|
||||
`include "coverage/RV64F_coverage.svh"
|
||||
|
|
@ -7,7 +7,7 @@ SECTIONS
|
|||
.text : { *(.text.init) *(.text) }
|
||||
. = ALIGN(0x1000);
|
||||
.tohost : { *(.tohost) }
|
||||
. = ALIGN(0x1000);
|
||||
. = ALIGN(0x4000);
|
||||
.data : { *(.data) }
|
||||
.data.string : { *(.data.string)}
|
||||
. = ALIGN(0x1000);
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
# This clock is not used by wally or the AHB Bus. However it is used by the AXI BUS on the DD3 IP.
|
||||
|
||||
#create_generated_clock -name CLKDiv64_Gen -source [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/I0] -multiply_by 1 -divide_by 1 [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/O]
|
||||
create_generated_clock -name SPISDCClock -source [get_pins clk_out3_xlnx_mmcm] -multiply_by 1 -divide_by 1 [get_pins wallypipelinedsoc/uncore.uncore/sdc.sdc/SPICLK]
|
||||
create_generated_clock -name SPISDCClock -source [get_pins mmcm/clk_out3] -multiply_by 1 -divide_by 1 [get_pins wallypipelinedsoc/uncoregen.uncore/sdc.sdc/SPICLK]
|
||||
|
||||
##### clock #####
|
||||
set_property PACKAGE_PIN E3 [get_ports default_100mhz_clk]
|
||||
|
|
@ -45,8 +45,8 @@ set_property IOSTANDARD LVCMOS33 [get_ports {GPI[3]}]
|
|||
set_property IOSTANDARD LVCMOS33 [get_ports {GPI[2]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {GPI[1]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {GPI[0]}]
|
||||
set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -min -add_delay 0.000 [get_ports {GPI[*]}]
|
||||
set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 0.000 [get_ports {GPI[*]}]
|
||||
set_input_delay -clock [get_clocks clk_out3_mmcm] -min -add_delay 0.000 [get_ports {GPI[*]}]
|
||||
set_input_delay -clock [get_clocks clk_out3_mmcm] -max -add_delay 0.000 [get_ports {GPI[*]}]
|
||||
set_max_delay -from [get_ports {GPI[*]}] 20.000
|
||||
|
||||
##### GPO ####
|
||||
|
|
@ -62,8 +62,8 @@ set_property IOSTANDARD LVCMOS33 [get_ports {GPO[1]}]
|
|||
set_property IOSTANDARD LVCMOS33 [get_ports {GPO[0]}]
|
||||
set_max_delay -to [get_ports {GPO[*]}] 20.000
|
||||
|
||||
set_output_delay -clock [get_clocks clk_out3_xlnx_mmcm] -min -add_delay 0.000 [get_ports {GPO[*]}]
|
||||
set_output_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 0.000 [get_ports {GPO[*]}]
|
||||
set_output_delay -clock [get_clocks clk_out3_mmcm] -min -add_delay 0.000 [get_ports {GPO[*]}]
|
||||
set_output_delay -clock [get_clocks clk_out3_mmcm] -max -add_delay 0.000 [get_ports {GPO[*]}]
|
||||
|
||||
|
||||
##### UART #####
|
||||
|
|
@ -75,24 +75,24 @@ set_max_delay -to [get_ports UARTSout] 20.000
|
|||
set_property IOSTANDARD LVCMOS33 [get_ports UARTSin]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports UARTSout]
|
||||
set_property DRIVE 4 [get_ports UARTSout]
|
||||
set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -min -add_delay 0.000 [get_ports UARTSin]
|
||||
set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 0.000 [get_ports UARTSin]
|
||||
set_output_delay -clock [get_clocks clk_out3_xlnx_mmcm] -min -add_delay 0.000 [get_ports UARTSout]
|
||||
set_output_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 0.000 [get_ports UARTSout]
|
||||
set_input_delay -clock [get_clocks clk_out3_mmcm] -min -add_delay 0.000 [get_ports UARTSin]
|
||||
set_input_delay -clock [get_clocks clk_out3_mmcm] -max -add_delay 0.000 [get_ports UARTSin]
|
||||
set_output_delay -clock [get_clocks clk_out3_mmcm] -min -add_delay 0.000 [get_ports UARTSout]
|
||||
set_output_delay -clock [get_clocks clk_out3_mmcm] -max -add_delay 0.000 [get_ports UARTSout]
|
||||
|
||||
|
||||
##### reset #####
|
||||
#************** reset is inverted
|
||||
set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -min -add_delay 2.000 [get_ports resetn]
|
||||
set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 2.000 [get_ports resetn]
|
||||
set_input_delay -clock [get_clocks clk_out3_mmcm] -min -add_delay 2.000 [get_ports resetn]
|
||||
set_input_delay -clock [get_clocks clk_out3_mmcm] -max -add_delay 2.000 [get_ports resetn]
|
||||
set_max_delay -from [get_ports resetn] 20.000
|
||||
set_false_path -from [get_ports resetn]
|
||||
set_property PACKAGE_PIN C2 [get_ports resetn]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports resetn]
|
||||
|
||||
|
||||
set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -min -add_delay 2.000 [get_ports south_reset]
|
||||
set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 2.000 [get_ports south_reset]
|
||||
set_input_delay -clock [get_clocks clk_out3_mmcm] -min -add_delay 2.000 [get_ports south_reset]
|
||||
set_input_delay -clock [get_clocks clk_out3_mmcm] -max -add_delay 2.000 [get_ports south_reset]
|
||||
set_max_delay -from [get_ports south_reset] 20.000
|
||||
set_false_path -from [get_ports south_reset]
|
||||
set_property PACKAGE_PIN D9 [get_ports south_reset]
|
||||
|
|
@ -220,77 +220,77 @@ set_property IOSTANDARD SSTL135 [get_ports {ddr3_odt[0]}]
|
|||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_cs_n[0]}]
|
||||
|
||||
|
||||
set_properity PACKAGE_PIN K5 [get_ports ddr3_dq[0]]
|
||||
set_properity PACKAGE_PIN L3 [get_ports ddr3_dq[1]]
|
||||
set_properity PACKAGE_PIN K3 [get_ports ddr3_dq[2]]
|
||||
set_properity PACKAGE_PIN L6 [get_ports ddr3_dq[3]]
|
||||
set_properity PACKAGE_PIN M3 [get_ports ddr3_dq[4]]
|
||||
set_properity PACKAGE_PIN M1 [get_ports ddr3_dq[5]]
|
||||
set_properity PACKAGE_PIN L4 [get_ports ddr3_dq[6]]
|
||||
set_properity PACKAGE_PIN M2 [get_ports ddr3_dq[7]]
|
||||
set_properity PACKAGE_PIN V4 [get_ports ddr3_dq[8]]
|
||||
set_properity PACKAGE_PIN T5 [get_ports ddr3_dq[9]]
|
||||
set_properity PACKAGE_PIN U4 [get_ports ddr3_dq[10]]
|
||||
set_properity PACKAGE_PIN V5 [get_ports ddr3_dq[11]]
|
||||
set_properity PACKAGE_PIN V1 [get_ports ddr3_dq[12]]
|
||||
set_properity PACKAGE_PIN T3 [get_ports ddr3_dq[13]]
|
||||
set_properity PACKAGE_PIN U3 [get_ports ddr3_dq[14]]
|
||||
set_properity PACKAGE_PIN R3 [get_ports ddr3_dq[15]]
|
||||
set_properity PACKAGE_PIN L1 [get_ports ddr3_dm[0]]
|
||||
set_properity PACKAGE_PIN U1 [get_ports ddr3_dm[1]]
|
||||
set_properity PACKAGE_PIN N2 [get_ports ddr3_dqs_p[0]]
|
||||
set_properity PACKAGE_PIN N1 [get_ports ddr3_dqs_n[0]]
|
||||
set_properity PACKAGE_PIN U2 [get_ports ddr3_dqs_p[1]]
|
||||
set_properity PACKAGE_PIN V2 [get_ports ddr3_dqs_n[1]]
|
||||
set_properity PACKAGE_PIN T8 [get_ports ddr3_addr[13]]
|
||||
set_properity PACKAGE_PIN T6 [get_ports ddr3_addr[12]]
|
||||
set_properity PACKAGE_PIN U6 [get_ports ddr3_addr[11]]
|
||||
set_properity PACKAGE_PIN R6 [get_ports ddr3_addr[10]]
|
||||
set_properity PACKAGE_PIN V7 [get_ports ddr3_addr[9]]
|
||||
set_properity PACKAGE_PIN R8 [get_ports ddr3_addr[8]]
|
||||
set_properity PACKAGE_PIN U7 [get_ports ddr3_addr[7]]
|
||||
set_properity PACKAGE_PIN V6 [get_ports ddr3_addr[6]]
|
||||
set_properity PACKAGE_PIN R7 [get_ports ddr3_addr[5]]
|
||||
set_properity PACKAGE_PIN N6 [get_ports ddr3_addr[4]]
|
||||
set_properity PACKAGE_PIN T1 [get_ports ddr3_addr[3]]
|
||||
set_properity PACKAGE_PIN N4 [get_ports ddr3_addr[2]]
|
||||
set_properity PACKAGE_PIN M6 [get_ports ddr3_addr[1]]
|
||||
set_properity PACKAGE_PIN R2 [get_ports ddr3_addr[0]]
|
||||
set_properity PACKAGE_PIN P2 [get_ports ddr3_ba[2]]
|
||||
set_properity PACKAGE_PIN P4 [get_ports ddr3_ba[1]]
|
||||
set_properity PACKAGE_PIN R1 [get_ports ddr3_ba[0]]
|
||||
set_properity PACKAGE_PIN U9 [get_ports ddr3_ck_p[0]]
|
||||
set_properity PACKAGE_PIN V9 [get_ports ddr3_ck_n[0]]
|
||||
set_properity PACKAGE_PIN P3 [get_ports ddr3_ras_n]
|
||||
set_properity PACKAGE_PIN M4 [get_ports ddr3_cas_n]
|
||||
set_properity PACKAGE_PIN P5 [get_ports ddr3_we_n]
|
||||
set_properity PACKAGE_PIN K6 [get_ports ddr3_reset_n]
|
||||
set_properity PACKAGE_PIN N5 [get_ports ddr3_cke[0]]
|
||||
set_properity PACKAGE_PIN R5 [get_ports ddr3_odt[0]]
|
||||
set_properity PACKAGE_PIN U8 [get_ports ddr3_cs_n[0]]
|
||||
set_property PACKAGE_PIN K5 [get_ports ddr3_dq[0]]
|
||||
set_property PACKAGE_PIN L3 [get_ports ddr3_dq[1]]
|
||||
set_property PACKAGE_PIN K3 [get_ports ddr3_dq[2]]
|
||||
set_property PACKAGE_PIN L6 [get_ports ddr3_dq[3]]
|
||||
set_property PACKAGE_PIN M3 [get_ports ddr3_dq[4]]
|
||||
set_property PACKAGE_PIN M1 [get_ports ddr3_dq[5]]
|
||||
set_property PACKAGE_PIN L4 [get_ports ddr3_dq[6]]
|
||||
set_property PACKAGE_PIN M2 [get_ports ddr3_dq[7]]
|
||||
set_property PACKAGE_PIN V4 [get_ports ddr3_dq[8]]
|
||||
set_property PACKAGE_PIN T5 [get_ports ddr3_dq[9]]
|
||||
set_property PACKAGE_PIN U4 [get_ports ddr3_dq[10]]
|
||||
set_property PACKAGE_PIN V5 [get_ports ddr3_dq[11]]
|
||||
set_property PACKAGE_PIN V1 [get_ports ddr3_dq[12]]
|
||||
set_property PACKAGE_PIN T3 [get_ports ddr3_dq[13]]
|
||||
set_property PACKAGE_PIN U3 [get_ports ddr3_dq[14]]
|
||||
set_property PACKAGE_PIN R3 [get_ports ddr3_dq[15]]
|
||||
set_property PACKAGE_PIN L1 [get_ports ddr3_dm[0]]
|
||||
set_property PACKAGE_PIN U1 [get_ports ddr3_dm[1]]
|
||||
set_property PACKAGE_PIN N2 [get_ports ddr3_dqs_p[0]]
|
||||
set_property PACKAGE_PIN N1 [get_ports ddr3_dqs_n[0]]
|
||||
set_property PACKAGE_PIN U2 [get_ports ddr3_dqs_p[1]]
|
||||
set_property PACKAGE_PIN V2 [get_ports ddr3_dqs_n[1]]
|
||||
set_property PACKAGE_PIN T8 [get_ports ddr3_addr[13]]
|
||||
set_property PACKAGE_PIN T6 [get_ports ddr3_addr[12]]
|
||||
set_property PACKAGE_PIN U6 [get_ports ddr3_addr[11]]
|
||||
set_property PACKAGE_PIN R6 [get_ports ddr3_addr[10]]
|
||||
set_property PACKAGE_PIN V7 [get_ports ddr3_addr[9]]
|
||||
set_property PACKAGE_PIN R8 [get_ports ddr3_addr[8]]
|
||||
set_property PACKAGE_PIN U7 [get_ports ddr3_addr[7]]
|
||||
set_property PACKAGE_PIN V6 [get_ports ddr3_addr[6]]
|
||||
set_property PACKAGE_PIN R7 [get_ports ddr3_addr[5]]
|
||||
set_property PACKAGE_PIN N6 [get_ports ddr3_addr[4]]
|
||||
set_property PACKAGE_PIN T1 [get_ports ddr3_addr[3]]
|
||||
set_property PACKAGE_PIN N4 [get_ports ddr3_addr[2]]
|
||||
set_property PACKAGE_PIN M6 [get_ports ddr3_addr[1]]
|
||||
set_property PACKAGE_PIN R2 [get_ports ddr3_addr[0]]
|
||||
set_property PACKAGE_PIN P2 [get_ports ddr3_ba[2]]
|
||||
set_property PACKAGE_PIN P4 [get_ports ddr3_ba[1]]
|
||||
set_property PACKAGE_PIN R1 [get_ports ddr3_ba[0]]
|
||||
set_property PACKAGE_PIN U9 [get_ports ddr3_ck_p[0]]
|
||||
set_property PACKAGE_PIN V9 [get_ports ddr3_ck_n[0]]
|
||||
set_property PACKAGE_PIN P3 [get_ports ddr3_ras_n]
|
||||
set_property PACKAGE_PIN M4 [get_ports ddr3_cas_n]
|
||||
set_property PACKAGE_PIN P5 [get_ports ddr3_we_n]
|
||||
set_property PACKAGE_PIN K6 [get_ports ddr3_reset_n]
|
||||
set_property PACKAGE_PIN N5 [get_ports ddr3_cke[0]]
|
||||
set_property PACKAGE_PIN R5 [get_ports ddr3_odt[0]]
|
||||
set_property PACKAGE_PIN U8 [get_ports ddr3_cs_n[0]]
|
||||
|
||||
|
||||
create_clock -period 40.000 -name VIRTUAL_clk_out3_mmcm -waveform {0.000 20.000}
|
||||
set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 10.000 [get_ports {GPI[*]}]
|
||||
set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports {GPI[*]}]
|
||||
set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 10.000 [get_ports SDCCD]
|
||||
set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports SDCCD]
|
||||
set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 10.000 [get_ports SDCIn]
|
||||
set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports SDCIn]
|
||||
set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 10.000 [get_ports SDCWP]
|
||||
set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports SDCWP]
|
||||
set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 10.000 [get_ports UARTSin]
|
||||
set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports UARTSin]
|
||||
create_clock -period 12.000 -name VIRTUAL_clk_pll_i -waveform {0.000 6.000}
|
||||
set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 0.000 [get_ports {GPO[*]}]
|
||||
set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports {GPO[*]}]
|
||||
set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 0.000 [get_ports SDCCLK]
|
||||
set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 0.000 [get_ports SDCCLK]
|
||||
set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 0.000 [get_ports SDCCS]
|
||||
set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports SDCCS]
|
||||
set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 0.000 [get_ports SDCCmd]
|
||||
set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports SDCCmd]
|
||||
set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 0.000 [get_ports UARTSout]
|
||||
set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports UARTSout]
|
||||
#create_clock -period 50.000 -name VIRTUAL_clk_out3_mmcm -waveform {0.000 25.000}
|
||||
#set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 10.000 [get_ports {GPI[*]}]
|
||||
#set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports {GPI[*]}]
|
||||
#set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 10.000 [get_ports SDCCD]
|
||||
#set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports SDCCD]
|
||||
#set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 10.000 [get_ports SDCIn]
|
||||
#set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports SDCIn]
|
||||
#set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 10.000 [get_ports SDCWP]
|
||||
#set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports SDCWP]
|
||||
#set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 10.000 [get_ports UARTSin]
|
||||
#set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports UARTSin]
|
||||
#create_clock -period 12.000 -name VIRTUAL_clk_pll_i -waveform {0.000 6.000}
|
||||
#set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 0.000 [get_ports {GPO[*]}]
|
||||
#set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports {GPO[*]}]
|
||||
#set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 0.000 [get_ports SDCCLK]
|
||||
#set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 0.000 [get_ports SDCCLK]
|
||||
#set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 0.000 [get_ports SDCCS]
|
||||
#set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports SDCCS]
|
||||
#set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 0.000 [get_ports SDCCmd]
|
||||
#set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports SDCCmd]
|
||||
#set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 0.000 [get_ports UARTSout]
|
||||
#set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports UARTSout]
|
||||
#set_output_delay -clock [get_clocks VIRTUAL_clk_pll_i] -min -add_delay 0.000 [get_ports ddr3_reset_n]
|
||||
#set_output_delay -clock [get_clocks VIRTUAL_clk_pll_i] -max -add_delay 80.000 [get_ports ddr3_reset_n]
|
||||
|
|
|
|||
|
|
@ -83,12 +83,20 @@ set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_port
|
|||
##### SD Card I/O #####
|
||||
|
||||
# create the generated SPICLK
|
||||
#create_generated_clock -name SPISDCClock -source [get_pins ddr4/addn_ui_clkout1] -multiply_by 1 -divide_by 1 [get_pins wallypipelinedsoc/uncoregen.uncore/spi.spi/SPICLK]
|
||||
create_generated_clock -name SPISDCClock -source [get_pins ddr4/addn_ui_clkout1] -multiply_by 1 -divide_by 1 [get_pins wallypipelinedsoc/uncoregen.uncore/spi.spi/SPICLK]
|
||||
|
||||
set_output_delay -clock [get_clocks mmcm_clkout1] 0 [get_ports {SDCCS}]
|
||||
set_input_delay -clock [get_clocks mmcm_clkout1] 0 [get_ports {SDCIn}]
|
||||
set_output_delay -clock [get_clocks mmcm_clkout1] 0 [get_ports {SDCCmd}]
|
||||
set_output_delay -clock [get_clocks mmcm_clkout1] 0.000 [get_ports SDCCLK]
|
||||
set_output_delay -clock [get_clocks SPISDCClock] -max 5.0 [get_ports {SDCCS}]
|
||||
set_output_delay -clock [get_clocks SPISDCClock] -min -5.0 [get_ports {SDCCS}]
|
||||
set_input_delay -clock [get_clocks SPISDCClock] -max 5.0 [get_ports {SDCIn}]
|
||||
set_input_delay -clock [get_clocks SPISDCClock] -min -5.0 [get_ports {SDCIn}]
|
||||
set_input_delay -clock [get_clocks SPISDCClock] -max 5.0 [get_ports {SDCCD}]
|
||||
set_input_delay -clock [get_clocks SPISDCClock] -min -5.0 [get_ports {SDCCD}]
|
||||
set_input_delay -clock [get_clocks SPISDCClock] -max 5.0 [get_ports {SDCWP}]
|
||||
set_input_delay -clock [get_clocks SPISDCClock] -min -5.0 [get_ports {SDCWP}]
|
||||
set_output_delay -clock [get_clocks SPISDCClock] -max 5.0 [get_ports {SDCCmd}]
|
||||
set_output_delay -clock [get_clocks SPISDCClock] -min -5.0 [get_ports {SDCCmd}]
|
||||
create_generated_clock -name SPISDCClockOut -multiply_by 1 -source [get_pins sdcclkoddr/C] [get_ports SDCCLK]
|
||||
set_clock_latency -source -max 3.0 [get_ports SDCCLK]
|
||||
|
||||
|
||||
set_property -dict {PACKAGE_PIN BC14 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCCS}]
|
||||
|
|
|
|||
|
|
@ -5,18 +5,3 @@ wally/wallypipelinedcore.sv: logic InstrM
|
|||
lsu/lsu.sv: logic IEUAdrM
|
||||
lsu/lsu.sv: logic MemRWM
|
||||
mmu/hptw.sv: logic SATP_REGW
|
||||
uncore/spi_apb.sv: logic ShiftIn
|
||||
uncore/spi_apb.sv: logic ReceiveShiftReg
|
||||
uncore/spi_apb.sv: logic SCLKenable
|
||||
uncore/spi_apb.sv: logic SampleEdge
|
||||
uncore/spi_apb.sv: logic Active
|
||||
uncore/spi_apb.sv: statetype state
|
||||
uncore/spi_apb.sv: typedef rsrstatetype
|
||||
uncore/spi_apb.sv: logic SPICLK
|
||||
uncore/spi_apb.sv: logic SPIOut
|
||||
uncore/spi_apb.sv: logic SPICS
|
||||
uncore/spi_apb.sv: logic SckMode
|
||||
uncore/spi_apb.sv: logic SckDiv
|
||||
uncore/spi_apb.sv: logic ShiftEdge
|
||||
uncore/spi_apb.sv: logic TransmitShiftRegLoad
|
||||
uncore/spi_apb.sv: logic TransmitShiftReg
|
||||
|
|
|
|||
36
fpga/constraints/marked_debug_spi.txt
Normal file
36
fpga/constraints/marked_debug_spi.txt
Normal file
|
|
@ -0,0 +1,36 @@
|
|||
wally/wallypipelinedcore.sv: logic PCM
|
||||
wally/wallypipelinedcore.sv: logic TrapM
|
||||
wally/wallypipelinedcore.sv: logic InstrValidM
|
||||
wally/wallypipelinedcore.sv: logic InstrM
|
||||
lsu/lsu.sv: logic IEUAdrM
|
||||
lsu/lsu.sv: logic MemRWM
|
||||
mmu/hptw.sv: logic SATP_REGW
|
||||
uncore/spi_apb.sv: logic ShiftIn
|
||||
uncore/spi_apb.sv: logic ReceiveShiftReg
|
||||
uncore/spi_apb.sv: logic SCLKenable
|
||||
uncore/spi_apb.sv: logic SampleEdge
|
||||
uncore/spi_apb.sv: logic Active
|
||||
uncore/spi_apb.sv: statetype state
|
||||
uncore/spi_apb.sv: typedef rsrstatetype
|
||||
uncore/spi_apb.sv: logic SPICLK
|
||||
uncore/spi_apb.sv: logic SPIOut
|
||||
uncore/spi_apb.sv: logic SPICS
|
||||
uncore/spi_apb.sv: logic SckMode
|
||||
uncore/spi_apb.sv: logic SckDiv
|
||||
uncore/spi_apb.sv: logic ShiftEdge
|
||||
uncore/spi_apb.sv: logic TransmitShiftRegLoadSingleCycle
|
||||
uncore/spi_apb.sv: logic TransmitShiftReg
|
||||
uncore/spi_apb.sv: logic TransmitData
|
||||
uncore/spi_apb.sv: logic ReceiveData
|
||||
uncore/spi_apb.sv: logic ReceiveShiftRegEndian
|
||||
uncore/spi_apb.sv: logic TransmitShiftReg
|
||||
uncore/spi_apb.sv: logic TransmitShift
|
||||
uncore/spi_apb.sv: logic ReceiveShiftFullDelay
|
||||
uncore/spi_apb.sv: logic TransmitShiftEmpty
|
||||
uncore/spi_apb.sv: logic ReceiveFIFOWriteFull
|
||||
uncore/spi_apb.sv: logic ReceiveFIFOReadIncrement
|
||||
uncore/spi_apb.sv: logic ReceiveFIFOReadEmpty
|
||||
uncore/spi_apb.sv: logic TransmitFIFOWriteIncrement
|
||||
uncore/spi_apb.sv: logic TransmitFIFOReadIncrement
|
||||
uncore/spi_apb.sv: logic TransmitFIFOWriteFull
|
||||
uncore/spi_apb.sv: logic TransmitFIFOReadEmpty
|
||||
197
fpga/constraints/small-debug-spi.xdc
Normal file
197
fpga/constraints/small-debug-spi.xdc
Normal file
|
|
@ -0,0 +1,197 @@
|
|||
create_debug_core u_ila_0 ila
|
||||
|
||||
|
||||
|
||||
|
||||
set_property C_DATA_DEPTH 65536 [get_debug_cores u_ila_0]
|
||||
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
|
||||
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
|
||||
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
|
||||
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
|
||||
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
|
||||
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
|
||||
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
|
||||
startgroup
|
||||
set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0 ]
|
||||
set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0 ]
|
||||
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0 ]
|
||||
set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0 ]
|
||||
endgroup
|
||||
connect_debug_port u_ila_0/clk [get_nets CPUCLK]
|
||||
|
||||
set_property port_width 64 [get_debug_ports u_ila_0/probe0]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
|
||||
connect_debug_port u_ila_0/probe0 [get_nets [list {wallypipelinedsoc/core/PCM[0]} {wallypipelinedsoc/core/PCM[1]} {wallypipelinedsoc/core/PCM[2]} {wallypipelinedsoc/core/PCM[3]} {wallypipelinedsoc/core/PCM[4]} {wallypipelinedsoc/core/PCM[5]} {wallypipelinedsoc/core/PCM[6]} {wallypipelinedsoc/core/PCM[7]} {wallypipelinedsoc/core/PCM[8]} {wallypipelinedsoc/core/PCM[9]} {wallypipelinedsoc/core/PCM[10]} {wallypipelinedsoc/core/PCM[11]} {wallypipelinedsoc/core/PCM[12]} {wallypipelinedsoc/core/PCM[13]} {wallypipelinedsoc/core/PCM[14]} {wallypipelinedsoc/core/PCM[15]} {wallypipelinedsoc/core/PCM[16]} {wallypipelinedsoc/core/PCM[17]} {wallypipelinedsoc/core/PCM[18]} {wallypipelinedsoc/core/PCM[19]} {wallypipelinedsoc/core/PCM[20]} {wallypipelinedsoc/core/PCM[21]} {wallypipelinedsoc/core/PCM[22]} {wallypipelinedsoc/core/PCM[23]} {wallypipelinedsoc/core/PCM[24]} {wallypipelinedsoc/core/PCM[25]} {wallypipelinedsoc/core/PCM[26]} {wallypipelinedsoc/core/PCM[27]} {wallypipelinedsoc/core/PCM[28]} {wallypipelinedsoc/core/PCM[29]} {wallypipelinedsoc/core/PCM[30]} {wallypipelinedsoc/core/PCM[31]} {wallypipelinedsoc/core/PCM[32]} {wallypipelinedsoc/core/PCM[33]} {wallypipelinedsoc/core/PCM[34]} {wallypipelinedsoc/core/PCM[35]} {wallypipelinedsoc/core/PCM[36]} {wallypipelinedsoc/core/PCM[37]} {wallypipelinedsoc/core/PCM[38]} {wallypipelinedsoc/core/PCM[39]} {wallypipelinedsoc/core/PCM[40]} {wallypipelinedsoc/core/PCM[41]} {wallypipelinedsoc/core/PCM[42]} {wallypipelinedsoc/core/PCM[43]} {wallypipelinedsoc/core/PCM[44]} {wallypipelinedsoc/core/PCM[45]} {wallypipelinedsoc/core/PCM[46]} {wallypipelinedsoc/core/PCM[47]} {wallypipelinedsoc/core/PCM[48]} {wallypipelinedsoc/core/PCM[49]} {wallypipelinedsoc/core/PCM[50]} {wallypipelinedsoc/core/PCM[51]} {wallypipelinedsoc/core/PCM[52]} {wallypipelinedsoc/core/PCM[53]} {wallypipelinedsoc/core/PCM[54]} {wallypipelinedsoc/core/PCM[55]} {wallypipelinedsoc/core/PCM[56]} {wallypipelinedsoc/core/PCM[57]} {wallypipelinedsoc/core/PCM[58]} {wallypipelinedsoc/core/PCM[59]} {wallypipelinedsoc/core/PCM[60]} {wallypipelinedsoc/core/PCM[61]} {wallypipelinedsoc/core/PCM[62]} {wallypipelinedsoc/core/PCM[63]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe1]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
|
||||
connect_debug_port u_ila_0/probe1 [get_nets [list wallypipelinedsoc/core/TrapM ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe2]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
|
||||
connect_debug_port u_ila_0/probe2 [get_nets [list wallypipelinedsoc/core/InstrValidM ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 32 [get_debug_ports u_ila_0/probe3]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
|
||||
connect_debug_port u_ila_0/probe3 [get_nets [list {wallypipelinedsoc/core/InstrM[0]} {wallypipelinedsoc/core/InstrM[1]} {wallypipelinedsoc/core/InstrM[2]} {wallypipelinedsoc/core/InstrM[3]} {wallypipelinedsoc/core/InstrM[4]} {wallypipelinedsoc/core/InstrM[5]} {wallypipelinedsoc/core/InstrM[6]} {wallypipelinedsoc/core/InstrM[7]} {wallypipelinedsoc/core/InstrM[8]} {wallypipelinedsoc/core/InstrM[9]} {wallypipelinedsoc/core/InstrM[10]} {wallypipelinedsoc/core/InstrM[11]} {wallypipelinedsoc/core/InstrM[12]} {wallypipelinedsoc/core/InstrM[13]} {wallypipelinedsoc/core/InstrM[14]} {wallypipelinedsoc/core/InstrM[15]} {wallypipelinedsoc/core/InstrM[16]} {wallypipelinedsoc/core/InstrM[17]} {wallypipelinedsoc/core/InstrM[18]} {wallypipelinedsoc/core/InstrM[19]} {wallypipelinedsoc/core/InstrM[20]} {wallypipelinedsoc/core/InstrM[21]} {wallypipelinedsoc/core/InstrM[22]} {wallypipelinedsoc/core/InstrM[23]} {wallypipelinedsoc/core/InstrM[24]} {wallypipelinedsoc/core/InstrM[25]} {wallypipelinedsoc/core/InstrM[26]} {wallypipelinedsoc/core/InstrM[27]} {wallypipelinedsoc/core/InstrM[28]} {wallypipelinedsoc/core/InstrM[29]} {wallypipelinedsoc/core/InstrM[30]} {wallypipelinedsoc/core/InstrM[31]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 2 [get_debug_ports u_ila_0/probe4]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
|
||||
connect_debug_port u_ila_0/probe4 [get_nets [list {wallypipelinedsoc/core/lsu/MemRWM[0]} {wallypipelinedsoc/core/lsu/MemRWM[1]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 64 [get_debug_ports u_ila_0/probe5]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
|
||||
connect_debug_port u_ila_0/probe5 [get_nets [list {wallypipelinedsoc/core/lsu/IEUAdrM[0]} {wallypipelinedsoc/core/lsu/IEUAdrM[1]} {wallypipelinedsoc/core/lsu/IEUAdrM[2]} {wallypipelinedsoc/core/lsu/IEUAdrM[3]} {wallypipelinedsoc/core/lsu/IEUAdrM[4]} {wallypipelinedsoc/core/lsu/IEUAdrM[5]} {wallypipelinedsoc/core/lsu/IEUAdrM[6]} {wallypipelinedsoc/core/lsu/IEUAdrM[7]} {wallypipelinedsoc/core/lsu/IEUAdrM[8]} {wallypipelinedsoc/core/lsu/IEUAdrM[9]} {wallypipelinedsoc/core/lsu/IEUAdrM[10]} {wallypipelinedsoc/core/lsu/IEUAdrM[11]} {wallypipelinedsoc/core/lsu/IEUAdrM[12]} {wallypipelinedsoc/core/lsu/IEUAdrM[13]} {wallypipelinedsoc/core/lsu/IEUAdrM[14]} {wallypipelinedsoc/core/lsu/IEUAdrM[15]} {wallypipelinedsoc/core/lsu/IEUAdrM[16]} {wallypipelinedsoc/core/lsu/IEUAdrM[17]} {wallypipelinedsoc/core/lsu/IEUAdrM[18]} {wallypipelinedsoc/core/lsu/IEUAdrM[19]} {wallypipelinedsoc/core/lsu/IEUAdrM[20]} {wallypipelinedsoc/core/lsu/IEUAdrM[21]} {wallypipelinedsoc/core/lsu/IEUAdrM[22]} {wallypipelinedsoc/core/lsu/IEUAdrM[23]} {wallypipelinedsoc/core/lsu/IEUAdrM[24]} {wallypipelinedsoc/core/lsu/IEUAdrM[25]} {wallypipelinedsoc/core/lsu/IEUAdrM[26]} {wallypipelinedsoc/core/lsu/IEUAdrM[27]} {wallypipelinedsoc/core/lsu/IEUAdrM[28]} {wallypipelinedsoc/core/lsu/IEUAdrM[29]} {wallypipelinedsoc/core/lsu/IEUAdrM[30]} {wallypipelinedsoc/core/lsu/IEUAdrM[31]} {wallypipelinedsoc/core/lsu/IEUAdrM[32]} {wallypipelinedsoc/core/lsu/IEUAdrM[33]} {wallypipelinedsoc/core/lsu/IEUAdrM[34]} {wallypipelinedsoc/core/lsu/IEUAdrM[35]} {wallypipelinedsoc/core/lsu/IEUAdrM[36]} {wallypipelinedsoc/core/lsu/IEUAdrM[37]} {wallypipelinedsoc/core/lsu/IEUAdrM[38]} {wallypipelinedsoc/core/lsu/IEUAdrM[39]} {wallypipelinedsoc/core/lsu/IEUAdrM[40]} {wallypipelinedsoc/core/lsu/IEUAdrM[41]} {wallypipelinedsoc/core/lsu/IEUAdrM[42]} {wallypipelinedsoc/core/lsu/IEUAdrM[43]} {wallypipelinedsoc/core/lsu/IEUAdrM[44]} {wallypipelinedsoc/core/lsu/IEUAdrM[45]} {wallypipelinedsoc/core/lsu/IEUAdrM[46]} {wallypipelinedsoc/core/lsu/IEUAdrM[47]} {wallypipelinedsoc/core/lsu/IEUAdrM[48]} {wallypipelinedsoc/core/lsu/IEUAdrM[49]} {wallypipelinedsoc/core/lsu/IEUAdrM[50]} {wallypipelinedsoc/core/lsu/IEUAdrM[51]} {wallypipelinedsoc/core/lsu/IEUAdrM[52]} {wallypipelinedsoc/core/lsu/IEUAdrM[53]} {wallypipelinedsoc/core/lsu/IEUAdrM[54]} {wallypipelinedsoc/core/lsu/IEUAdrM[55]} {wallypipelinedsoc/core/lsu/IEUAdrM[56]} {wallypipelinedsoc/core/lsu/IEUAdrM[57]} {wallypipelinedsoc/core/lsu/IEUAdrM[58]} {wallypipelinedsoc/core/lsu/IEUAdrM[59]} {wallypipelinedsoc/core/lsu/IEUAdrM[60]} {wallypipelinedsoc/core/lsu/IEUAdrM[61]} {wallypipelinedsoc/core/lsu/IEUAdrM[62]} {wallypipelinedsoc/core/lsu/IEUAdrM[63]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 64 [get_debug_ports u_ila_0/probe6]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
|
||||
connect_debug_port u_ila_0/probe6 [get_nets [list {wallypipelinedsoc/core/lsu/ReadDataM[0]} {wallypipelinedsoc/core/lsu/ReadDataM[1]} {wallypipelinedsoc/core/lsu/ReadDataM[2]} {wallypipelinedsoc/core/lsu/ReadDataM[3]} {wallypipelinedsoc/core/lsu/ReadDataM[4]} {wallypipelinedsoc/core/lsu/ReadDataM[5]} {wallypipelinedsoc/core/lsu/ReadDataM[6]} {wallypipelinedsoc/core/lsu/ReadDataM[7]} {wallypipelinedsoc/core/lsu/ReadDataM[8]} {wallypipelinedsoc/core/lsu/ReadDataM[9]} {wallypipelinedsoc/core/lsu/ReadDataM[10]} {wallypipelinedsoc/core/lsu/ReadDataM[11]} {wallypipelinedsoc/core/lsu/ReadDataM[12]} {wallypipelinedsoc/core/lsu/ReadDataM[13]} {wallypipelinedsoc/core/lsu/ReadDataM[14]} {wallypipelinedsoc/core/lsu/ReadDataM[15]} {wallypipelinedsoc/core/lsu/ReadDataM[16]} {wallypipelinedsoc/core/lsu/ReadDataM[17]} {wallypipelinedsoc/core/lsu/ReadDataM[18]} {wallypipelinedsoc/core/lsu/ReadDataM[19]} {wallypipelinedsoc/core/lsu/ReadDataM[20]} {wallypipelinedsoc/core/lsu/ReadDataM[21]} {wallypipelinedsoc/core/lsu/ReadDataM[22]} {wallypipelinedsoc/core/lsu/ReadDataM[23]} {wallypipelinedsoc/core/lsu/ReadDataM[24]} {wallypipelinedsoc/core/lsu/ReadDataM[25]} {wallypipelinedsoc/core/lsu/ReadDataM[26]} {wallypipelinedsoc/core/lsu/ReadDataM[27]} {wallypipelinedsoc/core/lsu/ReadDataM[28]} {wallypipelinedsoc/core/lsu/ReadDataM[29]} {wallypipelinedsoc/core/lsu/ReadDataM[30]} {wallypipelinedsoc/core/lsu/ReadDataM[31]} {wallypipelinedsoc/core/lsu/ReadDataM[32]} {wallypipelinedsoc/core/lsu/ReadDataM[33]} {wallypipelinedsoc/core/lsu/ReadDataM[34]} {wallypipelinedsoc/core/lsu/ReadDataM[35]} {wallypipelinedsoc/core/lsu/ReadDataM[36]} {wallypipelinedsoc/core/lsu/ReadDataM[37]} {wallypipelinedsoc/core/lsu/ReadDataM[38]} {wallypipelinedsoc/core/lsu/ReadDataM[39]} {wallypipelinedsoc/core/lsu/ReadDataM[40]} {wallypipelinedsoc/core/lsu/ReadDataM[41]} {wallypipelinedsoc/core/lsu/ReadDataM[42]} {wallypipelinedsoc/core/lsu/ReadDataM[43]} {wallypipelinedsoc/core/lsu/ReadDataM[44]} {wallypipelinedsoc/core/lsu/ReadDataM[45]} {wallypipelinedsoc/core/lsu/ReadDataM[46]} {wallypipelinedsoc/core/lsu/ReadDataM[47]} {wallypipelinedsoc/core/lsu/ReadDataM[48]} {wallypipelinedsoc/core/lsu/ReadDataM[49]} {wallypipelinedsoc/core/lsu/ReadDataM[50]} {wallypipelinedsoc/core/lsu/ReadDataM[51]} {wallypipelinedsoc/core/lsu/ReadDataM[52]} {wallypipelinedsoc/core/lsu/ReadDataM[53]} {wallypipelinedsoc/core/lsu/ReadDataM[54]} {wallypipelinedsoc/core/lsu/ReadDataM[55]} {wallypipelinedsoc/core/lsu/ReadDataM[56]} {wallypipelinedsoc/core/lsu/ReadDataM[57]} {wallypipelinedsoc/core/lsu/ReadDataM[58]} {wallypipelinedsoc/core/lsu/ReadDataM[59]} {wallypipelinedsoc/core/lsu/ReadDataM[60]} {wallypipelinedsoc/core/lsu/ReadDataM[61]} {wallypipelinedsoc/core/lsu/ReadDataM[62]} {wallypipelinedsoc/core/lsu/ReadDataM[63]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 64 [get_debug_ports u_ila_0/probe7]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
|
||||
connect_debug_port u_ila_0/probe7 [get_nets [list {wallypipelinedsoc/core/lsu/WriteDataM[0]} {wallypipelinedsoc/core/lsu/WriteDataM[1]} {wallypipelinedsoc/core/lsu/WriteDataM[2]} {wallypipelinedsoc/core/lsu/WriteDataM[3]} {wallypipelinedsoc/core/lsu/WriteDataM[4]} {wallypipelinedsoc/core/lsu/WriteDataM[5]} {wallypipelinedsoc/core/lsu/WriteDataM[6]} {wallypipelinedsoc/core/lsu/WriteDataM[7]} {wallypipelinedsoc/core/lsu/WriteDataM[8]} {wallypipelinedsoc/core/lsu/WriteDataM[9]} {wallypipelinedsoc/core/lsu/WriteDataM[10]} {wallypipelinedsoc/core/lsu/WriteDataM[11]} {wallypipelinedsoc/core/lsu/WriteDataM[12]} {wallypipelinedsoc/core/lsu/WriteDataM[13]} {wallypipelinedsoc/core/lsu/WriteDataM[14]} {wallypipelinedsoc/core/lsu/WriteDataM[15]} {wallypipelinedsoc/core/lsu/WriteDataM[16]} {wallypipelinedsoc/core/lsu/WriteDataM[17]} {wallypipelinedsoc/core/lsu/WriteDataM[18]} {wallypipelinedsoc/core/lsu/WriteDataM[19]} {wallypipelinedsoc/core/lsu/WriteDataM[20]} {wallypipelinedsoc/core/lsu/WriteDataM[21]} {wallypipelinedsoc/core/lsu/WriteDataM[22]} {wallypipelinedsoc/core/lsu/WriteDataM[23]} {wallypipelinedsoc/core/lsu/WriteDataM[24]} {wallypipelinedsoc/core/lsu/WriteDataM[25]} {wallypipelinedsoc/core/lsu/WriteDataM[26]} {wallypipelinedsoc/core/lsu/WriteDataM[27]} {wallypipelinedsoc/core/lsu/WriteDataM[28]} {wallypipelinedsoc/core/lsu/WriteDataM[29]} {wallypipelinedsoc/core/lsu/WriteDataM[30]} {wallypipelinedsoc/core/lsu/WriteDataM[31]} {wallypipelinedsoc/core/lsu/WriteDataM[32]} {wallypipelinedsoc/core/lsu/WriteDataM[33]} {wallypipelinedsoc/core/lsu/WriteDataM[34]} {wallypipelinedsoc/core/lsu/WriteDataM[35]} {wallypipelinedsoc/core/lsu/WriteDataM[36]} {wallypipelinedsoc/core/lsu/WriteDataM[37]} {wallypipelinedsoc/core/lsu/WriteDataM[38]} {wallypipelinedsoc/core/lsu/WriteDataM[39]} {wallypipelinedsoc/core/lsu/WriteDataM[40]} {wallypipelinedsoc/core/lsu/WriteDataM[41]} {wallypipelinedsoc/core/lsu/WriteDataM[42]} {wallypipelinedsoc/core/lsu/WriteDataM[43]} {wallypipelinedsoc/core/lsu/WriteDataM[44]} {wallypipelinedsoc/core/lsu/WriteDataM[45]} {wallypipelinedsoc/core/lsu/WriteDataM[46]} {wallypipelinedsoc/core/lsu/WriteDataM[47]} {wallypipelinedsoc/core/lsu/WriteDataM[48]} {wallypipelinedsoc/core/lsu/WriteDataM[49]} {wallypipelinedsoc/core/lsu/WriteDataM[50]} {wallypipelinedsoc/core/lsu/WriteDataM[51]} {wallypipelinedsoc/core/lsu/WriteDataM[52]} {wallypipelinedsoc/core/lsu/WriteDataM[53]} {wallypipelinedsoc/core/lsu/WriteDataM[54]} {wallypipelinedsoc/core/lsu/WriteDataM[55]} {wallypipelinedsoc/core/lsu/WriteDataM[56]} {wallypipelinedsoc/core/lsu/WriteDataM[57]} {wallypipelinedsoc/core/lsu/WriteDataM[58]} {wallypipelinedsoc/core/lsu/WriteDataM[59]} {wallypipelinedsoc/core/lsu/WriteDataM[60]} {wallypipelinedsoc/core/lsu/WriteDataM[61]} {wallypipelinedsoc/core/lsu/WriteDataM[62]} {wallypipelinedsoc/core/lsu/WriteDataM[63]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe8]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
|
||||
connect_debug_port u_ila_0/probe8 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ShiftIn} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 8 [get_debug_ports u_ila_0/probe9]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
|
||||
connect_debug_port u_ila_0/probe9 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftReg[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftReg[1]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftReg[2]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftReg[3]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftReg[4]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftReg[5]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftReg[6]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftReg[7]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe10]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
|
||||
connect_debug_port u_ila_0/probe10 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/SCLKenable} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe11]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
|
||||
connect_debug_port u_ila_0/probe11 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/SampleEdge} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe12]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
|
||||
connect_debug_port u_ila_0/probe12 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/Active} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 3 [get_debug_ports u_ila_0/probe13]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
|
||||
connect_debug_port u_ila_0/probe13 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/state[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/state[1]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/state[2]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe14]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
|
||||
connect_debug_port u_ila_0/probe14 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/SPICLK} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe15]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
|
||||
connect_debug_port u_ila_0/probe15 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/SPIOut} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe16]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
|
||||
connect_debug_port u_ila_0/probe16 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/SPICS[0]} ]]
|
||||
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 12 [get_debug_ports u_ila_0/probe17]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
|
||||
connect_debug_port u_ila_0/probe17 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/SckDiv[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/SckDiv[1]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/SckDiv[2]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/SckDiv[3]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/SckDiv[4]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/SckDiv[5]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/SckDiv[6]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/SckDiv[7]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/SckDiv[8]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/SckDiv[9]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/SckDiv[10]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/SckDiv[11]} ]]
|
||||
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 2 [get_debug_ports u_ila_0/probe18]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
|
||||
connect_debug_port u_ila_0/probe18 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/SckMode[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/SckMode[1]} ]]
|
||||
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe19]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
|
||||
connect_debug_port u_ila_0/probe19 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ShiftEdge} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 8 [get_debug_ports u_ila_0/probe20]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
|
||||
connect_debug_port u_ila_0/probe20 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitShiftReg[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitShiftReg[1]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitShiftReg[2]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitShiftReg[3]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitShiftReg[4]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitShiftReg[5]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitShiftReg[6]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitShiftReg[7]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 8 [get_debug_ports u_ila_0/probe21]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
|
||||
connect_debug_port u_ila_0/probe21 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveData[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveData[1]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveData[2]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveData[3]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveData[4]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveData[5]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveData[6]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveData[7]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 8 [get_debug_ports u_ila_0/probe22]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22]
|
||||
connect_debug_port u_ila_0/probe22 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftRegEndian[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftRegEndian[1]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftRegEndian[2]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftRegEndian[3]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftRegEndian[4]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftRegEndian[5]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftRegEndian[6]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftRegEndian[7]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 9 [get_debug_ports u_ila_0/probe23]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23]
|
||||
connect_debug_port u_ila_0/probe23 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitData[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitData[1]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitData[2]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitData[3]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitData[4]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitData[5]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitData[6]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitData[7]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitData[8]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe24]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24]
|
||||
connect_debug_port u_ila_0/probe24 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftFullDelay} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe25]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25]
|
||||
connect_debug_port u_ila_0/probe25 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitShiftRegLoadSingleCycle} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe26]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26]
|
||||
connect_debug_port u_ila_0/probe26 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitShiftEmpty} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe27]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27]
|
||||
connect_debug_port u_ila_0/probe27 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveFIFOWriteFull} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe28]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28]
|
||||
connect_debug_port u_ila_0/probe28 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveFIFOReadIncrement} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe29]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29]
|
||||
connect_debug_port u_ila_0/probe29 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveFIFOReadEmpty} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe30]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30]
|
||||
connect_debug_port u_ila_0/probe30 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitFIFOWriteIncrement} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe31]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31]
|
||||
connect_debug_port u_ila_0/probe31 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitFIFOReadIncrement} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe32]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32]
|
||||
connect_debug_port u_ila_0/probe32 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitFIFOWriteFull} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe33]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33]
|
||||
connect_debug_port u_ila_0/probe33 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitFIFOReadEmpty} ]]
|
||||
|
||||
|
||||
# the debug hub has issues with the clocks from the mmcm so lets give up an connect to the 100Mhz input clock.
|
||||
#connect_debug_port dbg_hub/clk [get_nets default_100mhz_clk]
|
||||
connect_debug_port dbg_hub/clk [get_nets CPUCLK]
|
||||
|
|
@ -7,22 +7,34 @@ all: ArtyA7
|
|||
ArtyA7: export XILINX_PART := xc7a100tcsg324-1
|
||||
ArtyA7: export XILINX_BOARD := digilentinc.com:arty-a7-100:part0:1.1
|
||||
ArtyA7: export board := ArtyA7
|
||||
ArtyA7: export SYSTEMCLOCK := 20000000
|
||||
ArtyA7: export MAXSDCCLOCK := 5000000
|
||||
ArtyA7: FPGA_Arty
|
||||
|
||||
vcu118: export XILINX_PART := xcvu9p-flga2104-2L-e
|
||||
vcu118: export XILINX_BOARD := xilinx.com:vcu118:part0:2.4
|
||||
vcu118: export board := vcu118
|
||||
vcu118: export SYSTEMCLOCK := 71000000
|
||||
vcu118: export MAXSDCCLOCK := 1000000
|
||||
vcu118: FPGA_VCU
|
||||
|
||||
vcu108: export XILINX_PART := xcvu095-ffva2104-2-e
|
||||
vcu108: export XILINX_BOARD := xilinx.com:vcu108:part0:1.7
|
||||
vcu108: export board := vcu108
|
||||
vcu108: export SYSTEMCLOCK := 50000000
|
||||
vcu108: export MAXSDCCLOCK := 12500000
|
||||
vcu108: FPGA_VCU
|
||||
|
||||
# variables computed from config
|
||||
EXT_MEM_BASE = $(shell grep 'EXT_MEM_BASE' ../../config/deriv/fpga$(board)/config.vh | sed 's/.*=.*h\([[:alnum:]]*\);/0x\1/g')
|
||||
|
||||
EXT_MEM_RANGE = $(shell grep 'EXT_MEM_RANGE' ../../config/deriv/fpga$(board)/config.vh | sed 's/.*=.*h\([[:alnum:]]*\);/\1/g' | sed 's/\(.*\)/base=16;\1+1/g' | bc | sed 's/\(.*\)/0x\1/g')
|
||||
|
||||
|
||||
.PHONY: FPGA_Arty FPGA_VCU
|
||||
FPGA_Arty: PreProcessFiles IP_Arty
|
||||
FPGA_Arty: PreProcessFiles IP_Arty zsbl
|
||||
vivado -mode tcl -source wally.tcl 2>&1 | tee wally.log
|
||||
FPGA_VCU: PreProcessFiles IP_VCU
|
||||
FPGA_VCU: PreProcessFiles IP_VCU zsbl
|
||||
vivado -mode tcl -source wally.tcl 2>&1 | tee wally.log
|
||||
|
||||
# Generate IP Blocks
|
||||
|
|
@ -33,13 +45,9 @@ IP_VCU: $(dst)/sysrst.log \
|
|||
$(dst)/ahbaxibridge.log
|
||||
IP_Arty: $(dst)/sysrst.log \
|
||||
MEM_Arty \
|
||||
$(dst)/xlnx_mmcm.log \
|
||||
$(dst)/mmcm.log \
|
||||
$(dst)/clkconverter.log \
|
||||
$(dst)/ahbaxibridge.log
|
||||
#$(dst)/xlnx_axi_crossbar.log \
|
||||
#$(dst)/xlnx_axi_dwidth_conv_32to64.log \
|
||||
#$(dst)/xlnx_axi_dwidth_conv_64to32.log \
|
||||
#$(dst)/xlnx_axi_prtcl_conv.log
|
||||
|
||||
# Generate Memory IP Blocks
|
||||
.PHONY: MEM_VCU MEM_Arty
|
||||
|
|
@ -57,15 +65,19 @@ PreProcessFiles:
|
|||
cp -r ../../addins/verilog-ethernet/*/*.sv ../src/CopiedFiles_do_not_add_to_repo/rvvi
|
||||
cp -r ../../addins/verilog-ethernet/*/*/*/*.sv ../src/CopiedFiles_do_not_add_to_repo/rvvi
|
||||
mkdir ../src/CopiedFiles_do_not_add_to_repo/config/
|
||||
cp ../../config/deriv/fpga/config.vh ../src/CopiedFiles_do_not_add_to_repo/config/
|
||||
cp ../../config/deriv/fpga$(board)/config.vh ../src/CopiedFiles_do_not_add_to_repo/config/
|
||||
./insert_debug_comment.sh
|
||||
# modify config *** RT: eventually setup for variably defined sized memory
|
||||
#sed -i "s/EXT_MEM_RANGE.*/EXT_MEM_RANGE = 64'h0FFFFFFF;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
|
||||
# This line allows the Bootloader to be loaded in a Block RAM on the FPGA
|
||||
sed -i "s/bit \[DATA_WIDTH-1:0\].*ROM.*/(\* rom_style=\"block\" \*) &/g" ../src/CopiedFiles_do_not_add_to_repo/generic/mem/rom1p1r.sv
|
||||
sed -i 's/$$WALLY/\.\.\/\.\.\/\.\.\//g' ../src/CopiedFiles_do_not_add_to_repo/generic/mem/rom1p1r.sv
|
||||
sed -i 's/$$WALLY/\.\.\/\.\.\/\.\.\//g' ../src/CopiedFiles_do_not_add_to_repo/generic/mem/ram1p1rwbe.sv
|
||||
|
||||
# build the Zero stage boot loader (ZSBL)
|
||||
.PHONY: zsbl
|
||||
zsbl:
|
||||
$(MAKE) -C ../zsbl clean
|
||||
SYSTEMCLOCK=$(SYSTEMCLOCK) EXT_MEM_BASE=$(EXT_MEM_BASE) EXT_MEM_RANGE=$(EXT_MEM_RANGE) $(MAKE) -C ../zsbl
|
||||
|
||||
# Generate Individual IP Blocks
|
||||
$(dst)/%.log: %.tcl
|
||||
mkdir -p IP
|
||||
|
|
|
|||
|
|
@ -1,11 +1,14 @@
|
|||
|
||||
set partNumber $::env(XILINX_PART)
|
||||
set boardName $::env(XILINX_BOARD)
|
||||
set SYSTEMCLOCK $::env(SYSTEMCLOCK)
|
||||
#set partNumber xcvu9p-flga2104-2L-e
|
||||
#set boardName xilinx.com:vcu118:part0:2.4
|
||||
|
||||
set ipName ddr4
|
||||
|
||||
set SYSTEMCLOCK_MHz [expr $SYSTEMCLOCK/1000000]
|
||||
|
||||
create_project $ipName . -force -part $partNumber
|
||||
set_property board_part $boardName [current_project]
|
||||
|
||||
|
|
@ -38,7 +41,7 @@ set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \
|
|||
CONFIG.C0.DDR4_AxiNarrowBurst {false} \
|
||||
CONFIG.Reference_Clock {Differential} \
|
||||
CONFIG.ADDN_UI_CLKOUT1.INSERT_VIP {0} \
|
||||
CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {50} \
|
||||
CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ $SYSTEMCLOCK_MHz \
|
||||
CONFIG.ADDN_UI_CLKOUT2.INSERT_VIP {0} \
|
||||
CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ {300} \
|
||||
CONFIG.ADDN_UI_CLKOUT3.INSERT_VIP {0} \
|
||||
|
|
|
|||
|
|
@ -1,11 +1,14 @@
|
|||
|
||||
set partNumber $::env(XILINX_PART)
|
||||
set boardName $::env(XILINX_BOARD)
|
||||
set SYSTEMCLOCK $::env(SYSTEMCLOCK)
|
||||
#set partNumber xcvu9p-flga2104-2L-e
|
||||
#set boardName xilinx.com:vcu118:part0:2.4
|
||||
|
||||
set ipName ddr4
|
||||
|
||||
set SYSTEMCLOCK_MHz [expr $SYSTEMCLOCK/1000000.0]
|
||||
|
||||
create_project $ipName . -force -part $partNumber
|
||||
set_property board_part $boardName [current_project]
|
||||
|
||||
|
|
@ -38,7 +41,7 @@ set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \
|
|||
CONFIG.C0.DDR4_AxiNarrowBurst {false} \
|
||||
CONFIG.Reference_Clock {Differential} \
|
||||
CONFIG.ADDN_UI_CLKOUT1.INSERT_VIP {0} \
|
||||
CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {71} \
|
||||
CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ $SYSTEMCLOCK_MHz \
|
||||
CONFIG.ADDN_UI_CLKOUT2.INSERT_VIP {0} \
|
||||
CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ {300} \
|
||||
CONFIG.ADDN_UI_CLKOUT3.INSERT_VIP {0} \
|
||||
|
|
|
|||
|
|
@ -1,25 +1,29 @@
|
|||
set partNumber $::env(XILINX_PART)
|
||||
set boardName $::env(XILINX_BOARD)
|
||||
|
||||
set SYSTEMCLOCK $::env(SYSTEMCLOCK)
|
||||
set ipName mmcm
|
||||
|
||||
set SYSTEMCLOCK_MHz [expr $SYSTEMCLOCK/1000000.0]
|
||||
|
||||
create_project $ipName . -force -part $partNumber
|
||||
set_property board_part $boardName [current_project]
|
||||
|
||||
create_ip -name clk_wiz -vendor xilinx.com -library ip -module_name $ipName
|
||||
|
||||
set_property -dict [list CONFIG.PRIM_IN_FREQ {100.000} \
|
||||
CONFIG.NUM_OUT_CLKS {3} \
|
||||
CONFIG.NUM_OUT_CLKS {4} \
|
||||
CONFIG.CLKOUT2_USED {true} \
|
||||
CONFIG.CLKOUT3_USED {true} \
|
||||
CONFIG.CLKOUT4_USED {true} \
|
||||
CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {166.66667} \
|
||||
CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {200} \
|
||||
CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {25} \
|
||||
CONFIG.CLKOUT3_REQUESTED_OUT_FREQ $SYSTEMCLOCK_MHz \
|
||||
CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {25} \
|
||||
CONFIG.CLKIN1_JITTER_PS {10.0} \
|
||||
] [get_ips $ipName]
|
||||
|
||||
#set_property CONFIG.CLKOUT3_REQUESTED_OUT_FREQ $SYSTEMCLOCK_MHz [get_ips $ipName]
|
||||
|
||||
generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
|
||||
generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
|
||||
create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
|
||||
|
|
|
|||
|
|
@ -98,6 +98,7 @@ write_verilog -force -mode funcsim sim/syn-funcsim.v
|
|||
if {$board=="ArtyA7"} {
|
||||
#source ../constraints/small-debug.xdc
|
||||
#source ../constraints/small-debug-rvvi.xdc
|
||||
#source ../constraints/small-debug-spi.xdc
|
||||
} else {
|
||||
#source ../constraints/vcu-small-debug.xdc
|
||||
#source ../constraints/small-debug.xdc
|
||||
|
|
|
|||
|
|
@ -182,6 +182,7 @@ module fpgaTop
|
|||
logic [511 : 0] dbg_bus;
|
||||
|
||||
logic CLK208;
|
||||
logic SDCCLKInternal;
|
||||
|
||||
assign GPIOIN = {25'b0, SDCCD, SDCWP, 2'b0, GPI};
|
||||
assign GPO = GPIOOUT[4:0];
|
||||
|
|
@ -215,8 +216,12 @@ module fpgaTop
|
|||
.HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
|
||||
.HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0),
|
||||
.GPIOIN, .GPIOOUT, .GPIOEN,
|
||||
.UARTSin, .UARTSout, .SDCIn, .SDCCmd, .SDCCS(SDCCSin), .SDCCLK, .ExternalStall(RVVIStall));
|
||||
|
||||
.UARTSin, .UARTSout, .SDCIn, .SDCCmd, .SDCCS(SDCCSin), .SDCCLK(SDCCLKInternal), .ExternalStall(RVVIStall));
|
||||
|
||||
// *** these are different for different fpga ugh.
|
||||
ODDRE1 sdcclkoddr(.Q(SDCCLK), .C(SDCCLKInternal), .D1('0),
|
||||
.D2(1'b1), .SR('0));
|
||||
|
||||
// ahb lite to axi bridge
|
||||
ahbaxibridge ahbaxibridge
|
||||
(.s_ahb_hclk(CPUCLK),
|
||||
|
|
|
|||
|
|
@ -27,11 +27,17 @@ MABI :=-mabi=lp64d
|
|||
LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles -L $(RISCV)/riscv64-unknown-elf/lib
|
||||
LINKER :=linker1000.x
|
||||
|
||||
# FGPA parameters
|
||||
SYSTEMCLOCK ?= 20000000
|
||||
MAXSDCCLOCK ?= 5000000
|
||||
EXT_MEM_BASE ?= 0x80000000
|
||||
EXT_MEM_RANGE ?= 0x10000000
|
||||
|
||||
|
||||
AFLAGS =$(MARCH) $(MABI) -W
|
||||
# Override directive allows us to prepend other options on the command line
|
||||
# e.g. $ make CFLAGS=-g
|
||||
override CFLAGS +=$(MARCH) $(MABI) -mcmodel=medany -O2 -g
|
||||
override CFLAGS +=$(MARCH) $(MABI) -mcmodel=medany -O2 -g -DSYSTEMCLOCK=${SYSTEMCLOCK} -DMAXSDCCLOCK=${MAXSDCCLOCK} -DEXT_MEM_BASE=${EXT_MEM_BASE} -DEXT_MEM_RANGE=${EXT_MEM_RANGE}
|
||||
AS=riscv64-unknown-elf-as
|
||||
CC=riscv64-unknown-elf-gcc
|
||||
AR=riscv64-unknown-elf-ar
|
||||
|
|
|
|||
|
|
@ -1,5 +1,6 @@
|
|||
PERIOD = 11000000
|
||||
#PERIOD = 20
|
||||
#include "system.h"
|
||||
|
||||
PERIOD = (SYSTEMCLOCK / 2)
|
||||
|
||||
.section .init
|
||||
.global _start
|
||||
|
|
@ -47,10 +48,10 @@ _start:
|
|||
|
||||
|
||||
# set the stack pointer to the top of memory - 8 bytes (pointer size)
|
||||
li sp, 0x87FFFFF8
|
||||
li sp, (EXT_MEM_END - 8)
|
||||
|
||||
li a0, 0x00000000
|
||||
li a1, 0x80000000
|
||||
li a1, EXT_MEM_BASE
|
||||
#li a2, 128*1024*1024/512 # copy 128MB
|
||||
li a2, 127*1024*1024/512 # copy 127MB upper 1MB contains the return address (ra)
|
||||
#li a2, 800 # copy 400KB
|
||||
|
|
@ -88,9 +89,9 @@ delay2:
|
|||
|
||||
jumpToLinux:
|
||||
csrrs a0, 0xF14, x0 # copy hart ID to a0
|
||||
li a1, 0x87000000 # end of memory? not 100% sure on this but it's 112MB
|
||||
li a1, FDT_ADDRESS # This is the device tree address
|
||||
la a2, end_of_bios
|
||||
li t0, 0x80000000 # start of code
|
||||
li t0, EXT_MEM_BASE # start of code
|
||||
|
||||
jalr x0, t0, 0
|
||||
|
||||
|
|
@ -31,6 +31,7 @@
|
|||
#define WALLYBOOT 10000
|
||||
|
||||
#include <stdint.h>
|
||||
#include "system.h"
|
||||
typedef unsigned int UINT; /* int must be 16-bit or 32-bit */
|
||||
typedef unsigned char BYTE; /* char must be 8-bit */
|
||||
typedef uint16_t WORD; /* 16-bit unsigned integer */
|
||||
|
|
@ -44,8 +45,10 @@ typedef QWORD LBA_t;
|
|||
// These locations are copied from the generic configuration
|
||||
// of OpenSBI. These addresses can be found in:
|
||||
// buildroot/output/build/opensbi-0.9/platform/generic/config.mk
|
||||
#define FDT_ADDRESS 0x87000000 // FW_JUMP_FDT_ADDR
|
||||
#define OPENSBI_ADDRESS 0x80000000 // FW_TEXT_START
|
||||
|
||||
// FDT_ADDRESS now defined in system.h
|
||||
//#define FDT_ADDRESS 0xFF000000 // FW_JUMP_FDT_ADDR
|
||||
#define OPENSBI_ADDRESS EXT_MEM_BASE // FW_TEXT_START
|
||||
#define KERNEL_ADDRESS 0x80200000 // FW_JUMP_ADDR
|
||||
|
||||
#define BANNER " █▀█ █▀█ █▀█ █▀▀ █ █\r\n" \
|
||||
|
|
@ -61,12 +64,6 @@ typedef QWORD LBA_t;
|
|||
// Export disk_read
|
||||
int disk_read(BYTE * buf, LBA_t sector, UINT count);
|
||||
|
||||
#define SYSTEMCLOCK 20000000
|
||||
|
||||
// TODO: This line needs to change back to 20MHz when we fix the
|
||||
// timing problems.
|
||||
#define MAXSDCCLOCK 5000000
|
||||
|
||||
// Maximum SDC speed is either the system clock divided by 2 (because
|
||||
// of the SPI peripheral clock division) or the maximum speed an SD
|
||||
// card can be pushed to.
|
||||
|
|
|
|||
23
fpga/zsbl/system.h
Normal file
23
fpga/zsbl/system.h
Normal file
|
|
@ -0,0 +1,23 @@
|
|||
#ifndef __system_H
|
||||
#define __system_H
|
||||
|
||||
#ifndef SYSTEMCLOCK
|
||||
#define SYSTEMCLOCK 100000000
|
||||
#endif
|
||||
|
||||
#ifndef MAXSDCCLOCK
|
||||
#define MAXSDCCLOCK 5000000
|
||||
#endif
|
||||
|
||||
#ifndef EXT_MEM_BASE
|
||||
#define EXT_MEM_BASE 0x80000000
|
||||
#endif
|
||||
|
||||
#ifndef EXT_MEM_RANGE
|
||||
#define EXT_MEM_RANGE 0x10000000
|
||||
#endif
|
||||
|
||||
#define EXT_MEM_END (EXT_MEM_BASE + EXT_MEM_RANGE)
|
||||
#define FDT_ADDRESS (EXT_MEM_END - 0x1000000)
|
||||
|
||||
#endif
|
||||
|
|
@ -21,8 +21,8 @@
|
|||
cpus {
|
||||
#address-cells = <0x01>;
|
||||
#size-cells = <0x00>;
|
||||
clock-frequency = <0x17D7840>;
|
||||
timebase-frequency = <0x17D7840>;
|
||||
clock-frequency = <20000000>;
|
||||
timebase-frequency = <20000000>;
|
||||
|
||||
cpu@0 {
|
||||
phandle = <0x01>;
|
||||
|
|
@ -54,7 +54,7 @@
|
|||
refclk: refclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <0x17D7840>;
|
||||
clock-frequency = <20000000>;
|
||||
clock-output-names = "xtal";
|
||||
};
|
||||
|
||||
|
|
@ -73,7 +73,7 @@
|
|||
uart@10000000 {
|
||||
interrupts = <0x0a>;
|
||||
interrupt-parent = <0x03>;
|
||||
clock-frequency = <0x17D7840>;
|
||||
clock-frequency = <20000000>;
|
||||
reg = <0x00 0x10000000 0x00 0x100>;
|
||||
compatible = "ns16550a";
|
||||
};
|
||||
|
|
@ -102,7 +102,7 @@
|
|||
mmc@0 {
|
||||
compatible = "mmc-spi-slot";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <5000000>;
|
||||
spi-max-frequency = <1000000>;
|
||||
voltage-ranges = <3300 3300>;
|
||||
disable-wp;
|
||||
// gpios = <&gpio0 6 1>;
|
||||
|
|
|
|||
|
|
@ -15,7 +15,7 @@
|
|||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x00 0x80000000 0x00 0x10000000>;
|
||||
reg = <0x00 0x80000000 0x00 0x80000000>;
|
||||
};
|
||||
|
||||
cpus {
|
||||
|
|
|
|||
|
|
@ -115,8 +115,8 @@ if {[lcheck lst "--fcovrvvi"]} {
|
|||
set FCdefineRVVI_COVERAGE "+define+RVVI_COVERAGE"
|
||||
}
|
||||
|
||||
# if --fcov found set flag and remove from list
|
||||
if {[lcheck lst "--fcov"]} {
|
||||
# if --fcovimp found set flag and remove from list
|
||||
if {[lcheck lst "--fcovimp"]} {
|
||||
set FunctCoverage 1
|
||||
set FCvlog "+define+INCLUDE_TRACE2COV \
|
||||
+define+IDV_INCLUDE_TRACE2COV \
|
||||
|
|
@ -135,23 +135,17 @@ if {[lcheck lst "--fcov"]} {
|
|||
|
||||
}
|
||||
|
||||
# if --fcov2 found set flag and remove from list
|
||||
if {[lcheck lst "--fcov2"]} {
|
||||
# if --fcov found set flag and remove from list
|
||||
if {[lcheck lst "--fcov"]} {
|
||||
set FunctCoverage 1
|
||||
# COVER_BASE_RV32I is just needed to keep riscvISACOV happy, but no longer affects tests
|
||||
set FCvlog "+define+INCLUDE_TRACE2COV \
|
||||
+define+IDV_INCLUDE_TRACE2COV \
|
||||
+define+COVER_BASE_RV32I \
|
||||
+define+COVER_LEVEL_DV_PR_EXT \
|
||||
+incdir+$env(WALLY)/addins/riscvISACOV/source"
|
||||
+incdir+$env(WALLY)/addins/riscvISACOV/source \
|
||||
"
|
||||
set FCvopt "+TRACE2COV_ENABLE=1 +IDV_TRACE2COV=1"
|
||||
# Uncomment various cover statements below to control which extensions get functional coverage
|
||||
lappend FCdefineCOVER_EXTS "+define+COVER_RV32I"
|
||||
#lappend FCdefineCOVER_EXTS "+define+COVER_RV64M"
|
||||
#lappend FCdefineCOVER_EXTS "+define+COVER_RV64A"
|
||||
#lappend FCdefineCOVER_EXTS "+define+COVER_RV64F"
|
||||
#lappend FCdefineCOVER_EXTS "+define+COVER_RV64D"
|
||||
#lappend FCdefineCOVER_EXTS "+define+COVER_RV64ZICSR"
|
||||
#lappend FCdefineCOVER_EXTS "+define+COVER_RV64C"
|
||||
|
||||
}
|
||||
|
||||
# if --lockstep or --fcov found set flag and remove from list
|
||||
|
|
@ -199,7 +193,7 @@ if {$DEBUG > 0} {
|
|||
# suppress spurious warnngs about
|
||||
# "Extra checking for conflicts with always_comb done at vopt time"
|
||||
# because vsim will run vopt
|
||||
set INC_DIRS "+incdir+${CONFIG}/${CFG} +incdir+${CONFIG}/deriv/${CFG} +incdir+${CONFIG}/shared +incdir+${FCRVVI}/common +incdir+${FCRVVI}"
|
||||
set INC_DIRS "+incdir+${CONFIG}/${CFG} +incdir+${CONFIG}/deriv/${CFG} +incdir+${CONFIG}/shared +incdir+${FCRVVI} +incdir+${FCRVVI}/rv32 +incdir+${FCRVVI}/rv64 +incdir+${FCRVVI}/common +incdir+${FCRVVI}"
|
||||
set SOURCES "${SRC}/cvw.sv ${TB}/${TESTBENCH}.sv ${TB}/common/*.sv ${SRC}/*/*.sv ${SRC}/*/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*/*/*.sv"
|
||||
vlog -lint +nowarnRDGN -work ${WKDIR} {*}${INC_DIRS} {*}${FCvlog} {*}${FCdefineCOVER_EXTS} {*}${lockstepvlog} ${FCdefineRVVI_COVERAGE} {*}${SOURCES} -suppress 2244 -suppress 2282 -suppress 2583 -suppress 7063,2596,13286
|
||||
|
||||
|
|
|
|||
|
|
@ -90,6 +90,7 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
|
|||
logic TransmitWriteMark, TransmitReadMark, RecieveWriteMark, RecieveReadMark;
|
||||
logic TransmitFIFOWriteFull, TransmitFIFOReadEmpty;
|
||||
logic TransmitFIFOWriteIncrement;
|
||||
logic ReceiveFiFoWriteInc;
|
||||
logic ReceiveFIFOReadIncrement;
|
||||
logic ReceiveFIFOWriteFull, ReceiveFIFOReadEmpty;
|
||||
logic [7:0] TransmitFIFOReadData;
|
||||
|
|
@ -98,9 +99,10 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
|
|||
/* verilator lint_off UNDRIVEN */
|
||||
logic [7:0] ReceiveShiftRegEndian; // Reverses ReceiveShiftReg if Format[2] set (little endian transmission)
|
||||
rsrstatetype ReceiveState;
|
||||
logic ReceiveFiFoTakingData;
|
||||
|
||||
// Transmission signals
|
||||
// logic sck;
|
||||
logic ZeroDiv; // High when SckDiv is 0
|
||||
logic [11:0] DivCounter; // Counter for sck
|
||||
logic SCLKenable; // Flip flop enable high every sclk edge
|
||||
|
||||
|
|
@ -114,6 +116,7 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
|
|||
logic ZeroDelayHoldMode; // High when ChipSelectMode is hold and Delay1[15:8] (InterXFR delay) is 0
|
||||
|
||||
// Frame counting signals
|
||||
logic FirstFrame;
|
||||
logic [3:0] FrameCount; // Counter for number of frames in transmission
|
||||
logic ReceivePenultimateFrame; // High when penultimate frame in transmission has been reached
|
||||
|
||||
|
|
@ -128,11 +131,15 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
|
|||
logic SampleEdge; // Determines which edge of sck to sample from ReceiveShiftReg
|
||||
logic [7:0] TransmitDataEndian; // Reverses TransmitData from txFIFO if littleendian, since TransmitReg always shifts MSB
|
||||
logic TransmitShiftRegLoad; // Determines when to load TransmitShiftReg
|
||||
logic TransmitShiftRegLoadSingleCycle; // Version of TransmitShiftRegLoad which is only high for a single SCLK cycle to prevent double loads
|
||||
logic TransmitShiftRegLoadDelay; // TransmitShiftRegLoad delayed by an SCLK cycle, inverted and anded with TransmitShiftRegLoad to create a single cycle signal
|
||||
logic TransmitFIFOReadIncrement; // Increments Tx FIFO read ptr 1 cycle after Tx FIFO is read
|
||||
logic ReceiveShiftFull; // High when receive shift register is full
|
||||
logic TransmitShiftEmpty; // High when transmit shift register is empty
|
||||
logic ShiftIn; // Determines whether to shift from SPIIn or SPIOut (if SPI_LOOPBACK_TEST)
|
||||
logic [3:0] LeftShiftAmount; // Determines left shift amount to left-align data when little endian
|
||||
logic [7:0] ASR; // AlignedReceiveShiftReg
|
||||
logic [7:0] ASR; // AlignedReceiveShiftReg
|
||||
logic ShiftEdgeSPICLK; // Changes ShiftEdge when SckDiv is 0
|
||||
|
||||
// CS signals
|
||||
logic [3:0] ChipSelectAuto; // Assigns ChipSelect value to selected CS signal based on CS ID
|
||||
|
|
@ -145,6 +152,8 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
|
|||
logic TransmitFIFOReadEmptyDelay;
|
||||
logic SCLKenableEarly; // SCLKenable 1 PCLK cycle early, needed for on time register changes when ChipSelectMode is hold and Delay1[15:8] (InterXFR delay) is 0
|
||||
|
||||
|
||||
|
||||
// APB access
|
||||
assign Entry = {PADDR[7:2],2'b00}; // 32-bit word-aligned accesses
|
||||
assign Memwrite = PWRITE & PENABLE & PSEL; // Only write in access phase
|
||||
|
|
@ -225,7 +234,9 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
|
|||
// SPI enable generation, where SCLK = PCLK/(2*(SckDiv + 1))
|
||||
// Asserts SCLKenable at the rising and falling edge of SCLK by counting from 0 to SckDiv
|
||||
// Active at 2x SCLK frequency to account for implicit half cycle delays and actions on both clock edges depending on phase
|
||||
assign SCLKenable = (DivCounter == SckDiv);
|
||||
// When SckDiv is 0, count doesn't work and SCLKenable is simply PCLK
|
||||
assign ZeroDiv = ~|(SckDiv[10:0]);
|
||||
assign SCLKenable = ZeroDiv ? PCLK : (DivCounter == SckDiv);
|
||||
assign SCLKenableEarly = ((DivCounter + 12'b1) == SckDiv);
|
||||
always_ff @(posedge PCLK)
|
||||
if (~PRESETn) DivCounter <= '0;
|
||||
|
|
@ -234,6 +245,7 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
|
|||
|
||||
// Asserts when transmission is one frame before complete
|
||||
assign ReceivePenultimateFrame = ((FrameCount + 4'b0001) == Format[4:1]);
|
||||
assign FirstFrame = (FrameCount == 4'b0);
|
||||
|
||||
// Computing delays
|
||||
// When sckmode.pha = 0, an extra half-period delay is implicit in the cs-sck delay, and vice-versa for sck-cs
|
||||
|
|
@ -276,11 +288,20 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
|
|||
always_ff @(posedge PCLK)
|
||||
if (~PRESETn) ReceiveFIFOReadIncrement <= 1'b0;
|
||||
else ReceiveFIFOReadIncrement <= ((Entry == SPI_RXDATA) & ~ReceiveFIFOReadEmpty & PSEL & ~ReceiveFIFOReadIncrement);
|
||||
|
||||
|
||||
assign TransmitShiftRegLoad = ~TransmitShiftEmpty & ~Active | (((ChipSelectMode == 2'b10) & ~|(Delay1[15:8])) & ((ReceiveShiftFullDelay | ReceiveShiftFull) & ~SampleEdge & ~TransmitFIFOReadEmpty));
|
||||
|
||||
always_ff @(posedge PCLK)
|
||||
if (~PRESETn) TransmitShiftRegLoadDelay <=0;
|
||||
else if (SCLKenable) TransmitShiftRegLoadDelay <= TransmitShiftRegLoad;
|
||||
assign TransmitShiftRegLoadSingleCycle = TransmitShiftRegLoad & ~TransmitShiftRegLoadDelay;
|
||||
always_ff @(posedge PCLK)
|
||||
if (~PRESETn) TransmitFIFOReadIncrement <= 0;
|
||||
else if (SCLKenable) TransmitFIFOReadIncrement <= TransmitShiftRegLoadSingleCycle;
|
||||
// Tx/Rx FIFOs
|
||||
spi_fifo #(3,8) txFIFO(PCLK, 1'b1, SCLKenable, PRESETn, TransmitFIFOWriteIncrement, TransmitShiftEmpty, TransmitData[7:0], TransmitWriteWatermarkLevel, TransmitWatermark[2:0],
|
||||
spi_fifo #(3,8) txFIFO(PCLK, 1'b1, SCLKenable, PRESETn, TransmitFIFOWriteIncrement, TransmitFIFOReadIncrement, TransmitData[7:0], TransmitWriteWatermarkLevel, TransmitWatermark[2:0],
|
||||
TransmitFIFOReadData[7:0], TransmitFIFOWriteFull, TransmitFIFOReadEmpty, TransmitWriteMark, TransmitReadMark);
|
||||
spi_fifo #(3,8) rxFIFO(PCLK, SCLKenable, 1'b1, PRESETn, ReceiveShiftFullDelay, ReceiveFIFOReadIncrement, ReceiveShiftRegEndian, ReceiveWatermark[2:0], ReceiveReadWatermarkLevel,
|
||||
spi_fifo #(3,8) rxFIFO(PCLK, SCLKenable, 1'b1, PRESETn, ReceiveFiFoWriteInc, ReceiveFIFOReadIncrement, ReceiveShiftRegEndian, ReceiveWatermark[2:0], ReceiveReadWatermarkLevel,
|
||||
ReceiveData[7:0], ReceiveFIFOWriteFull, ReceiveFIFOReadEmpty, RecieveWriteMark, RecieveReadMark);
|
||||
|
||||
always_ff @(posedge PCLK)
|
||||
|
|
@ -290,11 +311,19 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
|
|||
always_ff @(posedge PCLK)
|
||||
if (~PRESETn) ReceiveShiftFullDelay <= 1'b0;
|
||||
else if (SCLKenable) ReceiveShiftFullDelay <= ReceiveShiftFull;
|
||||
|
||||
assign ReceiveFiFoTakingData = ReceiveFiFoWriteInc & ~ReceiveFIFOWriteFull;
|
||||
|
||||
always_ff @(posedge PCLK)
|
||||
if (~PRESETn) ReceiveFiFoWriteInc <= 1'b0;
|
||||
else if (SCLKenable & ReceiveShiftFull) ReceiveFiFoWriteInc <= 1'b1;
|
||||
else if (SCLKenable & ReceiveFiFoTakingData) ReceiveFiFoWriteInc <= 1'b0;
|
||||
always_ff @(posedge PCLK)
|
||||
if (~PRESETn) ReceiveShiftFullDelayPCLK <= 1'b0;
|
||||
else if (SCLKenableEarly) ReceiveShiftFullDelayPCLK <= ReceiveShiftFull;
|
||||
|
||||
assign TransmitShiftRegLoad = ~TransmitShiftEmpty & ~Active | (((ChipSelectMode == 2'b10) & ~|(Delay1[15:8])) & ((ReceiveShiftFullDelay | ReceiveShiftFull) & ~SampleEdge & ~TransmitFIFOReadEmpty));
|
||||
|
||||
|
||||
|
||||
// Main FSM which controls SPI transmission
|
||||
typedef enum logic [2:0] {CS_INACTIVE, DELAY_0, ACTIVE_0, ACTIVE_1, DELAY_1,INTER_CS, INTER_XFR} statetype;
|
||||
|
|
@ -365,7 +394,7 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
|
|||
FrameCount <= 4'b0;
|
||||
InterCSCount <= 9'b10;
|
||||
InterXFRCount <= InterXFRCount + 9'b1;
|
||||
if ((InterXFRCount >= ({Delay1[15:8], 1'b0})) & ~TransmitFIFOReadEmptyDelay) begin
|
||||
if ((InterXFRCount >= ({Delay1[15:8], 1'b0})) & (~TransmitFIFOReadEmptyDelay | ~TransmitShiftEmpty)) begin
|
||||
state <= ACTIVE_0;
|
||||
SPICLK <= ~SckMode[1];
|
||||
end else if (~|ChipSelectMode[1:0]) state <= CS_INACTIVE;
|
||||
|
|
@ -384,22 +413,23 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
|
|||
assign ZeroDelayHoldMode = ((ChipSelectMode == 2'b10) & (~|(Delay1[7:4])));
|
||||
assign TransmitInactive = ((state == INTER_CS) | (state == CS_INACTIVE) | (state == INTER_XFR) | (ReceiveShiftFullDelayPCLK & ZeroDelayHoldMode) | ((state == ACTIVE_1) & ((ChipSelectMode[1:0] == 2'b10) & ~|(Delay1[15:8]) & (~TransmitFIFOReadEmpty) & (FrameCount == Format[4:1]))));
|
||||
assign Active0 = (state == ACTIVE_0);
|
||||
assign ShiftEdgeSPICLK = ZeroDiv ? ~SPICLK : SPICLK;
|
||||
|
||||
// Signal tracks which edge of sck to shift data
|
||||
always_comb
|
||||
case(SckMode[1:0])
|
||||
2'b00: ShiftEdge = SPICLK & SCLKenable;
|
||||
2'b01: ShiftEdge = (~SPICLK & (|(FrameCount) | (CS_SCKCount >= (({Delay0[7:0], 1'b0}) + ImplicitDelay1))) & SCLKenable & (FrameCount != Format[4:1]) & ~TransmitInactive);
|
||||
2'b10: ShiftEdge = ~SPICLK & SCLKenable;
|
||||
2'b11: ShiftEdge = (SPICLK & (|(FrameCount) | (CS_SCKCount >= (({Delay0[7:0], 1'b0}) + ImplicitDelay1))) & SCLKenable & (FrameCount != Format[4:1]) & ~TransmitInactive);
|
||||
default: ShiftEdge = SPICLK & SCLKenable;
|
||||
2'b00: ShiftEdge = ShiftEdgeSPICLK & SCLKenable;
|
||||
2'b01: ShiftEdge = (~ShiftEdgeSPICLK & ~FirstFrame & (|(FrameCount) | (CS_SCKCount >= (({Delay0[7:0], 1'b0}) + ImplicitDelay1))) & SCLKenable & (FrameCount != Format[4:1]) & ~TransmitInactive);
|
||||
2'b10: ShiftEdge = ~ShiftEdgeSPICLK & SCLKenable;
|
||||
2'b11: ShiftEdge = (ShiftEdgeSPICLK & ~FirstFrame & (|(FrameCount) | (CS_SCKCount >= (({Delay0[7:0], 1'b0}) + ImplicitDelay1))) & SCLKenable & (FrameCount != Format[4:1]) & ~TransmitInactive);
|
||||
default: ShiftEdge = ShiftEdgeSPICLK & SCLKenable;
|
||||
endcase
|
||||
|
||||
// Transmit shift register
|
||||
assign TransmitDataEndian = Format[0] ? {TransmitFIFOReadData[0], TransmitFIFOReadData[1], TransmitFIFOReadData[2], TransmitFIFOReadData[3], TransmitFIFOReadData[4], TransmitFIFOReadData[5], TransmitFIFOReadData[6], TransmitFIFOReadData[7]} : TransmitFIFOReadData[7:0];
|
||||
always_ff @(posedge PCLK)
|
||||
if(~PRESETn) TransmitShiftReg <= 8'b0;
|
||||
else if (TransmitShiftRegLoad) TransmitShiftReg <= TransmitDataEndian;
|
||||
else if (TransmitShiftRegLoadSingleCycle) TransmitShiftReg <= TransmitDataEndian;
|
||||
else if (ShiftEdge & Active) TransmitShiftReg <= {TransmitShiftReg[6:0], TransmitShiftReg[0]};
|
||||
|
||||
assign SPIOut = TransmitShiftReg[7];
|
||||
|
|
|
|||
|
|
@ -52,7 +52,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
|
|||
logic [NUMREGS-1:0] rf_wb;
|
||||
logic [4:0] rf_a3;
|
||||
logic rf_we3;
|
||||
logic [P.XLEN-1:0] frf[32];
|
||||
logic [P.FLEN-1:0] frf[32];
|
||||
logic [`NUM_REGS-1:0] frf_wb;
|
||||
logic [4:0] frf_a4;
|
||||
logic frf_we4;
|
||||
|
|
|
|||
|
|
@ -1,39 +0,0 @@
|
|||
#all:
|
||||
# ./covergen.py
|
||||
# cd ../riscof; make wally-riscv-arch-test
|
||||
# cd ../../sim; make memfiles
|
||||
|
||||
CEXT := c
|
||||
CPPEXT := cpp
|
||||
AEXT := s
|
||||
SEXT := S
|
||||
SRCEXT := \([$(CEXT)$(AEXT)$(SEXT)]\|$(CPPEXT)\)
|
||||
#SRCS = $(wildcard *.S)
|
||||
#PROGS = $(patsubst %.S,%,$(SRCS))
|
||||
SRCDIR = ${WALLY}/tests/functcov/rv64/I
|
||||
SRCEXT = S
|
||||
SOURCES ?= $(shell find $(SRCDIR) -type f -regex ".*\.$(SRCEXT)" | sort)
|
||||
OBJEXT = elf
|
||||
OBJECTS := $(SOURCES:.$(SEXT)=.$(OBJEXT))
|
||||
|
||||
all:
|
||||
./covergen.py
|
||||
make build
|
||||
|
||||
build: $(OBJECTS)
|
||||
|
||||
%.elf.objdump: %.elf
|
||||
|
||||
# Change many things if bit width isn't 64
|
||||
$(SRCDIR)/%.elf: $(SRCDIR)/%.$(SEXT)
|
||||
riscv64-unknown-elf-gcc -g -o $@ -march=rv64gqc_zfa_zba_zbb_zbc_zbs_zfh_zicboz_zicbop_zicbom -mabi=lp64 -mcmodel=medany \
|
||||
-nostartfiles -T${WALLY}/examples/link/link.ld $<
|
||||
riscv64-unknown-elf-objdump -S -D $@ > $@.objdump
|
||||
riscv64-unknown-elf-elf2hex --bit-width 64 --input $@ --output $@.memfile
|
||||
extractFunctionRadix.sh $@.objdump
|
||||
|
||||
clean:
|
||||
rm -f ${SRCDIR}/*.elf ${SRCDIR}/*.objdump ${SRCDIR}/*.addr *${SRCDIR}/.lab ${SRCDIR}/*.memfile
|
||||
|
||||
|
||||
|
||||
|
|
@ -1,491 +0,0 @@
|
|||
#!/usr/bin/env python3
|
||||
##################################
|
||||
# covergen.py
|
||||
#
|
||||
# David_Harris@hmc.edu 27 March 2024
|
||||
#
|
||||
# Generate directed tests for functional coverage
|
||||
##################################
|
||||
|
||||
##################################
|
||||
# libraries
|
||||
##################################
|
||||
from datetime import datetime
|
||||
from random import randint
|
||||
from random import seed
|
||||
from random import getrandbits
|
||||
import os
|
||||
import re
|
||||
|
||||
##################################
|
||||
# functions
|
||||
##################################
|
||||
|
||||
def shiftImm(imm, xlen):
|
||||
imm = imm % xlen
|
||||
return str(imm)
|
||||
|
||||
def signedImm12(imm):
|
||||
imm = imm % pow(2, 12)
|
||||
if (imm & 0x800):
|
||||
imm = imm - 0x1000
|
||||
return str(imm)
|
||||
|
||||
def unsignedImm20(imm):
|
||||
imm = imm % pow(2, 20)
|
||||
return str(imm)
|
||||
|
||||
def writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, immval, rdval, test, xlen):
|
||||
lines = "\n# Testcase " + str(desc) + "\n"
|
||||
if (rs1val < 0):
|
||||
rs1val = rs1val + 2**xlen
|
||||
if (rs2val < 0):
|
||||
rs2val = rs2val + 2**xlen
|
||||
lines = lines + "li x" + str(rd) + ", " + formatstr.format(rdval) + " # initialize rd to a random value that should get changed; helps covering rd_toggle\n"
|
||||
if (test in rtype):
|
||||
lines = lines + "li x" + str(rs1) + ", " + formatstr.format(rs1val) + " # initialize rs1\n"
|
||||
lines = lines + "li x" + str(rs2) + ", " + formatstr.format(rs2val) + " # initialize rs2\n"
|
||||
lines = lines + test + " x" + str(rd) + ", x" + str(rs1) + ", x" + str(rs2) + " # perform operation\n"
|
||||
elif (test in shiftitype):
|
||||
lines = lines + "li x" + str(rs1) + ", " + formatstr.format(rs1val) + " # initialize rs1\n"
|
||||
if (test in shiftiwtype):
|
||||
lines = lines + test + " x" + str(rd) + ", x" + str(rs1) + ", " + shiftImm(immval, 32) + " # perform operation\n"
|
||||
else:
|
||||
lines = lines + test + " x" + str(rd) + ", x" + str(rs1) + ", " + shiftImm(immval, xlen) + " # perform operation\n"
|
||||
elif (test in itype):
|
||||
lines = lines + "li x" + str(rs1) + ", " + formatstr.format(rs1val) + " # initialize rs1\n"
|
||||
lines = lines + test + " x" + str(rd) + ", x" + str(rs1) + ", " + signedImm12(immval) + " # perform operation\n"
|
||||
elif (test in loaditype):#["lb", "lh", "lw", "ld", "lbu", "lhu", "lwu"]
|
||||
if (rs1 != 0):
|
||||
lines = lines + "li x" + str(rs2) + ", " + formatstr.format(rs2val) + " # initialize rs2\n"
|
||||
lines = lines + "la x" + str(rs1) + ", scratch" + " # base address \n"
|
||||
lines = lines + "addi x" + str(rs1) + ", x" + str(rs1) + ", " + signedImm12(-immval) + " # sub immediate from rs1 to counter offset\n"
|
||||
if (xlen == 32):
|
||||
storeop = "sw"
|
||||
else:
|
||||
storeop = "sd"
|
||||
lines = lines + storeop + " x" + str(rs2) + ", " + signedImm12(immval) +" (x" + str(rs1) + ") # store value to put someting in memory\n"
|
||||
lines = lines + test + " x" + str(rd) + ", " + signedImm12(immval) + "(x" + str(rs1) + ") # perform operation\n"
|
||||
# lines = lines + test + " x" + str(rd) + ", 0(x" + str(rs1) + ") # perform operation\n"
|
||||
elif (test in stype):#["sb", "sh", "sw", "sd"]
|
||||
if (rs1 != 0):
|
||||
if (rs2 == rs1): # make sure registers are different so they don't conflict
|
||||
rs2 = (rs1 + 1) % 32
|
||||
if (rs2 == 0):
|
||||
rs2 = 1
|
||||
lines = lines + "li x" + str(rs2) + ", " + formatstr.format(rs2val) + " # initialize rs2\n"
|
||||
lines = lines + "la x" + str(rs1) + ", scratch" + " # base address \n"
|
||||
lines = lines + "addi x" + str(rs1) + ", x" + str(rs1) + ", " + signedImm12(-immval) + " # sub immediate from rs1 to counter offset\n"
|
||||
lines = lines + test + " x" + str(rs2) + ", " + signedImm12(immval) + "(x" + str(rs1) + ") # perform operation \n"
|
||||
elif (test in btype):#["beq", "bne", "blt", "bge", "bltu", "bgeu"]
|
||||
for same in range(2):
|
||||
if (same):
|
||||
rs1val = rs2val
|
||||
lines = lines + "# same values in both registers\n"
|
||||
lines = lines + "nop\n"
|
||||
lines = lines + "li x" + str(rs1) + ", " + formatstr.format(rs1val) + " # initialize rs1\n"
|
||||
lines = lines + "li x" + str(rs2) + ", " + formatstr.format(rs2val) + " # initialize rs2\n"
|
||||
lines = lines + test + " x" + str(rs1) + ", x" + str(rs2) + ", some_label_for_btype_" + str(immval) + str(same) + " # perform operation \n"
|
||||
lines = lines + "addi x0, x1, 1\n"
|
||||
lines = lines + "some_label_for_btype_" + str(immval)+ str(same) + ":\n"
|
||||
lines = lines + "addi x0, x2, 2\n"
|
||||
lines = lines + "nop\nnop\nnop\nnop\nnop\n"
|
||||
elif (test in jtype):#["jal"]
|
||||
lines = lines + "jal x" + str(rd) + ", 1f # perform operation\n"
|
||||
lines = lines + "nop\n"
|
||||
lines = lines + "1:\n"
|
||||
elif (test in jalrtype):#["jalr"]
|
||||
lines = lines + "la x" + str(rs1) + ", 1f\n"
|
||||
lines = lines + "addi x" + str(rs1) + ", x" + str(rs1) + ", " + signedImm12(-immval) + " # add immediate to lower part of rs1\n"
|
||||
lines = lines + "jalr x" + str(rd) + ", x" + str(rs1) + ", " + signedImm12(immval) + " # perform operation\n"
|
||||
lines = lines + "nop\n"
|
||||
lines = lines + "1:\n"
|
||||
elif (test in utype):#["lui", "auipc"]
|
||||
lines = lines + test + " x" + str(rd) + ", " + unsignedImm20(immval) + " # perform operation\n"
|
||||
else:
|
||||
pass
|
||||
#print("Error: %s type not implemented yet" % test)
|
||||
f.write(lines)
|
||||
|
||||
def writeHazardVector(desc, rs1a, rs2a, rda, rs1b, rs2b, rdb, test):
|
||||
# consecutive R-type instructions to trigger hazards
|
||||
lines = "\n# Testcase " + str(desc) + "\n"
|
||||
lines = lines + test + " x" + str(rda) + ", x" + str(rs1a) + ", x" + str(rs2a) + " # perform first operation\n"
|
||||
lines = lines + test + " x" + str(rdb) + ", x" + str(rs1b) + ", x" + str(rs2b) + " # perform second operation\n"
|
||||
f.write(lines)
|
||||
|
||||
def randomize():
|
||||
rs1 = randint(1, 31)
|
||||
rs2 = randint(1, 31)
|
||||
# choose rd that is different than rs1 and rs2
|
||||
rd = rs1
|
||||
while (rd == rs1 or rd == rs2):
|
||||
rd = randint(1, 31)
|
||||
rd = randint(1, 31)
|
||||
rs1val = randint(0, 2**xlen-1)
|
||||
rs2val = randint(0, 2**xlen-1)
|
||||
immval = randint(0, 2**xlen-1)
|
||||
rdval = randint(0, 2**xlen-1)
|
||||
return [rs1, rs2, rd, rs1val, rs2val, immval, rdval]
|
||||
|
||||
def make_rd(test, xlen):
|
||||
for r in range(32):
|
||||
[rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize()
|
||||
desc = "cp_rd (Test destination rd = x" + str(r) + ")"
|
||||
writeCovVector(desc, rs1, rs2, r, rs1val, rs2val, immval, rdval, test, xlen)
|
||||
|
||||
def make_rs1(test, xlen):
|
||||
for r in range(32):
|
||||
[rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize()
|
||||
desc = "cp_rs1 (Test source rs1 = x" + str(r) + ")"
|
||||
writeCovVector(desc, r, rs2, rd, rs1val, rs2val, immval, rdval, test, xlen)
|
||||
|
||||
def make_rs2(test, xlen):
|
||||
for r in range(32):
|
||||
[rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize()
|
||||
desc = "cp_rs2 (Test source rs2 = x" + str(r) + ")"
|
||||
writeCovVector(desc, rs1, r, rd, rs1val, rs2val, immval, rdval, test, xlen)
|
||||
|
||||
def make_rd_rs1(test, xlen):
|
||||
for r in range(32):
|
||||
[rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize()
|
||||
desc = "cmp_rd_rs1 (Test rd = rs1 = x" + str(r) + ")"
|
||||
writeCovVector(desc, r, rs2, r, rs1val, rs2val, immval, rdval, test, xlen)
|
||||
|
||||
def make_rd_rs2(test, xlen):
|
||||
for r in range(32):
|
||||
[rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize()
|
||||
desc = "cmp_rd_rs2 (Test rd = rs1 = x" + str(r) + ")"
|
||||
writeCovVector(desc, rs1, r, r, rs1val, rs2val, immval, rdval, test, xlen)
|
||||
|
||||
def make_rd_rs1_rs2(test, xlen):
|
||||
for r in range(32):
|
||||
[rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize()
|
||||
desc = "cmp_rd_rs1_rs2 (Test rd = rs1 = rs2 = x" + str(r) + ")"
|
||||
writeCovVector(desc, r, r, r, rs1val, rs2val, immval, rdval, test, xlen)
|
||||
|
||||
def make_rs1_rs2(test, xlen):
|
||||
for r in range(32):
|
||||
[rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize()
|
||||
desc = "cmp_rs1_rs2 (Test rs1 = rs2 = x" + str(r) + ")"
|
||||
writeCovVector(desc, r, r, rd, rs1val, rs2val, immval, rdval, test, xlen)
|
||||
|
||||
def make_rs1_maxvals(test, xlen):
|
||||
for v in [0, 2**(xlen-1), 2**(xlen-1)-1, 2**xlen-1, 1, 2**(xlen-1)+1]:
|
||||
[rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize()
|
||||
desc = "cp_rs1_maxvals (Test source rs1 value = " + hex(v) + ")"
|
||||
writeCovVector(desc, rs1, rs2, rd, v, rs2val, immval, rdval, test, xlen)
|
||||
|
||||
def make_rs2_maxvals(test, xlen):
|
||||
for v in [0, 2**(xlen-1), 2**(xlen-1)-1, 2**xlen-1, 1, 2**(xlen-1)+1]:
|
||||
[rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize()
|
||||
desc = "cp_rs2_maxvals (Test source rs2 value = " + hex(v) + ")"
|
||||
writeCovVector(desc, rs1, rs2, rd, rs1val, v, immval, rdval, test, xlen)
|
||||
|
||||
def make_rd_maxvals(test, xlen):
|
||||
for v in [0, 2**(xlen-1), 2**(xlen-1)-1, 2**xlen-1, 1, 2**(xlen-1)+1]:
|
||||
# rs1 = 0, rs2 = v, others are random
|
||||
[rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize()
|
||||
desc = "cp_rd_maxvals (Test rd value = " + hex(v) + ")"
|
||||
writeCovVector(desc, rs1, 0, rd, v, rs2val, 0, rdval, test, xlen)
|
||||
# rs1, rs2 = v, others are random
|
||||
[rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize()
|
||||
desc = "cp_rd_maxvals (Test rd value = " + hex(v) + ")"
|
||||
writeCovVector(desc, rs1, rs2, rd, v, v, v, rdval, test, xlen)
|
||||
# rs1 = all 1s, rs2 = v, others are random
|
||||
[rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize()
|
||||
desc = "cp_rd_maxvals (Test rd value = " + hex(v) + ")"
|
||||
writeCovVector(desc, rs1, rs2, rd, v, -1, -1, rdval, test, xlen)
|
||||
|
||||
def make_rd_rs1_eqval(test, xlen):
|
||||
[rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize()
|
||||
desc = "cmp_rdm_rs1_eqval (Test rs1 = rd = " + hex(rs1val) + ")"
|
||||
writeCovVector(desc, rs1, 0, rd, rdval, rs2val, immval, rdval, test, xlen)
|
||||
|
||||
def make_rd_rs2_eqval(test, xlen):
|
||||
[rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize()
|
||||
desc = "cmp_rd_rs2_eqval (Test rs2 = rd = " + hex(rs2val) + ")"
|
||||
writeCovVector(desc, 0, rs2, rd, rs1val, rdval, immval, rdval, test, xlen)
|
||||
|
||||
def make_rs1_rs2_eqval(test, xlen):
|
||||
[rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize()
|
||||
desc = "cmp_rs1_rs2_eqval (Test rs1 = rs2 = " + hex(rs1val) + ")"
|
||||
writeCovVector(desc, rs1, rs2, rd, rs1val, rs1val, immval, rdval, test, xlen)
|
||||
|
||||
def make_cp_gpr_hazard(test, xlen):
|
||||
for haz in ["raw", "waw", "war"]:
|
||||
for src in range(2):
|
||||
[rs1a, rs2a, rda, rs1vala, rs2vala, immvala, rdvala] = randomize()
|
||||
[rs1b, rs2b, rdb, rs1valb, rs2valb, immvalb, rdvalb] = randomize()
|
||||
# set up hazard
|
||||
if (haz == "raw"):
|
||||
if (src):
|
||||
rs2b = rda
|
||||
else:
|
||||
rs1b = rda
|
||||
elif (haz == "waw"):
|
||||
rdb = rda
|
||||
elif (haz == "war"):
|
||||
if (src):
|
||||
rdb = rs2a
|
||||
else:
|
||||
rdb = rs1a
|
||||
desc = "cmp_gpr_hazard " + haz + " test"
|
||||
writeHazardVector(desc, rs1a, rs2a, rda, rs1b, rs2b, rdb, test)
|
||||
|
||||
def make_rs1_sign(test, xlen):
|
||||
for v in [1, -1]:
|
||||
[rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize()
|
||||
rs1val = abs(rs1val % 2**(xlen-1)) * v;
|
||||
desc = "cp_rs1_sign (Test source rs1 value = " + hex(rs1val) + ")"
|
||||
writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, immval, rdval, test, xlen)
|
||||
|
||||
def make_rs2_sign(test, xlen):
|
||||
for v in [1, -1]:
|
||||
[rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize()
|
||||
rs2val = abs(rs2val % 2**(xlen-1)) * v;
|
||||
desc = "cp_rs2_sign (Test source rs2 value = " + hex(rs2val) + ")"
|
||||
writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, immval, rdval, test, xlen)
|
||||
|
||||
def make_cr_rs1_rs2_sign(test, xlen):
|
||||
for v1 in [1, -1]:
|
||||
for v2 in [1, -1]:
|
||||
[rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize()
|
||||
rs1val = abs(rs1val % 2**(xlen-1)) * v1;
|
||||
rs2val = abs(rs2val % 2**(xlen-1)) * v2;
|
||||
desc = "cr_rs1_rs2 (Test source rs1 = " + hex(rs1val) + " rs2 = " + hex(rs2val) + ")"
|
||||
writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, immval, rdval, test, xlen)
|
||||
|
||||
def make_imm_zero(test, xlen):
|
||||
[rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize()
|
||||
desc = "cp_imm_zero"
|
||||
writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, 0, rdval, test, xlen)
|
||||
|
||||
def make_j_imm_ones_zeros(test, xlen):
|
||||
for align in range(2,19):
|
||||
lines = "\n# Testcase cp_imm_ones_zeros " + str(align) + "\n"
|
||||
lines = lines + "li x1, " + formatstr.format(randint(0, 2**xlen-1)) + "\n"
|
||||
lines = lines + "jal x20, 1f # jump to aligned address to stress immediate\n"
|
||||
lines = lines + ".align " + str(align) + "\n"
|
||||
lines = lines + "1:\n"
|
||||
f.write(lines)
|
||||
|
||||
def make_offset(test, xlen):
|
||||
if (test in btype):
|
||||
lines = "\n# Testcase cp_offset\n"
|
||||
lines = lines + "j 2f # jump past backward branch target\n"
|
||||
lines = lines + "1: j 3f # backward branch target: jump past backward branch\n"
|
||||
lines = lines + "2: " + test + " x0, x0, 1b # backward branch\n"
|
||||
lines = lines + "3: nop # done with sequence\n"
|
||||
f.write(lines)
|
||||
|
||||
def make_mem_hazard(test, xlen):
|
||||
lines = "\n# Testcase mem_hazard (no dependency)\n"
|
||||
lines = lines + "la x1, scratch\n"
|
||||
lines = lines + test + " x2, 0(x1)\n"
|
||||
f.write(lines)
|
||||
|
||||
def make_cr_rs1_imm(test, xlen):
|
||||
desc = "cp_cr_rs1_imm"
|
||||
[rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize()
|
||||
for s1 in range(2):
|
||||
for s2 in range(3):
|
||||
if (s1):
|
||||
rs1v = -abs(rs1val)
|
||||
else:
|
||||
rs1v = abs(rs1val)
|
||||
if (s2 == 0):
|
||||
immv = 0
|
||||
elif (s2 == 1):
|
||||
immv = abs(immval)
|
||||
else:
|
||||
immv = -abs(immval)
|
||||
writeCovVector(desc, rs1, rs2, rd, rs1v, rs2val, immv, rdval, test, xlen)
|
||||
|
||||
def make_imm_shift(test, xlen):
|
||||
desc = "cp_imm_shift"
|
||||
for shift in range(0, xlen):
|
||||
[rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize()
|
||||
writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, shift, rdval, test, xlen)
|
||||
|
||||
def write_tests(coverpoints, test, xlen):
|
||||
for coverpoint in coverpoints:
|
||||
if (coverpoint == "cp_asm_count"):
|
||||
pass
|
||||
elif (coverpoint == "cp_rd"):
|
||||
make_rd(test, xlen)
|
||||
elif (coverpoint == "cp_rs1"):
|
||||
make_rs1(test, xlen)
|
||||
elif (coverpoint == "cp_rs2"):
|
||||
make_rs2(test, xlen)
|
||||
elif (coverpoint == "cmp_rd_rs1"):
|
||||
make_rd_rs1(test, xlen)
|
||||
elif (coverpoint == "cmp_rd_rs2"):
|
||||
make_rd_rs2(test, xlen)
|
||||
elif (coverpoint == "cmp_rd_rs1_rs2"):
|
||||
make_rd_rs1_rs2(test, xlen)
|
||||
elif (coverpoint == "cmp_rd_rs1_eq"):
|
||||
pass # duplicate of cmp_rd_rs1
|
||||
elif (coverpoint == "cmp_rd_rs2_eq"):
|
||||
pass # duplicate of cmp_rd_rs2
|
||||
elif (coverpoint == "cmp_rs1_rs2_eq"):
|
||||
make_rs1_rs2(test, xlen)
|
||||
elif (coverpoint == "cp_rs1_maxvals"):
|
||||
make_rs1_maxvals(test, xlen)
|
||||
elif (coverpoint == "cp_rs2_maxvals"):
|
||||
make_rs2_maxvals(test, xlen)
|
||||
elif (coverpoint == "cp_rd_maxvals"):
|
||||
make_rd_maxvals(test, xlen)
|
||||
elif (coverpoint == "cmp_rd_rs1_eqval"):
|
||||
make_rd_rs1_eqval(test, xlen)
|
||||
elif (coverpoint == "cmp_rd_rs2_eqval"):
|
||||
make_rd_rs2_eqval(test, xlen)
|
||||
elif (coverpoint == "cmp_rs1_rs2_eqval"):
|
||||
make_rs1_rs2_eqval(test, xlen)
|
||||
elif (coverpoint == "cp_rs1_sign"):
|
||||
make_rs1_sign(test, xlen)
|
||||
elif (coverpoint == "cp_rs2_sign"):
|
||||
make_rs2_sign(test, xlen)
|
||||
elif (coverpoint == "cp_rd_sign"):
|
||||
pass #TODO hope already covered by rd_maxvals
|
||||
elif (coverpoint == "cr_rs1_rs2"):
|
||||
make_cr_rs1_rs2_sign(test, xlen)
|
||||
elif (coverpoint == "cp_gpr_hazard"):
|
||||
make_cp_gpr_hazard(test, xlen)
|
||||
elif (coverpoint == "cp_rs1_toggle"):
|
||||
pass #TODO toggle not needed and seems to be covered by other things
|
||||
elif (coverpoint == "cp_rs2_toggle"):
|
||||
pass #TODO toggle not needed and seems to be covered by other things
|
||||
elif (coverpoint == "cp_rd_toggle"):
|
||||
pass #TODO toggle not needed and seems to be covered by other things
|
||||
elif (coverpoint == "cp_imm_sign"):
|
||||
make_imm_zero(test, xlen)
|
||||
elif (coverpoint == "cr_rs1_imm"):
|
||||
make_cr_rs1_imm(test, xlen)
|
||||
elif (coverpoint == "cp_imm_ones_zeros"):
|
||||
if (test in jtype):
|
||||
make_j_imm_ones_zeros(test, xlen)
|
||||
elif (coverpoint == "cp_mem_hazard"):
|
||||
make_mem_hazard(test, xlen)
|
||||
elif (coverpoint == "cp_imm_zero"):
|
||||
make_imm_zero(test, xlen)
|
||||
elif (coverpoint == "cp_mem_unaligned"):
|
||||
pass # seems this should be part of privileged tests
|
||||
elif (coverpoint == "cp_offset"):
|
||||
make_offset(test, xlen)
|
||||
elif (coverpoint == "cr_nord_rs1_rs2"):
|
||||
pass #TODO (not if crosses are not needed)
|
||||
elif (coverpoint == "cp_imm_shift"):
|
||||
make_imm_shift(test, xlen)
|
||||
elif (coverpoint == "cp_rd_boolean"):
|
||||
pass # covered by other generators
|
||||
else:
|
||||
print("Warning: " + coverpoint + " not implemented yet for " + test)
|
||||
|
||||
def getcovergroups(coverdefdir, coverfiles):
|
||||
coverpoints = {}
|
||||
curinstr = ""
|
||||
for coverfile in coverfiles:
|
||||
coverfile = coverdefdir + "/" + coverfile + "_coverage.svh"
|
||||
f = open(coverfile, "r")
|
||||
for line in f:
|
||||
m = re.search(r'cp_asm_count.*\"(.*)"', line)
|
||||
if (m):
|
||||
# if (curinstr != ""):
|
||||
# print(curinstr + ": " + str(coverpoints[curinstr]))
|
||||
curinstr = m.group(1)
|
||||
coverpoints[curinstr] = []
|
||||
m = re.search("\s*(\S+) :", line)
|
||||
if (m):
|
||||
coverpoints[curinstr].append(m.group(1))
|
||||
f.close()
|
||||
print(coverpoints)
|
||||
return coverpoints
|
||||
|
||||
##################################
|
||||
# main body
|
||||
##################################
|
||||
|
||||
# change these to suite your tests
|
||||
riscv = os.environ.get("RISCV")
|
||||
coverdefdir = riscv+"/ImperasDV-OpenHW/Imperas/ImpProprietary/source/host/riscvISACOV/source/coverage";
|
||||
#coverfiles = ["RV64I", "RV64M", "RV64A", "RV64C", "RV64F", "RV64D"] # add more later
|
||||
coverfiles = ["RV64I"] # add more later
|
||||
rtype = ["add", "sub", "sll", "slt", "sltu", "xor", "srl", "sra", "or", "and",
|
||||
"addw", "subw", "sllw", "srlw", "sraw"
|
||||
"mul", "mulh", "mulhsu", "mulhu", "div", "divu", "rem", "remu",
|
||||
"mulw", "divw", "divuw", "remw", "remuw"]
|
||||
loaditype = ["lb", "lh", "lw", "ld", "lbu", "lhu", "lwu"]
|
||||
shiftitype = ["slli", "srli", "srai", "slliw", "srliw", "sraiw"]
|
||||
shiftiwtype = ["slliw", "srliw", "sraiw"]
|
||||
itype = ["addi", "slti", "sltiu", "xori", "ori", "andi", "addiw"]
|
||||
stype = ["sb", "sh", "sw", "sd"]
|
||||
btype = ["beq", "bne", "blt", "bge", "bltu", "bgeu"]
|
||||
jtype = ["jal"]
|
||||
jalrtype = ["jalr"]
|
||||
utype = ["lui", "auipc"]
|
||||
# TODO: auipc missing, check whatelse is missing in ^these^ types
|
||||
|
||||
coverpoints = getcovergroups(coverdefdir, coverfiles)
|
||||
|
||||
author = "David_Harris@hmc.edu"
|
||||
xlens = [64]
|
||||
numrand = 3
|
||||
|
||||
# setup
|
||||
seed(0) # make tests reproducible
|
||||
|
||||
# generate files for each test
|
||||
for xlen in xlens:
|
||||
formatstrlen = str(int(xlen/4))
|
||||
formatstr = "0x{:0" + formatstrlen + "x}" # format as xlen-bit hexadecimal number
|
||||
formatrefstr = "{:08x}" # format as xlen-bit hexadecimal number with no leading 0x
|
||||
if (xlen == 32):
|
||||
storecmd = "sw"
|
||||
wordsize = 4
|
||||
else:
|
||||
storecmd = "sd"
|
||||
wordsize = 8
|
||||
WALLY = os.environ.get('WALLY')
|
||||
pathname = WALLY+"/tests/functcov/rv" + str(xlen) + "/I/"
|
||||
cmd = "mkdir -p " + pathname + " ; rm -f " + pathname + "/*" # make directory and remove old tests in dir
|
||||
os.system(cmd)
|
||||
for test in coverpoints.keys():
|
||||
basename = "WALLY-COV-" + test
|
||||
fname = pathname + "/" + basename + ".S"
|
||||
|
||||
# print custom header part
|
||||
f = open(fname, "w")
|
||||
line = "///////////////////////////////////////////\n"
|
||||
f.write(line)
|
||||
line="// "+fname+ "\n// " + author + "\n"
|
||||
f.write(line)
|
||||
line ="// Created " + str(datetime.now()) + "\n"
|
||||
f.write(line)
|
||||
|
||||
# insert generic header
|
||||
h = open("covergen_header.S", "r")
|
||||
for line in h:
|
||||
f.write(line)
|
||||
|
||||
# print directed and random test vectors
|
||||
# Coverage for R-type arithmetic instructions
|
||||
#if (test not in rtests):
|
||||
# exit("Error: %s not implemented yet" % test)
|
||||
#else:
|
||||
# write_rtype_arith_vectors(test, xlen)
|
||||
write_tests(coverpoints[test], test, xlen)
|
||||
|
||||
# print footer
|
||||
line = "\n.EQU NUMTESTS," + str(1) + "\n\n"
|
||||
f.write(line)
|
||||
h = open("covergen_footer.S", "r")
|
||||
for line in h:
|
||||
f.write(line)
|
||||
|
||||
# Finish
|
||||
f.close()
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
@ -1,11 +0,0 @@
|
|||
|
||||
self_loop:
|
||||
j self_loop
|
||||
|
||||
.data
|
||||
|
||||
.align 4
|
||||
scratch:
|
||||
.bss 8
|
||||
|
||||
.end
|
||||
|
|
@ -1,12 +0,0 @@
|
|||
//
|
||||
// Copyright (C) 2024 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
///////////////////////////////////////////
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
|
||||
rvtest_entry_point:
|
||||
|
||||
|
||||
|
|
@ -84,6 +84,38 @@
|
|||
|
||||
000000FF
|
||||
|
||||
000000AE
|
||||
|
||||
000000AD
|
||||
|
||||
000000AC
|
||||
|
||||
000000AB
|
||||
|
||||
000000AE
|
||||
|
||||
000000AD
|
||||
|
||||
000000AC
|
||||
|
||||
000000AB
|
||||
|
||||
000000AE
|
||||
|
||||
000000AD
|
||||
|
||||
000000AC
|
||||
|
||||
000000AB
|
||||
|
||||
000000AE
|
||||
|
||||
000000AD
|
||||
|
||||
000000AC
|
||||
|
||||
000000AB
|
||||
|
||||
000000A0
|
||||
|
||||
0000000B
|
||||
|
|
|
|||
|
|
@ -162,6 +162,45 @@ test_cases:
|
|||
.4byte 0x0, 0x00000000, spi_data_wait # wait for transmission to end
|
||||
.4byte rx_data, 0x000000FF, read32_test # read rx_data
|
||||
|
||||
# Test min sck_div
|
||||
|
||||
.4byte sck_div, 0x000000000, write32_test #set sck_div to 0
|
||||
.4byte tx_data, 0xABACADAE, spi_burst_send
|
||||
.4byte 0x0, 0x00000003, spi_data_wait
|
||||
.4byte rx_data, 0x000000AE, read32_test
|
||||
.4byte rx_data, 0x000000AD, read32_test
|
||||
.4byte rx_data, 0x000000AC, read32_test
|
||||
.4byte rx_data, 0x000000AB, read32_test
|
||||
|
||||
# min sck_div, sckmode 01
|
||||
|
||||
.4byte sck_mode, 0x00000001, write32_test
|
||||
.4byte tx_data, 0xABACADAE, spi_burst_send
|
||||
.4byte 0x0, 0x00000003, spi_data_wait
|
||||
.4byte rx_data, 0x000000AE, read32_test
|
||||
.4byte rx_data, 0x000000AD, read32_test
|
||||
.4byte rx_data, 0x000000AC, read32_test
|
||||
.4byte rx_data, 0x000000AB, read32_test
|
||||
|
||||
#min sck_div, sckmode 10
|
||||
.4byte sck_mode, 0x00000002, write32_test
|
||||
.4byte tx_data, 0xABACADAE, spi_burst_send
|
||||
.4byte 0x0, 0x00000003, spi_data_wait
|
||||
.4byte rx_data, 0x000000AE, read32_test
|
||||
.4byte rx_data, 0x000000AD, read32_test
|
||||
.4byte rx_data, 0x000000AC, read32_test
|
||||
.4byte rx_data, 0x000000AB, read32_test
|
||||
|
||||
#min sck_div, sckmode 11
|
||||
.4byte sck_mode, 0x00000003, write32_test
|
||||
.4byte tx_data, 0xABACADAE, spi_burst_send
|
||||
.4byte 0x0, 0x00000003, spi_data_wait
|
||||
.4byte rx_data, 0x000000AE, read32_test
|
||||
.4byte rx_data, 0x000000AD, read32_test
|
||||
.4byte rx_data, 0x000000AC, read32_test
|
||||
.4byte rx_data, 0x000000AB, read32_test
|
||||
|
||||
|
||||
# Test phase
|
||||
|
||||
.4byte sck_div, 0x00000003, write32_test # reset sck_div to 0x03 so only sck_mode is different
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@ This folder consists of all the required files and tools to generate Q tests for
|
|||
|
||||
NOTE : Only some of the IBM tests are currently supporting Quad testing.
|
||||
|
||||
Tests which are working : ibm1, ibm9,ibm21,ibm23,ibm24,ibm25,ibm26,ibm27,ibm28,ibm29
|
||||
Tests which are implemented in riscv-isac/riscv_isac/fp_dataset.py : ibm1, ibm9,ibm21,ibm23,ibm24,ibm25,ibm26,ibm27,ibm28,ibm29
|
||||
These ibm tests can be included in the riscv-ctg tests generation command, along with riscof.
|
||||
|
||||
The tests which are currently breaking due to overflow errors are : ibm2,ibm3,ibm4,ibm5,ibm6,ibm7,ibm8,ibm10,ibm11,ibm12,ibm13,ibm14,ibm15,ibm16,ibm17,ibm18,ibm19,ibm20,ibm22
|
||||
|
|
@ -26,7 +26,7 @@ TO DO:
|
|||
Debug why fadd.q_b1 doesn't match Sail vs. Spike
|
||||
Run the q test on Wally RTL
|
||||
Make more tests from the working datasets
|
||||
Get other datasets working by using softfloat to do quad math
|
||||
Get other fp_dataset.py datasets working by using softfloat to do quad math
|
||||
Push changes back to riscv-ctg and riscv-isac and remove them from wally-riscv-arch/tsts/riscv-test-suite/rv64i_m/Q
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -1,24 +1,24 @@
|
|||
alabaster==0.7.12
|
||||
Babel==2.7.0
|
||||
Cerberus==1.3.1
|
||||
certifi==2019.6.16
|
||||
certifi==2023.7.22
|
||||
chardet==3.0.4
|
||||
doc8==0.8.0
|
||||
docutils==0.14
|
||||
gitdb2==2.0.5
|
||||
idna==2.8
|
||||
idna==3.7
|
||||
imagesize==1.1.0
|
||||
Jinja2==2.10.1
|
||||
MarkupSafe==1.1.1
|
||||
oyaml==0.9
|
||||
packaging==19.0
|
||||
pbr==5.3.1
|
||||
Pygments==2.4.2
|
||||
Pygments==2.15.0
|
||||
pyparsing==2.4.0
|
||||
python-dateutil==2.8.0
|
||||
pytz==2019.1
|
||||
PyYAML==5.1.1
|
||||
requests==2.22.0
|
||||
PyYAML==5.4
|
||||
requests==2.32.0
|
||||
restructuredtext-lint==1.3.0
|
||||
ruamel.yaml==0.15.97
|
||||
six==1.12.0
|
||||
|
|
@ -31,7 +31,7 @@ sphinxcontrib-mermaid
|
|||
sphinxcontrib-websupport==1.1.2
|
||||
sphinxcontrib-bibtex==1.0.0
|
||||
stevedore==1.30.1
|
||||
urllib3==1.25.3
|
||||
urllib3==1.26.19
|
||||
twine==1.13.0
|
||||
sphinx_tabs
|
||||
m2r2==0.2.7
|
||||
|
|
|
|||
|
|
@ -393,7 +393,7 @@ def ibm_b1(flen, iflen, opcode, ops):
|
|||
qinfinity + qdefaultnan + [qqnan[0], qqnan[1]] + \
|
||||
[qsnan[0], qsnan[1]] + qone
|
||||
else:
|
||||
logger.error('Invalid iflen value!')
|
||||
logger.error('Invalid iflen value is ' + iflen)
|
||||
sys.exit(1)
|
||||
|
||||
# the following creates a cross product for ops number of variables
|
||||
|
|
@ -4073,7 +4073,7 @@ def ibm_b21(flen, iflen, opcode, ops):
|
|||
qinfinity + qdefaultnan + [qqnan[0], qqnan[1]] + \
|
||||
[qsnan[0], qsnan[1]]
|
||||
else:
|
||||
logger.error('Invalid iflen value!')
|
||||
logger.error('Invalid iflen value 2 ' + iflen)
|
||||
sys.exit(1)
|
||||
|
||||
# the following creates a cross product for ops number of variables
|
||||
|
|
|
|||
|
|
@ -84,6 +84,38 @@
|
|||
00000000
|
||||
000000FF
|
||||
00000000
|
||||
000000AE
|
||||
00000000
|
||||
000000AD
|
||||
00000000
|
||||
000000AC
|
||||
00000000
|
||||
000000AB
|
||||
00000000
|
||||
000000AE
|
||||
00000000
|
||||
000000AD
|
||||
00000000
|
||||
000000AC
|
||||
00000000
|
||||
000000AB
|
||||
00000000
|
||||
000000AE
|
||||
00000000
|
||||
000000AD
|
||||
00000000
|
||||
000000AC
|
||||
00000000
|
||||
000000AB
|
||||
00000000
|
||||
000000AE
|
||||
00000000
|
||||
000000AD
|
||||
00000000
|
||||
000000AC
|
||||
00000000
|
||||
000000AB
|
||||
00000000
|
||||
000000A0
|
||||
00000000
|
||||
0000000B
|
||||
|
|
|
|||
|
|
@ -164,6 +164,47 @@ test_cases:
|
|||
.8byte 0x0, 0x00000000, spi_data_wait # wait for transmission to end
|
||||
.8byte rx_data, 0x000000FF, read32_test # read rx_data
|
||||
|
||||
# Test min sck_div
|
||||
|
||||
.8byte sck_div, 0x000000000, write32_test #set sck_div to 0
|
||||
.8byte tx_data, 0xABACADAE, spi_burst_send
|
||||
.8byte 0x0, 0x00000003, spi_data_wait
|
||||
.8byte rx_data, 0x000000AE, read32_test
|
||||
.8byte rx_data, 0x000000AD, read32_test
|
||||
.8byte rx_data, 0x000000AC, read32_test
|
||||
.8byte rx_data, 0x000000AB, read32_test
|
||||
|
||||
# min sck_div, sckmode 01
|
||||
|
||||
.8byte sck_mode, 0x00000001, write32_test
|
||||
.8byte tx_data, 0xABACADAE, spi_burst_send
|
||||
.8byte 0x0, 0x00000003, spi_data_wait
|
||||
.8byte rx_data, 0x000000AE, read32_test
|
||||
.8byte rx_data, 0x000000AD, read32_test
|
||||
.8byte rx_data, 0x000000AC, read32_test
|
||||
.8byte rx_data, 0x000000AB, read32_test
|
||||
|
||||
#min sck_div, sckmode 10
|
||||
.8byte sck_mode, 0x00000002, write32_test
|
||||
.8byte tx_data, 0xABACADAE, spi_burst_send
|
||||
.8byte 0x0, 0x00000003, spi_data_wait
|
||||
.8byte rx_data, 0x000000AE, read32_test
|
||||
.8byte rx_data, 0x000000AD, read32_test
|
||||
.8byte rx_data, 0x000000AC, read32_test
|
||||
.8byte rx_data, 0x000000AB, read32_test
|
||||
|
||||
#min sck_div, sckmode 11
|
||||
.8byte sck_mode, 0x00000003, write32_test
|
||||
.8byte tx_data, 0xABACADAE, spi_burst_send
|
||||
.8byte 0x0, 0x00000003, spi_data_wait
|
||||
.8byte rx_data, 0x000000AE, read32_test
|
||||
.8byte rx_data, 0x000000AD, read32_test
|
||||
.8byte rx_data, 0x000000AC, read32_test
|
||||
.8byte rx_data, 0x000000AB, read32_test
|
||||
|
||||
|
||||
|
||||
|
||||
# Test phase
|
||||
|
||||
.8byte sck_div, 0x00000003, write32_test # reset sck_div to 0x03 so only sck_mode is different
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue