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Gated InstrOrigM and PCMReg when not needed
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2d17a991d8
commit
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1 changed files with 10 additions and 7 deletions
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@ -396,17 +396,20 @@ module ifu import cvw::*; #(parameter cvw_t P) (
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flopenr #(32) InstrEReg(clk, reset, ~StallE, NextInstrD, InstrE);
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flopenr #(32) InstrMReg(clk, reset, ~StallM, NextInstrE, InstrM);
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flopenr #(P.XLEN) PCEReg(clk, reset, ~StallE, PCD, PCE);
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flopenr #(P.XLEN) PCMReg(clk, reset, ~StallM, PCE, PCM);
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//flopenr #(P.XLEN) PCPDReg(clk, reset, ~StallD, PCPlus2or4F, PCLinkD);
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//flopenr #(P.XLEN) PCPEReg(clk, reset, ~StallE, PCLinkD, PCLinkE);
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// PCM is only needed with CSRs or branch prediction
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if (P.ZICSR_SUPPORTED | P.BPRED_SUPPORTED)
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flopenr #(P.XLEN) PCMReg(clk, reset, ~StallM, PCE, PCM);
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else assign PCM = 0;
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flopenrc #(1) CompressedDReg(clk, reset, FlushD, ~StallD, CompressedF, CompressedD);
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flopenrc #(1) CompressedEReg(clk, reset, FlushE, ~StallE, CompressedD, CompressedE);
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assign PCLinkE = PCE + (CompressedE ? 'd2 : 'd4); // 'd4 means 4 but stops Design Compiler complaining about signed to unsigned conversion
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// pipeline original compressed instruction in case it is needed for MTVAL on an illegal instruction exception
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flopenrc #(16) InstrRawEReg(clk, reset, FlushE, ~StallE, InstrRawD[15:0], InstrRawE);
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flopenrc #(16) InstrRawMReg(clk, reset, FlushM, ~StallM, InstrRawE, InstrRawM);
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flopenrc #(1) CompressedMReg(clk, reset, FlushM, ~StallM, CompressedE, CompressedM);
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mux2 #(32) InstrOrigMux(InstrM, {16'b0, InstrRawM}, CompressedM, InstrOrigM);
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if (P.ZICSR_SUPPORTED) begin
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flopenrc #(16) InstrRawEReg(clk, reset, FlushE, ~StallE, InstrRawD[15:0], InstrRawE);
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flopenrc #(16) InstrRawMReg(clk, reset, FlushM, ~StallM, InstrRawE, InstrRawM);
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flopenrc #(1) CompressedMReg(clk, reset, FlushM, ~StallM, CompressedE, CompressedM);
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mux2 #(32) InstrOrigMux(InstrM, {16'b0, InstrRawM}, CompressedM, InstrOrigM);
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end else assign InstrOrigM = 0;
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endmodule
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