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https://github.com/openhwgroup/cvw.git
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Code cleanup: RAM, fdivsqrt
This commit is contained in:
David Harris
parent
6789f32154
commit
b1c9450b4a
10 changed files with 35 additions and 33 deletions
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@ -114,11 +114,12 @@ module ahbcacheinterface import cvw::*; #(
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.s(~(CacheableOrFlushCacheM)), .y(PreHWDATA));
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flopen #(P.AHBW) wdreg(HCLK, HREADY, PreHWDATA, HWDATA); // delay HWDATA by 1 cycle per spec
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// *** bummer need a second byte mask for bus as it is AHBW rather than LLEN.
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// probably can merge by muxing PAdrM's LLEN/8-1 index bit based on HTRANS being != 0.
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if (READ_ONLY_CACHE) begin
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assign HWSTRB = '0;
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end else begin // compute byte mask for AHB transaction based on size and address. AHBW may be different than LLEN
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swbytemask #(P.AHBW) busswbytemask(.Size(HSIZE), .Adr(HADDR[$clog2(P.AHBW/8)-1:0]), .ByteMask(BusByteMaskM), .ByteMaskExtended());
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flopen #(P.AHBW/8) HWSTRBReg(HCLK, HREADY, BusByteMaskM[P.AHBW/8-1:0], HWSTRB);
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end
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buscachefsm #(BeatCountThreshold, AHBWLOGBWPL, READ_ONLY_CACHE, P.BURST_EN) AHBBuscachefsm(
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.HCLK, .HRESETn, .Flush, .BusRW, .BusAtomic, .Stall, .BusCommitted, .BusStall, .CaptureEn, .SelBusBeat,
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@ -44,7 +44,7 @@ module fdivsqrtiter import cvw::*; #(parameter cvw_t P) (
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logic [P.DIVb+3:0] WCNext[P.DIVCOPIES-1:0]; // Q4.DIVb
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logic [P.DIVb+3:0] WS[P.DIVCOPIES:0]; // Q4.DIVb
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logic [P.DIVb+3:0] WC[P.DIVCOPIES:0]; // Q4.DIVb
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logic [P.DIVb:0] U[P.DIVCOPIES:0]; // U1.DIVb // *** probably Q not U. See Table 16.26 notes
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logic [P.DIVb:0] U[P.DIVCOPIES:0]; // U1.DIVb
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logic [P.DIVb:0] UM[P.DIVCOPIES:0]; // U1.DIVb
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logic [P.DIVb:0] UNext[P.DIVCOPIES-1:0]; // U1.DIVb
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logic [P.DIVb:0] UMNext[P.DIVCOPIES-1:0]; // U1.DIVb
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@ -222,7 +222,7 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) (
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logic RemOpE;
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/* verilator lint_off WIDTH */
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assign IntDivNormShiftE = P.DIVb - (CyclesE * P.RK - P.LOGR); // b - rn, used for integer normalization right shift. rn = Cycles * r * k - r ***explain
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assign IntDivNormShiftE = P.DIVb - (CyclesE * P.RK - P.LOGR); // b - rn, used for integer normalization right shift. n = (Cycles * k - 1)
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assign IntRemNormShiftE = mE + (P.DIVb-(P.XLEN-1)); // m + b - (N-1) for remainder normalization shift
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/* verilator lint_on WIDTH */
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assign RemOpE = Funct3E[1];
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@ -52,7 +52,7 @@ module fdivsqrtstage4 import cvw::*; #(parameter cvw_t P) (
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// Digit Selection logic
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assign j0 = ~C[P.DIVb+1]; // first step of R digit selection: C = 00...0
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assign j1 = C[P.DIVb] & ~C[P.DIVb-1]; // second step of R digit selection: C = 1100...0; *** could simplify to ~C[P.DIVb-1] because j=0 case takes priority
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assign j1 = ~C[P.DIVb-1]; // second step of R digit selection: C = 1100...0; simplified from C[P.DIVb] & ~C[P.DIVb-1] because j=0 case takes priority
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assign Smsbs = U[P.DIVb:P.DIVb-4]; // U1.4 most significant bits of square root
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assign Dmsbs = D[P.DIVb-1:P.DIVb-3]; // U0.3 most significant fractional bits of divisor after leading 1
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assign WCmsbs = WC[P.DIVb+3:P.DIVb-4]; // Q4.4 most significant bits of residual
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@ -95,7 +95,7 @@ module fdivsqrtuslc4cmp (
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// Choose A for current operation
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always_comb
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if (SqrtE) begin
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if (Smsbs[4]) A = 3'b111; // for S = 1.0000 *** can we optimize away this case?
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if (Smsbs[4]) A = 3'b111; // for S = 1.0000
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else A = Smsbs[2:0];
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end else A = Dmsbs;
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@ -108,7 +108,7 @@ module fdivsqrtuslc4cmp (
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/* Nannarelli12 design to exploit symmetry is slower because of negation and mux for special case of A = 000
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assign mk0 = -mk1;
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assign mkm1 = (A == 3'b000) ? -13 : -mk2; // asymmetry in table *** can we hide from critical path
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assign mkm1 = (A == 3'b000) ? -13 : -mk2; // asymmetry in table
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*/
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// Compare residual W to selection constants to choose digit
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@ -44,8 +44,6 @@ module ram1p1rwbe import cvw::*; #(parameter USE_SRAM=0, DEPTH=64, WIDTH=44, PRE
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output logic [WIDTH-1:0] dout
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);
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bit [WIDTH-1:0] RAM[DEPTH-1:0];
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///////////////////////////////////////////////////////////////////////////////
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// TRUE SRAM macro
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///////////////////////////////////////////////////////////////////////////////
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@ -83,6 +81,7 @@ module ram1p1rwbe import cvw::*; #(parameter USE_SRAM=0, DEPTH=64, WIDTH=44, PRE
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// READ first SRAM model
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///////////////////////////////////////////////////////////////////////////////
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end else begin: ram
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bit [WIDTH-1:0] RAM[DEPTH-1:0];
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integer i;
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if (PRELOAD_ENABLED) begin
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@ -41,11 +41,9 @@ module ram1p1rwe import cvw::* ; #(parameter USE_SRAM=0, DEPTH=64, WIDTH=44) (
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output logic [WIDTH-1:0] dout
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);
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bit [WIDTH-1:0] RAM[DEPTH-1:0];
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// ***************************************************************************
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//////////////////////////////////////////////////////////////////////////////
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// TRUE SRAM macro
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// ***************************************************************************
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//////////////////////////////////////////////////////////////////////////////
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if ((USE_SRAM == 1) & (WIDTH == 128) & (DEPTH == 64)) begin // Cache data subarray
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// 64 x 128-bit SRAM
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ram1p1rwbe_64x128 sram1A (.CLK(clk), .CEB(~ce), .WEB(~we),
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@ -64,12 +62,15 @@ module ram1p1rwe import cvw::* ; #(parameter USE_SRAM=0, DEPTH=64, WIDTH=44) (
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.A(addr), .D(din),
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.BWEB('0), .Q(dout));
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// ***************************************************************************
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//////////////////////////////////////////////////////////////////////////////
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// READ first SRAM model
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// ***************************************************************************
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//////////////////////////////////////////////////////////////////////////////
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end else begin: ram
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// *** Vivado is not implementing this as block ram for some reason.
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// The version with byte write enables it correctly infers block ram.
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bit [WIDTH-1:0] RAM[DEPTH-1:0];
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integer i;
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// Combinational read: register address and read after clock edge
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@ -44,7 +44,6 @@ module ram2p1r1wbe import cvw::*; #(parameter USE_SRAM=0, DEPTH=1024, WIDTH=68)
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output logic [WIDTH-1:0] rd1
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);
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bit [WIDTH-1:0] mem[DEPTH-1:0];
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localparam SRAMWIDTH = 32;
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localparam SRAMNUMSETS = SRAMWIDTH/WIDTH;
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@ -105,24 +104,26 @@ module ram2p1r1wbe import cvw::*; #(parameter USE_SRAM=0, DEPTH=1024, WIDTH=68)
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.QA(SRAMReadData),
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.QB());
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end else begin
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end else begin:ram
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///////////////////////////////////////////////////////////////////////////////
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// READ first SRAM model
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///////////////////////////////////////////////////////////////////////////////
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bit [WIDTH-1:0] RAM[DEPTH-1:0];
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integer i;
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/*
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initial begin // initialize memory for simulation only; not needed because done in the testbench now
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integer j;
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for (j=0; j < DEPTH; j++)
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mem[j] = '0;
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RAM[j] = '0;
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end
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*/
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// Read
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logic [$clog2(DEPTH)-1:0] ra1d;
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flopen #($clog2(DEPTH)) adrreg(clk, ce1, ra1, ra1d);
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assign rd1 = mem[ra1d];
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assign rd1 = RAM[ra1d];
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// Write divided into part for bytes and part for extra msbs
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// coverage off
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@ -131,13 +132,13 @@ module ram2p1r1wbe import cvw::*; #(parameter USE_SRAM=0, DEPTH=1024, WIDTH=68)
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always @(posedge clk)
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if (ce2 & we2)
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for(i = 0; i < WIDTH/8; i++)
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if(bwe2[i]) mem[wa2][i*8 +: 8] <= wd2[i*8 +: 8];
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if(bwe2[i]) RAM[wa2][i*8 +: 8] <= wd2[i*8 +: 8];
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// coverage on
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if (WIDTH%8 != 0) // handle msbs if width not a multiple of 8
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always @(posedge clk)
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if (ce2 & we2 & bwe2[WIDTH/8])
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mem[wa2][WIDTH-1:WIDTH-WIDTH%8] <= wd2[WIDTH-1:WIDTH-WIDTH%8];
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RAM[wa2][WIDTH-1:WIDTH-WIDTH%8] <= wd2[WIDTH-1:WIDTH-WIDTH%8];
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end
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endmodule
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@ -64,13 +64,13 @@ module DCacheFlushFSM import cvw::*; #(parameter cvw_t P)
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.loglinebytelen(loglinebytelen), .sramlen(sramlen))
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copyShadow(.clk,
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.start,
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.tag(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].CacheTagMem.RAM[index][P.PA_BITS-1-tagstart:0]),
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.tag(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].CacheTagMem.ram.RAM[index][P.PA_BITS-1-tagstart:0]),
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.valid(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].ValidBits[index]),
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.dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].DirtyBits[index]),
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// these dirty bit selections would be needed if dirty is moved inside the tag array.
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//.dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].dirty.DirtyMem.RAM[index]),
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//.dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].CacheTagMem.RAM[index][P.PA_BITS+tagstart]),
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.data(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].word[cacheWord].wordram.CacheDataMem.RAM[index]),
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.data(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].word[cacheWord].wordram.CacheDataMem.ram.RAM[index]),
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.index(index),
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.cacheWord(cacheWord),
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.CacheData(CacheData[way][index][cacheWord]),
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@ -499,10 +499,10 @@ module testbench;
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readResult = $fread(dut.uncoregen.uncore.bootrom.bootrom.memory.ROM, memFile);
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$fclose(memFile);
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memFile = $fopen(memfilename, "rb");
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readResult = $fread(dut.uncoregen.uncore.ram.ram.memory.RAM, memFile);
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readResult = $fread(dut.uncoregen.uncore.ram.ram.memory.ram.RAM, memFile);
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$fclose(memFile);
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end else
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$readmemh(memfilename, dut.uncoregen.uncore.ram.ram.memory.RAM);
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$readmemh(memfilename, dut.uncoregen.uncore.ram.ram.memory.ram.RAM);
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if (TEST == "embench") $display("Read memfile %s", memfilename);
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end
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if (CopyRAM) begin
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@ -511,7 +511,7 @@ module testbench;
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EndIndex = (end_signature_addr >> LogXLEN) + 8;
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BaseIndex = P.UNCORE_RAM_BASE >> LogXLEN;
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for(ShadowIndex = StartIndex; ShadowIndex <= EndIndex; ShadowIndex++) begin
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testbench.DCacheFlushFSM.ShadowRAM[ShadowIndex] = dut.uncoregen.uncore.ram.ram.memory.RAM[ShadowIndex - BaseIndex];
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testbench.DCacheFlushFSM.ShadowRAM[ShadowIndex] = dut.uncoregen.uncore.ram.ram.memory.ram.RAM[ShadowIndex - BaseIndex];
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end
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end
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end
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@ -519,7 +519,7 @@ module testbench;
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if (P.DTIM_SUPPORTED) begin
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always @(posedge clk) begin
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if (LoadMem) begin
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$readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM);
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$readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.ram.RAM);
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$display("Read memfile %s", memfilename);
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end
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if (CopyRAM) begin
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@ -528,7 +528,7 @@ module testbench;
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EndIndex = (end_signature_addr >> LogXLEN) + 8;
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BaseIndex = P.UNCORE_RAM_BASE >> LogXLEN;
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for(ShadowIndex = StartIndex; ShadowIndex <= EndIndex; ShadowIndex++) begin
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testbench.DCacheFlushFSM.ShadowRAM[ShadowIndex] = dut.core.lsu.dtim.dtim.ram.RAM[ShadowIndex - BaseIndex];
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testbench.DCacheFlushFSM.ShadowRAM[ShadowIndex] = dut.core.lsu.dtim.dtim.ram.ram.RAM[ShadowIndex - BaseIndex];
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end
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end
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end
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@ -539,7 +539,7 @@ module testbench;
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always @(posedge clk)
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if (ResetMem) // program memory is sometimes reset (e.g. for CoreMark, which needs zeroed memory)
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for (adrindex=0; adrindex<(P.UNCORE_RAM_RANGE>>1+(P.XLEN/32)); adrindex = adrindex+1)
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dut.uncoregen.uncore.ram.ram.memory.RAM[adrindex] = '0;
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dut.uncoregen.uncore.ram.ram.memory.ram.RAM[adrindex] = '0;
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////////////////////////////////////////////////////////////////////////////////
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// Actual hardware
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