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Merge pull request #1209 from jordancarlin/update_fetch_buffer

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Update fetch buffer
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David Harris 2024-12-30 12:49:29 -08:00 • committed by GitHub
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21
.github/dependabot.yml vendored Normal file
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@ -0,0 +1,21 @@
# To get started with Dependabot version updates, you'll need to specify which
# package ecosystems to update and where the package manifests are located.
# Please see the documentation for all configuration options:
# https://docs.github.com/code-security/dependabot/dependabot-version-updates/configuration-options-for-the-dependabot.yml-file
version: 2
updates:
# Update git submodules to latest version
- package-ecosystem: "gitsubmodule"
directory: "/"
schedule:
interval: "weekly"
ignore:
- dependency-name: "addins/coremark"
- dependency-name: "addins/embench-iot"
- dependency-name: "addins/verilog-ethernet"
# Update actions in the GitHub Actions workflow files
- package-ecosystem: "github-actions"
directory: "/"
schedule:
interval: "weekly"

38
.github/workflows/install.yml vendored
View file

@ -38,25 +38,46 @@ jobs:
- name: ubuntu-20.04
os: ubuntu-20.04
container: null
regressionFail: true
- name: ubuntu-22.04
os: ubuntu-22.04
container: null
- name: ubuntu-24.04
os: ubuntu-24.04
container: null
# Debian Installations
- name: debian-12
os: ubuntu-latest
image: debian:12
imageFamily: debian
- name: debian-11
os: ubuntu-latest
image: debian:11
imageFamily: debian
# Red Hat Installations
- name: rocky-8
os: ubuntu-latest
image: rockylinux:8
imageFamily: redhat
regressionFail: true
- name: rocky-9
os: ubuntu-latest
image: rockylinux:9
imageFamily: redhat
- name: almalinux-8
os: ubuntu-latest
image: almalinux:8
imageFamily: redhat
regressionFail: true
- name: almalinux-9
os: ubuntu-latest
image: almalinux:9
imageFamily: redhat
# SUSE Installations
- name: opensuse-15.6
os: ubuntu-latest
image: opensuse/leap:15.6
imageFamily: suse
# User level installation
- name: user-install
os: ubuntu-latest
@ -82,11 +103,18 @@ jobs:
steps:
# Docker images need git installed or the checkout action fails
- name: Install Dependencies for Red Hat
- name: Install Dependencies for Container Image
if: ${{ matrix.image != null }}
run: |
dnf install -y sudo git
dnf install curl -y --allowerasing || true
if [ ${{ matrix.imageFamily }} == "debian" ]; then
apt-get update
apt-get install -y sudo git
elif [ ${{ matrix.imageFamily }} == "redhat" ]; then
dnf install -y sudo git
dnf install curl -y --allowerasing || true
elif [ ${{ matrix.imageFamily }} == "suse" ]; then
zypper install -y sudo git
fi
# Only clone submodules needed for standard tests/regression to save space
- uses: actions/checkout@v4
- name: Clone Necessary Submodules
@ -140,12 +168,12 @@ jobs:
df -h
# Run standard regression, skipping distros that are known to be broken with Verilator
- name: Regression
if: ${{ matrix.name != 'ubuntu-20.04' && matrix.name != 'rocky-8' && matrix.name != 'almalinux-8'}}
if: ${{ matrix.regressionFail != true }}
run: |
source setup.sh
regression-wally
- name: Lint + wsim Test Only (for distros with broken Verilator sim)
if: ${{ matrix.name == 'ubuntu-20.04' || matrix.name == 'rocky-8' || matrix.name == 'almalinux-8'}}
if: ${{ matrix.regressionFail == true }}
run: |
source setup.sh
mkdir -p $WALLY/sim/verilator/logs/

7
.gitignore vendored
View file

@ -12,6 +12,7 @@
*.map
*.elf*
*.list
*.memfile
# General directories to ignore
.vscode/
@ -33,6 +34,7 @@ tests/fp/combined_IF_vectors/IF_vectors/*.tv
tests/custom/*/*/
tests/custom/*/*/*.memfile
sim/tests/riscvdv
testbench/trek_files/uvm_output
# Linux
linux/buildroot
@ -105,9 +107,6 @@ sim/questa/wkdir
sim/questa/ucdb
sim/questa/cov
sim/questa/fcov
sim/questa/fcovrvvi
sim/questa/fcovrvvi_logs
sim/questa/fcovrvvi_ucdb
sim/questa/fcov_logs
sim/questa/fcov_ucdb
sim/questa/riscv.ucdb
@ -156,6 +155,8 @@ examples/C/mcmodel/mcmodel_medany
examples/C/mcmodel/mcmodel_medlow
examples/C/sum/sum
examples/C/sum_mixed/sum_mixed
examples/C/hello/hello
examples/C/gpio/gpio
examples/asm/sumtest/sumtest
examples/asm/example/example
examples/asm/trap/trap

6
.gitmodules vendored
View file

@ -8,9 +8,6 @@
[submodule "addins/coremark"]
path = addins/coremark
url = https://github.com/eembc/coremark
[submodule "addins/FreeRTOS-Kernel"]
path = addins/FreeRTOS-Kernel
url = https://github.com/FreeRTOS/FreeRTOS-Kernel.git
[submodule "addins/vivado-boards"]
path = addins/vivado-boards
url = https://github.com/Digilent/vivado-boards/
@ -29,9 +26,6 @@
path = addins/cvw-arch-verif
url = https://github.com/openhwgroup/cvw-arch-verif
ignore = dirty
[submodule "addins/riscvISACOV"]
path = addins/riscvISACOV
url = https://github.com/riscv-verification/riscvISACOV.git
[submodule "addins/berkeley-softfloat-3"]
path = addins/berkeley-softfloat-3
url = https://github.com/ucb-bar/berkeley-softfloat-3.git

13
Makefile
View file

@ -6,9 +6,9 @@ MAKEFLAGS += --output-sync --no-print-directory
SIM = ${WALLY}/sim
.PHONY: all riscof testfloat combined_IF_vectors zsbl benchmarks coremark embench coverage clean
.PHONY: all riscof testfloat combined_IF_vectors zsbl benchmarks coremark embench coverage cvw-arch-verif clean
all: riscof testfloat combined_IF_vectors zsbl coverage # benchmarks
all: riscof testfloat combined_IF_vectors zsbl coverage cvw-arch-verif # benchmarks
# riscof builds the riscv-arch-test and wally-riscv-arch-test suites
riscof:
@ -36,6 +36,15 @@ embench:
coverage:
$(MAKE) -C tests/coverage
cvw-arch-verif:
$(MAKE) -C ${WALLY}/addins/cvw-arch-verif
# Requires a license for the Breker tool. See tests/breker/README.md for details
breker:
$(MAKE) -C ${WALLY}/testbench/trek_files
$(MAKE) -C ${WALLY}/tests/breker
clean:
$(MAKE) clean -C sim
$(MAKE) clean -C ${WALLY}/tests/fp
$(MAKE) clean -C ${WALLY}/addins/cvw-arch-verif

66
README.md
View file

@ -59,7 +59,19 @@ Then fork and clone the repo, source setup, make the tests and run regression
fi
```
9. Build the tests and run a regression simulation to prove everything is installed. Building tests may take a while.
9. Try compiling the HelloWally program and simulating it on the SystemVerilog with Verilator and on the Spike simulator.
```
$ cd examples/C/hello
$ make
$ wsim --sim verilator rv64gc --elf hello
Hello Wally!
0 1 2 3 4 5 6 7 8 9
$ spike hello
Hello Wally!
0 1 2 3 4 5 6 7 8 9
```
10. Build the tests and run a regression simulation to prove everything is installed. Building tests may take a while.
```bash
$ make --jobs
@ -71,7 +83,8 @@ Then fork and clone the repo, source setup, make the tests and run regression
> This section describes the open source toolchain installation.
### Compatibility
The current version of the toolchain has been tested on Ubuntu (versions 20.04 LTS, 22.04 LTS, and 24.04 LTS) and on Red Hat/Rocky/AlmaLinux (versions 8 and 9).
The current version of the toolchain has been tested on Ubuntu (versions 20.04 LTS, 22.04 LTS, and 24.04 LTS), Debian (versions 11 and 12), Red Hat/Rocky/AlmaLinux (versions 8 and 9),
and SUSE version 15.6. Only the latest minor release of each major version is tested.
> [!WARNING]
> - Ubuntu 22.04LTS is incompatible with Synopsys Design Compiler.
@ -135,11 +148,17 @@ export VCS_HOME=.. # Change this for your path to Synopsys VCS
Electronic Design Automation (EDA) tools are vital to implementations of System on Chip architectures as well as validating different designs. Open-source and commercial tools exist for multiple strategies and although the one can spend a lifetime using combinations of different tools, only a small subset of tools is utilized for this text. The tools are chosen because of their ease in access as well as their repeatability for accomplishing many of the tasks utilized to design Wally. It is anticipated that additional tools may be documented later after this is text is published to improve use and access.
Siemens Questa is the primary tool utilized for simulating and validating Wally. For logic synthesis, you will need Synopsys Design Compiler. Questa and Design Compiler are commercial tools that require an educational or commercial license.
Verilator is an open-source Verilog simulator. It is fast and free. Run Wally on the riscv-arch-test suite using Verilator with:
```
regression-wally
```
Running code or functional coverage simulations or lock-step presently require commercial tools. Siemens Questa is the primary tool utilized for simulating and validating Wally. Synopsys VCS also can run regression-wally and lock-step simulation. For logic synthesis, you will need Synopsys Design Compiler. Questa and Design Compiler are commercial tools that require an educational or commercial license.
Note: Some EDA tools utilize `LM_LICENSE_FILE` for their environmental variable to point to their license server. Some operating systems may also utilize `MGLS_LICENSE_FILE` instead, therefore, it is important to read the user manual on the preferred environmental variable required to point to a user’s license file. Although there are different mechanisms to allow licenses to work, many companies commonly utilize the FlexLM (i.e., Flex-enabled) license server manager that runs off a node locked license.
Although most EDA tools are Linux-friendly, they tend to have issues when not installed on recommended OS flavors. Both Red Hat Enterprise Linux and SUSE Linux products typically tend to be recommended for installing commercial-based EDA tools and are recommended for utilizing complex simulation and architecture exploration. Questa can also be installed on Microsoft Windows as well as Mac OS with a Virtual Machine such as Parallels.
Although most EDA tools are Linux-friendly, they tend to have issues when not installed on recommended OS flavors. Red Hat Enterprise Linux (and its free Rocky clone) and SUSE Linux products typically tend to be recommended for installing commercial-based EDA tools and are recommended for utilizing complex simulation and architecture exploration.
### Siemens Questa
@ -196,37 +215,40 @@ Startups can expect to spend more than $1 million on CAD tools to get a chip to
# Adding Cron Job for nightly builds
If you want to add a cronjob you can do the following:
1) Set up the email client `mutt` for your distribution
1) Set up the email client `mutt` to send emails through the command line
2) Enter `crontab -e` into a terminal
3) add this code to test building CVW and then running `regression-wally --nightly` at 9:30 PM each day
3) add this code to test cloning CVW, making CVW's tests, then running `regression-wally --nightly --buildroot` every day at 21:30 in your local time
```bash
30 21 * * * bash -l -c "source ~/PATH/TO/CVW/setup.sh; PATH_TO_CVW/cvw/bin/wrapper_nightly_runs.sh --path {PATH_TO_TEST_LOCATION} --target all --tests nightly --send_email harris@hmc.edu,kaitlin.verilog@gmail.com"
30 21 * * * curl -L https://raw.githubusercontent.com/openhwgroup/cvw/refs/heads/main/bin/nightly_build.py | python - --path {PATH_FOR_NIGHTLY_RUNS} --target all --tests all --send_email harris@hmc.edu,rose@rosethompson.net
```
This utility will take up approximately 100 GB on your hard drive. You can also run the script directly from `bin/nightly_build.py`.
# Example wsim commands
wsim runs one of multiple simulators, Questa, VCS, or Verilator using a specific configuration and either a suite of tests or a specific elf file.
The general syntax is
`wsim <config> <suite or elf file or directory> [--options]`
`wsim <config> <suite or elf file> [--options]`
Parameters and options:
```
-h, --help show this help message and exit
--elf ELF, -e ELF ELF File name; use if name does not end in .elf
--sim {questa,verilator,vcs}, -s {questa,verilator,vcs} Simulator
--tb {testbench,testbench_fp}, -t {testbench,testbench_fp} Testbench
--gui, -g Simulate with GUI
--coverage, -c Code & Functional Coverage
--fcov, -f Code & Functional Coverage
--ccov, -c Code Coverage
--fcov, -f Functional Coverage with cvw-arch-verif, implies lockstep
--args ARGS, -a ARGS Optional arguments passed to simulator via $value$plusargs
--params PARAMS, -p PARAMS Optional top-level parameter overrides of the form param=value
--define DEFINE, -d DEFINE Optional define macros passed to simulator
--vcd, -v Generate testbench.vcd
--lockstep, -l Run ImperasDV lock, step, and compare.
--locksteplog LOCKSTEPLOG, -b LOCKSTEPLOG Retired instruction number to be begin logging.
--covlog COVLOG, -d COVLOG Log coverage after n instructions.
--elfext ELFEXT, -e ELFEXT When searching for elf files only includes ones which end in this extension
--lockstepverbose, -lv Run ImperasDV lock, step, and compare with tracing enabled
--rvvi, -r Simulate rvvi hardware interface and ethernet.
```
Run basic test with questa
Run basic test with Questa
```bash
wsim rv64gc arch64i
@ -238,26 +260,26 @@ Run Questa with gui
wsim rv64gc wally64priv --gui
```
Run lockstep against ImperasDV with a single elf file in the gui. Lockstep requires single elf.
Run basic test with Verilator
```bash
wsim rv64gc ../../tests/riscof/work/riscv-arch-test/rv64i_m/I/src/add-01.S/ref/ref.elf --lockstep --gui
wsim rv32i arch32i --sim verilator
```
Run lockstep against ImperasDV with a single elf file. Compute coverage.
Run lockstep against ImperasDV with a single elf file in the gui. Lockstep requires single elf.
```bash
wsim rv64gc ../../tests/riscof/work/riscv-arch-test/rv64i_m/I/src/add-01.S/ref/ref.elf --lockstep --coverage
wsim rv64gc $WALLY/tests/riscof/work/riscv-arch-test/rv64i_m/I/src/add-01.S/ref/ref.elf --lockstep --gui
```
Run lockstep against ImperasDV with directory file.
Run lockstep against ImperasDV with a single elf file. Collect functional coverage.
```bash
wsim rv64gc ../../tests/riscof/work/riscv-arch-test/rv64i_m/I/src/ --lockstep
wsim rv64gc $WALLY/addins/cvw-arch-verif/tests/rv64/Zicsr/WALLY-COV-ALL.elf --fcov
```
Run lockstep against ImperasDV with directory file and specify specific extension.
Run Linux boot simulation in lock step between Wally and ImperasDV
```bash
wsim rv64gc ../../tests/riscof/work/riscv-arch-test/rv64i_m/I/src/ --lockstep --elfext ref.elf
wsim buildroot buildroot --args +INSTR_LIMIT=600000000 --lockstep
```

1
addins/FreeRTOS-Kernel

@ -1 +0,0 @@
Subproject commit 17a46c252f2f237e03a6768c5d15731215322f31

2
addins/cvw-arch-verif

@ -1 +1 @@
Subproject commit 6d658b7b42c83fd584008d72964cc75d0876b769
Subproject commit acf99b1df40b4c90090f17ce1448a7d6a6fde1f5

2
addins/riscv-arch-test

@ -1 +1 @@
Subproject commit 3843c736e427a2b52a0d06e6220b073afa4be401
Subproject commit a079bb263b04dde4028efee134f3a4e42799a5ca

1
addins/riscvISACOV

@ -1 +0,0 @@
Subproject commit ac9fa2d386c0cb2f44e1e1e83a555d585034dfa3

2
addins/vivado-boards

@ -1 +1 @@
Subproject commit e5f0728cd284d10080ae8eb03fc86e7b5eafcb72
Subproject commit 8ed4f9981da1d80badb0b1f65e250b2dbf7a564d

19
bin/CacheSim.py
View file

@ -84,7 +84,16 @@ class Cache:
for way in self.ways:
for line in way:
line.dirty = False
# access a cbo type instruction
def cbo(self, addr, invalidate):
tag, setnum, _ = self.splitaddr(addr)
for waynum in range(self.numways):
line = self.ways[waynum][setnum]
if line.tag == tag and line.valid:
line.dirty = 0
if invalidate: line.valid = 0
# invalidates the cache by setting all valid bits to False
def invalidate(self):
for way in self.ways:
@ -243,9 +252,15 @@ def main():
cache.invalidate()
if args.verbose:
print("I")
elif lninfo[1] == 'V' or lninfo[1] == 'L' or lninfo[1] == 'C':
addr = int(lninfo[0], 16)
IsCBOClean = lninfo[1] != 'C'
cache.cbo(addr, IsCBOClean)
if args.verbose:
print(lninfo[1]);
else:
addr = int(lninfo[0], 16)
iswrite = lninfo[1] == 'W' or lninfo[1] == 'A'
iswrite = lninfo[1] == 'W' or lninfo[1] == 'A' or lninfo[1] == 'Z'
result = cache.cacheaccess(addr, iswrite)
if args.verbose:

2
bin/lint-wally
View file

@ -30,7 +30,7 @@ for config in ${configs[@]}; do
if !($verilator --lint-only --quiet --top-module wallywrapper \
"-I$basepath/config/shared" "-I$basepath/config/$config" "-I$basepath/config/deriv/$config" \
$basepath/src/cvw.sv $basepath/testbench/wallywrapper.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv \
-Wall -Wno-UNUSEDSIGNAL -Wno-UNUSEDPARAM -Wno-VARHIDDEN -Wno-GENUNNAMED -Wno-PINCONNECTEMPTY); then
-Wall -Wno-UNUSEDSIGNAL -Wno-VARHIDDEN -Wno-GENUNNAMED -Wno-PINCONNECTEMPTY); then
if [ "$1" == "-nightly" ]; then
echo -e "${RED}$config failed lint${NC}"
fails=$((fails+1))

105
bin/regression-wally
View file

@ -34,7 +34,7 @@ tests = [
"arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "arch32zfh", "arch32zfh_fma",
"arch32zfh_divsqrt", "arch32zfaf", "arch32zfad", "wally32a_lrsc", "wally32priv", "wally32periph", "arch32zcb",
"arch32zbkb", "arch32zbkc", "arch32zbkx", "arch32zknd", "arch32zkne", "arch32zknh"]],
["rv64i", ["arch64i"]]
["rv64i", ["arch64i"]]
]
# Separate test for short buildroot run through OpenSBI UART output
@ -265,8 +265,8 @@ class bcolors:
def addTests(tests, sim):
sim_logdir = WALLY+ "/sim/" + sim + "/logs/"
for test in tests:
config = test[0];
suites = test[1];
config = test[0]
suites = test[1]
if (len(test) >= 3):
args = " --args " + " ".join(test[2])
else:
@ -291,17 +291,39 @@ def addTests(tests, sim):
configs.append(tc)
def addLockstepTestsByDir(dir, config, sim, fcovMode):
sim_logdir = WALLY+ "/sim/" + sim + "/logs/"
if (coverStr != ""): # use --fcov in place of --lockstep
cmdPrefix="wsim --sim " + sim + " " + coverStr + " " + config
else:
cmdPrefix="wsim --lockstep --sim " + sim + " " + config
if (os.path.isdir(dir)):
def addTestsByDir(dir, config, sim, lockstepMode=0, brekerMode=0):
if os.path.isdir(dir):
sim_logdir = WALLY+ "/sim/" + sim + "/logs/"
if coverStr == "--fcov": # use --fcov in place of --lockstep
cmdPrefix="wsim --sim " + sim + " " + coverStr + " " + config
gs="Mismatches : 0"
if ("cvw-arch-verif/tests" in dir and not "priv" in dir):
fileEnd = "ALL.elf"
else:
fileEnd = ".elf"
elif coverStr == "--ccov":
cmdPrefix="wsim --sim " + sim + " " + coverStr + " " + config
gs="Single Elf file tests are not signatured verified."
if ("cvw-arch-verif/tests" in dir and not "priv" in dir):
fileEnd = "ALL.elf"
else:
fileEnd = ".elf"
elif lockstepMode:
cmdPrefix="wsim --lockstep --sim " + sim + " " + config
gs="Mismatches : 0"
fileEnd = ".elf"
elif brekerMode:
cmdPrefix="wsim --sim " + sim + " " + config
gs="# trek: info: summary: Test PASSED"
fileEnd = ".elf"
else:
cmdPrefix="wsim --sim " + sim + " " + config
gs="Single Elf file tests are not signatured verified."
fileEnd = ".elf"
for dirpath, dirnames, filenames in os.walk(os.path.abspath(dir)):
for file in filenames:
# fcov lockstep only runs on WALLY-COV-ALL.elf files; other lockstep runs on all files
if (file.endswith(".elf") and fcovMode == 0 or file.endswith("ALL.elf") and fcovMode == 1):
if file.endswith(fileEnd):
fullfile = os.path.join(dirpath, file)
fields = fullfile.rsplit('/', 3)
if (fields[2] == "ref"):
@ -317,7 +339,7 @@ def addLockstepTestsByDir(dir, config, sim, fcovMode):
name=file,
variant=config,
cmd=cmdPrefix + " " + fullfile + " > " + sim_log,
grepstr="Mismatches : 0",
grepstr=gs,
grepfile = sim_log)
configs.append(tc)
else:
@ -378,14 +400,14 @@ parser.add_argument("--fcov", help="Functional Coverage", action="store_true")
parser.add_argument("--nightly", help="Run large nightly regression", action="store_true")
parser.add_argument("--buildroot", help="Include Buildroot Linux boot test (takes many hours, done along with --nightly)", action="store_true")
parser.add_argument("--testfloat", help="Include Testfloat floating-point unit tests", action="store_true")
parser.add_argument("--fp", help="Include floating-point tests in coverage (slower runtime)", action="store_true")
parser.add_argument("--fp", help="Include floating-point tests in coverage (slower runtime)", action="store_true") # Currently not used
parser.add_argument("--breker", help="Run Breker tests", action="store_true") # Requires a license for the breker tool. See tests/breker/README.md for details
parser.add_argument("--dryrun", help="Print commands invoked to console without running regression", action="store_true")
args = parser.parse_args()
if (args.nightly):
nightMode = "--nightly";
nightMode = "--nightly"
sims = ["questa", "verilator", "vcs"] # exercise all simulators; can omit a sim if no license is available
# sims = ["questa", "verilator"] # exercise all simulators; can omit a sim if no license is available
else:
nightMode = ""
sims = [defaultsim]
@ -395,7 +417,7 @@ if (args.ccov): # only run RV64GC tests in coverage mode
elif (args.fcov): # only run RV64GC tests in lockstep in coverage mode
coverStr = '--fcov'
else:
coverStr = ''
coverStr = ''
# Run Lint
@ -416,14 +438,16 @@ if (args.buildroot):
addTests(tests_buildrootbootlockstep, lockstepsim) # lockstep with Questa and ImperasDV runs overnight
if (args.ccov): # only run RV64GC tests on Questa in code coverage mode
addTests(tests64gc_nofp, coveragesim)
if (args.fp):
addTests(tests64gc_fp, coveragesim)
elif (args.fcov): # only run RV64GC tests on Questa in lockstep in functional coverage mode
addLockstepTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/rv32/", "rv32gc", coveragesim, 1)
addLockstepTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/rv64/", "rv64gc", coveragesim, 1)
#addLockstepTestsByDir(WALLY+"/tests/riscof/work/wally-riscv-arch-test/rv64i_m/privilege/src/", "rv64gc", coveragesim, 0)
addTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/rv64/", "rv64gc", coveragesim)
addTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/priv/rv64/", "rv64gc", coveragesim)
addTestsByDir(WALLY+"/tests/coverage/", "rv64gc", coveragesim)
elif (args.fcov): # run tests in lockstep in functional coverage mode
addTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/rv32/", "rv32gc", coveragesim)
addTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/rv64/", "rv64gc", coveragesim)
addTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/priv/rv32/", "rv32gc", coveragesim)
addTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/priv/rv64/", "rv64gc", coveragesim)
elif (args.breker):
addTestsByDir(WALLY+"/tests/breker/work", "breker", "questa", brekerMode=1)
else:
for sim in sims:
if (not (args.buildroot and sim == lockstepsim)): # skip short buildroot sim if running long one
@ -434,8 +458,9 @@ else:
# run derivative configurations and lockstep tests in nightly regression
if (args.nightly):
addLockstepTestsByDir(WALLY+"/tests/coverage", "rv64gc", lockstepsim, 0)
addLockstepTestsByDir(WALLY+"/tests/riscof/work/wally-riscv-arch-test/rv64i_m", "rv64gc", lockstepsim, 0)
addTestsByDir(WALLY+"/tests/coverage", "rv64gc", lockstepsim, lockstepMode=1)
addTestsByDir(WALLY+"/tests/riscof/work/wally-riscv-arch-test/rv64i_m", "rv64gc", lockstepsim, lockstepMode=1)
addTestsByDir(WALLY+"/tests/riscof/work/wally-riscv-arch-test/rv32i_m", "rv32gc", lockstepsim, lockstepMode=1)
addTests(derivconfigtests, defaultsim)
# addTests(bpredtests, defaultsim) # This is currently broken in regression due to something related to the new wsim script.
@ -515,7 +540,7 @@ def main():
pass
if args.ccov:
TIMEOUT_DUR = 20*60 # seconds
os.system('rm -f questa/cov/*.ucdb')
os.system('rm -f questa/ucdb/* questa/cov/*')
elif args.fcov:
TIMEOUT_DUR = 8*60
os.system('rm -f questa/fcov_ucdb/* questa/fcov_logs/* questa/fcov/*')
@ -532,27 +557,27 @@ def main():
# max out at a limited number of concurrent processes to not overwhelm the system
# right now fcov, ccov, nightly all use Imperas
if (args.ccov or args.fcov or args.nightly):
ImperasDVLicenseCount = 8 # limit number of concurrent processes to avoid overloading ImperasDV licenses
ImperasDVLicenseCount = 16 # limit number of concurrent processes to avoid overloading ImperasDV licenses
else:
ImperasDVLicenseCount = 10000 # effectively no license limit for non-lockstep tests
with Pool(processes=min(len(configs),multiprocessing.cpu_count(), ImperasDVLicenseCount)) as pool:
num_fail = 0
results = {}
for config in configs:
results[config] = pool.apply_async(run_test_case,(config, args.dryrun))
for (config,result) in results.items():
try:
num_fail+=result.get(timeout=TIMEOUT_DUR)
except TimeoutError:
pool.terminate()
num_fail+=1
print(f"{bcolors.FAIL}%s: Timeout - runtime exceeded %d seconds{bcolors.ENDC}" % (config.cmd, TIMEOUT_DUR))
num_fail = 0
results = {}
for config in configs:
results[config] = pool.apply_async(run_test_case,(config, args.dryrun))
for (config,result) in results.items():
try:
num_fail+=result.get(timeout=TIMEOUT_DUR)
except TimeoutError:
pool.terminate()
num_fail+=1
print(f"{bcolors.FAIL}%s: Timeout - runtime exceeded %d seconds{bcolors.ENDC}" % (config.cmd, TIMEOUT_DUR))
# Coverage report
if args.ccov:
os.system('make QuestaCodeCoverage')
if args.fcov:
os.system('make -f '+WALLY+'/addins/cvw-arch-verif/Makefile merge')
os.system('make -C '+WALLY+'/addins/cvw-arch-verif merge')
# Count the number of failures
if num_fail:
print(f"{bcolors.FAIL}Regression failed with %s failed configurations{bcolors.ENDC}" % num_fail)

74
bin/wally-distro-check.sh
View file

@ -41,52 +41,96 @@ ENDC='\033[0m' # Reset to default color
# Print section header
section_header() {
if tput cols > /dev/null 2>&1; then
printf "${SECTION_COLOR}%$(tput cols)s" | tr ' ' '#'
printf "%$(tput cols)s" | tr ' ' '#'
echo -e "$1"
printf "%$(tput cols)s" | tr ' ' '#'
printf "%$(tput cols)s${ENDC}" | tr ' ' '#'
printf "${SECTION_COLOR}%$(tput cols)s\n" | tr ' ' '#'
printf "%$(tput cols)s\n" | tr ' ' '#'
printf "%s\n" "$1"
printf "%$(tput cols)s\n" | tr ' ' '#'
printf "%$(tput cols)s${ENDC}\n" | tr ' ' '#'
else
echo -e "${SECTION_COLOR}$1${ENDC}"
printf "${SECTION_COLOR}%s\n${ENDC}" "$1"
fi
}
section_header "Checking System Requirements and Configuring Installation"
# Get distribution information
test -e /etc/os-release && os_release="/etc/os-release" || os_release="/usr/lib/os-release"
source "$os_release"
if [ -f /etc/os-release ]; then
source /etc/os-release
else
printf "${FAIL_COLOR}%s\n${ENDC}" "/etc/os-release file not found. Distribution unknown."
PRETTY_NAME=UNKNOWN
fi
# Check for compatible distro
if [[ "$ID" == rhel || "$ID_LIKE" == *rhel* ]]; then
export FAMILY=rhel
if [ "$ID" != rhel ] && [ "$ID" != rocky ] && [ "$ID" != almalinux ]; then
printf "${WARNING_COLOR}%s\n${ENDC}" "For Red Hat family distros, the Wally install script has only been tested on RHEL, Rocky Linux," \
printf "${WARNING_COLOR}%s%s\n${ENDC}" "For Red Hat family distros, the Wally installation script has only been tested on RHEL, Rocky Linux," \
" and AlmaLinux. Your distro is $PRETTY_NAME. The regular Red Hat install will be attempted, but there may be issues."
fi
export RHEL_VERSION="${VERSION_ID:0:1}"
if (( RHEL_VERSION < 8 )); then
echo "${FAIL_COLOR}The Wally install script is only compatible with versions 8 and 9 of RHEL, Rocky Linux, and AlmaLinux. You have version $VERSION.${ENDC}"
printf "${FAIL_COLOR}%s\n${ENDC}" "The Wally installation script is only compatible with versions 8 and 9 of RHEL, Rocky Linux, and AlmaLinux. You have version $VERSION."
exit 1
fi
elif [[ "$ID" == ubuntu || "$ID_LIKE" == *ubuntu* ]]; then
export FAMILY=ubuntu
if [ "$ID" != ubuntu ]; then
printf "${WARNING_COLOR}%s\n${ENDC}" "For Ubuntu family distros, the Wally install script has only been tested on standard Ubuntu. Your distro " \
printf "${WARNING_COLOR}%s%s\n${ENDC}" "For Ubuntu family distros, the Wally installation script is only tested on standard Ubuntu. Your distro " \
"is $PRETTY_NAME. The regular Ubuntu install will be attempted, but there may be issues."
# Ubuntu derivates may use different version numbers. Attempt to derive version from Ubuntu codename
case "$UBUNTU_CODENAME" in
noble)
export UBUNTU_VERSION=24
;;
jammy)
export UBUNTU_VERSION=22
;;
focal)
export UBUNTU_VERSION=20
;;
*)
printf "${FAIL_COLOR}%s\n${ENDC}" "Unable to determine which base Ubuntu version you are using."
exit 1
;;
esac
echo "Detected Ubuntu derivative baesd on Ubuntu $UBUNTU_VERSION.04."
else
export UBUNTU_VERSION="${VERSION_ID:0:2}"
fi
export UBUNTU_VERSION="${VERSION_ID:0:2}"
if (( UBUNTU_VERSION < 20 )); then
echo "${FAIL_COLOR}The Wally install script has only been tested with versions 20.04 LTS, 22.04 LTS, and 24.04 LTS of Ubuntu. You have version $VERSION.${ENDC}"
printf "${FAIL_COLOR}%s\n${ENDC}" "The Wally installation script has only been tested with Ubuntu versions 20.04 LTS, 22.04 LTS, and 24.04 LTS. You have version $VERSION."
exit 1
fi
elif [[ "$ID" == debian || "$ID_LIKE" == *debian* ]]; then
export FAMILY=debian
if [ "$ID" != debian ]; then
printf "${WARNING_COLOR}%s%s\n${ENDC}" "For Debian family distros, the Wally installation script has only been tested on standard Debian (and Ubuntu). Your distro " \
"is $PRETTY_NAME. The regular Debian install will be attempted, but there may be issues."
fi
export DEBIAN_VERSION="$VERSION_ID"
if (( DEBIAN_VERSION < 11 )); then
printf "${FAIL_COLOR}%s\n${ENDC}" "The Wally installation script has only been tested with Debian versions 11 and 12. You have version $VERSION."
exit 1
fi
elif [[ "$ID" == opensuse-leap || "$ID" == sles || "$ID_LIKE" == *suse* ]]; then
export FAMILY=suse
if [[ "$ID" != opensuse-leap && "$ID" != sles ]]; then
printf "${WARNING_COLOR}%s%s\n${ENDC}" "For SUSE family distros, the Wally installation script has only been tested on OpenSUSE Leap and SLES. Your distro " \
"is $PRETTY_NAME. The regular SUSE install will be attempted, but there may be issues. If you are using OpenSUSE Tumbleweed, the version check will fail."
fi
export SUSE_VERSION="${VERSION_ID//.}"
if (( SUSE_VERSION < 156 )); then
printf "${FAIL_COLOR}%s\n${ENDC}" "The Wally installation script has only been tested with SUSE version 15.6. You have version $VERSION."
exit 1
fi
else
printf "${FAIL_COLOR}%s\n${ENDC}" "The Wally install script is currently only compatible with Ubuntu and Red Hat family " \
printf "${FAIL_COLOR}%s%s%s\n${ENDC}" "The Wally installation script is currently only compatible with Ubuntu, Debian, SUSE, and Red Hat family " \
"(RHEL, Rocky Linux, or AlmaLinux) distros. Your detected distro is $PRETTY_NAME. You may try manually running the " \
"commands in this script, but it is likely that some will need to be altered."
exit 1
fi
echo -e "${OK_COLOR}${UNDERLINE}Detected information${ENDC}"
printf "${OK_COLOR}${UNDERLINE}%s\n${ENDC}" "Detected information"
echo "Distribution: $PRETTY_NAME"
echo "Version: $VERSION"

108
bin/wally-package-install.sh
View file

@ -43,55 +43,83 @@ if [ -z "$FAMILY" ]; then
fi
# Generate list of packages to install and package manager commands based on distro
# Packages are grouped by which tool requires them. If multiple tools need a package, it is included in the first tool only
if [ "$FAMILY" == rhel ]; then
PYTHON_VERSION=python3.12
PACKAGE_MANAGER="dnf"
UPDATE_COMMAND="sudo $PACKAGE_MANAGER update -y"
GENERAL_PACKAGES+=(which rsync git make cmake "$PYTHON_VERSION" "$PYTHON_VERSION"-pip curl wget tar pkgconf-pkg-config dialog mutt ssmtp)
GNU_PACKAGES+=(autoconf automake libmpc-devel mpfr-devel gmp-devel gawk bison flex texinfo gperf libtool patchutils bc gcc gcc-c++ zlib-devel expat-devel libslirp-devel)
QEMU_PACKAGES+=(glib2-devel libfdt-devel pixman-devel bzip2 ninja-build)
SPIKE_PACKAGES+=(dtc boost-regex boost-system)
VERILATOR_PACKAGES+=(help2man perl clang ccache gperftools numactl mold)
BUILDROOT_PACKAGES+=(ncurses-base ncurses ncurses-libs ncurses-devel gcc-gfortran cpio) # gcc-gfortran is only needed for compiling spec benchmarks on buildroot linux
# Extra packages not availale in rhel8, nice for Verilator
if (( RHEL_VERSION >= 9 )); then
VERILATOR_PACKAGES+=(perl-doc)
fi
# A newer version of gcc is required for qemu
OTHER_PACKAGES=(gcc-toolset-13)
elif [ "$FAMILY" == ubuntu ]; then
if (( UBUNTU_VERSION >= 24 )); then
# Packages that are constant across distros
GENERAL_PACKAGES+=(rsync git make cmake curl wget tar unzip bzip2 dialog mutt)
GNU_PACKAGES+=(autoconf automake gawk bison flex texinfo gperf libtool patchutils bc gcc)
VERILATOR_PACKAGES+=(help2man perl clang ccache numactl)
BUILDROOT_PACKAGES+=(cpio)
# Distro specific packages and package manager
case "$FAMILY" in
rhel)
PYTHON_VERSION=python3.12
VERILATOR_PACKAGES+=(mold) # Not availale in Ubuntu 20.04, nice for Verilator
elif (( UBUNTU_VERSION >= 22 )); then
PYTHON_VERSION=python3.11
VERILATOR_PACKAGES+=(mold) # Not availale in Ubuntu 20.04, nice for Verilator
elif (( UBUNTU_VERSION >= 20 )); then
PYTHON_VERSION=python3.9
OTHER_PACKAGES+=(gcc-10 g++-10 cpp-10) # Newer version of gcc needed for Verilator
fi
PACKAGE_MANAGER="DEBIAN_FRONTEND=noninteractive apt-get"
UPDATE_COMMAND="sudo $PACKAGE_MANAGER update -y && sudo $PACKAGE_MANAGER upgrade -y --with-new-pkgs"
GENERAL_PACKAGES+=(rsync git make cmake "$PYTHON_VERSION" python3-pip "$PYTHON_VERSION"-venv curl wget tar pkg-config dialog mutt ssmtp)
GNU_PACKAGES+=(autoconf automake autotools-dev curl libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev libexpat1-dev ninja-build libglib2.0-dev libslirp-dev)
QEMU_PACKAGES+=(libfdt-dev libpixman-1-dev)
SPIKE_PACKAGES+=(device-tree-compiler libboost-regex-dev libboost-system-dev)
VERILATOR_PACKAGES+=(help2man perl g++ clang ccache libunwind-dev libgoogle-perftools-dev numactl perl-doc libfl2 libfl-dev zlib1g)
BUILDROOT_PACKAGES+=(ncurses-base ncurses-bin libncurses-dev gfortran cpio) # gfortran is only needed for compiling spec benchmarks on buildroot linux
VIVADO_PACKAGES+=(libncurses*) # Vivado hangs on the third stage of installation without this
fi
PACKAGE_MANAGER="dnf -y"
UPDATE_COMMAND="sudo $PACKAGE_MANAGER update"
GENERAL_PACKAGES+=(which "$PYTHON_VERSION" "$PYTHON_VERSION"-pip pkgconf-pkg-config gcc-c++ ssmtp)
GNU_PACKAGES+=(libmpc-devel mpfr-devel gmp-devel zlib-devel expat-devel libslirp-devel ninja-build)
QEMU_PACKAGES+=(glib2-devel libfdt-devel pixman-devel)
SPIKE_PACKAGES+=(dtc boost-regex boost-system)
VERILATOR_PACKAGES+=(gperftools mold)
BUILDROOT_PACKAGES+=(ncurses ncurses-base ncurses-libs ncurses-devel gcc-gfortran) # gcc-gfortran is only needed for compiling spec benchmarks on buildroot linux
# Extra packages not availale in rhel8, nice for Verilator
if (( RHEL_VERSION >= 9 )); then
VERILATOR_PACKAGES+=(perl-doc)
fi
# A newer version of gcc is required for qemu
OTHER_PACKAGES+=(gcc-toolset-13)
;;
ubuntu | debian)
if (( UBUNTU_VERSION >= 24 )); then
PYTHON_VERSION=python3.12
elif (( UBUNTU_VERSION >= 22 )); then
PYTHON_VERSION=python3.11
elif (( UBUNTU_VERSION >= 20 )); then
PYTHON_VERSION=python3.9
OTHER_PACKAGES+=(gcc-10 g++-10 cpp-10) # Newer version of gcc needed for Verilator
elif (( DEBIAN_VERSION >= 12 )); then
PYTHON_VERSION=python3.11
elif (( DEBIAN_VERSION >= 11 )); then
PYTHON_VERSION=python3.9
fi
# Mold not available in older distros for Verilator, will download binary instead
if (( UBUNTU_VERSION != 20 && DEBIAN_VERSION != 11 )); then
VERILATOR_PACKAGES+=(mold)
fi
PACKAGE_MANAGER="DEBIAN_FRONTEND=noninteractive apt-get -y"
UPDATE_COMMAND="sudo $PACKAGE_MANAGER update && sudo $PACKAGE_MANAGER upgrade --with-new-pkgs"
GENERAL_PACKAGES+=("$PYTHON_VERSION" python3-pip "$PYTHON_VERSION"-venv pkg-config g++ ssmtp)
GNU_PACKAGES+=(autotools-dev libmpc-dev libmpfr-dev libgmp-dev build-essential ninja-build zlib1g-dev libexpat1-dev libglib2.0-dev libslirp-dev)
QEMU_PACKAGES+=(libfdt-dev libpixman-1-dev)
SPIKE_PACKAGES+=(device-tree-compiler libboost-regex-dev libboost-system-dev)
VERILATOR_PACKAGES+=(libunwind-dev libgoogle-perftools-dev perl-doc libfl2 libfl-dev zlib1g)
BUILDROOT_PACKAGES+=(ncurses-base ncurses-bin libncurses-dev gfortran) # gfortran is only needed for compiling spec benchmarks on buildroot linux
VIVADO_PACKAGES+=(libncurses*) # Vivado hangs on the third stage of installation without this
;;
suse)
PYTHON_VERSION=python3.12
PYTHON_VERSION_PACKAGE=python312
PACKAGE_MANAGER="zypper -n"
UPDATE_COMMAND="sudo $PACKAGE_MANAGER update"
GENERAL_PACKAGES+=("$PYTHON_VERSION_PACKAGE" "$PYTHON_VERSION_PACKAGE"-pip pkg-config)
GNU_PACKAGES+=(mpc-devel mpfr-devel gmp-devel zlib-devel libexpat-devel libslirp-devel ninja)
QEMU_PACKAGES+=(glib2-devel libpixman-1-0-devel) # maybe also need qemu itself?
SPIKE_PACKAGES+=(dtc libboost_regex1_75_0-devel libboost_system1_75_0-devel)
VERILATOR_PACKAGES+=(gperftools perl-doc)
BUILDROOT_PACKAGES+=(ncurses-utils ncurses-devel ncurses5-devel gcc-fortran) # gcc-fortran is only needed for compiling spec benchmarks on buildroot linux
OTHER_PACKAGES+=(gcc13 gcc13-c++ cpp13) # Newer version of gcc needed for many tools. Default is gcc7
;;
esac
# Check if required packages are installed or install/update them depending on passed flag.
if [ "${1}" == "--check" ]; then
section_header "Checking Dependencies from Package Manager"
if [ "$FAMILY" == rhel ]; then
if [[ "$FAMILY" == rhel || "$FAMILY" == suse ]]; then
for pack in "${GENERAL_PACKAGES[@]}" "${GNU_PACKAGES[@]}" "${QEMU_PACKAGES[@]}" "${SPIKE_PACKAGES[@]}" "${VERILATOR_PACKAGES[@]}" "${BUILDROOT_PACKAGES[@]}" "${OTHER_PACKAGES[@]}"; do
rpm -q "$pack" > /dev/null || (echo -e "${FAIL_COLOR}Missing packages detected (${WARNING_COLOR}$pack${FAIL_COLOR}). Run as root to auto-install or run wally-package-install.sh first.${ENDC}" && exit 1)
done
elif [ "$FAMILY" == ubuntu ]; then
elif [[ "$FAMILY" == ubuntu || "$FAMILY" == debian ]]; then
for pack in "${GENERAL_PACKAGES[@]}" "${GNU_PACKAGES[@]}" "${QEMU_PACKAGES[@]}" "${SPIKE_PACKAGES[@]}" "${VERILATOR_PACKAGES[@]}" "${BUILDROOT_PACKAGES[@]}" "${OTHER_PACKAGES[@]}"; do
dpkg -l "$pack" | grep "ii" > /dev/null || (echo -e "${FAIL_COLOR}Missing packages detected (${WARNING_COLOR}$pack${FAIL_COLOR}). Run as root to auto-install or run wally-package-install.sh first." && exit 1)
done
@ -122,7 +150,7 @@ else
# Update and Upgrade tools
eval "$UPDATE_COMMAND"
# Install packages listed above using appropriate package manager
sudo $PACKAGE_MANAGER install -y "${GENERAL_PACKAGES[@]}" "${GNU_PACKAGES[@]}" "${QEMU_PACKAGES[@]}" "${SPIKE_PACKAGES[@]}" "${VERILATOR_PACKAGES[@]}" "${BUILDROOT_PACKAGES[@]}" "${OTHER_PACKAGES[@]}" "${VIVADO_PACKAGES[@]}"
sudo $PACKAGE_MANAGER install "${GENERAL_PACKAGES[@]}" "${GNU_PACKAGES[@]}" "${QEMU_PACKAGES[@]}" "${SPIKE_PACKAGES[@]}" "${VERILATOR_PACKAGES[@]}" "${BUILDROOT_PACKAGES[@]}" "${OTHER_PACKAGES[@]}" "${VIVADO_PACKAGES[@]}"
# Post install steps
# Vivado looks for ncurses5 libraries, but Ubuntu 24.04 only has ncurses6

25
bin/wally-tool-chain-install.sh
View file

@ -118,7 +118,7 @@ if [ "$1" == "--clean" ] || [ "$2" == "--clean" ]; then
shift
fi
# Check for clean flag
# Check for no-buildroot flag
if [ "$1" == "--no-buildroot" ] || [ "$2" == "--no-buildroot" ]; then
no_buidroot=true
shift
@ -191,6 +191,12 @@ fi
# Enable newer version of gcc for older distros (required for QEMU/Verilator)
if [ "$FAMILY" == rhel ]; then
source /opt/rh/gcc-toolset-13/enable
elif [ "$FAMILY" == suse ]; then
mkdir -p "$RISCV"/gcc-13/bin
for f in gcc cpp g++ gcc-ar gcc-nm gcc-ranlib gcov gcov-dump gcov-tool lto-dump; do
ln -vsf /usr/bin/$f-13 "$RISCV"/gcc-13/bin/$f
done
export PATH="$RISCV"/gcc-13/bin:$PATH
elif (( UBUNTU_VERSION == 20 )); then
mkdir -p "$RISCV"/gcc-10/bin
for f in gcc cpp g++ gcc-ar gcc-nm gcc-ranlib gcov gcov-dump gcov-tool lto-dump; do
@ -263,17 +269,30 @@ if (( RHEL_VERSION == 8 )); then
fi
fi
# Mold needed for Verilator
if (( UBUNTU_VERSION == 20 || DEBIAN_VERSION == 11 )) || [ "$FAMILY" == suse ]; then
STATUS="mold"
if [ ! -e "$RISCV"/bin/mold ]; then
section_header "Installing mold"
cd "$RISCV"
wget -nv --retry-connrefused $retry_on_host_error --output-document=mold.tar.gz https://github.com/rui314/mold/releases/download/v2.34.1/mold-2.34.1-x86_64-linux.tar.gz
tar xz --directory="$RISCV" --strip-components=1 -f mold.tar.gz
rm -f mold.tar.gz
echo -e "${SUCCESS_COLOR}Mold successfully installed/updated!${ENDC}"
else
echo -e "${SUCCESS_COLOR}Mold already installed.${ENDC}"
fi
fi
# RISC-V GNU Toolchain (https://github.com/riscv-collab/riscv-gnu-toolchain)
# The RISC-V GNU Toolchain includes the GNU Compiler Collection (gcc), GNU Binutils, Newlib,
# and the GNU Debugger Project (gdb). It is a collection of tools used to compile RISC-V programs.
# To install GCC from source can take hours to compile.
# This configuration enables multilib to target many flavors of RISC-V.
# This book is tested with GCC 13.2.0
# This book is tested with GCC 13.2.0 and 14.2.0.
section_header "Installing/Updating RISC-V GNU Toolchain"
STATUS="riscv-gnu-toolchain"
cd "$RISCV"
# Temporarily pin riscv-gnu-toolchain to use GCC 13.2.0. GCC 14 does not work with the Q extension.
if git_check "riscv-gnu-toolchain" "https://github.com/riscv/riscv-gnu-toolchain" "$RISCV/riscv-gnu-toolchain/stamps/build-gcc-newlib-stage2"; then
cd "$RISCV"/riscv-gnu-toolchain
git reset --hard && git clean -f && git checkout master && git pull && git submodule update

320
bin/wsim
View file

@ -13,179 +13,177 @@
import argparse
import os
import sys
########################
# main wsim script
########################
# Parse arguments
parser = argparse.ArgumentParser()
parser.add_argument("config", help="Configuration file")
parser.add_argument("testsuite", help="Test suite or path to .elf file")
parser.add_argument("--elf", "-e", help="ELF File name; use if name does not end in .elf", default="")
parser.add_argument("--sim", "-s", help="Simulator", choices=["questa", "verilator", "vcs"], default="questa")
parser.add_argument("--tb", "-t", help="Testbench", choices=["testbench", "testbench_fp"], default="testbench")
parser.add_argument("--gui", "-g", help="Simulate with GUI", action="store_true")
parser.add_argument("--ccov", "-c", help="Code Coverage", action="store_true")
parser.add_argument("--fcovimp", "-f2", help="Functional Coverage with Imperas licensed riscvISACOV, implies lockstep", action="store_true")
parser.add_argument("--fcov", "-f", help="Functional Coverage with cvw-arch-verif, implies lockstep", action="store_true")
parser.add_argument("--args", "-a", help="Optional arguments passed to simulator via $value$plusargs", default="")
parser.add_argument("--params", "-p", help="Optional top-level parameter overrides of the form param=value", default="")
parser.add_argument("--vcd", "-v", help="Generate testbench.vcd", action="store_true")
parser.add_argument("--lockstep", "-l", help="Run ImperasDV lock, step, and compare.", action="store_true")
parser.add_argument("--locksteplog", "-b", help="Retired instruction number to be begin logging.", default=0)
parser.add_argument("--lockstepverbose", "-lv", help="Run ImperasDV lock, step, and compare with tracing enabled", action="store_true")
parser.add_argument("--covlog", "-d", help="Log coverage after n instructions.", default=0)
parser.add_argument("--rvvi", "-r", help="Simulate rvvi hardware interface and ethernet.", action="store_true")
args = parser.parse_args()
print("Config=" + args.config + " tests=" + args.testsuite + " sim=" + args.sim + " gui=" + str(args.gui) + " args='" + args.args + "'")
ElfFile=""
# Global variable
WALLY = os.environ.get('WALLY')
if(os.path.isfile(args.elf)):
ElfFile = "+ElfFile=" + os.path.abspath(args.elf)
elif (args.elf != ""):
print("ELF file not found: " + args.elf)
exit(1)
def parseArgs():
parser = argparse.ArgumentParser()
parser.add_argument("config", help="Configuration file")
parser.add_argument("testsuite", nargs="?", help="Test suite or path to .elf file")
parser.add_argument("--elf", "-e", help="ELF File name; use if name does not end in .elf", default="")
parser.add_argument("--sim", "-s", help="Simulator", choices=["questa", "verilator", "vcs"], default="questa")
parser.add_argument("--tb", "-t", help="Testbench", choices=["testbench", "testbench_fp"], default="testbench")
parser.add_argument("--gui", "-g", help="Simulate with GUI", action="store_true")
parser.add_argument("--ccov", "-c", help="Code Coverage", action="store_true")
parser.add_argument("--fcov", "-f", help="Functional Coverage with cvw-arch-verif, implies lockstep", action="store_true")
parser.add_argument("--args", "-a", help="Optional arguments passed to simulator via $value$plusargs", default="")
parser.add_argument("--params", "-p", help="Optional top-level parameter overrides of the form param=value", default="")
parser.add_argument("--define", "-d", help="Optional define macros passed to simulator", default="")
parser.add_argument("--vcd", "-v", help="Generate testbench.vcd", action="store_true")
parser.add_argument("--lockstep", "-l", help="Run ImperasDV lock, step, and compare.", action="store_true")
parser.add_argument("--lockstepverbose", "-lv", help="Run ImperasDV lock, step, and compare with tracing enabled", action="store_true")
parser.add_argument("--rvvi", "-r", help="Simulate rvvi hardware interface and ethernet.", action="store_true")
return parser.parse_args()
if(args.testsuite.endswith('.elf') and args.elf == ""): # No --elf argument; check if testsuite has a .elf extension and use that instead
if (os.path.isfile(args.testsuite)):
ElfFile = "+ElfFile=" + os.path.abspath(args.testsuite)
# extract the elf name from the path to be the test suite
fields = args.testsuite.rsplit('/', 3)
# if the name is just ref.elf in a deep path (riscv-arch-test/wally-riscv-arch-test), then use the directory name as the test suite to make it unique; otherwise work directory will have duplicates.
if (len(fields) > 3):
if (fields[2] == "ref"):
args.testsuite = fields[1] + "_" + fields[3]
else:
args.testsuite = fields[2] + "_" + fields[3]
elif ('/' in args.testsuite):
args.testsuite=args.testsuite.rsplit('/', 1)[1] # strip off path if present
else:
print("ELF file not found: " + args.testsuite)
exit(1)
if(args.lockstep and not args.testsuite.endswith('.elf') and not args.testsuite == "buildroot"):
print(f"Invalid Options. Cannot run a testsuite, {args.testsuite} with lockstep. Must run a single elf.")
exit(1)
# Validate arguments
if (args.gui or args.ccov or args.fcov or args.fcovimp or args.lockstep or args.lockstepverbose):
if args.sim not in ["questa", "vcs"]:
def validateArgs(args):
if not args.testsuite and not args.elf:
print("Error: Missing test suite or ELF file")
sys.exit(1)
if any([args.lockstep, args.lockstepverbose, args.fcov]) and not (args.testsuite.endswith('.elf') or args.elf) and args.testsuite != "buildroot":
print(f"Invalid Options. Cannot run a testsuite, {args.testsuite} with lockstep or fcov. Must run a single elf or buildroot.")
sys.exit(1)
elif any([args.gui, args.ccov, args.fcov, args.lockstep, args.lockstepverbose]) and args.sim not in ["questa", "vcs"]:
print("Option only supported for Questa and VCS")
exit(1)
sys.exit(1)
elif (args.tb == "testbench_fp" and args.sim != "questa"):
print("Error: testbench_fp presently only supported by Questa, not VCS or Verilator, because of a touchy testbench")
sys.exit(1)
elif (args.config == "breker" and args.sim != "questa"):
print("Error: Breker tests currently only supported by Questa")
sys.exit(1)
if (args.vcd):
args.args += " -DMAKEVCD=1"
def elfFileCheck(args):
ElfFile = ""
if os.path.isfile(args.elf):
ElfFile = os.path.abspath(args.elf)
elif args.elf:
print(f"ELF file not found: {args.elf}")
sys.exit(1)
elif args.testsuite.endswith('.elf'): # No --elf argument; check if testsuite has a .elf extension and use that instead
if os.path.isfile(args.testsuite):
ElfFile = os.path.abspath(args.testsuite)
# extract the elf name from the path to be the test suite
fields = args.testsuite.rsplit('/', 3)
# if the name is just ref.elf in a deep path (riscv-arch-test/wally-riscv-arch-test), then use the directory name as the test suite to make it unique; otherwise work directory will have duplicates.
if "breker" in args.testsuite:
args.testsuite = fields[-1]
elif len(fields) > 3:
if fields[2] == "ref":
args.testsuite = f"{fields[1]}_{fields[3]}"
else:
args.testsuite = f"{fields[2]}_{fields[3]}"
elif '/' in args.testsuite:
args.testsuite=args.testsuite.rsplit('/', 1)[1] # strip off path if present
else:
print(f"ELF file not found: {args.testsuite}")
sys.exit(1)
return ElfFile
if (args.rvvi):
args.params += " RVVI_SYNTH_SUPPORTED=1 "
def prepSim(args, ElfFile):
prefix = ""
paramsList = []
argsList = []
flagsList = []
defineList = []
if args.vcd:
paramsList.append("MAKE_VCD=1")
if args.rvvi:
paramsList.append("RVVI_SYNTH_SUPPORTED=1")
if args.tb == "testbench_fp":
paramsList.append(f'TEST="{args.testsuite}"')
if ElfFile:
argsList.append(f"+ElfFile={ElfFile}")
if args.gui and args.tb == "testbench":
paramsList.append("DEBUG=1")
if args.ccov:
flagsList.append("--ccov")
if args.fcov:
flagsList.append("--fcov")
defineList.extend(["+define+INCLUDE_TRACE2COV", "+define+IDV_INCLUDE_TRACE2COV", "+define+COVER_BASE_RV32I"]) # COVER_BASE_RV32I is just needed to keep riscvISACOV happy, but does not affect tests
argsList.extend(["+TRACE2COV_ENABLE=1", "+IDV_TRACE2COV=1"])
if args.gui:
flagsList.append("--gui")
if args.lockstep or args.lockstepverbose:
flagsList.append("--lockstep")
if args.lockstep or args.lockstepverbose or args.fcov:
prefix = lockstepSetup(args)
defineList.append("+define+USE_IMPERAS_DV")
if args.config == "breker": # Requires a license for the breker tool. See tests/breker/README.md for details
ElfFileNoExtension = os.path.splitext(ElfFile)[0]
flagsList.append("--breker")
defineList.append("+define+USE_TREK_DV")
argsList.append(f"+TREK_TBX_FILE={ElfFileNoExtension}.tbx")
# Combine into a single string
args.args += " ".join(argsList)
args.params += " ".join(paramsList)
args.define += " ".join(defineList)
flags = " ".join(flagsList)
return flags, prefix
if (args.tb == "testbench_fp"):
args.params += " TEST=\"" + args.testsuite + "\" "
def lockstepSetup(args):
imperasicVerbosePath = os.path.join(WALLY, "sim", "imperas-verbose.ic")
imperasicPath = os.path.join(WALLY, "config", args.config, "imperas.ic")
if not os.path.isfile(imperasicPath): # If config is a derivative, look for imperas.ic in derivative configs
imperasicPath = os.path.join(WALLY, "config", "deriv", args.config, "imperas.ic")
if not os.path.isfile(imperasicPath):
print("Error: imperas.ic not found")
sys.exit(1)
prefix = f"IMPERAS_TOOLS={imperasicPath}{f':{imperasicVerbosePath}' if args.lockstepverbose else ''}"
return prefix
# if lockstep is enabled, then we need to pass the Imperas lockstep arguments
if(int(args.locksteplog) >= 1): EnableLog = 1
else: EnableLog = 0
prefix = ""
if (args.lockstep or args.lockstepverbose or args.fcov or args.fcovimp):
if (args.sim == "questa" or args.sim == "vcs"):
imperasicPath = os.path.join(WALLY, "config", args.config, "imperas.ic")
if not os.path.isfile(imperasicPath): # If config is a derivative, look for imperas.ic in derivative configs
imperasicPath = os.path.join(WALLY, "config", "deriv", args.config, "imperas.ic")
prefix = "IMPERAS_TOOLS=" + imperasicPath
# Force Questa to use 64-bit mode, sometimes it defaults to 32-bit even on 64-bit machines
if (args.sim == "questa"):
def createDirs(sim):
for d in ["logs", "wkdir", "cov", "ucdb", "fcov", "fcov_ucdb"]:
os.makedirs(os.path.join(WALLY, "sim", sim, d), exist_ok=True)
def runSim(args, flags, prefix):
if args.sim == "questa":
runQuesta(args, flags, prefix)
elif args.sim == "verilator":
runVerilator(args)
elif args.sim == "vcs":
runVCS(args, flags, prefix)
def runQuesta(args, flags, prefix):
# Force Questa to use 64-bit mode, sometimes it defaults to 32-bit even on 64-bit machines
prefix = "MTI_VCO_MODE=64 " + prefix
if (args.lockstep or args.lockstepverbose):
if(args.locksteplog != 0): ImperasPlusArgs = " +IDV_TRACE2LOG=" + str(EnableLog) + " +IDV_TRACE2LOG_AFTER=" + str(args.locksteplog)
else: ImperasPlusArgs = ""
if(args.fcovimp):
CovEnableStr = "1" if int(args.covlog) > 0 else "0"
if(args.covlog >= 1): EnableLog = 1
else: EnableLog = 0
ImperasPlusArgs = " +IDV_TRACE2COV=" + str(EnableLog) + " +TRACE2LOG_AFTER=" + str(args.covlog) + " +TRACE2COV_ENABLE=" + CovEnableStr
suffix = ""
if(args.fcov):
CovEnableStr = "1" if int(args.covlog) > 0 else "0";
if(args.covlog >= 1): EnableLog = 1
else: EnableLog = 0
ImperasPlusArgs = " +IDV_TRACE2COV=" + str(EnableLog) + " +TRACE2LOG_AFTER=" + str(args.covlog) + " +TRACE2COV_ENABLE=" + CovEnableStr;
suffix = ""
else:
CovEnableStr = ""
suffix = "--lockstep"
if(args.lockstepverbose):
prefix += ":" + WALLY + "/sim/imperas-verbose.ic"
else:
ImperasPlusArgs = ""
suffix = ""
flags = suffix
args.args += ImperasPlusArgs
# other flags
if (args.ccov):
flags += " --ccov"
if (args.fcov):
flags += " --fcov"
if (args.fcovimp):
flags += " --fcovimp"
# create the output sub-directories.
regressionDir = WALLY + '/sim/'
for d in ["logs", "wkdir", "cov", "ucdb", "fcov", "fcov_ucdb"]:
try:
os.mkdir(regressionDir+args.sim+"/"+d)
except:
pass
cd = "cd $WALLY/sim/" +args.sim
# check for unsupported sims
if (args.tb == "testbench_fp" and args.sim != "questa"):
print("Error: testbench_fp presently only supported by Questa, not VCS or Verilator, because of a touchy testbench")
exit(1)
# per-simulator launch
if (args.sim == "questa"):
if (args.gui) and (args.tb == "testbench"):
args.params += "DEBUG=1"
if (ElfFile != ""):
args.args += " " + ElfFile
if (args.args != ""):
args.args = " --args \\\"" + args.args + "\\\""
if (args.params != ""):
args.params = " --params \\\"" + args.params + "\\\""
if args.args:
args.args = fr'--args \"{args.args}\"'
if args.params:
args.params = fr'--params \"{args.params}\"'
if args.define:
args.define = fr'--define \"{args.define}\"'
# Questa cannot accept more than 9 arguments. fcov implies lockstep
cmd = "do wally.do " + args.config + " " + args.testsuite + " " + args.tb + " " + args.args + " " + args.params + " " + flags
if (args.gui): # launch Questa with GUI; add +acc to keep variables accessible
cmd = cd + "; " + prefix + " vsim -do \"" + cmd + " +acc\""
else: # launch Questa in batch mode
cmd = cd + "; " + prefix + " vsim -c -do \"" + cmd + "\""
print("Running Questa with command: " + cmd)
cmd = f"do wally.do {args.config} {args.testsuite} {args.tb} {args.args} {args.params} {args.define} {flags}"
cmd = f'cd $WALLY/sim/questa; {prefix} vsim {"-c" if not args.gui else ""} -do "{cmd}"'
print(f"Running Questa with command: {cmd}")
os.system(cmd)
elif (args.sim == "verilator"):
# PWD=${WALLY}/sim CONFIG=rv64gc TESTSUITE=arch64i
def runVerilator(args):
print(f"Running Verilator on {args.config} {args.testsuite}")
os.system(f"/usr/bin/make -C {regressionDir}/verilator WALLYCONF={args.config} TEST={args.testsuite} TESTBENCH={args.tb} PLUS_ARGS=\"{args.args}\" PARAM_ARGS=\"{args.params}\"")
elif (args.sim == "vcs"):
print("wsim params: " + args.params)
print(f"Running VCS on " + args.config + " " + args.testsuite)
# if (args.gui):
# flags += " --gui"
if (args.args == ""):
vcsargs = ""
else:
vcsargs = " --args \"" + args.args + "\" "
if (args.params == ""):
vcsparams = ""
else:
vcsparams = " --params \"" + args.params + "\" "
print("VCS params: " + vcsparams)
if (ElfFile != ""):
ElfFile = " --elffile " + ElfFile
cmd = cd + "; " + prefix + " ./run_vcs " + args.config + " " + args.testsuite + " " + " --tb " + args.tb + " " + vcsargs + vcsparams + ElfFile + " " + flags
os.system(f'make -C {WALLY}/sim/verilator WALLYCONF={args.config} TEST={args.testsuite} TESTBENCH={args.tb} PLUS_ARGS="{args.args}" PARAM_ARGS="{args.params}" DEFINE_ARGS="{args.define}"')
def runVCS(args, flags, prefix):
print(f"Running VCS on {args.config} {args.testsuite}")
if args.args:
args.args = f'--args "{args.args}"'
if args.params:
args.params = f'--params "{args.params}"'
if args.define:
args.define = f'--define "{args.define}"'
cmd = f"cd $WALLY/sim/vcs; {prefix} ./run_vcs {args.config} {args.testsuite} --tb {args.tb} {args.args} {args.params} {args.define} {flags}"
print(cmd)
os.system(cmd)
def main(args):
validateArgs(args)
print(f"Config={args.config} tests={args.testsuite} sim={args.sim} gui={args.gui} args='{args.args}' params='{args.params}' define='{args.define}'")
ElfFile = elfFileCheck(args)
flags, prefix = prepSim(args, ElfFile)
createDirs(args.sim)
sys.exit(runSim(args, flags, prefix))
if __name__ == "__main__":
args = parseArgs()
main(args)

9
config/derivlist.txt
View file

@ -444,6 +444,7 @@ DCACHE_SUPPORTED 0
VIRTMEM_SUPPORTED 0
ZICBOM_SUPPORTED 0
ZICBOZ_SUPPORTED 0
ZICCLSM_SUPPORTED 0
SVPBMT_SUPPORTED 0
SVNAPOT_SUPPORTED 0
ZAAMO_SUPPORTED 0
@ -455,6 +456,7 @@ DCACHE_SUPPORTED 0
VIRTMEM_SUPPORTED 0
ZICBOM_SUPPORTED 0
ZICBOZ_SUPPORTED 0
ZICCLSM_SUPPORTED 0
SVPBMT_SUPPORTED 0
SVNAPOT_SUPPORTED 0
ZAAMO_SUPPORTED 0
@ -1430,5 +1432,8 @@ UART_SUPPORTED 0
PLIC_SUPPORTED 0
SPI_SUPPORTED 0
# Breker tests require a different memory configuration
# See tests/breker/README.md for details on the testsuite
derive breker rv64gc
EXT_MEM_SUPPORTED 1
EXT_MEM_BASE 64'h90000000

9
config/rv32e/config.vh
View file

@ -31,7 +31,7 @@
localparam XLEN = 32'd32;
// IEEE 754 compliance
localparam IEEE754 = 0;
localparam logic IEEE754 = 0;
// RISC-V configuration per specification
// Base instruction set (defaults to I if E is not supported)
@ -150,7 +150,6 @@ localparam WFI_TIMEOUT_BIT = 32'd16;
// Peripheral Physical Addresses
// Peripheral memory space extends from BASE to BASE+RANGE
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
localparam logic DTIM_SUPPORTED = 0;
localparam logic [63:0] DTIM_BASE = 64'h80000000;
localparam logic [63:0] DTIM_RANGE = 64'h007FFFFF;
@ -160,11 +159,11 @@ localparam logic [63:0] IROM_RANGE = 64'h007FFFFF;
localparam logic BOOTROM_SUPPORTED = 1;
localparam logic [63:0] BOOTROM_BASE = 64'h00001000;
localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF;
localparam BOOTROM_PRELOAD = 1'b0;
localparam logic BOOTROM_PRELOAD = 1'b0;
localparam logic UNCORE_RAM_SUPPORTED = 1;
localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000;
localparam logic [63:0] UNCORE_RAM_RANGE = 64'h07FFFFFF;
localparam UNCORE_RAM_PRELOAD = 1'b0;
localparam logic UNCORE_RAM_PRELOAD = 1'b0;
localparam logic EXT_MEM_SUPPORTED = 0;
localparam logic [63:0] EXT_MEM_BASE = 64'h80000000;
localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF;
@ -182,7 +181,7 @@ localparam logic [63:0] PLIC_BASE = 64'h0C000000;
localparam logic [63:0] PLIC_RANGE = 64'h03FFFFFF;
localparam logic SDC_SUPPORTED = 0;
localparam logic [63:0] SDC_BASE = 64'h00013000;
localparam logic [63:0] SDC_RANGE = 64'h0000007F;
localparam logic [63:0] SDC_RANGE = 64'h00000FFF;
localparam logic SPI_SUPPORTED = 0;
localparam logic [63:0] SPI_BASE = 64'h10040000;
localparam logic [63:0] SPI_RANGE = 64'h00000FFF;

9
config/rv32gc/config.vh
View file

@ -31,7 +31,7 @@
localparam XLEN = 32'd32;
// IEEE 754 compliance
localparam IEEE754 = 0;
localparam logic IEEE754 = 0;
// RISC-V configuration per specification
// Base instruction set (defaults to I if E is not supported)
@ -150,7 +150,6 @@ localparam WFI_TIMEOUT_BIT = 32'd16;
// Peripheral Physical Addresses
// Peripheral memory space extends from BASE to BASE+RANGE
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
localparam logic DTIM_SUPPORTED = 0;
localparam logic [63:0] DTIM_BASE = 64'h80000000;
localparam logic [63:0] DTIM_RANGE = 64'h007FFFFF;
@ -160,11 +159,11 @@ localparam logic [63:0] IROM_RANGE = 64'h007FFFFF;
localparam logic BOOTROM_SUPPORTED = 1;
localparam logic [63:0] BOOTROM_BASE = 64'h00001000;
localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF;
localparam BOOTROM_PRELOAD = 1'b0;
localparam logic BOOTROM_PRELOAD = 1'b0;
localparam logic UNCORE_RAM_SUPPORTED = 1;
localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000;
localparam logic [63:0] UNCORE_RAM_RANGE = 64'h07FFFFFF;
localparam UNCORE_RAM_PRELOAD = 1'b0;
localparam logic UNCORE_RAM_PRELOAD = 1'b0;
localparam logic EXT_MEM_SUPPORTED = 0;
localparam logic [63:0] EXT_MEM_BASE = 64'h80000000;
localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF;
@ -182,7 +181,7 @@ localparam logic [63:0] PLIC_BASE = 64'h0C000000;
localparam logic [63:0] PLIC_RANGE = 64'h03FFFFFF;
localparam logic SDC_SUPPORTED = 0;
localparam logic [63:0] SDC_BASE = 64'h00013000;
localparam logic [63:0] SDC_RANGE = 64'h0000007F;
localparam logic [63:0] SDC_RANGE = 64'h00000FFF;
localparam logic SPI_SUPPORTED = 1;
localparam logic [63:0] SPI_BASE = 64'h10040000;
localparam logic [63:0] SPI_RANGE = 64'h00000FFF;

61
config/rv32gc/coverage.svh
View file

@ -5,25 +5,54 @@
// This file is needed in the config subdirectory for each config supporting coverage.
// It defines which extensions are enabled for that config.
// Define XLEN, used in covergroups
`define XLEN32 1
// Define relevant addresses
`define ACCESS_FAULT_ADDRESS 32'h0000
`define CLINT_BASE 64'h02000000
// Unprivileged extensions
`include "RV32I_coverage.svh"
`include "RV32M_coverage.svh"
`include "RV32F_coverage.svh"
`include "RV32D_coverage.svh"
`include "RV32ZfaF_coverage.svh"
`include "RV32ZfaD_coverage.svh"
`include "RV32ZfaZfh_coverage.svh"
`include "RV32ZfhD_coverage.svh"
`include "RV32Zfh_coverage.svh"
`include "RV32Zicond_coverage.svh"
`include "RV32Zca_coverage.svh"
`include "RV32Zcb_coverage.svh"
`include "RV32ZcbM_coverage.svh"
`include "RV32ZcbZbb_coverage.svh"
`include "RV32Zcf_coverage.svh"
`include "RV32Zcd_coverage.svh"
`include "I_coverage.svh"
`include "M_coverage.svh"
`include "F_coverage.svh"
`include "D_coverage.svh"
`include "Zba_coverage.svh"
`include "Zbb_coverage.svh"
`include "Zbc_coverage.svh"
`include "Zbs_coverage.svh"
`include "ZfaF_coverage.svh"
`include "ZfaD_coverage.svh"
`include "ZfaZfh_coverage.svh"
`include "Zfh_coverage.svh"
`include "ZfhD_coverage.svh"
// Note: Zfhmin is a subset of Zfh, so usually only one or the other would be used. When Zfhmin and D are supported, ZfhD should also be enabled
`include "Zfhmin_coverage.svh"
`include "Zicond_coverage.svh"
`include "Zca_coverage.svh"
`include "Zcb_coverage.svh"
`include "ZcbM_coverage.svh"
`include "ZcbZbb_coverage.svh"
`include "Zcf_coverage.svh"
`include "Zcd_coverage.svh"
`include "Zicsr_coverage.svh"
`include "Zbkb_coverage.svh"
`include "Zbkc_coverage.svh"
`include "Zbkx_coverage.svh"
`include "Zknd_coverage.svh"
`include "Zkne_coverage.svh"
`include "Zknh_coverage.svh"
`include "Zaamo_coverage.svh"
`include "Zalrsc_coverage.svh"
// Privileged extensions
`include "ZicsrM_coverage.svh"
`include "ZicsrF_coverage.svh"
`include "ZicsrU_coverage.svh"
`include "RV32VM_coverage.svh"
`include "RV32VM_PMP_coverage.svh"
`include "EndianU_coverage.svh"
`include "EndianM_coverage.svh"
`include "EndianS_coverage.svh"
`include "ExceptionsM_coverage.svh"
`include "ExceptionsZc_coverage.svh"

26
config/rv32gc/imperas.ic
View file

@ -9,8 +9,8 @@
#--showcommands
# Core settings
--variant RV32GC # for RV32GC
--override cpu/priv_version=1.12
--variant RV32GCK # for RV32GC
--override cpu/priv_version=1.12
--override cpu/user_version=20191213
# arch
--override cpu/mimpid=0x100
@ -20,7 +20,7 @@
--override refRoot/cpu/envcfg_mask=1 # dh 1/26/24 this should be deleted when ImperasDV is updated to allow envcfg.FIOM to be written
# bit manipulation
--override cpu/add_Extensions=B
--override cpu/add_Extensions=B
--override cpu/bitmanip_version=1.0.0
--override cpu/misa_B_Zba_Zbb_Zbs=T
@ -36,7 +36,7 @@
--override cpu/Zicboz=T
--override cmomp_bytes=64 # Zic64b
--override cmoz_bytes=64 # Zic64b
--override lr_sc_grain=8 # Za64rs requires <=64; we use native word size
--override lr_sc_grain=4 # Za64rs requires <=64; we use native word size
# 64 KiB continuous huge pages supported
#--override cpu/Svpbmt=F
@ -59,7 +59,7 @@
#--override cpu/instret_undefined=T
#--override cpu/hpmcounter_undefined=T
## context registers not implemented
# context registers not implemented
#--override cpu/scontext_undefined=True
#--override cpu/mcontext_undefined=True
@ -69,9 +69,14 @@
#--override cpu/Zicfilp=F
--override cpu/trigger_num=0 # disable CSRs 7a0-7a8
--override no_pseudo_inst=T # For code coverage, don't produce pseudoinstructions
# For code coverage, don't produce pseudoinstructions
--override no_pseudo_inst=T
--override show_c_prefix=T # Show "c." with compressed instructions
# Show "c." with compressed instructions
--override show_c_prefix=T
# nonratified mnoise register not implemented
--override cpu/mnoise_undefined=T
# mcause and scause only have 4 lsbs of code and 1 msb of interrupt flag
#--override cpu/ecode_mask=0x8000000F # for RV32
@ -80,7 +85,12 @@
# Debug mode not yet supported
--override cpu/debug_mode=none
# Zkr entropy source and seed register not supported.
--override cpu/Zkr=F
# ShangMi Crypto not supported
--override cpu/Zksed=F
--override cpu/Zksh=F
--override cpu/reset_address=0x80000000
@ -101,7 +111,7 @@
# mstatus.FS is set dirty on any write to a FPR, or when a fp operation signals an exception
--override cpu/mstatus_fs_mode=write_1
# PMA Settings
# PMA Settings
# 'r': read access allowed
# 'w': write access allowed
# 'x': execute access allowed

9
config/rv32i/config.vh
View file

@ -31,7 +31,7 @@
localparam XLEN = 32'd32;
// IEEE 754 compliance
localparam IEEE754 = 0;
localparam logic IEEE754 = 0;
// RISC-V configuration per specification
// Base instruction set (defaults to I if E is not supported)
@ -150,7 +150,6 @@ localparam WFI_TIMEOUT_BIT = 32'd16;
// Peripheral Physical Addresses
// Peripheral memory space extends from BASE to BASE+RANGE
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
localparam logic DTIM_SUPPORTED = 1;
localparam logic [63:0] DTIM_BASE = 64'h80000000;
localparam logic [63:0] DTIM_RANGE = 64'h007FFFFF;
@ -160,11 +159,11 @@ localparam logic [63:0] IROM_RANGE = 64'h007FFFFF;
localparam logic BOOTROM_SUPPORTED = 0;
localparam logic [63:0] BOOTROM_BASE = 64'h00001000;
localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF;
localparam BOOTROM_PRELOAD = 1'b0;
localparam logic BOOTROM_PRELOAD = 1'b0;
localparam logic UNCORE_RAM_SUPPORTED = 0;
localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000;
localparam logic [63:0] UNCORE_RAM_RANGE = 64'h07FFFFFF;
localparam UNCORE_RAM_PRELOAD = 1'b0;
localparam logic UNCORE_RAM_PRELOAD = 1'b0;
localparam logic EXT_MEM_SUPPORTED = 0;
localparam logic [63:0] EXT_MEM_BASE = 64'h80000000;
localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF;
@ -182,7 +181,7 @@ localparam logic [63:0] PLIC_BASE = 64'h0C000000;
localparam logic [63:0] PLIC_RANGE = 64'h03FFFFFF;
localparam logic SDC_SUPPORTED = 0;
localparam logic [63:0] SDC_BASE = 64'h00013000;
localparam logic [63:0] SDC_RANGE = 64'h0000007F;
localparam logic [63:0] SDC_RANGE = 64'h00000FFF;
localparam logic SPI_SUPPORTED = 0;
localparam logic [63:0] SPI_BASE = 64'h10040000;
localparam logic [63:0] SPI_RANGE = 64'h00000FFF;

9
config/rv32imc/config.vh
View file

@ -31,7 +31,7 @@
localparam XLEN = 32'd32;
// IEEE 754 compliance
localparam IEEE754 = 0;
localparam logic IEEE754 = 0;
// RISC-V configuration per specification
// Base instruction set (defaults to I if E is not supported)
@ -150,7 +150,6 @@ localparam WFI_TIMEOUT_BIT = 32'd16;
// Peripheral Physical Addresses
// Peripheral memory space extends from BASE to BASE+RANGE
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
localparam logic DTIM_SUPPORTED = 1;
localparam logic [63:0] DTIM_BASE = 64'h80000000;
localparam logic [63:0] DTIM_RANGE = 64'h007FFFFF;
@ -160,11 +159,11 @@ localparam logic [63:0] IROM_RANGE = 64'h007FFFFF;
localparam logic BOOTROM_SUPPORTED = 0;
localparam logic [63:0] BOOTROM_BASE = 64'h00001000;
localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF;
localparam BOOTROM_PRELOAD = 1'b0;
localparam logic BOOTROM_PRELOAD = 1'b0;
localparam logic UNCORE_RAM_SUPPORTED = 0;
localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000;
localparam logic [63:0] UNCORE_RAM_RANGE = 64'h07FFFFFF;
localparam UNCORE_RAM_PRELOAD = 1'b0;
localparam logic UNCORE_RAM_PRELOAD = 1'b0;
localparam logic EXT_MEM_SUPPORTED = 0;
localparam logic [63:0] EXT_MEM_BASE = 64'h80000000;
localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF;
@ -182,7 +181,7 @@ localparam logic [63:0] PLIC_BASE = 64'h0C000000;
localparam logic [63:0] PLIC_RANGE = 64'h03FFFFFF;
localparam logic SDC_SUPPORTED = 0;
localparam logic [63:0] SDC_BASE = 64'h00013000;
localparam logic [63:0] SDC_RANGE = 64'h0000007F;
localparam logic [63:0] SDC_RANGE = 64'h00000FFF;
localparam logic SPI_SUPPORTED = 1;
localparam logic [63:0] SPI_BASE = 64'h10040000;
localparam logic [63:0] SPI_RANGE = 64'h00000FFF;

9
config/rv64gc/config.vh
View file

@ -31,7 +31,7 @@
localparam XLEN = 32'd64;
// IEEE 754 compliance
localparam IEEE754 = 0;
localparam logic IEEE754 = 0;
// RISC-V configuration per specification
// Base instruction set (defaults to I if E is not supported)
@ -150,7 +150,6 @@ localparam WFI_TIMEOUT_BIT = 32'd16;
// Peripheral Physical Addresses
// Peripheral memory space extends from BASE to BASE+RANGE
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
localparam logic DTIM_SUPPORTED = 0;
localparam logic [63:0] DTIM_BASE = 64'h80000000;
localparam logic [63:0] DTIM_RANGE = 64'h007FFFFF;
@ -160,11 +159,11 @@ localparam logic [63:0] IROM_RANGE = 64'h007FFFFF;
localparam logic BOOTROM_SUPPORTED = 1;
localparam logic [63:0] BOOTROM_BASE = 64'h00001000;
localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF;
localparam BOOTROM_PRELOAD = 1'b0;
localparam logic BOOTROM_PRELOAD = 1'b0;
localparam logic UNCORE_RAM_SUPPORTED = 1;
localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000;
localparam logic [63:0] UNCORE_RAM_RANGE = 64'h07FFFFFF;
localparam UNCORE_RAM_PRELOAD = 1'b0;
localparam logic UNCORE_RAM_PRELOAD = 1'b0;
localparam logic EXT_MEM_SUPPORTED = 0;
localparam logic [63:0] EXT_MEM_BASE = 64'h80000000;
localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF;
@ -182,7 +181,7 @@ localparam logic [63:0] PLIC_BASE = 64'h0C000000;
localparam logic [63:0] PLIC_RANGE = 64'h03FFFFFF;
localparam logic SDC_SUPPORTED = 0;
localparam logic [63:0] SDC_BASE = 64'h00013000;
localparam logic [63:0] SDC_RANGE = 64'h0000007F;
localparam logic [63:0] SDC_RANGE = 64'h00000FFF;
localparam logic SPI_SUPPORTED = 1;
localparam logic [63:0] SPI_BASE = 64'h10040000;
localparam logic [63:0] SPI_RANGE = 64'h00000FFF;

61
config/rv64gc/coverage.svh
View file

@ -5,27 +5,56 @@
// This file is needed in the config subdirectory for each config supporting coverage.
// It defines which extensions are enabled for that config.
// Define XLEN, used in covergroups
`define XLEN64 1
// Define relevant addresses
`define ACCESS_FAULT_ADDRESS 64'h00000000
`define CLINT_BASE 64'h02000000
// Unprivileged extensions
`include "RV64I_coverage.svh"
`include "RV64M_coverage.svh"
`include "RV64F_coverage.svh"
`include "RV64D_coverage.svh"
`include "RV64ZfaF_coverage.svh"
`include "RV64ZfaD_coverage.svh"
`include "RV64ZfaZfh_coverage.svh"
`include "RV64ZfhD_coverage.svh"
`include "RV64Zfh_coverage.svh"
`include "RV64Zicond_coverage.svh"
`include "RV64Zca_coverage.svh"
`include "RV64Zcb_coverage.svh"
`include "RV64ZcbM_coverage.svh"
`include "RV64ZcbZbb_coverage.svh"
`include "RV64ZcbZba_coverage.svh"
`include "RV64Zcd_coverage.svh"
`include "I_coverage.svh"
`include "M_coverage.svh"
`include "F_coverage.svh"
`include "D_coverage.svh"
`include "Zba_coverage.svh"
`include "Zbb_coverage.svh"
`include "Zbc_coverage.svh"
`include "Zbs_coverage.svh"
`include "ZfaF_coverage.svh"
`include "ZfaD_coverage.svh"
`include "ZfaZfh_coverage.svh"
`include "ZfhD_coverage.svh"
`include "Zfh_coverage.svh"
// Note: Zfhmin is a subset of Zfh, so usually only one or the other would be used. When Zfhmin and D are supported, ZfhD should also be enabled
`include "Zfhmin_coverage.svh"
`include "Zicond_coverage.svh"
`include "Zca_coverage.svh"
`include "Zcb_coverage.svh"
`include "ZcbM_coverage.svh"
`include "ZcbZbb_coverage.svh"
`include "ZcbZba_coverage.svh"
`include "Zcd_coverage.svh"
`include "Zicsr_coverage.svh"
`include "Zbkb_coverage.svh"
`include "Zbkc_coverage.svh"
`include "Zbkx_coverage.svh"
`include "Zknd_coverage.svh"
`include "Zkne_coverage.svh"
`include "Zknh_coverage.svh"
`include "Zaamo_coverage.svh"
`include "Zalrsc_coverage.svh"
// Privileged extensions
`include "RV64VM_coverage.svh"
`include "ZicsrM_coverage.svh"
`include "ZicsrF_coverage.svh"
`include "ZicsrU_coverage.svh"
`include "EndianU_coverage.svh"
`include "EndianM_coverage.svh"
`include "EndianS_coverage.svh"
`include "ExceptionsM_coverage.svh"
`include "ExceptionsZc_coverage.svh"
// `include "RV64VM_PMP_coverage.svh"
// `include "RV64CBO_VM_coverage.svh"
// `include "RV64CBO_PMP_coverage.svh"

16
config/rv64gc/imperas.ic
View file

@ -9,7 +9,7 @@
#--showcommands
# Core settings
--override cpu/priv_version=1.12
--override cpu/priv_version=1.12
--override cpu/user_version=20191213
# arch
--override cpu/mimpid=0x100
@ -19,7 +19,7 @@
--override refRoot/cpu/envcfg_mask=1 # dh 1/26/24 this should be deleted when ImperasDV is updated to allow envcfg.FIOM to be written
# bit manipulation
--override cpu/add_Extensions=B
--override cpu/add_Extensions=B
--override cpu/bitmanip_version=1.0.0
--override cpu/misa_B_Zba_Zbb_Zbs=T
@ -68,12 +68,12 @@
--override cpu/trigger_num=0 # disable CSRs 7a0-7a8
# For code coverage, don't produce pseudoinstructions
--override no_pseudo_inst=T
--override no_pseudo_inst=T
# Show "c." with compressed instructions
# Show "c." with compressed instructions
--override show_c_prefix=T
# nonratified mnosie register not implemented
# nonratified mnoise register not implemented
--override cpu/mnoise_undefined=T
# mcause and scause only have 4 lsbs of code and 1 msb of interrupt flag
@ -86,7 +86,9 @@
# Zkr entropy source and seed register not supported.
--override cpu/Zkr=F
# ShangMi Crypto not supported
--override cpu/Zksed=F
--override cpu/Zksh=F
--override cpu/reset_address=0x80000000
@ -107,7 +109,7 @@
# mstatus.FS is set dirty on any write to a FPR, or when a fp operation signals an exception
--override cpu/mstatus_fs_mode=write_1
# PMA Settings
# PMA Settings
# 'r': read access allowed
# 'w': write access allowed
# 'x': execute access allowed

9
config/rv64i/config.vh
View file

@ -31,7 +31,7 @@
localparam XLEN = 32'd64;
// IEEE 754 compliance
localparam IEEE754 = 0;
localparam logic IEEE754 = 0;
// RISC-V configuration per specification
// Base instruction set (defaults to I if E is not supported)
@ -150,7 +150,6 @@ localparam WFI_TIMEOUT_BIT = 32'd16;
// Peripheral Physical Addresses
// Peripheral memory space extends from BASE to BASE+RANGE
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
localparam logic DTIM_SUPPORTED = 1;
localparam logic [63:0] DTIM_BASE = 64'h80000000;
localparam logic [63:0] DTIM_RANGE = 64'h007FFFFF;
@ -160,11 +159,11 @@ localparam logic [63:0] IROM_RANGE = 64'h007FFFFF;
localparam logic BOOTROM_SUPPORTED = 0;
localparam logic [63:0] BOOTROM_BASE = 64'h00001000;
localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF;
localparam BOOTROM_PRELOAD = 1'b0;
localparam logic BOOTROM_PRELOAD = 1'b0;
localparam logic UNCORE_RAM_SUPPORTED = 0;
localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000;
localparam logic [63:0] UNCORE_RAM_RANGE = 64'h07FFFFFF;
localparam UNCORE_RAM_PRELOAD = 1'b0;
localparam logic UNCORE_RAM_PRELOAD = 1'b0;
localparam logic EXT_MEM_SUPPORTED = 0;
localparam logic [63:0] EXT_MEM_BASE = 64'h80000000;
localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF;
@ -182,7 +181,7 @@ localparam logic [63:0] PLIC_BASE = 64'h0C000000;
localparam logic [63:0] PLIC_RANGE = 64'h03FFFFFF;
localparam logic SDC_SUPPORTED = 0;
localparam logic [63:0] SDC_BASE = 64'h00013000;
localparam logic [63:0] SDC_RANGE = 64'h0000007F;
localparam logic [63:0] SDC_RANGE = 64'h00000FFF;
localparam logic SPI_SUPPORTED = 0;
localparam logic [63:0] SPI_BASE = 64'h10040000;
localparam logic [63:0] SPI_RANGE = 64'h00000FFF;

6
config/shared/config-shared.vh
View file

@ -122,9 +122,3 @@ localparam FMALEN = 3*NF + 6;
localparam NORMSHIFTSZ = `max(`max((CVTLEN+NF+1), (DIVb + 1 + NF + 1)), (FMALEN + 2));
localparam LOGNORMSHIFTSZ = ($clog2(NORMSHIFTSZ)); // log_2(NORMSHIFTSZ)
// Disable spurious Verilator warnings
/* verilator lint_off STMTDLY */
/* verilator lint_off ASSIGNDLY */
/* verilator lint_off PINCONNECTEMPTY */

4
config/shared/parameter-defs.vh
View file

@ -96,11 +96,7 @@ localparam cvw_t P = '{
PLIC_SPI_ID : PLIC_SPI_ID,
PLIC_SDC_ID : PLIC_SDC_ID,
BPRED_SUPPORTED : BPRED_SUPPORTED,
/* verilator lint_off ENUMVALUE */
// *** definitely need to fix this.
// it thinks we are casting from the enum type to BPRED_TYPE.
BPRED_TYPE : BPRED_TYPE,
/* verilator lint_on ENUMVALUE */
BPRED_SIZE : BPRED_SIZE,
BPRED_NUM_LHR : BPRED_NUM_LHR,
BTB_SIZE : BTB_SIZE,

60
examples/C/common/syscalls.c
View file

@ -15,6 +15,44 @@
extern volatile uint64_t tohost;
extern volatile uint64_t fromhost;
/////////////////////////////
// Start of code added for Wally
// Use UART rather than syscall host interface for printing
//////////////////////////////
#include <stdint.h>
void uartInit(void) {
volatile uint8_t *UART_LCR = (uint8_t*)0x10000003;
*UART_LCR = 0b0000011; // 8-bit characters, 1 stop bit, no parity
}
void uartSend(char c) {
volatile uint8_t *UART_THR = (uint8_t*)0x10000000;
volatile uint8_t *UART_LSR = (uint8_t*)0x10000005;
while (!(*UART_LSR & (1<<5))); // wait for THRE (trans hold reg empty)
*UART_THR = c;
}
char uartReceive(void) {
volatile uint8_t *UART_RBR = (uint8_t*)0x10000000;
volatile uint8_t *UART_LSR = (uint8_t*)0x10000005;
while (!(*UART_LSR & (1<<0))); // wait for DR (Data Ready)
return *UART_RBR;
}
char uartPutStr(const char *str) {
while (*str) {
uartSend(*str++);
}
}
/////////////////////////////
// End of code added for Wally
//////////////////////////////
static uintptr_t syscall(uintptr_t which, uint64_t arg0, uint64_t arg1, uint64_t arg2)
{
volatile uint64_t magic_mem[8] __attribute__((aligned(64)));
@ -76,7 +114,19 @@ void abort()
void printstr(const char* s)
{
syscall(SYS_write, 1, (uintptr_t)s, strlen(s));
// david_harris@hmc.edu 11/30/24 switch to printing via UART rather than syscall
// This works on both Spike and Wally simulations
//syscall(SYS_write, 1, (uintptr_t)s, strlen(s));
uartPutStr(s);
}
// Added 30 November 2024 David_Harris@hmc.edu
// The compiler encountering printf with a pure string argument tries to invoke puts
// rather than the usual printf, so puts must be defined.
int puts(const char* s)
{
printstr(s);
return 0;
}
void __attribute__((weak)) thread_entry(int cid, int nc)
@ -107,6 +157,7 @@ void _init(int cid, int nc)
{
init_tls();
thread_entry(cid, nc);
uartInit(); // added 11/30/2024 David_Harris@hmc.edu for printing via UART
// only single-threaded programs should ever get here.
int ret = main(0, 0);
@ -125,6 +176,11 @@ void _init(int cid, int nc)
#undef putchar
int putchar(int ch)
{
// David_Harris@hmc.edu 11/30/2024
// Replaced syscall with uartSend
uartSend(ch);
/*
static __thread char buf[64] __attribute__((aligned(64)));
static __thread int buflen = 0;
@ -134,7 +190,7 @@ int putchar(int ch)
{
syscall(SYS_write, 1, (uintptr_t)buf, buflen);
buflen = 0;
}
} */
return 0;
}

32
examples/C/gpio/Makefile Normal file
View file

@ -0,0 +1,32 @@
TARGET = gpio
$(TARGET).objdump: $(TARGET)
riscv64-unknown-elf-objdump -S -D $(TARGET) > $(TARGET).objdump
$(TARGET): $(TARGET).c Makefile
riscv64-unknown-elf-gcc -o $(TARGET) -gdwarf-2 -O\
-march=rv64gc -mabi=lp64d -mcmodel=medany \
-nostdlib -static -lm -fno-tree-loop-distribute-patterns \
-T../common/test.ld -I../common \
$(TARGET).c ../common/crt.S ../common/syscalls.c
# Compiler flags:
# -o $(TARGET) defines the name of the output file
# -g generates debugging symbols for gdb
# -O turns on basic optimization; -O3 turns on heavy optimization; omit for no optimization
# -march=rv64gc -mabi=lp64d =mcmodel=medany generates code for RV64GC with doubles and long/ptrs = 64 bits
# -static forces static linking (no dynamic shared libraries on bare metal)
# -lm links the math library if necessary (when #include math.h)
# -nostdlib avoids inserting standard startup files and default libraries
# because we are using crt.s on bare metal
# -fno-tree-loop-distribute-patterns turns replacing loops with memcpy/memset in the std library
# -T specifies the linker file
# -I specifies the include path (e.g. for util.h)
# The last line defines the C files to compile.
# crt.S is needed as our startup file to initialize the processor
# syscalls.c implements printf through the HTIF for Spike
# other flags from riscv-tests makefiles that don't seem to be important
# -ffast-math -DPREALLOCATE=1 -std=gnu99 \
# -fno-common -fno-builtin-printf -nostartfiles -lgcc \
clean:
rm -f $(TARGET) $(TARGET).objdump* $(TARGET).memfile

28
examples/C/gpio/gpio.c Normal file
View file

@ -0,0 +1,28 @@
// gpio.c
// David_Harris@hmc.edu 30 November 2024
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
// General-Purpose I/O (GPIO) example program illustrating compiled C code
// compile with make
// simulate with: wsim rv64gc --elf gpio --sim verilator
#include <stdio.h>
#include "gpiolib.h"
int main(void) {
printf("GPIO Example!\n\r");
pinMode(0, INPUT);
pinMode(1, OUTPUT);
pinMode(2, OUTPUT);
for (int i=0; i<10; i++) {
// Read pin 0 and write it to pin 1
int val = digitalRead(0);
printf("Pin 0: %d\n", val);
digitalWrite(1, val);
// Toggle pin 2
printf("Pin 2: %d\n", i%2);
digitalWrite(2, i%2);
}
}

81
examples/C/gpio/gpiolib.h Normal file
View file

@ -0,0 +1,81 @@
// gpiolib.h
// Basic Arduino-compatible functions for general-purpose input/output
// Assumes GPIO0_BASE is set to the memory-mapped GPIO address from
// config/rv64gc/config.vh.
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
#include <stdint.h>
///////////////////////////////////////////////////////////////////////////////
// Bitfield Structs
///////////////////////////////////////////////////////////////////////////////
typedef struct
{
volatile uint32_t input_val; // (GPIO offset 0x00) Pin value
volatile uint32_t input_en; // (GPIO offset 0x04) Pin input enable*
volatile uint32_t output_en; // (GPIO offset 0x08) Pin output enable*
volatile uint32_t output_val; // (GPIO offset 0x0C) Output value
volatile uint32_t pue; // (GPIO offset 0x10) Internal pull-up enable*
volatile uint32_t ds; // (GPIO offset 0x14) Pin drive strength
volatile uint32_t rise_ie; // (GPIO offset 0x18) Rise interrupt enable
volatile uint32_t rise_ip; // (GPIO offset 0x1C) Rise interrupt pending
volatile uint32_t fall_ie; // (GPIO offset 0x20) Fall interrupt enable
volatile uint32_t fall_ip; // (GPIO offset 0x24) Fall interrupt pending
volatile uint32_t high_ie; // (GPIO offset 0x28) High interrupt enable
volatile uint32_t high_ip; // (GPIO offset 0x2C) High interrupt pending
volatile uint32_t low_ie; // (GPIO offset 0x30) Low interrupt enable
volatile uint32_t low_ip; // (GPIO offset 0x34) Low interrupt pending
volatile uint32_t iof_en; // (GPIO offset 0x38) HW-Driven functions enable
volatile uint32_t iof_sel; // (GPIO offset 0x3C) HW-Driven functions selection
volatile uint32_t out_xor; // (GPIO offset 0x40) Output XOR (invert)
// Registers marked with * are asynchronously reset to 0. All others are synchronously reset to 0.
} GPIO;
///////////////////////////////////////////////////////////////////////////////
// GPIO Constant Definitions
///////////////////////////////////////////////////////////////////////////////
#define GPIO0_BASE (0x10060000U) // GPIO memory-mapped base address
#define GPIO0 ((GPIO*) GPIO0_BASE) // Set up pointer to struct of type GPIO aligned at the base GPIO0 memory-mapped address
#define LOW 0
#define HIGH 1
#define INPUT 0
#define OUTPUT 1
#define GPIO_IOF0 2
///////////////////////////////////////////////////////////////////////////////
// GPIO Functions
///////////////////////////////////////////////////////////////////////////////
void pinMode(int pin, int function)
{
switch(function) {
case INPUT:
GPIO0->input_en |= (1 << pin); // Sets a pin as an input
break;
case OUTPUT:
GPIO0->output_en |= (1 << pin); // Set pin as an output
GPIO0->iof_en &= ~(1 << pin);
break;
case GPIO_IOF0:
GPIO0->iof_sel &= ~(1 << pin);
GPIO0->iof_en |= (1 << pin);
}
}
void digitalWrite(int pin, int val)
{
if (val) GPIO0->output_val |= (1 << pin);
else GPIO0->output_val &= ~(1 << pin);
}
int digitalRead(int pin)
{
return (GPIO0->input_val >> pin) & 0x1;
}

32
examples/C/hello/Makefile Normal file
View file

@ -0,0 +1,32 @@
TARGET = hello
$(TARGET).objdump: $(TARGET)
riscv64-unknown-elf-objdump -S -D $(TARGET) > $(TARGET).objdump
$(TARGET): $(TARGET).c Makefile
riscv64-unknown-elf-gcc -o $(TARGET) -gdwarf-2 -O\
-march=rv64gc -mabi=lp64d -mcmodel=medany \
-nostdlib -static -lm -fno-tree-loop-distribute-patterns \
-T../common/test.ld -I../common \
$(TARGET).c ../common/crt.S ../common/syscalls.c
# Compiler flags:
# -o $(TARGET) defines the name of the output file
# -g generates debugging symbols for gdb
# -O turns on basic optimization; -O3 turns on heavy optimization; omit for no optimization
# -march=rv64gc -mabi=lp64d =mcmodel=medany generates code for RV64GC with doubles and long/ptrs = 64 bits
# -static forces static linking (no dynamic shared libraries on bare metal)
# -lm links the math library if necessary (when #include math.h)
# -nostdlib avoids inserting standard startup files and default libraries
# because we are using crt.s on bare metal
# -fno-tree-loop-distribute-patterns turns replacing loops with memcpy/memset in the std library
# -T specifies the linker file
# -I specifies the include path (e.g. for util.h)
# The last line defines the C files to compile.
# crt.S is needed as our startup file to initialize the processor
# syscalls.c implements printf through the HTIF for Spike
# other flags from riscv-tests makefiles that don't seem to be important
# -ffast-math -DPREALLOCATE=1 -std=gnu99 \
# -fno-common -fno-builtin-printf -nostartfiles -lgcc \
clean:
rm -f $(TARGET) $(TARGET).objdump* $(TARGET).memfile

25
examples/C/hello/hello.c Normal file
View file

@ -0,0 +1,25 @@
// hello.c
// David_Harris@hmc.edu 30 November 2024
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
// Hello World program illustrating compiled C code printing via the UART
// The Wally team has modified the Berkeley syscalls.c (in examples/C/common)
// to print via UART rather than the syscall interface. This is supported
// on both Spike and Wally. It assumes the PC16550-compatible UART is at
// the default SiFive address of 0x10000000.
// Note that there seem to be some discrepancies between the UART and Spike
// such that using \n\r for new lines works best.
// compile with make
// simulate Wally with: wsim rv64gc --elf hello --sim verilator
// simulate in Spike with: spike hello
#include <stdio.h>
int main(void) {
printf("Hello Wally!\n\r");
for (int i = 0; i < 10; i++) {
printf("%d ", i);
}
printf("\n\r");
}

2
examples/fp/fpcalc/fpcalc.c
View file

@ -237,7 +237,7 @@ __uint128_t parseNum(char *num) {
if (strlen(num) < 8) size = 2;
else if (strlen(num) < 16) size = 4;
else if (strlen(num) < 32) size = 8;
else if (strlen(num) < 35) size = 16; // *** will need to increase
else if (strlen(num) < 35) size = 16;
else {
printf("Error: only half, single, double, or quad precision supported");
exit(1);

263
fpga/constraints/big-debug-spi.xdc Normal file
View file

@ -0,0 +1,263 @@
create_debug_core u_ila_0 ila
set_property C_DATA_DEPTH 65536 [get_debug_cores u_ila_0]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
startgroup
set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0 ]
set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0 ]
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0 ]
set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0 ]
endgroup
connect_debug_port u_ila_0/clk [get_nets CPUCLK]
set_property port_width 64 [get_debug_ports u_ila_0/probe0]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
connect_debug_port u_ila_0/probe0 [get_nets [list {wallypipelinedsoc/core/PCM[0]} {wallypipelinedsoc/core/PCM[1]} {wallypipelinedsoc/core/PCM[2]} {wallypipelinedsoc/core/PCM[3]} {wallypipelinedsoc/core/PCM[4]} {wallypipelinedsoc/core/PCM[5]} {wallypipelinedsoc/core/PCM[6]} {wallypipelinedsoc/core/PCM[7]} {wallypipelinedsoc/core/PCM[8]} {wallypipelinedsoc/core/PCM[9]} {wallypipelinedsoc/core/PCM[10]} {wallypipelinedsoc/core/PCM[11]} {wallypipelinedsoc/core/PCM[12]} {wallypipelinedsoc/core/PCM[13]} {wallypipelinedsoc/core/PCM[14]} {wallypipelinedsoc/core/PCM[15]} {wallypipelinedsoc/core/PCM[16]} {wallypipelinedsoc/core/PCM[17]} {wallypipelinedsoc/core/PCM[18]} {wallypipelinedsoc/core/PCM[19]} {wallypipelinedsoc/core/PCM[20]} {wallypipelinedsoc/core/PCM[21]} {wallypipelinedsoc/core/PCM[22]} {wallypipelinedsoc/core/PCM[23]} {wallypipelinedsoc/core/PCM[24]} {wallypipelinedsoc/core/PCM[25]} {wallypipelinedsoc/core/PCM[26]} {wallypipelinedsoc/core/PCM[27]} {wallypipelinedsoc/core/PCM[28]} {wallypipelinedsoc/core/PCM[29]} {wallypipelinedsoc/core/PCM[30]} {wallypipelinedsoc/core/PCM[31]} {wallypipelinedsoc/core/PCM[32]} {wallypipelinedsoc/core/PCM[33]} {wallypipelinedsoc/core/PCM[34]} {wallypipelinedsoc/core/PCM[35]} {wallypipelinedsoc/core/PCM[36]} {wallypipelinedsoc/core/PCM[37]} {wallypipelinedsoc/core/PCM[38]} {wallypipelinedsoc/core/PCM[39]} {wallypipelinedsoc/core/PCM[40]} {wallypipelinedsoc/core/PCM[41]} {wallypipelinedsoc/core/PCM[42]} {wallypipelinedsoc/core/PCM[43]} {wallypipelinedsoc/core/PCM[44]} {wallypipelinedsoc/core/PCM[45]} {wallypipelinedsoc/core/PCM[46]} {wallypipelinedsoc/core/PCM[47]} {wallypipelinedsoc/core/PCM[48]} {wallypipelinedsoc/core/PCM[49]} {wallypipelinedsoc/core/PCM[50]} {wallypipelinedsoc/core/PCM[51]} {wallypipelinedsoc/core/PCM[52]} {wallypipelinedsoc/core/PCM[53]} {wallypipelinedsoc/core/PCM[54]} {wallypipelinedsoc/core/PCM[55]} {wallypipelinedsoc/core/PCM[56]} {wallypipelinedsoc/core/PCM[57]} {wallypipelinedsoc/core/PCM[58]} {wallypipelinedsoc/core/PCM[59]} {wallypipelinedsoc/core/PCM[60]} {wallypipelinedsoc/core/PCM[61]} {wallypipelinedsoc/core/PCM[62]} {wallypipelinedsoc/core/PCM[63]} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe1]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
connect_debug_port u_ila_0/probe1 [get_nets [list wallypipelinedsoc/core/TrapM ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe2]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
connect_debug_port u_ila_0/probe2 [get_nets [list wallypipelinedsoc/core/InstrValidM ]]
create_debug_port u_ila_0 probe
set_property port_width 32 [get_debug_ports u_ila_0/probe3]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
connect_debug_port u_ila_0/probe3 [get_nets [list {wallypipelinedsoc/core/InstrM[0]} {wallypipelinedsoc/core/InstrM[1]} {wallypipelinedsoc/core/InstrM[2]} {wallypipelinedsoc/core/InstrM[3]} {wallypipelinedsoc/core/InstrM[4]} {wallypipelinedsoc/core/InstrM[5]} {wallypipelinedsoc/core/InstrM[6]} {wallypipelinedsoc/core/InstrM[7]} {wallypipelinedsoc/core/InstrM[8]} {wallypipelinedsoc/core/InstrM[9]} {wallypipelinedsoc/core/InstrM[10]} {wallypipelinedsoc/core/InstrM[11]} {wallypipelinedsoc/core/InstrM[12]} {wallypipelinedsoc/core/InstrM[13]} {wallypipelinedsoc/core/InstrM[14]} {wallypipelinedsoc/core/InstrM[15]} {wallypipelinedsoc/core/InstrM[16]} {wallypipelinedsoc/core/InstrM[17]} {wallypipelinedsoc/core/InstrM[18]} {wallypipelinedsoc/core/InstrM[19]} {wallypipelinedsoc/core/InstrM[20]} {wallypipelinedsoc/core/InstrM[21]} {wallypipelinedsoc/core/InstrM[22]} {wallypipelinedsoc/core/InstrM[23]} {wallypipelinedsoc/core/InstrM[24]} {wallypipelinedsoc/core/InstrM[25]} {wallypipelinedsoc/core/InstrM[26]} {wallypipelinedsoc/core/InstrM[27]} {wallypipelinedsoc/core/InstrM[28]} {wallypipelinedsoc/core/InstrM[29]} {wallypipelinedsoc/core/InstrM[30]} {wallypipelinedsoc/core/InstrM[31]} ]]
create_debug_port u_ila_0 probe
set_property port_width 2 [get_debug_ports u_ila_0/probe4]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
connect_debug_port u_ila_0/probe4 [get_nets [list {wallypipelinedsoc/core/lsu/MemRWM[0]} {wallypipelinedsoc/core/lsu/MemRWM[1]} ]]
create_debug_port u_ila_0 probe
set_property port_width 64 [get_debug_ports u_ila_0/probe5]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
connect_debug_port u_ila_0/probe5 [get_nets [list {wallypipelinedsoc/core/lsu/IEUAdrM[0]} {wallypipelinedsoc/core/lsu/IEUAdrM[1]} {wallypipelinedsoc/core/lsu/IEUAdrM[2]} {wallypipelinedsoc/core/lsu/IEUAdrM[3]} {wallypipelinedsoc/core/lsu/IEUAdrM[4]} {wallypipelinedsoc/core/lsu/IEUAdrM[5]} {wallypipelinedsoc/core/lsu/IEUAdrM[6]} {wallypipelinedsoc/core/lsu/IEUAdrM[7]} {wallypipelinedsoc/core/lsu/IEUAdrM[8]} {wallypipelinedsoc/core/lsu/IEUAdrM[9]} {wallypipelinedsoc/core/lsu/IEUAdrM[10]} {wallypipelinedsoc/core/lsu/IEUAdrM[11]} {wallypipelinedsoc/core/lsu/IEUAdrM[12]} {wallypipelinedsoc/core/lsu/IEUAdrM[13]} {wallypipelinedsoc/core/lsu/IEUAdrM[14]} {wallypipelinedsoc/core/lsu/IEUAdrM[15]} {wallypipelinedsoc/core/lsu/IEUAdrM[16]} {wallypipelinedsoc/core/lsu/IEUAdrM[17]} {wallypipelinedsoc/core/lsu/IEUAdrM[18]} {wallypipelinedsoc/core/lsu/IEUAdrM[19]} {wallypipelinedsoc/core/lsu/IEUAdrM[20]} {wallypipelinedsoc/core/lsu/IEUAdrM[21]} {wallypipelinedsoc/core/lsu/IEUAdrM[22]} {wallypipelinedsoc/core/lsu/IEUAdrM[23]} {wallypipelinedsoc/core/lsu/IEUAdrM[24]} {wallypipelinedsoc/core/lsu/IEUAdrM[25]} {wallypipelinedsoc/core/lsu/IEUAdrM[26]} {wallypipelinedsoc/core/lsu/IEUAdrM[27]} {wallypipelinedsoc/core/lsu/IEUAdrM[28]} {wallypipelinedsoc/core/lsu/IEUAdrM[29]} {wallypipelinedsoc/core/lsu/IEUAdrM[30]} {wallypipelinedsoc/core/lsu/IEUAdrM[31]} {wallypipelinedsoc/core/lsu/IEUAdrM[32]} {wallypipelinedsoc/core/lsu/IEUAdrM[33]} {wallypipelinedsoc/core/lsu/IEUAdrM[34]} {wallypipelinedsoc/core/lsu/IEUAdrM[35]} {wallypipelinedsoc/core/lsu/IEUAdrM[36]} {wallypipelinedsoc/core/lsu/IEUAdrM[37]} {wallypipelinedsoc/core/lsu/IEUAdrM[38]} {wallypipelinedsoc/core/lsu/IEUAdrM[39]} {wallypipelinedsoc/core/lsu/IEUAdrM[40]} {wallypipelinedsoc/core/lsu/IEUAdrM[41]} {wallypipelinedsoc/core/lsu/IEUAdrM[42]} {wallypipelinedsoc/core/lsu/IEUAdrM[43]} {wallypipelinedsoc/core/lsu/IEUAdrM[44]} {wallypipelinedsoc/core/lsu/IEUAdrM[45]} {wallypipelinedsoc/core/lsu/IEUAdrM[46]} {wallypipelinedsoc/core/lsu/IEUAdrM[47]} {wallypipelinedsoc/core/lsu/IEUAdrM[48]} {wallypipelinedsoc/core/lsu/IEUAdrM[49]} {wallypipelinedsoc/core/lsu/IEUAdrM[50]} {wallypipelinedsoc/core/lsu/IEUAdrM[51]} {wallypipelinedsoc/core/lsu/IEUAdrM[52]} {wallypipelinedsoc/core/lsu/IEUAdrM[53]} {wallypipelinedsoc/core/lsu/IEUAdrM[54]} {wallypipelinedsoc/core/lsu/IEUAdrM[55]} {wallypipelinedsoc/core/lsu/IEUAdrM[56]} {wallypipelinedsoc/core/lsu/IEUAdrM[57]} {wallypipelinedsoc/core/lsu/IEUAdrM[58]} {wallypipelinedsoc/core/lsu/IEUAdrM[59]} {wallypipelinedsoc/core/lsu/IEUAdrM[60]} {wallypipelinedsoc/core/lsu/IEUAdrM[61]} {wallypipelinedsoc/core/lsu/IEUAdrM[62]} {wallypipelinedsoc/core/lsu/IEUAdrM[63]} ]]
create_debug_port u_ila_0 probe
set_property port_width 64 [get_debug_ports u_ila_0/probe6]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
connect_debug_port u_ila_0/probe6 [get_nets [list {wallypipelinedsoc/core/lsu/ReadDataM[0]} {wallypipelinedsoc/core/lsu/ReadDataM[1]} {wallypipelinedsoc/core/lsu/ReadDataM[2]} {wallypipelinedsoc/core/lsu/ReadDataM[3]} {wallypipelinedsoc/core/lsu/ReadDataM[4]} {wallypipelinedsoc/core/lsu/ReadDataM[5]} {wallypipelinedsoc/core/lsu/ReadDataM[6]} {wallypipelinedsoc/core/lsu/ReadDataM[7]} {wallypipelinedsoc/core/lsu/ReadDataM[8]} {wallypipelinedsoc/core/lsu/ReadDataM[9]} {wallypipelinedsoc/core/lsu/ReadDataM[10]} {wallypipelinedsoc/core/lsu/ReadDataM[11]} {wallypipelinedsoc/core/lsu/ReadDataM[12]} {wallypipelinedsoc/core/lsu/ReadDataM[13]} {wallypipelinedsoc/core/lsu/ReadDataM[14]} {wallypipelinedsoc/core/lsu/ReadDataM[15]} {wallypipelinedsoc/core/lsu/ReadDataM[16]} {wallypipelinedsoc/core/lsu/ReadDataM[17]} {wallypipelinedsoc/core/lsu/ReadDataM[18]} {wallypipelinedsoc/core/lsu/ReadDataM[19]} {wallypipelinedsoc/core/lsu/ReadDataM[20]} {wallypipelinedsoc/core/lsu/ReadDataM[21]} {wallypipelinedsoc/core/lsu/ReadDataM[22]} {wallypipelinedsoc/core/lsu/ReadDataM[23]} {wallypipelinedsoc/core/lsu/ReadDataM[24]} {wallypipelinedsoc/core/lsu/ReadDataM[25]} {wallypipelinedsoc/core/lsu/ReadDataM[26]} {wallypipelinedsoc/core/lsu/ReadDataM[27]} {wallypipelinedsoc/core/lsu/ReadDataM[28]} {wallypipelinedsoc/core/lsu/ReadDataM[29]} {wallypipelinedsoc/core/lsu/ReadDataM[30]} {wallypipelinedsoc/core/lsu/ReadDataM[31]} {wallypipelinedsoc/core/lsu/ReadDataM[32]} {wallypipelinedsoc/core/lsu/ReadDataM[33]} {wallypipelinedsoc/core/lsu/ReadDataM[34]} {wallypipelinedsoc/core/lsu/ReadDataM[35]} {wallypipelinedsoc/core/lsu/ReadDataM[36]} {wallypipelinedsoc/core/lsu/ReadDataM[37]} {wallypipelinedsoc/core/lsu/ReadDataM[38]} {wallypipelinedsoc/core/lsu/ReadDataM[39]} {wallypipelinedsoc/core/lsu/ReadDataM[40]} {wallypipelinedsoc/core/lsu/ReadDataM[41]} {wallypipelinedsoc/core/lsu/ReadDataM[42]} {wallypipelinedsoc/core/lsu/ReadDataM[43]} {wallypipelinedsoc/core/lsu/ReadDataM[44]} {wallypipelinedsoc/core/lsu/ReadDataM[45]} {wallypipelinedsoc/core/lsu/ReadDataM[46]} {wallypipelinedsoc/core/lsu/ReadDataM[47]} {wallypipelinedsoc/core/lsu/ReadDataM[48]} {wallypipelinedsoc/core/lsu/ReadDataM[49]} {wallypipelinedsoc/core/lsu/ReadDataM[50]} {wallypipelinedsoc/core/lsu/ReadDataM[51]} {wallypipelinedsoc/core/lsu/ReadDataM[52]} {wallypipelinedsoc/core/lsu/ReadDataM[53]} {wallypipelinedsoc/core/lsu/ReadDataM[54]} {wallypipelinedsoc/core/lsu/ReadDataM[55]} {wallypipelinedsoc/core/lsu/ReadDataM[56]} {wallypipelinedsoc/core/lsu/ReadDataM[57]} {wallypipelinedsoc/core/lsu/ReadDataM[58]} {wallypipelinedsoc/core/lsu/ReadDataM[59]} {wallypipelinedsoc/core/lsu/ReadDataM[60]} {wallypipelinedsoc/core/lsu/ReadDataM[61]} {wallypipelinedsoc/core/lsu/ReadDataM[62]} {wallypipelinedsoc/core/lsu/ReadDataM[63]} ]]
create_debug_port u_ila_0 probe
set_property port_width 64 [get_debug_ports u_ila_0/probe7]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
connect_debug_port u_ila_0/probe7 [get_nets [list {wallypipelinedsoc/core/lsu/WriteDataM[0]} {wallypipelinedsoc/core/lsu/WriteDataM[1]} {wallypipelinedsoc/core/lsu/WriteDataM[2]} {wallypipelinedsoc/core/lsu/WriteDataM[3]} {wallypipelinedsoc/core/lsu/WriteDataM[4]} {wallypipelinedsoc/core/lsu/WriteDataM[5]} {wallypipelinedsoc/core/lsu/WriteDataM[6]} {wallypipelinedsoc/core/lsu/WriteDataM[7]} {wallypipelinedsoc/core/lsu/WriteDataM[8]} {wallypipelinedsoc/core/lsu/WriteDataM[9]} {wallypipelinedsoc/core/lsu/WriteDataM[10]} {wallypipelinedsoc/core/lsu/WriteDataM[11]} {wallypipelinedsoc/core/lsu/WriteDataM[12]} {wallypipelinedsoc/core/lsu/WriteDataM[13]} {wallypipelinedsoc/core/lsu/WriteDataM[14]} {wallypipelinedsoc/core/lsu/WriteDataM[15]} {wallypipelinedsoc/core/lsu/WriteDataM[16]} {wallypipelinedsoc/core/lsu/WriteDataM[17]} {wallypipelinedsoc/core/lsu/WriteDataM[18]} {wallypipelinedsoc/core/lsu/WriteDataM[19]} {wallypipelinedsoc/core/lsu/WriteDataM[20]} {wallypipelinedsoc/core/lsu/WriteDataM[21]} {wallypipelinedsoc/core/lsu/WriteDataM[22]} {wallypipelinedsoc/core/lsu/WriteDataM[23]} {wallypipelinedsoc/core/lsu/WriteDataM[24]} {wallypipelinedsoc/core/lsu/WriteDataM[25]} {wallypipelinedsoc/core/lsu/WriteDataM[26]} {wallypipelinedsoc/core/lsu/WriteDataM[27]} {wallypipelinedsoc/core/lsu/WriteDataM[28]} {wallypipelinedsoc/core/lsu/WriteDataM[29]} {wallypipelinedsoc/core/lsu/WriteDataM[30]} {wallypipelinedsoc/core/lsu/WriteDataM[31]} {wallypipelinedsoc/core/lsu/WriteDataM[32]} {wallypipelinedsoc/core/lsu/WriteDataM[33]} {wallypipelinedsoc/core/lsu/WriteDataM[34]} {wallypipelinedsoc/core/lsu/WriteDataM[35]} {wallypipelinedsoc/core/lsu/WriteDataM[36]} {wallypipelinedsoc/core/lsu/WriteDataM[37]} {wallypipelinedsoc/core/lsu/WriteDataM[38]} {wallypipelinedsoc/core/lsu/WriteDataM[39]} {wallypipelinedsoc/core/lsu/WriteDataM[40]} {wallypipelinedsoc/core/lsu/WriteDataM[41]} {wallypipelinedsoc/core/lsu/WriteDataM[42]} {wallypipelinedsoc/core/lsu/WriteDataM[43]} {wallypipelinedsoc/core/lsu/WriteDataM[44]} {wallypipelinedsoc/core/lsu/WriteDataM[45]} {wallypipelinedsoc/core/lsu/WriteDataM[46]} {wallypipelinedsoc/core/lsu/WriteDataM[47]} {wallypipelinedsoc/core/lsu/WriteDataM[48]} {wallypipelinedsoc/core/lsu/WriteDataM[49]} {wallypipelinedsoc/core/lsu/WriteDataM[50]} {wallypipelinedsoc/core/lsu/WriteDataM[51]} {wallypipelinedsoc/core/lsu/WriteDataM[52]} {wallypipelinedsoc/core/lsu/WriteDataM[53]} {wallypipelinedsoc/core/lsu/WriteDataM[54]} {wallypipelinedsoc/core/lsu/WriteDataM[55]} {wallypipelinedsoc/core/lsu/WriteDataM[56]} {wallypipelinedsoc/core/lsu/WriteDataM[57]} {wallypipelinedsoc/core/lsu/WriteDataM[58]} {wallypipelinedsoc/core/lsu/WriteDataM[59]} {wallypipelinedsoc/core/lsu/WriteDataM[60]} {wallypipelinedsoc/core/lsu/WriteDataM[61]} {wallypipelinedsoc/core/lsu/WriteDataM[62]} {wallypipelinedsoc/core/lsu/WriteDataM[63]} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe8]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
connect_debug_port u_ila_0/probe8 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/SDCCLK}]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe9]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
connect_debug_port u_ila_0/probe9 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/SDCIn}]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe10]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
connect_debug_port u_ila_0/probe10 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/SDCCS[0]}]]
create_debug_port u_ila_0 probe
set_property port_width 2 [get_debug_ports u_ila_0/probe11]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
connect_debug_port u_ila_0/probe11 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/InterruptPending[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/InterruptPending[1]}]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe12]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
connect_debug_port u_ila_0/probe12 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitFIFOWriteInc}]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe13]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
connect_debug_port u_ila_0/probe13 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitFIFOEmpty}]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe14]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
connect_debug_port u_ila_0/probe14 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitFIFOReadInc}]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe15]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
connect_debug_port u_ila_0/probe15 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitLoad}]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe16]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
connect_debug_port u_ila_0/probe16 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/SDCCmd}]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe17]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
connect_debug_port u_ila_0/probe17 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ShiftEdge}]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe18]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
connect_debug_port u_ila_0/probe18 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/SampleEdge}]]
create_debug_port u_ila_0 probe
set_property port_width 8 [get_debug_ports u_ila_0/probe19]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
connect_debug_port u_ila_0/probe19 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftReg[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftReg[1]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftReg[2]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftReg[3]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftReg[4]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftReg[5]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftReg[6]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftReg[7]} ]]
create_debug_port u_ila_0 probe
set_property port_width 8 [get_debug_ports u_ila_0/probe20]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
connect_debug_port u_ila_0/probe20 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitReg[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitReg[1]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitReg[2]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitReg[3]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitReg[4]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitReg[5]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitReg[6]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitReg[7]} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe21]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
connect_debug_port u_ila_0/probe21 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitLoad}]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe22]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22]
connect_debug_port u_ila_0/probe22 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ShiftIn}]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe23]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23]
connect_debug_port u_ila_0/probe23 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/controller/SCLKenable} ]]
create_debug_port u_ila_0 probe
set_property port_width 3 [get_debug_ports u_ila_0/probe24]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24]
connect_debug_port u_ila_0/probe24 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/controller/CurrState[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/controller/CurrState[1]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/controller/CurrState[2]} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe25]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25]
connect_debug_port u_ila_0/probe25 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/EndOfFrame}]]
create_debug_port u_ila_0 probe
set_property port_width 3 [get_debug_ports u_ila_0/probe26]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26]
connect_debug_port u_ila_0/probe26 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/controller/NextState[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/controller/NextState[1]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/controller/NextState[2]} ]]
create_debug_port u_ila_0 probe
set_property port_width 4 [get_debug_ports u_ila_0/probe27]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27]
connect_debug_port u_ila_0/probe27 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/controller/BitNum[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/controller/BitNum[1]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/controller/BitNum[2]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/controller/BitNum[3]} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe28]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28]
connect_debug_port u_ila_0/probe28 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/controller/ContinueTransmit}]]
create_debug_port u_ila_0 probe
set_property port_width 4 [get_debug_ports u_ila_0/probe29]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29]
connect_debug_port u_ila_0/probe29 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/wptrnext[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/wptrnext[1]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/wptrnext[2]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/wptrnext[3]} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe30]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30]
connect_debug_port u_ila_0/probe30 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitRegLoaded}]]
create_debug_port u_ila_0 probe
set_property port_width 4 [get_debug_ports u_ila_0/probe31]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31]
connect_debug_port u_ila_0/probe31 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/rptrnext[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/rptrnext[1]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/rptrnext[2]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/rptrnext[3]} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe32]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32]
connect_debug_port u_ila_0/probe32 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/controller/SPICLK}]]
create_debug_port u_ila_0 probe
set_property port_width 9 [get_debug_ports u_ila_0/probe33]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33]
connect_debug_port u_ila_0/probe33 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitData[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitData[1]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitData[2]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitData[3]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitData[4]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitData[5]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitData[6]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitData[7]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitData[8]} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe34]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34]
connect_debug_port u_ila_0/probe34 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveFIFOWriteInc}]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe35]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35]
connect_debug_port u_ila_0/probe35 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveFIFOReadInc}]]
create_debug_port u_ila_0 probe
set_property port_width 8 [get_debug_ports u_ila_0/probe36]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe36]
connect_debug_port u_ila_0/probe36 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftRegEndian[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftRegEndian[1]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftRegEndian[2]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftRegEndian[3]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftRegEndian[4]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftRegEndian[5]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftRegEndian[6]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftRegEndian[7]} ]]
create_debug_port u_ila_0 probe
set_property port_width 3 [get_debug_ports u_ila_0/probe37]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe37]
connect_debug_port u_ila_0/probe37 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveWatermark[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveWatermark[1]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveWatermark[2]} ]]
create_debug_port u_ila_0 probe
set_property port_width 3 [get_debug_ports u_ila_0/probe38]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe38]
connect_debug_port u_ila_0/probe38 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveReadWatermarkLevel[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveReadWatermarkLevel[1]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveReadWatermarkLevel[2]} ]]
create_debug_port u_ila_0 probe
set_property port_width 8 [get_debug_ports u_ila_0/probe39]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe39]
connect_debug_port u_ila_0/probe39 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveData[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveData[1]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveData[2]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveData[3]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveData[4]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveData[5]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveData[6]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveData[7]} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe40]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe40]
connect_debug_port u_ila_0/probe40 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveFIFOFull}]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe41]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe41]
connect_debug_port u_ila_0/probe41 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveFIFOEmpty}]]
create_debug_port u_ila_0 probe
set_property port_width 3 [get_debug_ports u_ila_0/probe42]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe42]
connect_debug_port u_ila_0/probe42 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/raddr[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/raddr[1]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/raddr[2]} ]]
create_debug_port u_ila_0 probe
set_property port_width 3 [get_debug_ports u_ila_0/probe43]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe43]
connect_debug_port u_ila_0/probe43 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/waddr[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/waddr[1]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/waddr[2]} ]]
create_debug_port u_ila_0 probe
set_property port_width 4 [get_debug_ports u_ila_0/probe44]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe44]
connect_debug_port u_ila_0/probe44 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/rptr[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/rptr[1]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/rptr[2]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/rptr[3]} ]]
create_debug_port u_ila_0 probe
set_property port_width 4 [get_debug_ports u_ila_0/probe45]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe45]
connect_debug_port u_ila_0/probe45 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/wptr[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/wptr[1]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/wptr[2]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/wptr[3]} ]]
# the debug hub has issues with the clocks from the mmcm so lets give up an connect to the 100Mhz input clock.
#connect_debug_port dbg_hub/clk [get_nets default_100mhz_clk]
connect_debug_port dbg_hub/clk [get_nets CPUCLK]

6
fpga/constraints/constraints-vcu108.xdc
View file

@ -83,7 +83,7 @@ set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_port
##### SD Card I/O #####
# create the generated SPICLK
create_generated_clock -name SPISDCClock -source [get_pins ddr4/addn_ui_clkout1] -multiply_by 1 -divide_by 1 [get_pins wallypipelinedsoc/uncoregen.uncore/spi.spi/SPICLK]
create_generated_clock -name SPISDCClock -source [get_pins ddr4/addn_ui_clkout1] -multiply_by 1 -divide_by 1 [get_pins wallypipelinedsoc/uncoregen.uncore/sdc.sdc/SPICLK]
set_output_delay -clock [get_clocks SPISDCClock] -max 5.0 [get_ports {SDCCS}]
set_output_delay -clock [get_clocks SPISDCClock] -min -5.0 [get_ports {SDCCS}]
@ -95,8 +95,8 @@ set_input_delay -clock [get_clocks SPISDCClock] -max 5.0 [get_ports {SDCWP}]
set_input_delay -clock [get_clocks SPISDCClock] -min -5.0 [get_ports {SDCWP}]
set_output_delay -clock [get_clocks SPISDCClock] -max 5.0 [get_ports {SDCCmd}]
set_output_delay -clock [get_clocks SPISDCClock] -min -5.0 [get_ports {SDCCmd}]
create_generated_clock -name SPISDCClockOut -multiply_by 1 -source [get_pins sdcclkoddr/C] [get_ports SDCCLK]
set_clock_latency -source -max 3.0 [get_ports SDCCLK]
set_output_delay -clock [get_clocks SPISDCClock] -max 2.000 [get_ports SDCCLK]
set_output_delay -clock [get_clocks SPISDCClock] -min -2.000 [get_ports SDCCLK]
set_property -dict {PACKAGE_PIN BC14 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCCS}]

52
fpga/constraints/marked_debug.txt
View file

@ -5,22 +5,36 @@ wally/wallypipelinedcore.sv: logic InstrM
lsu/lsu.sv: logic IEUAdrM
lsu/lsu.sv: logic MemRWM
mmu/hptw.sv: logic SATP_REGW
uncore/spi_apb.sv: logic ShiftIn
uncore/spi_apb.sv: logic ReceiveShiftReg
uncore/spi_apb.sv: logic SCLKenable
uncore/spi_apb.sv: logic SampleEdge
uncore/spi_apb.sv: logic Active
uncore/spi_apb.sv: statetype state
uncore/spi_apb.sv: typedef rsrstatetype
uncore/spi_apb.sv: logic SPICLK
uncore/spi_apb.sv: logic SPIOut
uncore/spi_apb.sv: logic SPICS
uncore/spi_apb.sv: logic SckMode
uncore/spi_apb.sv: logic SckDiv
uncore/spi_apb.sv: logic ShiftEdge
uncore/spi_apb.sv: logic TransmitShiftRegLoad
uncore/spi_apb.sv: logic TransmitShiftReg
uncore/spi_apb.sv: logic TransmitData
uncore/spi_apb.sv: logic ReceiveData
uncore/spi_apb.sv: logic ReceiveShiftRegEndian
uncore/spi_apb.sv: logic ASR
uncore/uartPC16550D.sv : logic MCR
uncore/uartPC16550D.sv : logic FCR
uncore/uartPC16550D.sv : logic MSR
uncore/uartPC16550D.sv : logic DTRb
uncore/uartPC16550D.sv : logic INTR
uncore/uartPC16550D.sv : logic RXRDYb
uncore/uartPC16550D.sv : logic TXRDYb
uncore/uartPC16550D.sv : logic RXerrIP
uncore/uartPC16550D.sv : logic IER
uncore/uartPC16550D.sv : logic LSR
uncore/uartPC16550D.sv : logic SCR
uncore/uartPC16550D.sv : statetype txstate
uncore/uartPC16550D.sv : logic RBR
uncore/uartPC16550D.sv : logic rxparityerr
uncore/uartPC16550D.sv : logic LCR
uncore/uartPC16550D.sv : logic intrID
uncore/uartPC16550D.sv : logic rxdataavailintr
uncore/uartPC16550D.sv : logic fifoenabled
uncore/uartPC16550D.sv : logic rxfifoentries
uncore/uartPC16550D.sv : logic txsrfull
uncore/uartPC16550D.sv : logic txhrfull
uncore/uartPC16550D.sv : logic txfifofull
uncore/uartPC16550D.sv : logic txfifotail
uncore/uartPC16550D.sv : logic txfifohead
uncore/uartPC16550D.sv : logic rxfifotriggered
uncore/uartPC16550D.sv : logic rxdataready
privileged/privdec.sv : logic wfiM
privileged/privdec.sv : logic wfiW
privileged/privdec.sv : logic WFITimeoutM
uncore/plic_apb.sv : logic requests
uncore/plic_apb.sv : logic intInProgress
uncore/plic_apb.sv : logic intPending
uncore/plic_apb.sv : logic intClaim

59
fpga/constraints/marked_debug_spi.txt
View file

@ -5,32 +5,39 @@ wally/wallypipelinedcore.sv: logic InstrM
lsu/lsu.sv: logic IEUAdrM
lsu/lsu.sv: logic MemRWM
mmu/hptw.sv: logic SATP_REGW
uncore/spi_apb.sv: logic ShiftIn
uncore/spi_apb.sv: logic ReceiveShiftReg
uncore/spi_apb.sv: logic SCLKenable
uncore/spi_apb.sv: logic SampleEdge
uncore/spi_apb.sv: logic Active
uncore/spi_apb.sv: statetype state
uncore/spi_apb.sv: typedef rsrstatetype
uncore/spi_apb.sv: logic SPICLK
uncore/spi_apb.sv: logic SPIOut
uncore/spi_apb.sv: logic SPICS
uncore/spi_apb.sv: logic SckMode
uncore/spi_apb.sv: logic SckDiv
uncore/uncore.sv: logic SDCCmd
uncore/uncore.sv: logic SDCCLK
uncore/uncore.sv: logic SDCIn
uncore/uncore.sv: logic SDCCS
uncore/spi_apb.sv: logic InterruptPending
uncore/spi_apb.sv: logic TransmitFIFOWriteInc
uncore/spi_apb.sv: logic TransmitFIFOEmpty
uncore/spi_apb.sv: logic TransmitFIFOReadInc
uncore/spi_apb.sv: logic TransmitLoad
uncore/spi_apb.sv: logic ShiftEdge
uncore/spi_apb.sv: logic TransmitShiftRegLoadSingleCycle
uncore/spi_apb.sv: logic TransmitShiftReg
uncore/spi_apb.sv: logic SampleEdge
uncore/spi_apb.sv: logic ReceiveShiftReg
uncore/spi_apb.sv: logic TransmitReg
uncore/spi_apb.sv: logic ShiftIn
uncore/spi_apb.sv: logic EndOfFrame
uncore/spi_apb.sv: logic TransmitRegLoaded
uncore/spi_apb.sv: logic TransmitData
uncore/spi_apb.sv: logic ReceiveData
uncore/spi_apb.sv: logic ReceiveFIFOWriteInc
uncore/spi_apb.sv: logic ReceiveFIFOReadInc
uncore/spi_apb.sv: logic ReceiveShiftRegEndian
uncore/spi_apb.sv: logic TransmitShiftReg
uncore/spi_apb.sv: logic TransmitShift
uncore/spi_apb.sv: logic ReceiveShiftFullDelay
uncore/spi_apb.sv: logic TransmitShiftEmpty
uncore/spi_apb.sv: logic ReceiveFIFOWriteFull
uncore/spi_apb.sv: logic ReceiveFIFOReadIncrement
uncore/spi_apb.sv: logic ReceiveFIFOReadEmpty
uncore/spi_apb.sv: logic TransmitFIFOWriteIncrement
uncore/spi_apb.sv: logic TransmitFIFOReadIncrement
uncore/spi_apb.sv: logic TransmitFIFOWriteFull
uncore/spi_apb.sv: logic TransmitFIFOReadEmpty
uncore/spi_apb.sv: logic ReceiveWatermark
uncore/spi_apb.sv: logic ReceiveReadWatermarkLevel
uncore/spi_apb.sv: logic ReceiveData
uncore/spi_apb.sv: logic ReceiveFIFOFull
uncore/spi_apb.sv: logic ReceiveFIFOEmpty
uncore/spi_controller.sv: logic SCLKenable
uncore/spi_controller.sv: statetype CurrState
uncore/spi_controller.sv: statetype NextState
uncore/spi_controller.sv: logic BitNum
uncore/spi_controller.sv: logic ContinueTransmit
uncore/spi_controller.sv: logic PhaseOneOffset
uncore/spi_controller.sv: logic SPICLK
uncore/spi_fifo.sv: logic rptr
uncore/spi_fifo.sv: logic rptrnext
uncore/spi_fifo.sv: logic raddr
uncore/spi_fifo.sv: logic waddr

33
fpga/constraints/marked_debug_uart.txt Normal file
View file

@ -0,0 +1,33 @@
wally/wallypipelinedcore.sv: logic PCM
wally/wallypipelinedcore.sv: logic TrapM
wally/wallypipelinedcore.sv: logic InstrValidM
wally/wallypipelinedcore.sv: logic InstrM
lsu/lsu.sv: logic IEUAdrM
lsu/lsu.sv: logic MemRWM
mmu/hptw.sv: logic SATP_REGW
uncore/uartPC16550D.sv : logic MCR
uncore/uartPC16550D.sv : logic FCR
uncore/uartPC16550D.sv : logic MSR
uncore/uartPC16550D.sv : logic DTRb
uncore/uartPC16550D.sv : logic INTR
uncore/uartPC16550D.sv : logic RXRDYb
uncore/uartPC16550D.sv : logic TXRDYb
uncore/uartPC16550D.sv : logic RXerrIP
uncore/uartPC16550D.sv : logic IER
uncore/uartPC16550D.sv : logic LSR
uncore/uartPC16550D.sv : logic SCR
uncore/uartPC16550D.sv : statetype txstate
uncore/uartPC16550D.sv : logic RBR
uncore/uartPC16550D.sv : logic rxparityerr
uncore/uartPC16550D.sv : logic LCR
uncore/uartPC16550D.sv : logic intrID
uncore/uartPC16550D.sv : logic rxdataavailintr
uncore/uartPC16550D.sv : logic fifoenabled
uncore/uartPC16550D.sv : logic rxfifoentries
uncore/uartPC16550D.sv : logic txsrfull
uncore/uartPC16550D.sv : logic txhrfull
uncore/uartPC16550D.sv : logic txfifofull
uncore/uartPC16550D.sv : logic txfifotail
uncore/uartPC16550D.sv : logic txfifohead
uncore/uartPC16550D.sv : logic rxfifotriggered
uncore/uartPC16550D.sv : logic rxdataready

208
fpga/constraints/small-debug-uart.xdc Normal file
View file

@ -0,0 +1,208 @@
create_debug_core u_ila_0 ila
set_property C_DATA_DEPTH 4096 [get_debug_cores u_ila_0]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
startgroup
set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0 ]
set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0 ]
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0 ]
set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0 ]
endgroup
connect_debug_port u_ila_0/clk [get_nets CPUCLK]
set_property port_width 33 [get_debug_ports u_ila_0/probe0]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
connect_debug_port u_ila_0/probe0 [get_nets [list {wallypipelinedsoc/core/PCM[0]} {wallypipelinedsoc/core/PCM[1]} {wallypipelinedsoc/core/PCM[2]} {wallypipelinedsoc/core/PCM[3]} {wallypipelinedsoc/core/PCM[4]} {wallypipelinedsoc/core/PCM[5]} {wallypipelinedsoc/core/PCM[6]} {wallypipelinedsoc/core/PCM[7]} {wallypipelinedsoc/core/PCM[8]} {wallypipelinedsoc/core/PCM[9]} {wallypipelinedsoc/core/PCM[10]} {wallypipelinedsoc/core/PCM[11]} {wallypipelinedsoc/core/PCM[12]} {wallypipelinedsoc/core/PCM[13]} {wallypipelinedsoc/core/PCM[14]} {wallypipelinedsoc/core/PCM[15]} {wallypipelinedsoc/core/PCM[16]} {wallypipelinedsoc/core/PCM[17]} {wallypipelinedsoc/core/PCM[18]} {wallypipelinedsoc/core/PCM[19]} {wallypipelinedsoc/core/PCM[20]} {wallypipelinedsoc/core/PCM[21]} {wallypipelinedsoc/core/PCM[22]} {wallypipelinedsoc/core/PCM[23]} {wallypipelinedsoc/core/PCM[24]} {wallypipelinedsoc/core/PCM[25]} {wallypipelinedsoc/core/PCM[26]} {wallypipelinedsoc/core/PCM[27]} {wallypipelinedsoc/core/PCM[28]} {wallypipelinedsoc/core/PCM[29]} {wallypipelinedsoc/core/PCM[30]} {wallypipelinedsoc/core/PCM[31]} {wallypipelinedsoc/core/PCM[32]} } ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe1]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
connect_debug_port u_ila_0/probe1 [get_nets [list wallypipelinedsoc/core/TrapM ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe2]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
connect_debug_port u_ila_0/probe2 [get_nets [list wallypipelinedsoc/core/InstrValidM ]]
create_debug_port u_ila_0 probe
set_property port_width 32 [get_debug_ports u_ila_0/probe3]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
connect_debug_port u_ila_0/probe3 [get_nets [list {wallypipelinedsoc/core/InstrM[0]} {wallypipelinedsoc/core/InstrM[1]} {wallypipelinedsoc/core/InstrM[2]} {wallypipelinedsoc/core/InstrM[3]} {wallypipelinedsoc/core/InstrM[4]} {wallypipelinedsoc/core/InstrM[5]} {wallypipelinedsoc/core/InstrM[6]} {wallypipelinedsoc/core/InstrM[7]} {wallypipelinedsoc/core/InstrM[8]} {wallypipelinedsoc/core/InstrM[9]} {wallypipelinedsoc/core/InstrM[10]} {wallypipelinedsoc/core/InstrM[11]} {wallypipelinedsoc/core/InstrM[12]} {wallypipelinedsoc/core/InstrM[13]} {wallypipelinedsoc/core/InstrM[14]} {wallypipelinedsoc/core/InstrM[15]} {wallypipelinedsoc/core/InstrM[16]} {wallypipelinedsoc/core/InstrM[17]} {wallypipelinedsoc/core/InstrM[18]} {wallypipelinedsoc/core/InstrM[19]} {wallypipelinedsoc/core/InstrM[20]} {wallypipelinedsoc/core/InstrM[21]} {wallypipelinedsoc/core/InstrM[22]} {wallypipelinedsoc/core/InstrM[23]} {wallypipelinedsoc/core/InstrM[24]} {wallypipelinedsoc/core/InstrM[25]} {wallypipelinedsoc/core/InstrM[26]} {wallypipelinedsoc/core/InstrM[27]} {wallypipelinedsoc/core/InstrM[28]} {wallypipelinedsoc/core/InstrM[29]} {wallypipelinedsoc/core/InstrM[30]} {wallypipelinedsoc/core/InstrM[31]} ]]
create_debug_port u_ila_0 probe
set_property port_width 2 [get_debug_ports u_ila_0/probe4]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
connect_debug_port u_ila_0/probe4 [get_nets [list {wallypipelinedsoc/core/lsu/MemRWM[0]} {wallypipelinedsoc/core/lsu/MemRWM[1]} ]]
create_debug_port u_ila_0 probe
set_property port_width 64 [get_debug_ports u_ila_0/probe5]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
connect_debug_port u_ila_0/probe5 [get_nets [list {wallypipelinedsoc/core/lsu/IEUAdrM[0]} {wallypipelinedsoc/core/lsu/IEUAdrM[1]} {wallypipelinedsoc/core/lsu/IEUAdrM[2]} {wallypipelinedsoc/core/lsu/IEUAdrM[3]} {wallypipelinedsoc/core/lsu/IEUAdrM[4]} {wallypipelinedsoc/core/lsu/IEUAdrM[5]} {wallypipelinedsoc/core/lsu/IEUAdrM[6]} {wallypipelinedsoc/core/lsu/IEUAdrM[7]} {wallypipelinedsoc/core/lsu/IEUAdrM[8]} {wallypipelinedsoc/core/lsu/IEUAdrM[9]} {wallypipelinedsoc/core/lsu/IEUAdrM[10]} {wallypipelinedsoc/core/lsu/IEUAdrM[11]} {wallypipelinedsoc/core/lsu/IEUAdrM[12]} {wallypipelinedsoc/core/lsu/IEUAdrM[13]} {wallypipelinedsoc/core/lsu/IEUAdrM[14]} {wallypipelinedsoc/core/lsu/IEUAdrM[15]} {wallypipelinedsoc/core/lsu/IEUAdrM[16]} {wallypipelinedsoc/core/lsu/IEUAdrM[17]} {wallypipelinedsoc/core/lsu/IEUAdrM[18]} {wallypipelinedsoc/core/lsu/IEUAdrM[19]} {wallypipelinedsoc/core/lsu/IEUAdrM[20]} {wallypipelinedsoc/core/lsu/IEUAdrM[21]} {wallypipelinedsoc/core/lsu/IEUAdrM[22]} {wallypipelinedsoc/core/lsu/IEUAdrM[23]} {wallypipelinedsoc/core/lsu/IEUAdrM[24]} {wallypipelinedsoc/core/lsu/IEUAdrM[25]} {wallypipelinedsoc/core/lsu/IEUAdrM[26]} {wallypipelinedsoc/core/lsu/IEUAdrM[27]} {wallypipelinedsoc/core/lsu/IEUAdrM[28]} {wallypipelinedsoc/core/lsu/IEUAdrM[29]} {wallypipelinedsoc/core/lsu/IEUAdrM[30]} {wallypipelinedsoc/core/lsu/IEUAdrM[31]} {wallypipelinedsoc/core/lsu/IEUAdrM[32]} {wallypipelinedsoc/core/lsu/IEUAdrM[33]} {wallypipelinedsoc/core/lsu/IEUAdrM[34]} {wallypipelinedsoc/core/lsu/IEUAdrM[35]} {wallypipelinedsoc/core/lsu/IEUAdrM[36]} {wallypipelinedsoc/core/lsu/IEUAdrM[37]} {wallypipelinedsoc/core/lsu/IEUAdrM[38]} {wallypipelinedsoc/core/lsu/IEUAdrM[39]} {wallypipelinedsoc/core/lsu/IEUAdrM[40]} {wallypipelinedsoc/core/lsu/IEUAdrM[41]} {wallypipelinedsoc/core/lsu/IEUAdrM[42]} {wallypipelinedsoc/core/lsu/IEUAdrM[43]} {wallypipelinedsoc/core/lsu/IEUAdrM[44]} {wallypipelinedsoc/core/lsu/IEUAdrM[45]} {wallypipelinedsoc/core/lsu/IEUAdrM[46]} {wallypipelinedsoc/core/lsu/IEUAdrM[47]} {wallypipelinedsoc/core/lsu/IEUAdrM[48]} {wallypipelinedsoc/core/lsu/IEUAdrM[49]} {wallypipelinedsoc/core/lsu/IEUAdrM[50]} {wallypipelinedsoc/core/lsu/IEUAdrM[51]} {wallypipelinedsoc/core/lsu/IEUAdrM[52]} {wallypipelinedsoc/core/lsu/IEUAdrM[53]} {wallypipelinedsoc/core/lsu/IEUAdrM[54]} {wallypipelinedsoc/core/lsu/IEUAdrM[55]} {wallypipelinedsoc/core/lsu/IEUAdrM[56]} {wallypipelinedsoc/core/lsu/IEUAdrM[57]} {wallypipelinedsoc/core/lsu/IEUAdrM[58]} {wallypipelinedsoc/core/lsu/IEUAdrM[59]} {wallypipelinedsoc/core/lsu/IEUAdrM[60]} {wallypipelinedsoc/core/lsu/IEUAdrM[61]} {wallypipelinedsoc/core/lsu/IEUAdrM[62]} {wallypipelinedsoc/core/lsu/IEUAdrM[63]} ]]
create_debug_port u_ila_0 probe
set_property port_width 8 [get_debug_ports u_ila_0/probe6]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
connect_debug_port u_ila_0/probe6 [get_nets [list {wallypipelinedsoc/core/lsu/ReadDataM[0]} {wallypipelinedsoc/core/lsu/ReadDataM[1]} {wallypipelinedsoc/core/lsu/ReadDataM[2]} {wallypipelinedsoc/core/lsu/ReadDataM[3]} {wallypipelinedsoc/core/lsu/ReadDataM[4]} {wallypipelinedsoc/core/lsu/ReadDataM[5]} {wallypipelinedsoc/core/lsu/ReadDataM[6]} {wallypipelinedsoc/core/lsu/ReadDataM[7]} ]]
create_debug_port u_ila_0 probe
set_property port_width 8 [get_debug_ports u_ila_0/probe7]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
connect_debug_port u_ila_0/probe7 [get_nets [list {wallypipelinedsoc/core/lsu/WriteDataM[0]} {wallypipelinedsoc/core/lsu/WriteDataM[1]} {wallypipelinedsoc/core/lsu/WriteDataM[2]} {wallypipelinedsoc/core/lsu/WriteDataM[3]} {wallypipelinedsoc/core/lsu/WriteDataM[4]} {wallypipelinedsoc/core/lsu/WriteDataM[5]} {wallypipelinedsoc/core/lsu/WriteDataM[6]} {wallypipelinedsoc/core/lsu/WriteDataM[7]} ]]
create_debug_port u_ila_0 probe
set_property port_width 5 [get_debug_ports u_ila_0/probe8]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
connect_debug_port u_ila_0/probe8 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/MCR[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/MCR[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/MCR[2]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/MCR[3]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/MCR[4]} ]]
create_debug_port u_ila_0 probe
set_property port_width 8 [get_debug_ports u_ila_0/probe9]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
connect_debug_port u_ila_0/probe9 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/FCR[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/FCR[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/FCR[2]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/FCR[3]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/FCR[4]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/FCR[5]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/FCR[6]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/FCR[7]} ]]
create_debug_port u_ila_0 probe
set_property port_width 4 [get_debug_ports u_ila_0/probe10]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
connect_debug_port u_ila_0/probe10 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/MSR[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/MSR[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/MSR[2]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/MSR[3]} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe11]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
connect_debug_port u_ila_0/probe11 [get_nets [list wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/DTRb ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe12]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
connect_debug_port u_ila_0/probe12 [get_nets [list wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/INTR ]]
create_debug_port u_ila_0 probe
set_property port_width 4 [get_debug_ports u_ila_0/probe13]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
connect_debug_port u_ila_0/probe13 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifohead[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifohead[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifohead[2]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifohead[3]}]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe14]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
connect_debug_port u_ila_0/probe14 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txsrfull}]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe15]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
connect_debug_port u_ila_0/probe15 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txhrfull}]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe16]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
connect_debug_port u_ila_0/probe16 [get_nets [list wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/RXRDYb ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe17]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
connect_debug_port u_ila_0/probe17 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifofull}]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe18]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
connect_debug_port u_ila_0/probe18 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifoempty}]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe19]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
connect_debug_port u_ila_0/probe19 [get_nets [list wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/TXRDYb ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe20]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
connect_debug_port u_ila_0/probe20 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/RXerrIP} ]]
create_debug_port u_ila_0 probe
set_property port_width 4 [get_debug_ports u_ila_0/probe21]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
connect_debug_port u_ila_0/probe21 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/IER[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/IER[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/IER[2]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/IER[3]} ]]
create_debug_port u_ila_0 probe
set_property port_width 8 [get_debug_ports u_ila_0/probe22]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22]
connect_debug_port u_ila_0/probe22 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LSR[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LSR[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LSR[2]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LSR[3]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LSR[4]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LSR[5]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LSR[6]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LSR[7]} ]]
create_debug_port u_ila_0 probe
set_property port_width 8 [get_debug_ports u_ila_0/probe23]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23]
connect_debug_port u_ila_0/probe23 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/SCR[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/SCR[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/SCR[2]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/SCR[3]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/SCR[4]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/SCR[5]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/SCR[6]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/SCR[7]} ]]
create_debug_port u_ila_0 probe
set_property port_width 2 [get_debug_ports u_ila_0/probe24]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24]
connect_debug_port u_ila_0/probe24 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txstate[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txstate[1]} ]]
create_debug_port u_ila_0 probe
set_property port_width 11 [get_debug_ports u_ila_0/probe25]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25]
connect_debug_port u_ila_0/probe25 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/RBR[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/RBR[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/RBR[2]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/RBR[3]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/RBR[4]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/RBR[5]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/RBR[6]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/RBR[7]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/RBR[8]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/RBR[9]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/RBR[10]} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe26]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26]
connect_debug_port u_ila_0/probe26 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxparityerr} ]]
create_debug_port u_ila_0 probe
set_property port_width 2 [get_debug_ports u_ila_0/probe27]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27]
connect_debug_port u_ila_0/probe27 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxstate[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxstate[1]} ]]
create_debug_port u_ila_0 probe
set_property port_width 8 [get_debug_ports u_ila_0/probe28]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28]
connect_debug_port u_ila_0/probe28 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LCR[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LCR[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LCR[2]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LCR[3]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LCR[4]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LCR[5]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LCR[6]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LCR[7]} ]]
create_debug_port u_ila_0 probe
set_property port_width 3 [get_debug_ports u_ila_0/probe29]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29]
connect_debug_port u_ila_0/probe29 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/intrID[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/intrID[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/intrID[2]} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe30]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30]
connect_debug_port u_ila_0/probe30 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxdataavailintr} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe31]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31]
connect_debug_port u_ila_0/probe31 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/fifoenabled} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe32]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32]
connect_debug_port u_ila_0/probe32 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxfifotriggered} ]]
create_debug_port u_ila_0 probe
set_property port_width 4 [get_debug_ports u_ila_0/probe33]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33]
connect_debug_port u_ila_0/probe33 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxfifoentries[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxfifoentries[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxfifoentries[2]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxfifoentries[3]} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe34]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34]
connect_debug_port u_ila_0/probe34 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxdataready} ]]
create_debug_port u_ila_0 probe
set_property port_width 4 [get_debug_ports u_ila_0/probe35]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35]
connect_debug_port u_ila_0/probe35 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifotail[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifotail[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifotail[2]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifotail[3]}]]
# the debug hub has issues with the clocks from the mmcm so lets give up an connect to the 100Mhz input clock.
#connect_debug_port dbg_hub/clk [get_nets default_100mhz_clk]
connect_debug_port dbg_hub/clk [get_nets CPUCLK]

191
fpga/constraints/small-debug-wfi.xdc Normal file
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@ -0,0 +1,191 @@
create_debug_core u_ila_0 ila
set_property C_DATA_DEPTH 4096 [get_debug_cores u_ila_0]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
startgroup
set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0 ]
set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0 ]
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0 ]
set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0 ]
endgroup
connect_debug_port u_ila_0/clk [get_nets CPUCLK]
set_property port_width 33 [get_debug_ports u_ila_0/probe0]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
connect_debug_port u_ila_0/probe0 [get_nets [list {wallypipelinedsoc/core/PCM[0]} {wallypipelinedsoc/core/PCM[1]} {wallypipelinedsoc/core/PCM[2]} {wallypipelinedsoc/core/PCM[3]} {wallypipelinedsoc/core/PCM[4]} {wallypipelinedsoc/core/PCM[5]} {wallypipelinedsoc/core/PCM[6]} {wallypipelinedsoc/core/PCM[7]} {wallypipelinedsoc/core/PCM[8]} {wallypipelinedsoc/core/PCM[9]} {wallypipelinedsoc/core/PCM[10]} {wallypipelinedsoc/core/PCM[11]} {wallypipelinedsoc/core/PCM[12]} {wallypipelinedsoc/core/PCM[13]} {wallypipelinedsoc/core/PCM[14]} {wallypipelinedsoc/core/PCM[15]} {wallypipelinedsoc/core/PCM[16]} {wallypipelinedsoc/core/PCM[17]} {wallypipelinedsoc/core/PCM[18]} {wallypipelinedsoc/core/PCM[19]} {wallypipelinedsoc/core/PCM[20]} {wallypipelinedsoc/core/PCM[21]} {wallypipelinedsoc/core/PCM[22]} {wallypipelinedsoc/core/PCM[23]} {wallypipelinedsoc/core/PCM[24]} {wallypipelinedsoc/core/PCM[25]} {wallypipelinedsoc/core/PCM[26]} {wallypipelinedsoc/core/PCM[27]} {wallypipelinedsoc/core/PCM[28]} {wallypipelinedsoc/core/PCM[29]} {wallypipelinedsoc/core/PCM[30]} {wallypipelinedsoc/core/PCM[31]} {wallypipelinedsoc/core/PCM[32]} } ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe1]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
connect_debug_port u_ila_0/probe1 [get_nets [list wallypipelinedsoc/core/TrapM ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe2]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
connect_debug_port u_ila_0/probe2 [get_nets [list wallypipelinedsoc/core/InstrValidM ]]
create_debug_port u_ila_0 probe
set_property port_width 32 [get_debug_ports u_ila_0/probe3]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
connect_debug_port u_ila_0/probe3 [get_nets [list {wallypipelinedsoc/core/InstrM[0]} {wallypipelinedsoc/core/InstrM[1]} {wallypipelinedsoc/core/InstrM[2]} {wallypipelinedsoc/core/InstrM[3]} {wallypipelinedsoc/core/InstrM[4]} {wallypipelinedsoc/core/InstrM[5]} {wallypipelinedsoc/core/InstrM[6]} {wallypipelinedsoc/core/InstrM[7]} {wallypipelinedsoc/core/InstrM[8]} {wallypipelinedsoc/core/InstrM[9]} {wallypipelinedsoc/core/InstrM[10]} {wallypipelinedsoc/core/InstrM[11]} {wallypipelinedsoc/core/InstrM[12]} {wallypipelinedsoc/core/InstrM[13]} {wallypipelinedsoc/core/InstrM[14]} {wallypipelinedsoc/core/InstrM[15]} {wallypipelinedsoc/core/InstrM[16]} {wallypipelinedsoc/core/InstrM[17]} {wallypipelinedsoc/core/InstrM[18]} {wallypipelinedsoc/core/InstrM[19]} {wallypipelinedsoc/core/InstrM[20]} {wallypipelinedsoc/core/InstrM[21]} {wallypipelinedsoc/core/InstrM[22]} {wallypipelinedsoc/core/InstrM[23]} {wallypipelinedsoc/core/InstrM[24]} {wallypipelinedsoc/core/InstrM[25]} {wallypipelinedsoc/core/InstrM[26]} {wallypipelinedsoc/core/InstrM[27]} {wallypipelinedsoc/core/InstrM[28]} {wallypipelinedsoc/core/InstrM[29]} {wallypipelinedsoc/core/InstrM[30]} {wallypipelinedsoc/core/InstrM[31]} ]]
create_debug_port u_ila_0 probe
set_property port_width 2 [get_debug_ports u_ila_0/probe4]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
connect_debug_port u_ila_0/probe4 [get_nets [list {wallypipelinedsoc/core/lsu/MemRWM[0]} {wallypipelinedsoc/core/lsu/MemRWM[1]} ]]
create_debug_port u_ila_0 probe
set_property port_width 64 [get_debug_ports u_ila_0/probe5]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
connect_debug_port u_ila_0/probe5 [get_nets [list {wallypipelinedsoc/core/lsu/IEUAdrM[0]} {wallypipelinedsoc/core/lsu/IEUAdrM[1]} {wallypipelinedsoc/core/lsu/IEUAdrM[2]} {wallypipelinedsoc/core/lsu/IEUAdrM[3]} {wallypipelinedsoc/core/lsu/IEUAdrM[4]} {wallypipelinedsoc/core/lsu/IEUAdrM[5]} {wallypipelinedsoc/core/lsu/IEUAdrM[6]} {wallypipelinedsoc/core/lsu/IEUAdrM[7]} {wallypipelinedsoc/core/lsu/IEUAdrM[8]} {wallypipelinedsoc/core/lsu/IEUAdrM[9]} {wallypipelinedsoc/core/lsu/IEUAdrM[10]} {wallypipelinedsoc/core/lsu/IEUAdrM[11]} {wallypipelinedsoc/core/lsu/IEUAdrM[12]} {wallypipelinedsoc/core/lsu/IEUAdrM[13]} {wallypipelinedsoc/core/lsu/IEUAdrM[14]} {wallypipelinedsoc/core/lsu/IEUAdrM[15]} {wallypipelinedsoc/core/lsu/IEUAdrM[16]} {wallypipelinedsoc/core/lsu/IEUAdrM[17]} {wallypipelinedsoc/core/lsu/IEUAdrM[18]} {wallypipelinedsoc/core/lsu/IEUAdrM[19]} {wallypipelinedsoc/core/lsu/IEUAdrM[20]} {wallypipelinedsoc/core/lsu/IEUAdrM[21]} {wallypipelinedsoc/core/lsu/IEUAdrM[22]} {wallypipelinedsoc/core/lsu/IEUAdrM[23]} {wallypipelinedsoc/core/lsu/IEUAdrM[24]} {wallypipelinedsoc/core/lsu/IEUAdrM[25]} {wallypipelinedsoc/core/lsu/IEUAdrM[26]} {wallypipelinedsoc/core/lsu/IEUAdrM[27]} {wallypipelinedsoc/core/lsu/IEUAdrM[28]} {wallypipelinedsoc/core/lsu/IEUAdrM[29]} {wallypipelinedsoc/core/lsu/IEUAdrM[30]} {wallypipelinedsoc/core/lsu/IEUAdrM[31]} {wallypipelinedsoc/core/lsu/IEUAdrM[32]} {wallypipelinedsoc/core/lsu/IEUAdrM[33]} {wallypipelinedsoc/core/lsu/IEUAdrM[34]} {wallypipelinedsoc/core/lsu/IEUAdrM[35]} {wallypipelinedsoc/core/lsu/IEUAdrM[36]} {wallypipelinedsoc/core/lsu/IEUAdrM[37]} {wallypipelinedsoc/core/lsu/IEUAdrM[38]} {wallypipelinedsoc/core/lsu/IEUAdrM[39]} {wallypipelinedsoc/core/lsu/IEUAdrM[40]} {wallypipelinedsoc/core/lsu/IEUAdrM[41]} {wallypipelinedsoc/core/lsu/IEUAdrM[42]} {wallypipelinedsoc/core/lsu/IEUAdrM[43]} {wallypipelinedsoc/core/lsu/IEUAdrM[44]} {wallypipelinedsoc/core/lsu/IEUAdrM[45]} {wallypipelinedsoc/core/lsu/IEUAdrM[46]} {wallypipelinedsoc/core/lsu/IEUAdrM[47]} {wallypipelinedsoc/core/lsu/IEUAdrM[48]} {wallypipelinedsoc/core/lsu/IEUAdrM[49]} {wallypipelinedsoc/core/lsu/IEUAdrM[50]} {wallypipelinedsoc/core/lsu/IEUAdrM[51]} {wallypipelinedsoc/core/lsu/IEUAdrM[52]} {wallypipelinedsoc/core/lsu/IEUAdrM[53]} {wallypipelinedsoc/core/lsu/IEUAdrM[54]} {wallypipelinedsoc/core/lsu/IEUAdrM[55]} {wallypipelinedsoc/core/lsu/IEUAdrM[56]} {wallypipelinedsoc/core/lsu/IEUAdrM[57]} {wallypipelinedsoc/core/lsu/IEUAdrM[58]} {wallypipelinedsoc/core/lsu/IEUAdrM[59]} {wallypipelinedsoc/core/lsu/IEUAdrM[60]} {wallypipelinedsoc/core/lsu/IEUAdrM[61]} {wallypipelinedsoc/core/lsu/IEUAdrM[62]} {wallypipelinedsoc/core/lsu/IEUAdrM[63]} ]]
create_debug_port u_ila_0 probe
set_property port_width 8 [get_debug_ports u_ila_0/probe6]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
connect_debug_port u_ila_0/probe6 [get_nets [list {wallypipelinedsoc/core/lsu/ReadDataM[0]} {wallypipelinedsoc/core/lsu/ReadDataM[1]} {wallypipelinedsoc/core/lsu/ReadDataM[2]} {wallypipelinedsoc/core/lsu/ReadDataM[3]} {wallypipelinedsoc/core/lsu/ReadDataM[4]} {wallypipelinedsoc/core/lsu/ReadDataM[5]} {wallypipelinedsoc/core/lsu/ReadDataM[6]} {wallypipelinedsoc/core/lsu/ReadDataM[7]} ]]
create_debug_port u_ila_0 probe
set_property port_width 8 [get_debug_ports u_ila_0/probe7]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
connect_debug_port u_ila_0/probe7 [get_nets [list {wallypipelinedsoc/core/lsu/WriteDataM[0]} {wallypipelinedsoc/core/lsu/WriteDataM[1]} {wallypipelinedsoc/core/lsu/WriteDataM[2]} {wallypipelinedsoc/core/lsu/WriteDataM[3]} {wallypipelinedsoc/core/lsu/WriteDataM[4]} {wallypipelinedsoc/core/lsu/WriteDataM[5]} {wallypipelinedsoc/core/lsu/WriteDataM[6]} {wallypipelinedsoc/core/lsu/WriteDataM[7]} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe8]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
connect_debug_port u_ila_0/probe8 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/MExtInt}]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe9]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
connect_debug_port u_ila_0/probe9 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/SExtInt} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe10]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
connect_debug_port u_ila_0/probe10 [get_nets [list {wallypipelinedsoc/core/priv.priv/pmd/wfiM} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe11]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
connect_debug_port u_ila_0/probe11 [get_nets [list {wallypipelinedsoc/core/priv.priv/pmd/wfiW} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe12]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
connect_debug_port u_ila_0/probe12 [get_nets [list wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/INTR ]]
create_debug_port u_ila_0 probe
set_property port_width 4 [get_debug_ports u_ila_0/probe13]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
connect_debug_port u_ila_0/probe13 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifohead[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifohead[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifohead[2]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifohead[3]}]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe14]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
connect_debug_port u_ila_0/probe14 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txsrfull}]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe15]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
connect_debug_port u_ila_0/probe15 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txhrfull}]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe16]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
connect_debug_port u_ila_0/probe16 [get_nets [list wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/RXRDYb ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe17]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
connect_debug_port u_ila_0/probe17 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifofull}]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe18]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
connect_debug_port u_ila_0/probe18 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifoempty}]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe19]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
connect_debug_port u_ila_0/probe19 [get_nets [list {wallypipelinedsoc/core/priv.priv/pmd/WFITimeoutM} ]]
create_debug_port u_ila_0 probe
set_property port_width 12 [get_debug_ports u_ila_0/probe20]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
connect_debug_port u_ila_0/probe20 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/plic.plic/requests[1]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/requests[2]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/requests[3]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/requests[4]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/requests[5]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/requests[6]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/requests[7]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/requests[8]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/requests[9]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/requests[10]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/requests[11]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/requests[12]}]]
create_debug_port u_ila_0 probe
set_property port_width 4 [get_debug_ports u_ila_0/probe21]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
connect_debug_port u_ila_0/probe21 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/IER[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/IER[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/IER[2]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/IER[3]} ]]
create_debug_port u_ila_0 probe
set_property port_width 12 [get_debug_ports u_ila_0/probe22]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22]
connect_debug_port u_ila_0/probe22 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/plic.plic/intInProgress[1]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intInProgress[2]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intInProgress[3]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intInProgress[4]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intInProgress[5]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intInProgress[6]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intInProgress[7]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intInProgress[8]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intInProgress[9]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intInProgress[10]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intInProgress[11]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intInProgress[12]}]]
create_debug_port u_ila_0 probe
set_property port_width 12 [get_debug_ports u_ila_0/probe23]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23]
connect_debug_port u_ila_0/probe23 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/plic.plic/intPending[1]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intPending[2]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intPending[3]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intPending[4]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intPending[5]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intPending[6]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intPending[7]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intPending[8]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intPending[9]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intPending[10]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intPending[11]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intPending[12]}]]
create_debug_port u_ila_0 probe
set_property port_width 2 [get_debug_ports u_ila_0/probe24]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24]
connect_debug_port u_ila_0/probe24 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txstate[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txstate[1]} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe25]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25]
connect_debug_port u_ila_0/probe25 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxdataready} ]]
create_debug_port u_ila_0 probe
set_property port_width 4 [get_debug_ports u_ila_0/probe26]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26]
connect_debug_port u_ila_0/probe26 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifotail[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifotail[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifotail[2]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifotail[3]}]]
create_debug_port u_ila_0 probe
set_property port_width 2 [get_debug_ports u_ila_0/probe27]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27]
connect_debug_port u_ila_0/probe27 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxstate[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxstate[1]} ]]
create_debug_port u_ila_0 probe
set_property port_width 4 [get_debug_ports u_ila_0/probe28]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28]
connect_debug_port u_ila_0/probe28 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxfifoentries[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxfifoentries[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxfifoentries[2]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxfifoentries[3]} ]]
create_debug_port u_ila_0 probe
set_property port_width 3 [get_debug_ports u_ila_0/probe29]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29]
connect_debug_port u_ila_0/probe29 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/intrID[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/intrID[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/intrID[2]} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe30]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30]
connect_debug_port u_ila_0/probe30 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxfifotriggered} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe31]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31]
connect_debug_port u_ila_0/probe31 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/fifoenabled} ]]
# the debug hub has issues with the clocks from the mmcm so lets give up an connect to the 100Mhz input clock.
#connect_debug_port dbg_hub/clk [get_nets default_100mhz_clk]
connect_debug_port dbg_hub/clk [get_nets CPUCLK]

32
fpga/generator/debug/plic.tsm Normal file
View file

@ -0,0 +1,32 @@
##################################################
#
# For info on creating trigger state machines:
# 1) In the main Vivado menu bar, select
# Window > Language Templates
# 2) In the Templates window, select
# Debug > Trigger State Machine
# 3) Refer to the entry 'Info' for an overview
# of the trigger state machine language.
#
# More information can be found in this document:
#
# Vivado Design Suite User Guide: Programming
# and Debugging (UG908)
#
##################################################
state state_reset:
if(wallypipelinedsoc/uncoregen.uncore/plic.plic/intInProgress == 12'h200) then
goto state_1;
else
goto state_reset;
endif
state state_1:
if(wallypipelinedsoc/uncoregen.uncore/plic.plic/intInProgress == 12'h000) then
goto state_trigger;
else
goto state_1;
endif
state state_trigger:
trigger;

2
fpga/generator/wally.tcl
View file

@ -98,7 +98,7 @@ write_verilog -force -mode funcsim sim/syn-funcsim.v
if {$board=="ArtyA7"} {
#source ../constraints/small-debug.xdc
#source ../constraints/small-debug-rvvi.xdc
#source ../constraints/small-debug-spi.xdc
source ../constraints/small-debug-wfi.xdc
} else {
#source ../constraints/vcu-small-debug.xdc
#source ../constraints/small-debug.xdc

669
fpga/src/axi_sdc_controller.v
View file

@ -1,669 +0,0 @@
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2013-2022 Authors ////
//// ////
//// Based on original work by ////
//// Adam Edvardsson (adam.edvardsson@orsoc.se) ////
//// ////
//// Copyright (C) 2009 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from https://www.gnu.org/licenses/ ////
//// ////
//////////////////////////////////////////////////////////////////////
module sdc_controller #(
parameter dma_addr_bits = 32,
parameter fifo_addr_bits = 7,
parameter sdio_card_detect_level = 1,
parameter voltage_controll_reg = 3300,
parameter capabilies_reg = 16'b0000_0000_0000_0011
) (
input wire async_resetn,
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clock CLK" *)
(* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF M_AXI:S_AXI_LITE, FREQ_HZ 100000000" *)
input wire clock,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR" *)
(* X_INTERFACE_PARAMETER = "CLK_DOMAIN clock, ID_WIDTH 0, PROTOCOL AXI4LITE, DATA_WIDTH 32" *)
input wire [15:0] s_axi_awaddr,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID" *)
input wire s_axi_awvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY" *)
output wire s_axi_awready,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA" *)
input wire [31:0] s_axi_wdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID" *)
input wire s_axi_wvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY" *)
output wire s_axi_wready,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP" *)
output reg [1:0] s_axi_bresp,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID" *)
output reg s_axi_bvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY" *)
input wire s_axi_bready,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR" *)
input wire [15:0] s_axi_araddr,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID" *)
input wire s_axi_arvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY" *)
output wire s_axi_arready,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA" *)
output reg [31:0] s_axi_rdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP" *)
output reg [1:0] s_axi_rresp,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID" *)
output reg s_axi_rvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY" *)
input wire s_axi_rready,
(* X_INTERFACE_PARAMETER = "CLK_DOMAIN clock, ID_WIDTH 0, PROTOCOL AXI4, DATA_WIDTH 32" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output reg [dma_addr_bits-1:0] m_axi_awaddr,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
output reg [7:0] m_axi_awlen,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output reg m_axi_awvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31:0] m_axi_wdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
output reg m_axi_wlast,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output reg m_axi_wvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1:0] m_axi_bresp,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output reg [dma_addr_bits-1:0] m_axi_araddr,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
output reg [7:0] m_axi_arlen,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output reg m_axi_arvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31:0] m_axi_rdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
input wire m_axi_rlast,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1:0] m_axi_rresp,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready,
// SD BUS
//inout wire sdio_cmd,
//inout wire [3:0] sdio_dat,
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 sdio_clk CLK" *)
(* X_INTERFACE_PARAMETER = "FREQ_HZ 50000000" *)
output reg sdio_clk,
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 sdio_reset RST" *)
(* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_HIGH" *)
output reg sdio_reset,
input wire sdio_cd,
output reg sd_dat_reg_t,
output reg [3:0] sd_dat_reg_o,
input wire [3:0] sd_dat_i,
output reg sd_cmd_reg_t,
output reg sd_cmd_reg_o,
input wire sd_cmd_i,
// Interrupts
output wire interrupt
);
`include "sd_defines.h"
wire reset;
wire go_idle;
reg cmd_start;
wire [1:0] cmd_setting;
wire cmd_start_tx;
wire [39:0] cmd;
wire [119:0] cmd_response;
wire cmd_crc_ok;
wire cmd_index_ok;
wire cmd_finish;
wire d_write;
wire d_read;
wire [31:0] data_in_rx_fifo;
wire en_tx_fifo;
wire en_rx_fifo;
wire sd_data_busy;
(* mark_debug = "true" *) wire data_busy;
wire data_crc_ok;
wire tx_fifo_re;
wire rx_fifo_we;
reg data_start_rx;
reg data_start_tx;
reg data_prepare_tx;
reg cmd_int_rst;
reg data_int_rst;
reg ctrl_rst;
// AXI accessible registers
(* mark_debug = "true" *) reg [31:0] argument_reg;
(* mark_debug = "true" *) reg [`CMD_REG_SIZE-1:0] command_reg;
(* mark_debug = "true" *) reg [`CMD_TIMEOUT_W-1:0] cmd_timeout_reg;
(* mark_debug = "true" *) reg [`DATA_TIMEOUT_W-1:0] data_timeout_reg;
(* mark_debug = "true" *) reg [0:0] software_reset_reg;
(* mark_debug = "true" *) wire [31:0] response_0_reg;
(* mark_debug = "true" *) wire [31:0] response_1_reg;
(* mark_debug = "true" *) wire [31:0] response_2_reg;
(* mark_debug = "true" *) wire [31:0] response_3_reg;
(* mark_debug = "true" *) reg [`BLKSIZE_W-1:0] block_size_reg;
(* mark_debug = "true" *) reg [1:0] controller_setting_reg;
(* mark_debug = "true" *) wire [`INT_CMD_SIZE-1:0] cmd_int_status_reg;
(* mark_debug = "true" *) wire [`INT_DATA_SIZE-1:0] data_int_status_reg;
(* mark_debug = "true" *) wire [`INT_DATA_SIZE-1:0] data_int_status;
(* mark_debug = "true" *) reg [`INT_CMD_SIZE-1:0] cmd_int_enable_reg;
(* mark_debug = "true" *) reg [`INT_DATA_SIZE-1:0] data_int_enable_reg;
(* mark_debug = "true" *) reg [`BLKCNT_W-1:0] block_count_reg;
(* mark_debug = "true" *) reg [dma_addr_bits-1:0] dma_addr_reg;
(* mark_debug = "true" *) reg [7:0] clock_divider_reg = 124; // 400KHz
// ------ Clocks and resets
(* ASYNC_REG="true" *)
reg [2:0] reset_sync;
assign reset = reset_sync[2];
always @(posedge clock)
reset_sync <= {reset_sync[1:0], !async_resetn};
reg [7:0] clock_cnt;
(* mark_debug = "true" *) reg clock_state;
(* mark_debug = "true" *) reg clock_posedge;
reg clock_data_in;
wire fifo_almost_full;
wire fifo_almost_empty;
always @(posedge clock) begin
if (reset) begin
clock_posedge <= 0;
clock_data_in <= 0;
clock_state <= 0;
clock_cnt <= 0;
end else if (clock_cnt < clock_divider_reg) begin
clock_posedge <= 0;
clock_data_in <= 0;
clock_cnt <= clock_cnt + 1;
end else if (clock_cnt < 124 && data_busy && en_rx_fifo && fifo_almost_full) begin
// Prevent Rx FIFO overflow
clock_posedge <= 0;
clock_data_in <= 0;
clock_cnt <= clock_cnt + 1;
end else if (clock_cnt < 124 && data_busy && en_tx_fifo && fifo_almost_empty) begin
// Prevent Tx FIFO underflow
clock_posedge <= 0;
clock_data_in <= 0;
clock_cnt <= clock_cnt + 1;
end else begin
clock_state <= !clock_state;
clock_posedge <= !clock_state;
if (clock_divider_reg == 0)
clock_data_in <= !clock_state;
else
clock_data_in <= clock_state;
clock_cnt <= 0;
end
sdio_clk <= sdio_reset || clock_state;
if (reset) sdio_reset <= 0;
else if (clock_posedge) sdio_reset <= controller_setting_reg[1];
end
// ------ SD IO Buffers
// wire sd_cmd_i;
wire sd_cmd_o;
wire sd_cmd_oe;
// reg sd_cmd_reg_o;
// reg sd_cmd_reg_t;
// wire [3:0] sd_dat_i;
wire [3:0] sd_dat_o;
wire sd_dat_oe;
// reg [3:0] sd_dat_reg_o;
// reg sd_dat_reg_t;
// IOBUF IOBUF_cmd (.O(sd_cmd_i), .IO(sdio_cmd), .I(sd_cmd_reg_o), .T(sd_cmd_reg_t));
// IOBUF IOBUF_dat0 (.O(sd_dat_i[0]), .IO(sdio_dat[0]), .I(sd_dat_reg_o[0]), .T(sd_dat_reg_t));
// IOBUF IOBUF_dat1 (.O(sd_dat_i[1]), .IO(sdio_dat[1]), .I(sd_dat_reg_o[1]), .T(sd_dat_reg_t));
// IOBUF IOBUF_dat2 (.O(sd_dat_i[2]), .IO(sdio_dat[2]), .I(sd_dat_reg_o[2]), .T(sd_dat_reg_t));
// IOBUF IOBUF_dat3 (.O(sd_dat_i[3]), .IO(sdio_dat[3]), .I(sd_dat_reg_o[3]), .T(sd_dat_reg_t));
always @(negedge sdio_clk) begin
// Output data delayed by 1/2 clock cycle (5ns) to ensure
// required hold time: default speed - min 5ns, high speed - min 2ns (actual 5ns)
if (sdio_reset) begin
sd_cmd_reg_o <= 0;
sd_dat_reg_o <= 0;
sd_cmd_reg_t <= 0;
sd_dat_reg_t <= 0;
end else begin
sd_cmd_reg_o <= sd_cmd_o;
sd_dat_reg_o <= sd_dat_o;
sd_cmd_reg_t <= !sd_cmd_oe;
sd_dat_reg_t <= !(sd_dat_oe || (cmd_start_tx && (command_reg == 0)));
end
end
// ------ SD card detect
reg [25:0] sd_detect_cnt;
wire sd_insert_int = sd_detect_cnt[25];
wire sd_remove_int = !sd_detect_cnt[25];
reg sd_insert_ie;
reg sd_remove_ie;
always @(posedge clock) begin
if (sdio_cd != sdio_card_detect_level) begin
sd_detect_cnt <= 0;
end else if (!sd_insert_int) begin
sd_detect_cnt <= sd_detect_cnt + 1;
end
end
// ------ AXI Slave Interface
reg [15:0] read_addr;
reg [15:0] write_addr;
reg [31:0] write_data;
reg rd_req;
reg [1:0] wr_req;
assign s_axi_arready = !rd_req && !s_axi_rvalid;
assign s_axi_awready = !wr_req[0] && !s_axi_bvalid;
assign s_axi_wready = !wr_req[1] && !s_axi_bvalid;
always @(posedge clock) begin
if (reset) begin
s_axi_rdata <= 0;
s_axi_rresp <= 0;
s_axi_rvalid <= 0;
s_axi_bresp <= 0;
s_axi_bvalid <= 0;
rd_req <= 0;
wr_req <= 0;
read_addr <= 0;
write_addr <= 0;
write_data <= 0;
cmd_start <= 0;
data_int_rst <= 0;
cmd_int_rst <= 0;
ctrl_rst <= 0;
argument_reg <= 0;
command_reg <= 0;
cmd_timeout_reg <= 0;
data_timeout_reg <= 0;
block_size_reg <= `RESET_BLOCK_SIZE;
controller_setting_reg <= 0;
cmd_int_enable_reg <= 0;
data_int_enable_reg <= 0;
software_reset_reg <= 0;
clock_divider_reg <= `RESET_CLOCK_DIV;
block_count_reg <= 0;
sd_insert_ie <= 0;
sd_remove_ie <= 0;
dma_addr_reg <= 0;
end else begin
if (clock_posedge) begin
cmd_start <= 0;
data_int_rst <= 0;
cmd_int_rst <= 0;
ctrl_rst <= software_reset_reg[0];
end
if (s_axi_arready && s_axi_arvalid) begin
read_addr <= s_axi_araddr;
rd_req <= 1;
end
if (s_axi_rvalid && s_axi_rready) begin
s_axi_rvalid <= 0;
end else if (!s_axi_rvalid && rd_req) begin
s_axi_rdata <= 0;
if (read_addr[15:8] == 0) begin
case (read_addr[7:0])
`argument : s_axi_rdata <= argument_reg;
`command : s_axi_rdata <= command_reg;
`resp0 : s_axi_rdata <= response_0_reg;
`resp1 : s_axi_rdata <= response_1_reg;
`resp2 : s_axi_rdata <= response_2_reg;
`resp3 : s_axi_rdata <= response_3_reg;
`controller : s_axi_rdata <= controller_setting_reg;
`blksize : s_axi_rdata <= block_size_reg;
`voltage : s_axi_rdata <= voltage_controll_reg;
`capa : s_axi_rdata <= capabilies_reg | (dma_addr_bits << 8);
`clock_d : s_axi_rdata <= clock_divider_reg;
`reset : s_axi_rdata <= { cmd_start, data_int_rst, cmd_int_rst, ctrl_rst };
`cmd_timeout : s_axi_rdata <= cmd_timeout_reg;
`data_timeout : s_axi_rdata <= data_timeout_reg;
`cmd_isr : s_axi_rdata <= cmd_int_status_reg;
`cmd_iser : s_axi_rdata <= cmd_int_enable_reg;
`data_isr : s_axi_rdata <= data_int_status_reg;
`data_iser : s_axi_rdata <= data_int_enable_reg;
`blkcnt : s_axi_rdata <= block_count_reg;
`card_detect : s_axi_rdata <= { sd_remove_int, sd_remove_ie, sd_insert_int, sd_insert_ie };
`dst_src_addr : s_axi_rdata <= dma_addr_reg[31:0];
`dst_src_addr_high : if (dma_addr_bits > 32) s_axi_rdata <= dma_addr_reg[dma_addr_bits-1:32];
endcase
end
s_axi_rresp <= 0;
s_axi_rvalid <= 1;
rd_req <= 0;
end
if (s_axi_awready && s_axi_awvalid) begin
write_addr <= s_axi_awaddr;
wr_req[0] <= 1;
end
if (s_axi_wready && s_axi_wvalid) begin
write_data <= s_axi_wdata;
wr_req[1] <= 1;
end
if (s_axi_bvalid && s_axi_bready) begin
s_axi_bvalid <= 0;
end else if (!s_axi_bvalid && wr_req == 2'b11) begin
if (write_addr[15:8] == 0) begin
case (write_addr[7:0])
`argument : begin argument_reg <= write_data; cmd_start <= 1; end
`command : command_reg <= write_data;
`reset : software_reset_reg <= write_data;
`cmd_timeout : cmd_timeout_reg <= write_data;
`data_timeout : data_timeout_reg <= write_data;
`blksize : block_size_reg <= write_data;
`controller : controller_setting_reg <= write_data;
`cmd_isr : cmd_int_rst <= 1;
`cmd_iser : cmd_int_enable_reg <= write_data;
`clock_d : clock_divider_reg <= write_data;
`data_isr : data_int_rst <= 1;
`data_iser : data_int_enable_reg <= write_data;
`blkcnt : block_count_reg <= write_data;
`card_detect : begin sd_remove_ie <= write_data[2]; sd_insert_ie <= write_data[0]; end
`dst_src_addr : dma_addr_reg[31:0] <= write_data;
`dst_src_addr_high : if (dma_addr_bits > 32) dma_addr_reg[dma_addr_bits-1:32] <= write_data;
endcase
end
s_axi_bresp <= 0;
s_axi_bvalid <= 1;
wr_req <= 0;
end
end
end
// ------ Data FIFO
reg [31:0] fifo_mem [(1<<fifo_addr_bits)-1:0];
reg [fifo_addr_bits-1:0] fifo_inp_pos;
reg [fifo_addr_bits-1:0] fifo_out_pos;
wire [fifo_addr_bits-1:0] fifo_inp_nxt = fifo_inp_pos + 1;
wire [fifo_addr_bits-1:0] fifo_out_nxt = fifo_out_pos + 1;
wire [fifo_addr_bits-1:0] fifo_data_len = fifo_inp_pos - fifo_out_pos;
wire [fifo_addr_bits-1:0] fifo_free_len = fifo_out_pos - fifo_inp_nxt;
wire fifo_full = fifo_inp_nxt == fifo_out_pos;
wire fifo_empty = fifo_inp_pos == fifo_out_pos;
wire fifo_ready = fifo_data_len >= (1 << fifo_addr_bits) / 2;
wire [31:0] fifo_din = en_rx_fifo ? data_in_rx_fifo : m_bus_dat_i;
wire fifo_we = en_rx_fifo ? rx_fifo_we && clock_posedge : m_axi_rready && m_axi_rvalid;
wire fifo_re = en_rx_fifo ? m_axi_wready && m_axi_wvalid : tx_fifo_re && clock_posedge;
reg [31:0] fifo_dout;
assign fifo_almost_full = fifo_data_len > (1 << fifo_addr_bits) * 3 / 4;
assign fifo_almost_empty = fifo_free_len > (1 << fifo_addr_bits) * 3 / 4;
wire tx_stb = en_tx_fifo && fifo_free_len >= (1 << fifo_addr_bits) / 3;
wire rx_stb = en_rx_fifo && m_axi_bresp_cnt != 3'b111 && (fifo_data_len >= (1 << fifo_addr_bits) / 3 || (!fifo_empty && !data_busy));
always @(posedge clock)
if (reset || ctrl_rst || !(en_rx_fifo || en_tx_fifo)) begin
fifo_inp_pos <= 0;
fifo_out_pos <= 0;
end else begin
if (fifo_we && !fifo_full) begin
fifo_mem[fifo_inp_pos] <= fifo_din;
fifo_inp_pos <= fifo_inp_nxt;
if (fifo_empty) fifo_dout <= fifo_din;
end
if (fifo_re && !fifo_empty) begin
if (fifo_we && !fifo_full && fifo_out_nxt == fifo_inp_pos) fifo_dout <= fifo_din;
else fifo_dout <= fifo_mem[fifo_out_nxt];
fifo_out_pos <= fifo_out_nxt;
end
end
// ------ AXI Master Interface
// AXI transaction (DDR access) is over 80 clock cycles
// Must use burst to achive required throughput
reg m_axi_cyc;
wire m_axi_write = en_rx_fifo;
reg [7:0] m_axi_wcnt;
reg [dma_addr_bits-1:2] m_bus_adr_o;
wire [31:0] m_bus_dat_i;
reg [2:0] m_axi_bresp_cnt;
reg m_bus_error;
assign m_axi_bready = m_axi_bresp_cnt != 0;
assign m_axi_rready = m_axi_cyc & !m_axi_write;
assign m_bus_dat_i = {m_axi_rdata[7:0],m_axi_rdata[15:8],m_axi_rdata[23:16],m_axi_rdata[31:24]};
assign m_axi_wdata = {fifo_dout[7:0],fifo_dout[15:8],fifo_dout[23:16],fifo_dout[31:24]};
// AXI burst cannot cross a 4KB boundary
wire [fifo_addr_bits-1:0] tx_burst_len;
wire [fifo_addr_bits-1:0] rx_burst_len;
assign tx_burst_len = m_bus_adr_o[11:2] + fifo_free_len >= m_bus_adr_o[11:2] ? fifo_free_len - 1 : ~m_bus_adr_o[fifo_addr_bits+1:2];
assign rx_burst_len = m_bus_adr_o[11:2] + fifo_data_len >= m_bus_adr_o[11:2] ? fifo_data_len - 1 : ~m_bus_adr_o[fifo_addr_bits+1:2];
assign data_int_status_reg = { data_int_status[`INT_DATA_SIZE-1:1],
!en_rx_fifo && !en_tx_fifo && !m_axi_cyc && m_axi_bresp_cnt == 0 && data_int_status[0] };
always @(posedge clock) begin
if (reset | ctrl_rst) begin
m_axi_arvalid <= 0;
m_axi_awvalid <= 0;
m_axi_wvalid <= 0;
m_axi_cyc <= 0;
end else if (m_axi_cyc) begin
if (m_axi_awvalid && m_axi_awready) begin
m_axi_awvalid <= 0;
end
if (m_axi_arvalid && m_axi_arready) begin
m_axi_arvalid <= 0;
end
if (m_axi_wvalid && m_axi_wready) begin
if (m_axi_wlast) begin
m_axi_wvalid <= 0;
m_axi_cyc <= 0;
end else begin
m_axi_wlast <= m_axi_wcnt + 1 == m_axi_awlen;
m_axi_wcnt <= m_axi_wcnt + 1;
end
end
if (m_axi_rvalid && m_axi_rready && m_axi_rlast) begin
m_axi_cyc <= 0;
end
end else if (tx_stb || rx_stb) begin
m_axi_cyc <= 1;
m_axi_wcnt <= 0;
if (m_axi_write) begin
m_axi_awaddr <= { m_bus_adr_o, 2'b00 };
m_axi_awlen <= rx_burst_len < 8'hff ? rx_burst_len : 8'hff;
m_axi_wlast <= rx_burst_len == 0;
m_axi_awvalid <= 1;
m_axi_wvalid <= 1;
end else begin
m_axi_araddr <= { m_bus_adr_o, 2'b00 };
m_axi_arlen <= tx_burst_len < 8'hff ? tx_burst_len : 8'hff;
m_axi_arvalid <= 1;
end
end
if (reset | ctrl_rst) begin
m_bus_adr_o <= 0;
end else if ((m_axi_wready && m_axi_wvalid) || (m_axi_rready && m_axi_rvalid)) begin
m_bus_adr_o <= m_bus_adr_o + 1;
end else if (!m_axi_cyc && !en_rx_fifo && !en_tx_fifo) begin
m_bus_adr_o <= dma_addr_reg[dma_addr_bits-1:2];
end
if (reset | ctrl_rst) begin
m_axi_bresp_cnt <= 0;
end else if ((m_axi_awvalid && m_axi_awready) && !(m_axi_bvalid && m_axi_bready)) begin
m_axi_bresp_cnt <= m_axi_bresp_cnt + 1;
end else if (!(m_axi_awvalid && m_axi_awready) && (m_axi_bvalid && m_axi_bready)) begin
m_axi_bresp_cnt <= m_axi_bresp_cnt - 1;
end
if (reset | ctrl_rst | cmd_start) begin
m_bus_error <= 0;
end else if (m_axi_bvalid && m_axi_bready && m_axi_bresp) begin
m_bus_error <= 1;
end else if (m_axi_rvalid && m_axi_rready && m_axi_rresp) begin
m_bus_error <= 1;
end
if (reset | ctrl_rst) begin
data_start_tx <= 0;
data_start_rx <= 0;
data_prepare_tx <= 0;
end else if (clock_posedge) begin
data_start_tx <= 0;
data_start_rx <= 0;
if (cmd_start) begin
data_prepare_tx <= 0;
if (command_reg[`CMD_WITH_DATA] == 2'b01) data_start_rx <= 1;
else if (command_reg[`CMD_WITH_DATA] != 2'b00) data_prepare_tx <= 1;
end else if (data_prepare_tx) begin
if (cmd_int_status_reg[`INT_CMD_CC]) begin
data_prepare_tx <= 0;
data_start_tx <= 1;
end else if (cmd_int_status_reg[`INT_CMD_EI]) begin
data_prepare_tx <= 0;
end
end
end
end
// ------ SD Card Interface
sd_cmd_master sd_cmd_master0(
.clock (clock),
.clock_posedge (clock_posedge),
.reset (reset | ctrl_rst),
.start (cmd_start),
.int_status_rst (cmd_int_rst),
.setting (cmd_setting),
.start_xfr (cmd_start_tx),
.go_idle (go_idle),
.cmd (cmd),
.response (cmd_response),
.crc_error (!cmd_crc_ok),
.index_ok (cmd_index_ok),
.busy (sd_data_busy),
.finish (cmd_finish),
.argument (argument_reg),
.command (command_reg),
.timeout (cmd_timeout_reg),
.int_status (cmd_int_status_reg),
.response_0 (response_0_reg),
.response_1 (response_1_reg),
.response_2 (response_2_reg),
.response_3 (response_3_reg)
);
sd_cmd_serial_host cmd_serial_host0(
.clock (clock),
.clock_posedge (clock_posedge),
.clock_data_in (clock_data_in),
.reset (reset | ctrl_rst | go_idle),
.setting (cmd_setting),
.cmd (cmd),
.start (cmd_start_tx),
.finish (cmd_finish),
.response (cmd_response),
.crc_ok (cmd_crc_ok),
.index_ok (cmd_index_ok),
.cmd_i (sd_cmd_i),
.cmd_o (sd_cmd_o),
.cmd_oe (sd_cmd_oe)
);
sd_data_master sd_data_master0(
.clock (clock),
.clock_posedge (clock_posedge),
.reset (reset | ctrl_rst),
.start_tx (data_start_tx),
.start_rx (data_start_rx),
.timeout (data_timeout_reg),
.d_write (d_write),
.d_read (d_read),
.en_tx_fifo (en_tx_fifo),
.en_rx_fifo (en_rx_fifo),
.fifo_empty (fifo_empty),
.fifo_ready (fifo_ready),
.fifo_full (fifo_full),
.bus_cycle (m_axi_cyc || m_axi_bresp_cnt != 0),
.xfr_complete (!data_busy),
.crc_error (!data_crc_ok),
.bus_error (m_bus_error),
.int_status (data_int_status),
.int_status_rst (data_int_rst)
);
sd_data_serial_host sd_data_serial_host0(
.clock (clock),
.clock_posedge (clock_posedge),
.clock_data_in (clock_data_in),
.reset (reset | ctrl_rst),
.data_in (fifo_dout),
.rd (tx_fifo_re),
.data_out (data_in_rx_fifo),
.we (rx_fifo_we),
.dat_oe (sd_dat_oe),
.dat_o (sd_dat_o),
.dat_i (sd_dat_i),
.blksize (block_size_reg),
.bus_4bit (controller_setting_reg[0]),
.blkcnt (block_count_reg),
.start ({d_read, d_write}),
.byte_alignment (dma_addr_reg[1:0]),
.sd_data_busy (sd_data_busy),
.busy (data_busy),
.crc_ok (data_crc_ok)
);
assign interrupt =
|(cmd_int_status_reg & cmd_int_enable_reg) ||
|(data_int_status_reg & data_int_enable_reg) ||
(sd_insert_int & sd_insert_ie) ||
(sd_remove_int & sd_remove_ie);
endmodule

6
fpga/src/fpgaTop.sv
View file

@ -182,7 +182,6 @@ module fpgaTop
logic [511 : 0] dbg_bus;
logic CLK208;
logic SDCCLKInternal;
assign GPIOIN = {25'b0, SDCCD, SDCWP, 2'b0, GPI};
assign GPO = GPIOOUT[4:0];
@ -216,11 +215,8 @@ module fpgaTop
.HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
.HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0),
.GPIOIN, .GPIOOUT, .GPIOEN,
.UARTSin, .UARTSout, .SDCIn, .SDCCmd, .SDCCS(SDCCSin), .SDCCLK(SDCCLKInternal), .ExternalStall(RVVIStall));
.UARTSin, .UARTSout, .SDCIn, .SDCCmd, .SDCCS(SDCCSin), .SDCCLK, .ExternalStall(RVVIStall));
// *** these are different for different fpga ugh.
ODDRE1 sdcclkoddr(.Q(SDCCLK), .C(SDCCLKInternal), .D1('0),
.D2(1'b1), .SR('0));
// ahb lite to axi bridge
ahbaxibridge ahbaxibridge

2
fpga/zsbl/spi.c
View file

@ -31,7 +31,7 @@
uint8_t spi_txrx(uint8_t byte) {
spi_sendbyte(byte);
waittx();
waitrx();
return spi_readbyte();
}

2
fpga/zsbl/spi.h
View file

@ -106,7 +106,7 @@ static inline void waittx() {
}
static inline void waitrx() {
while(read_reg(SPI_IP) & 2) {}
while(!(read_reg(SPI_IP) & 2)) {}
}
static inline uint8_t spi_readbyte() {

2
linux/devicetree/wally-vcu108.dts
View file

@ -102,7 +102,7 @@
mmc@0 {
compatible = "mmc-spi-slot";
reg = <0>;
spi-max-frequency = <1000000>;
spi-max-frequency = <400000>;
voltage-ranges = <3300 3300>;
disable-wp;
// gpios = <&gpio0 6 1>;

4
sim/Makefile
View file

@ -29,8 +29,8 @@ deriv:
.PHONY: QuestaCodeCoverage collect_functcov combine_functcov remove_functcov_artifacts riscvdv riscvdv_functcov
QuestaCodeCoverage: questa/ucdb/rv64gc_arch64i.ucdb
vcover merge -out questa/ucdb/cov.ucdb questa/ucdb/rv64gc_arch64i.ucdb questa/ucdb/rv64gc*.ucdb -logfile questa/cov/log
QuestaCodeCoverage:
vcover merge -out questa/ucdb/cov.ucdb questa/ucdb/rv64gc*.ucdb -logfile questa/cov/log
# vcover merge -out questa/ucdb/cov.ucdb questa/ucdb/rv64gc_arch64i.ucdb questa/ucdb/rv64gc*.ucdb questa/ucdb/buildroot_buildroot.ucdb riscv.ucdb -logfile questa/cov/log
vcover report -details questa/ucdb/cov.ucdb > questa/cov/rv64gc_coverage_details.rpt
vcover report questa/ucdb/cov.ucdb -details -instance=/core/ebu. > questa/cov/rv64gc_coverage_ebu.rpt

107
sim/questa/wally.do
View file

@ -3,12 +3,12 @@
#
# Modification by Oklahoma State University & Harvey Mudd College
# Use with Testbench
# James Stine, 2008; David Harris 2021
# James Stine, 2008; David Harris 2021; Jordan Carlin 2024
# Go Cowboys!!!!!!
#
# Takes 1:10 to run RV64IC tests using gui
# Usage: do wally.do <config> <testcases> <testbench> [--ccov] [--fcov] [+acc] [--args "any number of +value"] [--params "any number of VAR=VAL parameter overrides"]
# Usage: do wally.do <config> <testcases> <testbench> [--ccov] [--fcov] [--gui] [--args "any number of +value"] [--params "any number of VAR=VAL parameter overrides"] [--define "any number of +define+VAR=VAL"]
# Example: do wally.do rv64gc arch64i testbench
# Use this wally.do file to run this example.
@ -40,7 +40,6 @@ set TESTSUITE ${2}
set TESTBENCH ${3}
set WKDIR wkdir/${CFG}_${TESTSUITE}
set WALLY $::env(WALLY)
set IMPERAS_HOME $::env(IMPERAS_HOME)
set CONFIG ${WALLY}/config
set SRC ${WALLY}/src
set TB ${WALLY}/testbench
@ -55,6 +54,7 @@ vlib ${WKDIR}
set PlusArgs ""
set ParamArgs ""
set ExpandedParamArgs {}
set DefineArgs ""
set ccov 0
set CoverageVoptArg ""
@ -62,11 +62,14 @@ set CoverageVsimArg ""
set FunctCoverage 0
set FCvlog ""
set FCvopt ""
set FCdefineCOVER_EXTS {}
set breker 0
set brekervlog ""
set brekervopt ""
set lockstep 0
set lockstepvlog ""
set SVLib ""
set GUI 0
@ -74,24 +77,27 @@ set accFlag ""
# Need to be able to pass arguments to vopt. Unforunately argv does not work because
# it takes on different values if vsim and the do file are called from the command line or
# if the do file is called from questa sim directly. This chunk of code uses the $4 through $n
# variables and compacts into a single list for passing to vopt.
set from 4
set step 1
# if the do file is called from questa sim directly. This chunk of code uses the $n variables
# and compacts them into a single list for passing to vopt. Shift is used to move the arguments
# through the list.
set lst {}
echo "number of args = $argc"
for {set i 0} true {incr i} {
set x [expr {$i*$step + $from}]
if {$x > $argc} break
set arg [expr "$$x"]
lappend lst $arg
# Shift off the first three arguments (config, testcases, testbench)
shift
shift
shift
# Copy the remaining arguments into a list
while {$argc > 0} {
lappend lst [expr "\$1"]
shift
}
echo "number of args = $argc"
echo "lst = $lst"
# if +acc found set flag and remove from list
if {[lcheck lst "+acc"]} {
if {[lcheck lst "--gui"]} {
set GUI 1
set accFlag "+acc"
}
@ -103,49 +109,35 @@ if {[lcheck lst "--ccov"]} {
set CoverageVsimArg "-coverage"
}
# if --fcovimp found set flag and remove from list
if {[lcheck lst "--fcovimp"]} {
set FunctCoverage 1
set FCvlog "+define+INCLUDE_TRACE2COV \
+define+IDV_INCLUDE_TRACE2COV \
+define+COVER_BASE_RV64I \
+define+COVER_LEVEL_DV_PR_EXT \
+incdir+${IMPERAS_HOME}/ImpProprietary/source/host/riscvISACOV/source"
set FCvopt "+TRACE2COV_ENABLE=1 +IDV_TRACE2COV=1"
# Uncomment various cover statements below to control which extensions get functional coverage
lappend FCdefineCOVER_EXTS "+define+COVER_RV64I"
#lappend FCdefineCOVER_EXTS "+define+COVER_RV64M"
#lappend FCdefineCOVER_EXTS "+define+COVER_RV64A"
#lappend FCdefineCOVER_EXTS "+define+COVER_RV64F"
#lappend FCdefineCOVER_EXTS "+define+COVER_RV64D"
#lappend FCdefineCOVER_EXTS "+define+COVER_RV64ZICSR"
#lappend FCdefineCOVER_EXTS "+define+COVER_RV64C"
}
# if --fcov found set flag and remove from list
if {[lcheck lst "--fcov"]} {
set FunctCoverage 1
# COVER_BASE_RV32I is just needed to keep riscvISACOV happy, but no longer affects tests
set FCvlog "+define+INCLUDE_TRACE2COV \
+define+IDV_INCLUDE_TRACE2COV \
+define+COVER_BASE_RV32I \
+incdir+$env(WALLY)/addins/riscvISACOV/source \
"
set FCvopt "+TRACE2COV_ENABLE=1 +IDV_TRACE2COV=1"
set FCvlog "+incdir+${FCRVVI}/unpriv \
+incdir+${FCRVVI}/priv +incdir+${FCRVVI}/rv64_priv +incdir+${FCRVVI}/rv32_priv \
+incdir+${FCRVVI}/common +incdir+${FCRVVI} \
+incdir+$env(WALLY)/addins/cvw-arch-verif/riscvISACOV/source"
}
# if --lockstep or --fcov found set flag and remove from list
if {[lcheck lst "--lockstep"] || $FunctCoverage == 1} {
set IMPERAS_HOME $::env(IMPERAS_HOME)
set lockstep 1
set lockstepvlog "+define+USE_IMPERAS_DV \
+incdir+${IMPERAS_HOME}/ImpPublic/include/host \
set lockstepvlog "+incdir+${IMPERAS_HOME}/ImpPublic/include/host \
+incdir+${IMPERAS_HOME}/ImpProprietary/include/host \
${IMPERAS_HOME}/ImpPublic/source/host/rvvi/*.sv \
${IMPERAS_HOME}/ImpProprietary/source/host/idv/*.sv"
set SVLib "-sv_lib ${IMPERAS_HOME}/lib/Linux64/ImperasLib/imperas.com/verification/riscv/1.0/model"
set SVLib " -sv_lib ${IMPERAS_HOME}/lib/Linux64/ImperasLib/imperas.com/verification/riscv/1.0/model "
}
# if --breker found set flag and remove from list
# Requires a license for the breker tool. See tests/breker/README.md for details
if {[lcheck lst "--breker"]} {
set breker 1
set BREKER_HOME $::env(BREKER_HOME)
set brekervlog "+incdir+${WALLY}/testbench/trek_files \
${WALLY}/testbench/trek_files/uvm_output/trek_uvm_pkg.sv"
set brekervopt "${WKDIR}.trek_uvm"
append SVLib " -sv_lib ${BREKER_HOME}/linux64/lib/libtrek "
}
# Set PlusArgs passed using the --args flag
@ -166,30 +158,39 @@ if {$ParamArgsIndex >= 0} {
set lst [lreplace $lst $ParamArgsIndex [expr {$ParamArgsIndex + 1}]]
}
# Set +define macros passed using the --define flag
set DefineArgsIndex [lsearch -exact $lst "--define"]
if {$DefineArgsIndex >= 0} {
set DefineArgs [lindex $lst [expr {$DefineArgsIndex + 1}]]
set lst [lreplace $lst $DefineArgsIndex [expr {$DefineArgsIndex + 1}]]
}
# Debug print statements
if {$DEBUG > 0} {
echo "GUI = $GUI"
echo "ccov = $ccov"
echo "lockstep = $lockstep"
echo "FunctCoverage = $FunctCoverage"
echo "Breker = $breker"
echo "remaining list = $lst"
echo "Extra +args = $PlusArgs"
echo "Extra -args = $ExpandedParamArgs"
echo "Extra params = $ExpandedParamArgs"
echo "Extra defines = $DefineArgs"
}
# compile source files
# suppress spurious warnngs about
# "Extra checking for conflicts with always_comb done at vopt time"
# because vsim will run vopt
set INC_DIRS "+incdir+${CONFIG}/${CFG} +incdir+${CONFIG}/deriv/${CFG} +incdir+${CONFIG}/shared +incdir+${FCRVVI} +incdir+${FCRVVI}/rv32 +incdir+${FCRVVI}/rv64 +incdir+${FCRVVI}/rv64_priv +incdir+${FCRVVI}/priv +incdir+${FCRVVI}/rv32_priv +incdir+${FCRVVI}/common +incdir+${FCRVVI}"
set INC_DIRS "+incdir+${CONFIG}/${CFG} +incdir+${CONFIG}/deriv/${CFG} +incdir+${CONFIG}/shared"
set SOURCES "${SRC}/cvw.sv ${TB}/${TESTBENCH}.sv ${TB}/common/*.sv ${SRC}/*/*.sv ${SRC}/*/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*/*/*.sv"
vlog -permissive -lint -work ${WKDIR} {*}${INC_DIRS} {*}${FCvlog} {*}${FCdefineCOVER_EXTS} {*}${lockstepvlog} {*}${SOURCES} -suppress 2282,2583,7053,7063,2596,13286
vlog -permissive -lint -work ${WKDIR} {*}${INC_DIRS} {*}${FCvlog} {*}${DefineArgs} {*}${lockstepvlog} {*}${brekervlog} {*}${SOURCES} -suppress 2282,2583,7053,7063,2596,13286,2605,2250
# start and run simulation
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
vopt $accFlag wkdir/${CFG}_${TESTSUITE}.${TESTBENCH} -work ${WKDIR} {*}${ExpandedParamArgs} -o testbenchopt ${CoverageVoptArg}
vopt $accFlag ${WKDIR}.${TESTBENCH} ${brekervopt} -work ${WKDIR} {*}${ExpandedParamArgs} -o testbenchopt ${CoverageVoptArg}
vsim -lib ${WKDIR} testbenchopt +TEST=${TESTSUITE} {*}${PlusArgs} -fatal 7 {*}${SVLib} {*}${FCvopt} -suppress 3829 ${CoverageVsimArg}
vsim -lib ${WKDIR} testbenchopt +TEST=${TESTSUITE} {*}${PlusArgs} -fatal 7 {*}${SVLib} -suppress 3829 ${CoverageVsimArg}
# power add generates the logging necessary for saif generation.
# power add -r /dut/core/*

53
sim/questa/wave.do
View file

@ -204,7 +204,6 @@ add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/SrcAE
add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/SrcBE
add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/ALUResultE
add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/ResultW
add wave -noupdate -expand -group {Memory Stage} /testbench/FunctionName/FunctionName/FunctionName
add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrValidM
add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/PCM
add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrM
@ -583,31 +582,31 @@ add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/csrs/csrs/STIME
add wave -noupdate -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/FRM_REGW
add wave -noupdate -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/FFLAGS_REGW
add wave -noupdate -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/STATUS_FS
add wave -noupdate -group CSRs -group {Performance Counters} -label MCYCLE -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[0]}
add wave -noupdate -group CSRs -group {Performance Counters} -label MINSTRET -radix hexadecimal {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[2]}
add wave -noupdate -group CSRs -group {Performance Counters} -expand -group BP -label Branch -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[3]}
add wave -noupdate -group CSRs -group {Performance Counters} -expand -group BP -label {BP Dir Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[7]}
add wave -noupdate -group CSRs -group {Performance Counters} -expand -group BP -label {Jump (Not Return)} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[4]}
add wave -noupdate -group CSRs -group {Performance Counters} -expand -group BP -label Return -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[5]}
add wave -noupdate -group CSRs -group {Performance Counters} -expand -group BP -label {BP Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[6]}
add wave -noupdate -group CSRs -group {Performance Counters} -expand -group BP -label {BTA Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[8]}
add wave -noupdate -group CSRs -group {Performance Counters} -expand -group BP -label {RAS Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[9]}
add wave -noupdate -group CSRs -group {Performance Counters} -expand -group BP -label {BP CLASS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[10]}
add wave -noupdate -group CSRs -group {Performance Counters} -group ICACHE -label {I Cache Access} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[16]}
add wave -noupdate -group CSRs -group {Performance Counters} -group ICACHE -label {I Cache Miss} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[17]}
add wave -noupdate -group CSRs -group {Performance Counters} -group ICACHE -label {I Cache Miss Cycles} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[18]}
add wave -noupdate -group CSRs -group {Performance Counters} -group DCACHE -label {Load Stall} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[11]}
add wave -noupdate -group CSRs -group {Performance Counters} -group DCACHE -label {Store Stall} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[12]}
add wave -noupdate -group CSRs -group {Performance Counters} -group DCACHE -label {DCACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[14]}
add wave -noupdate -group CSRs -group {Performance Counters} -group DCACHE -label {DCACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[13]}
add wave -noupdate -group CSRs -group {Performance Counters} -group DCACHE -label {D Cache Miss Cycles} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[15]}
add wave -noupdate -group CSRs -group {Performance Counters} -group Privileged -label {CSR Write} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[19]}
add wave -noupdate -group CSRs -group {Performance Counters} -group Privileged -label Fence.I {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[20]}
add wave -noupdate -group CSRs -group {Performance Counters} -group Privileged -label sfence.VMA {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[21]}
add wave -noupdate -group CSRs -group {Performance Counters} -group Privileged -label Interrupt {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[22]}
add wave -noupdate -group CSRs -group {Performance Counters} -group Privileged -label Exception {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[23]}
add wave -noupdate -group CSRs -group {Performance Counters} -label {FDiv or IDiv Cycles} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[24]}
add wave -noupdate -group CSRs -group {Performance Counters} /testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW
add wave -noupdate -group CSRs -expand -group {Performance Counters} -label MCYCLE -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[0]}
add wave -noupdate -group CSRs -expand -group {Performance Counters} -label MINSTRET -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[2]}
add wave -noupdate -group CSRs -expand -group {Performance Counters} -expand -group BP -label Branch -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[3]}
add wave -noupdate -group CSRs -expand -group {Performance Counters} -expand -group BP -label {BP Dir Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[7]}
add wave -noupdate -group CSRs -expand -group {Performance Counters} -expand -group BP -label {Jump (Not Return)} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[4]}
add wave -noupdate -group CSRs -expand -group {Performance Counters} -expand -group BP -label Return -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[5]}
add wave -noupdate -group CSRs -expand -group {Performance Counters} -expand -group BP -label {BP Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[6]}
add wave -noupdate -group CSRs -expand -group {Performance Counters} -expand -group BP -label {BTA Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[8]}
add wave -noupdate -group CSRs -expand -group {Performance Counters} -expand -group BP -label {RAS Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[9]}
add wave -noupdate -group CSRs -expand -group {Performance Counters} -expand -group BP -label {BP CLASS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[10]}
add wave -noupdate -group CSRs -expand -group {Performance Counters} -group ICACHE -label {I Cache Access} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[16]}
add wave -noupdate -group CSRs -expand -group {Performance Counters} -group ICACHE -label {I Cache Miss} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[17]}
add wave -noupdate -group CSRs -expand -group {Performance Counters} -group ICACHE -label {I Cache Miss Cycles} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[18]}
add wave -noupdate -group CSRs -expand -group {Performance Counters} -group DCACHE -label {Load Stall} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[11]}
add wave -noupdate -group CSRs -expand -group {Performance Counters} -group DCACHE -label {Store Stall} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[12]}
add wave -noupdate -group CSRs -expand -group {Performance Counters} -group DCACHE -label {DCACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[14]}
add wave -noupdate -group CSRs -expand -group {Performance Counters} -group DCACHE -label {DCACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[13]}
add wave -noupdate -group CSRs -expand -group {Performance Counters} -group DCACHE -label {D Cache Miss Cycles} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[15]}
add wave -noupdate -group CSRs -expand -group {Performance Counters} -group Privileged -label {CSR Write} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[19]}
add wave -noupdate -group CSRs -expand -group {Performance Counters} -group Privileged -label Fence.I {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[20]}
add wave -noupdate -group CSRs -expand -group {Performance Counters} -group Privileged -label sfence.VMA {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[21]}
add wave -noupdate -group CSRs -expand -group {Performance Counters} -group Privileged -label Interrupt {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[22]}
add wave -noupdate -group CSRs -expand -group {Performance Counters} -group Privileged -label Exception {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[23]}
add wave -noupdate -group CSRs -expand -group {Performance Counters} -label {FDiv or IDiv Cycles} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[24]}
add wave -noupdate -group CSRs -expand -group {Performance Counters} /testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW
add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/A
add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/B
add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/ALUResult
@ -659,9 +658,7 @@ add wave -noupdate -group spi -expand -group interface /testbench/dut/uncoregen/
add wave -noupdate -group spi -expand -group interface /testbench/dut/uncoregen/uncore/spi/spi/SPIIn
add wave -noupdate -group spi /testbench/dut/uncoregen/uncore/spi/spi/ChipSelectMode
add wave -noupdate -group spi /testbench/dut/uncoregen/uncore/spi/spi/SckMode
add wave -noupdate /testbench/dut/uncoregen/uncore/spi/spi/TransmitShiftRegLoad
add wave -noupdate /testbench/dut/uncoregen/uncore/spi/spi/ShiftEdge
add wave -noupdate /testbench/dut/uncoregen/uncore/spi/spi/Active
add wave -noupdate /testbench/dut/uncoregen/uncore/spi/spi/TransmitData
add wave -noupdate /testbench/dut/uncoregen/uncore/spi/spi/TransmitShiftReg
add wave -noupdate -expand -group {fetch buffer} /testbench/dut/core/ifu/fetchbuff/StallD

9
sim/rv64gc_CacheSim.py
View file

@ -49,12 +49,14 @@ class bcolors:
BOLD = '\033[1m'
UNDERLINE = '\033[4m'
tests64gc = ["coverage64gc", "arch64i", "arch64priv", "arch64c", "arch64m", "arch64zcb",
"arch64zifencei", "arch64zicond", "arch64a_amo", "wally64a_lrsc", "wally64periph", "wally64priv",
tests64gc = ["coverage64gc", "wally64priv", "arch64i", "arch64priv", "arch64c", "arch64m", "arch64zcb",
"arch64zifencei", "arch64zicond", "arch64a_amo", "wally64a_lrsc", "wally64periph",
"arch64zbkb", "arch64zbkc", "arch64zbkx", "arch64zknd", "arch64zkne", "arch64zknh",
"arch64zba", "arch64zbb", "arch64zbc", "arch64zbs"]
# arch64i is the most interesting case. Uncomment line below to run just that case
# tests64gc = ["arch64i"]
#tests64gc = ["arch64i"]
#tests64gc = ["coverage64gc"]
#tests64gc = ["wally64priv"]
cachetypes = ["ICache", "DCache"]
simdir = os.path.expandvars("$WALLY/sim")
@ -67,6 +69,7 @@ def main():
args = parser.parse_args()
simargs = "I_CACHE_ADDR_LOGGER=1\\\'b1 D_CACHE_ADDR_LOGGER=1\\\'b1"
testcmd = "wsim --sim " + args.sim + " rv64gc {} --params \"" + simargs + "\" > /dev/null"
#cachecmd = "CacheSim.py 64 4 56 44 -f {} --verbose"
cachecmd = "CacheSim.py 64 4 56 44 -f {}"
mismatches = 0

166
sim/vcs/run_vcs
View file

@ -2,98 +2,118 @@
# run_vcs
# David_Harris@hmc.edu 2 July 2024
# Modified Jordan Carlin jcarlin@hmc.edu Dec 9 2024
# Run VCS on a given file, passing appropriate flags
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
import argparse
import os
import subprocess
import sys
# Global variables
WALLY = os.environ.get('WALLY')
simdir = f"{WALLY}/sim/vcs"
cfgdir = f"{WALLY}/config"
srcdir = f"{WALLY}/src"
tbdir = f"{WALLY}/testbench"
logdir = f"{simdir}/logs"
# run a Linux command and return the result as a string in a form that VCS can use
def runfindcmd(cmd):
# print("Executing: " + str(cmd) )
res = subprocess.check_output(cmd, shell=True)
def runFindCommand(cmd):
res = subprocess.check_output(cmd, shell=True, )
res = str(res)
res = res.replace("\\n", " ") # replace newline with space
res = res.replace("\'", "") # strip off quotation marks
res = res[1:] # strip off leading b from byte string
return res
parser = argparse.ArgumentParser()
parser.add_argument("config", help="Configuration file")
parser.add_argument("testsuite", help="Test suite (or none, when running a single ELF file) ")
parser.add_argument("--tb", "-t", help="Testbench", choices=["testbench", "testbench_fp"], default="testbench")
parser.add_argument("--elffile", "-e", help="ELF file name", default="")
parser.add_argument("--coverage", "-c", help="Code & Functional Coverage", action="store_true")
parser.add_argument("--fcov", "-f", help="Code & Functional Coverage", action="store_true")
parser.add_argument("--args", "-a", help="Optional arguments passed to simulator via $value$plusargs", default="")
parser.add_argument("--params", "-p", help="Optional top-level parameter overrides of the form param=value", default="")
parser.add_argument("--lockstep", "-l", help="Run ImperasDV lock, step, and compare.", action="store_true")
# GUI not yet implemented
#parser.add_argument("--gui", "-g", help="Simulate with GUI", action="store_true")
args = parser.parse_args()
print("run_vcs Config=" + args.config + " tests=" + args.testsuite + " elffile=" + args.elffile + " lockstep=" + str(args.lockstep) + " args='" + args.args + "'")
def parseArgs():
parser = argparse.ArgumentParser()
parser.add_argument("config", help="Configuration file")
parser.add_argument("testsuite", help="Test suite (or none, when running a single ELF file) ")
parser.add_argument("--tb", "-t", help="Testbench", choices=["testbench", "testbench_fp"], default="testbench")
parser.add_argument("--ccov", "-c", help="Code Coverage", action="store_true")
parser.add_argument("--fcov", "-f", help="Functional Coverage", action="store_true")
parser.add_argument("--args", "-a", help="Optional arguments passed to simulator via $value$plusargs", default="")
parser.add_argument("--params", "-p", help="Optional top-level parameter overrides of the form param=value", default="")
parser.add_argument("--define", "-d", help="Optional define macros passed to simulator", default="")
parser.add_argument("--lockstep", "-l", help="Run ImperasDV lock, step, and compare.", action="store_true")
#parser.add_argument("--gui", "-g", help="Simulate with GUI", action="store_true") # GUI not yet implemented
return parser.parse_args()
cfgdir = "$WALLY/config"
srcdir = "$WALLY/src"
tbdir = "$WALLY/testbench"
wkdir = "$WALLY/sim/vcs/wkdir/" + args.config + "_" + args.testsuite
covdir = "$WALLY/sim/vcs/cov/" + args.config + "_" + args.testsuite
logdir = "$WALLY/sim/vcs/logs"
def createDirs(args):
wkdir = f"{simdir}/wkdir/{args.config}_{args.testsuite}"
covdir = f"{simdir}/cov/{args.config}_{args.testsuite}"
os.makedirs(wkdir, exist_ok=True)
os.makedirs(covdir, exist_ok=True)
os.makedirs(logdir, exist_ok=True)
return wkdir, covdir
os.system("mkdir -p " + wkdir)
os.system("mkdir -p " + covdir)
os.system("mkdir -p " + logdir)
def generateFileList():
rtlsrc_cmd = f'find {srcdir} -name "*.sv" ! -path "{srcdir}/generic/mem/rom1p1r_128x64.sv" ! -path "{srcdir}/generic/mem/ram2p1r1wbe_128x64.sv" ! -path "{srcdir}/generic/mem/rom1p1r_128x32.sv" ! -path "{srcdir}/generic/mem/ram2p1r1wbe_2048x64.sv"'
rtlsrc_files = runFindCommand(rtlsrc_cmd)
tbcommon_cmd = f'find {tbdir}/common -name "*.sv"'
tbcommon_files = runFindCommand(tbcommon_cmd)
tb_file = f'{tbdir}/{args.tb}.sv'
return f"{tb_file} {rtlsrc_files} {tbcommon_files}"
# Find RTL source files
rtlsrc_cmd = "find " + srcdir + ' -name "*.sv" ! -path "' + srcdir + '/generic/mem/rom1p1r_128x64.sv" ! -path "' + srcdir + '/generic/mem/ram2p1r1wbe_128x64.sv" ! -path "' + srcdir + '/generic/mem/rom1p1r_128x32.sv" ! -path "' + srcdir + '/generic/mem/ram2p1r1wbe_2048x64.sv"'
rtlsrc_files = runfindcmd(rtlsrc_cmd)
tbcommon_cmd = 'find ' + tbdir+'/common -name "*.sv" ! -path "' + tbdir+'/common/wallyTracer.sv"'
tbcommon_files = runfindcmd(tbcommon_cmd)
tb_file = tbdir + "/" + args.tb + ".sv"
RTL_FILES = tb_file + ' ' + str(rtlsrc_files) + ' ' + str(tbcommon_files)
def processArgs(wkdir, args):
compileOptions = []
simvOptions = []
if args.lockstep:
compileOptions.extend(["+incdir+$IMPERAS_HOME/ImpPublic/include/host",
"+incdir+$IMPERAS_HOME/ImpProprietary/include/host",
"$IMPERAS_HOME/ImpPublic/source/host/rvvi/*.sv",
"$IMPERAS_HOME/ImpProprietary/source/host/idv/*.sv"])
simvOptions.append("-sv_lib $IMPERAS_HOME/lib/Linux64/ImperasLib/imperas.com/verification/riscv/1.0/model")
if args.ccov:
compileOptions.extend(["-cm line+cond+branch+fsm+tgl", f"-cm_log {wkdir}/coverage.log", f"-cm_dir {wkdir}/coverage"])
if args.params:
compileOptions.append(setupParamOverrides(wkdir, args))
if args.define:
compileOptions.append(args.define)
# if args.gui:
# compileOptions.append("-debug_access+all+reverse -kdb +vcs+vcdpluson")
compileOptions = " ".join(compileOptions)
simvOptions = " ".join(simvOptions)
return compileOptions, simvOptions
# Include directories
INCLUDE_PATH="+incdir+" + cfgdir + "/" + args.config + " +incdir+" + cfgdir + "/deriv/" + args.config + " +incdir+" + cfgdir + "/shared +incdir+$WALLY/tests +incdir+" + tbdir + " +incdir+" + srcdir
def setupParamOverrides(wkdir, args):
paramOverrideFile = os.path.join(wkdir, "param_overrides.txt")
with open(paramOverrideFile, "w") as f:
for param in args.params.split():
[param, value] = param.split("=")
if fr"\'" in value: # for bit values
value = value.replace(fr"\'", "'")
else: # for strings
value = f'"{value}"'
f.write(f"assign {value} {args.tb}/{param}\n")
return f" -parameters {wkdir}/param_overrides.txt "
# lockstep mode
if (args.lockstep):
LOCKSTEP_OPTIONS = " +define+USE_IMPERAS_DV +incdir+$IMPERAS_HOME/ImpPublic/include/host +incdir+$IMPERAS_HOME/ImpProprietary/include/host $IMPERAS_HOME/ImpPublic/source/host/rvvi/*.sv $IMPERAS_HOME/ImpProprietary/source/host/idv/*.sv " + tbdir + "/common/wallyTracer.sv"
LOCKSTEP_SIMV = "-sv_lib $IMPERAS_HOME/lib/Linux64/ImperasLib/imperas.com/verification/riscv/1.0/model"
else:
LOCKSTEP_OPTIONS = ""
LOCKSTEP_SIMV = ""
def setupCommands(wkdir, rtlFiles, compileOptions, simvOptions, args):
includePath=f"+incdir+{cfgdir}/{args.config} +incdir+{cfgdir}/deriv/{args.config} +incdir+{cfgdir}/shared +incdir+$WALLY/tests +incdir+{tbdir} +incdir+{srcdir}"
vcsStandardFlags = "+lint=all,noGCWM,noUI,noSVA-UA,noIDTS,noNS,noULCO,noCAWM-L,noWMIA-L,noSV-PIU,noSTASKW_CO,noSTASKW_CO1,noSTASKW_RMCOF -suppress +warn -sverilog +vc -Mupdate -line -full64 -lca -ntb_opts sensitive_dyn"
vcsCMD = f"vcs {vcsStandardFlags} -top {args.tb} {compileOptions} -Mdir={wkdir} {includePath} {srcdir}/cvw.sv {rtlFiles} -o {wkdir}/sim_out -work {wkdir} -Mlib={wkdir} -l {logdir}/{args.config}_{args.testsuite}.log"
simvCMD = f"{wkdir}/sim_out +TEST={args.testsuite} {args.args} -no_save {simvOptions}"
return vcsCMD, simvCMD
# coverage mode
if (args.coverage):
COV_OPTIONS = "-cm line+cond+branch+fsm+tgl -cm_log " + wkdir + "/coverage.log -cm_dir " + wkdir + "/coverage"
else:
COV_OPTIONS = ""
def runVCS(wkdir, vcsCMD, simvCMD):
print(f"Executing: {vcsCMD}")
subprocess.run(vcsCMD, shell=True)
subprocess.run(simvCMD, shell=True)
if (args.ccov):
COV_RUN = f"urg -dir {wkdir}/coverage.vdb -format text -report IndividualCovReport/{args.config}_{args.testsuite}"
subprocess.run(COV_RUN, shell=True)
# Write parameter overrides to a file
f = open(os.path.expandvars(wkdir) + "/param_overrides.txt", "w")
for param in args.params.split():
[param, value] = param.split("=")
if "\\'" in value: # for bit values
value = value.replace("\\'", "'")
else: # for strings
value = "\"" + value + "\""
# print("param=" + param + " value=" + value)
f.write("assign " + value + " " + args.tb + "/" + param + "\n")
f.close()
PARAM_OVERRIDES=" -parameters " + wkdir + "/param_overrides.txt "
def main(args):
print(f"run_vcs Config={args.config} tests={args.testsuite} lockstep={args.lockstep} args='{args.args}' params='{args.params}' define='{args.define}'")
wkdir, covdir = createDirs(args)
rtlFiles = generateFileList()
compileOptions, simvOptions = processArgs(wkdir, args)
vcsCMD, simvCMD = setupCommands(wkdir, rtlFiles, compileOptions, simvOptions, args)
runVCS(wkdir, vcsCMD, simvCMD)
# Simulation commands
OUTPUT="sim_out"
VCS_CMD="vcs +lint=all,noGCWM,noUI,noSVA-UA,noIDTS,noNS,noULCO,noCAWM-L,noWMIA-L,noSV-PIU,noSTASKW_CO,noSTASKW_CO1,noSTASKW_RMCOF -suppress +warn -sverilog +vc -Mupdate -line -full64 -lca -ntb_opts sensitive_dyn " + "-top " + args.tb + PARAM_OVERRIDES + INCLUDE_PATH # Disabled Debug flags; add them back for a GUI mode -debug_access+all+reverse -kdb +vcs+vcdpluson
VCS = VCS_CMD + " -Mdir=" + wkdir + " " + srcdir + "/cvw.sv " + LOCKSTEP_OPTIONS + " " + COV_OPTIONS + " " + RTL_FILES + " -o " + wkdir + "/" + OUTPUT + " -work " + wkdir + " -Mlib=" + wkdir + " -l " + logdir + "/" + args.config + "_" + args.testsuite + ".log"
SIMV_CMD= wkdir + "/" + OUTPUT + " +TEST=" + args.testsuite + " " + args.elffile + " " + args.args + " -no_save " + LOCKSTEP_SIMV
# Run simulation
print("Executing: " + str(VCS) )
subprocess.run(VCS, shell=True)
subprocess.run(SIMV_CMD, shell=True)
if (args.coverage):
COV_RUN = "urg -dir " + wkdir + "/coverage.vdb -format text -report IndividualCovReport/" + args.config + "_" + args.testsuite
subprocess.run(COV_RUN, shell=True)
if __name__ == "__main__":
args = parseArgs()
sys.exit(main(args))

19
sim/verilator/Makefile
View file

@ -13,16 +13,15 @@ VERILATOR_DIR=${WALLY}/sim/verilator
SOURCE=${WALLY}/config/shared/*.vh ${WALLY}/config/${WALLYCONF} ${WALLY}/config/deriv/${WALLYCONF} ${WALLY}/src/cvw.sv ${WALLY}/testbench/*.sv ${WALLY}/testbench/common/*.sv ${WALLY}/src/*/*.sv ${WALLY}/src/*/*/*.sv
PLUS_ARGS=
PARAM_ARGS=
DEFINE_ARGS=
EXPANDED_PARAM_ARGS:=$(patsubst %,-G%,$(PARAM_ARGS))
WALLYCONF?=rv64gc
TEST?=arch64i
TESTBENCH?=testbench
TESTBENCH?=testbench
# constants
# assume WALLY variable is correctly configured in the shell environment
WORKING_DIR=${WALLY}/sim/verilator
TARGET=$(WORKING_DIR)/target
# INCLUDE_PATH are pathes that Verilator should search for files it needs
INCLUDE_PATH="-I${WALLY}/config/shared" "-I${WALLY}/config/$(WALLYCONF)" "-I${WALLY}/config/deriv/$(WALLYCONF)"
# SOURCES are source files
@ -30,6 +29,8 @@ SOURCES=${WALLY}/src/cvw.sv ${WALLY}/testbench/${TESTBENCH}.sv ${WALLY}/testbenc
# DEPENDENCIES are configuration files and source files, which leads to recompilation of executables
DEPENDENCIES=${WALLY}/config/shared/*.vh $(SOURCES)
WORKDIR = $(VERILATOR_DIR)/wkdir/$(WALLYCONF)_$(TEST)
# regular testbench requires a wrapper defining getenvval
ifeq ($(TESTBENCH), testbench)
WRAPPER=${WALLY}/sim/verilator/wrapper.c
@ -41,9 +42,9 @@ endif
default: run
run: wkdir/$(WALLYCONF)_$(TEST)/V${TESTBENCH}
run: $(WORKDIR)/V${TESTBENCH}
mkdir -p $(VERILATOR_DIR)/logs
wkdir/$(WALLYCONF)_$(TEST)/V${TESTBENCH} ${ARGTEST} $(PLUS_ARGS)
$(WORKDIR)/V${TESTBENCH} ${ARGTEST} $(PLUS_ARGS)
profile: obj_dir_profiling/V${TESTBENCH}_$(WALLYCONF)
$(VERILATOR_DIR)/obj_dir_profiling/V${TESTBENCH}_$(WALLYCONF) ${ARGTEST}
@ -54,15 +55,16 @@ profile: obj_dir_profiling/V${TESTBENCH}_$(WALLYCONF)
mv gmon_$(WALLYCONF)* $(VERILATOR_DIR)/logs_profiling
echo "Please check $(VERILATOR_DIR)/logs_profiling/gmon_$(WALLYCONF)* for logs and output files."
wkdir/$(WALLYCONF)_$(TEST)/V${TESTBENCH}: $(DEPENDENCIES)
mkdir -p wkdir/$(WALLYCONF)_$(TEST)
$(WORKDIR)/V${TESTBENCH}: $(DEPENDENCIES)
mkdir -p $(WORKDIR)
verilator \
--Mdir wkdir/$(WALLYCONF)_$(TEST) -o V${TESTBENCH} \
--Mdir $(WORKDIR) -o V${TESTBENCH} \
--binary --trace \
$(OPT) $(PARAMS) $(NONPROF) \
--top-module ${TESTBENCH} --relative-includes \
$(INCLUDE_PATH) \
${WRAPPER} \
${DEFINE_ARGS} \
${EXPANDED_PARAM_ARGS} \
$(SOURCES)
@ -75,6 +77,7 @@ obj_dir_profiling/V${TESTBENCH}_$(WALLYCONF): $(DEPENDENCIES)
--top-module ${TESTBENCH} --relative-includes \
$(INCLUDE_PATH) \
${WRAPPER} \
${DEFINE_ARGS} \
${EXPANDED_PARAM_ARGS} \
$(SOURCES)

2
site-setup.csh
View file

@ -49,7 +49,7 @@ setenv SPIKE_PATH $RISCV/bin # Change this for your path to riscv-isa-s
setenv IDV $RISCV/ImperasDV-OpenHW
if ($?IDV) then
# echo "Imperas exists"
setenv IMPERAS_HOME $IDV/Imperas
setenv IMPERAS_HOME $IDV
setenv IMPERAS_PERSONALITY CPUMAN_DV_ASYNC
setenv ROOTDIR ~/
source ${IMPERAS_HOME}/bin/setup.sh

5
site-setup.sh
View file

@ -15,6 +15,7 @@ export IMPERASD_LICENSE_FILE=27020@zircon.eng.hmc.edu # Change thi
export QUESTA_HOME=/cad/mentor/questa_sim-2023.4/questasim # Change this for your path to Questa, excluding bin
export DC_HOME=/cad/synopsys/SYN # Change this for your path to Synopsys DC, excluding bin
export VCS_HOME=/cad/synopsys/vcs/U-2023.03-SP2-4 # Change this for your path to Synopsys VCS, excluding bin
export BREKER_HOME=/cad/breker/trek5-2.1.10b-GCC6_el7 # Change this for your path to Breker Trek
# Tools
# Questa and Synopsys
@ -66,7 +67,7 @@ export SPIKE_PATH=$RISCV/bin # Copy this as it is
export IDV=$RISCV/ImperasDV-OpenHW
if [ -e "$IDV" ]; then
# echo "Imperas exists"
export IMPERAS_HOME=$IDV/Imperas
export IMPERAS_HOME=$IDV
export IMPERAS_PERSONALITY=CPUMAN_DV_ASYNC
export ROOTDIR=~/
source "${IMPERAS_HOME}"/bin/setup.sh
@ -77,6 +78,8 @@ fi
# Use newer gcc version for older distros
if [ -e /opt/rh/gcc-toolset-13/enable ]; then
source /opt/rh/gcc-toolset-13/enable # Red Hat Family
elif [ -e $RISCV/gcc-13 ]; then
export PATH=$RISCV/gcc-13/bin:$PATH # SUSE Family
elif [ -e $RISCV/gcc-10 ]; then
export PATH=$RISCV/gcc-10/bin:$PATH # Ubuntu 20.04 LTS
fi

28
src/cache/cache.sv vendored
View file

@ -29,7 +29,7 @@
////////////////////////////////////////////////////////////////////////////////////////////////
module cache import cvw::*; #(parameter cvw_t P,
parameter PA_BITS, XLEN, LINELEN, NUMSETS, NUMWAYS, LOGBWPL, WORDLEN, MUXINTERVAL, READ_ONLY_CACHE) (
parameter PA_BITS, LINELEN, NUMSETS, NUMWAYS, LOGBWPL, WORDLEN, MUXINTERVAL, READ_ONLY_CACHE) (
input logic clk,
input logic reset,
input logic Stall, // Stall the cache, preventing new accesses. In-flight access finished but does not return to READY
@ -66,18 +66,14 @@ module cache import cvw::*; #(parameter cvw_t P,
localparam SETLEN = $clog2(NUMSETS); // Number of set bits
localparam SETTOP = SETLEN+OFFSETLEN; // Number of set plus offset bits
localparam TAGLEN = PA_BITS - SETTOP; // Number of tag bits
localparam CACHEWORDSPERLINE = LINELEN/WORDLEN;// Number of words in cache line
localparam LOGCWPL = $clog2(CACHEWORDSPERLINE);// Log2 of ^
localparam FLUSHADRTHRESHOLD = NUMSETS - 1; // Used to determine when flush is complete
localparam LOGLLENBYTES = $clog2(WORDLEN/8); // Number of bits to address a word
logic SelAdrData;
logic SelAdrTag;
logic [1:0] AdrSelMuxSelData;
logic [1:0] AdrSelMuxSelTag;
logic [1:0] AdrSelMuxSelTag, AdrSelMuxSelLRU;
logic [SETLEN-1:0] CacheSetData;
logic [SETLEN-1:0] CacheSetTag;
logic [SETLEN-1:0] CacheSetTag, CacheSetLRU;
logic [LINELEN-1:0] LineWriteData;
logic ClearDirty, SetDirty, SetValid, ClearValid;
logic [LINELEN-1:0] ReadDataLineWay [NUMWAYS-1:0];
@ -117,16 +113,20 @@ module cache import cvw::*; #(parameter cvw_t P,
mux3 #(SETLEN) AdrSelMuxTag(NextSet[SETTOP-1:OFFSETLEN], PAdr[SETTOP-1:OFFSETLEN], FlushAdr,
AdrSelMuxSelTag, CacheSetTag);
assign AdrSelMuxSelLRU = {FlushCache, ((SelAdrTag | SelHPTW | Stall) & ~((READ_ONLY_CACHE == 1) & FlushStage))};
mux3 #(SETLEN) AdrSelMuxLRU(NextSet[SETTOP-1:OFFSETLEN], PAdr[SETTOP-1:OFFSETLEN], FlushAdr,
AdrSelMuxSelLRU, CacheSetLRU);
// Array of cache ways, along with victim, hit, dirty, and read merging logic
cacheway #(P, PA_BITS, XLEN, NUMSETS, LINELEN, TAGLEN, OFFSETLEN, SETLEN, READ_ONLY_CACHE) CacheWays[NUMWAYS-1:0](
cacheway #(P, PA_BITS, NUMSETS, LINELEN, TAGLEN, OFFSETLEN, SETLEN, READ_ONLY_CACHE) CacheWays[NUMWAYS-1:0](
.clk, .reset, .CacheEn, .CacheSetData, .CacheSetTag, .PAdr, .LineWriteData, .LineByteMask, .SelVictim,
.SetValid, .ClearValid, .SetDirty, .ClearDirty, .VictimWay,
.FlushWay, .FlushCache, .ReadDataLineWay, .HitWay, .ValidWay, .DirtyWay, .HitDirtyWay, .TagWay, .FlushStage, .InvalidateCache);
// Select victim way for associative caches
if(NUMWAYS > 1) begin:vict
cacheLRU #(NUMWAYS, SETLEN, OFFSETLEN, NUMSETS) cacheLRU(
.clk, .reset, .FlushStage, .CacheEn, .HitWay, .ValidWay, .VictimWay, .CacheSetTag, .LRUWriteEn,
cacheLRU #(NUMWAYS, SETLEN, NUMSETS) cacheLRU(
.clk, .reset, .FlushStage, .CacheEn, .HitWay, .ValidWay, .VictimWay, .CacheSetLRU, .LRUWriteEn,
.SetValid, .PAdr(PAdr[SETTOP-1:OFFSETLEN]), .InvalidateCache);
end else
assign VictimWay = 1'b1; // one hot.
@ -168,11 +168,7 @@ module cache import cvw::*; #(parameter cvw_t P,
if(!READ_ONLY_CACHE) begin:WriteSelLogic
logic [LINELEN/8-1:0] DemuxedByteMask, FetchBufferByteSel;
// Adjust byte mask from word to cache line
localparam CACHEMUXINVERALPERLINE = LINELEN/MUXINTERVAL;// Number of words in cache line
localparam LOGMIPL = $clog2(CACHEMUXINVERALPERLINE);// Log2 of ^
// Adjust byte mask from word to cache line
logic [LINELEN/8-1:0] BlankByteMask;
assign BlankByteMask[WORDLEN/8-1:0] = ByteMask;
assign BlankByteMask[LINELEN/8-1:WORDLEN/8] = 0;
@ -227,7 +223,7 @@ module cache import cvw::*; #(parameter cvw_t P,
// Cache FSM
/////////////////////////////////////////////////////////////////////////////////////////////
cachefsm #(P, READ_ONLY_CACHE) cachefsm(.clk, .reset, .CacheBusRW, .CacheBusAck,
cachefsm #(READ_ONLY_CACHE) cachefsm(.clk, .reset, .CacheBusRW, .CacheBusAck,
.FlushStage, .CacheRW, .Stall,
.Hit, .LineDirty, .HitLineDirty, .CacheStall, .CacheCommitted,
.CacheMiss, .CacheAccess, .SelAdrData, .SelAdrTag, .SelVictim,

8
src/cache/cacheLRU.sv vendored
View file

@ -29,14 +29,14 @@
////////////////////////////////////////////////////////////////////////////////////////////////
module cacheLRU
#(parameter NUMWAYS = 4, SETLEN = 9, OFFSETLEN = 5, NUMSETS = 128) (
#(parameter NUMWAYS = 4, SETLEN = 9, NUMSETS = 128) (
input logic clk,
input logic reset,
input logic FlushStage,
input logic CacheEn, // Enable the cache memory arrays. Disable hold read data constant
input logic [NUMWAYS-1:0] HitWay, // Which way is valid and matches PAdr's tag
input logic [NUMWAYS-1:0] ValidWay, // Which ways for a particular set are valid, ignores tag
input logic [SETLEN-1:0] CacheSetTag, // Cache address, the output of the address select mux, NextAdr, PAdr, or FlushAdr
input logic [SETLEN-1:0] CacheSetLRU, // Cache address, the output of the address select mux, NextAdr, PAdr, or FlushAdr
input logic [SETLEN-1:0] PAdr, // Physical address
input logic LRUWriteEn, // Update the LRU state
input logic SetValid, // Set the dirty bit in the selected way and set
@ -142,8 +142,8 @@ module cacheLRU
else if (CacheEn & LRUWriteEn) LRUMemory[PAdr] <= NextLRU;
// LRU read path with write forwarding
assign ReadLRU = LRUMemory[CacheSetTag];
assign ForwardLRU = LRUWriteEn & (PAdr == CacheSetTag);
assign ReadLRU = LRUMemory[CacheSetLRU];
assign ForwardLRU = LRUWriteEn & (PAdr == CacheSetLRU);
mux2 #(NUMWAYS-1) ReadLRUmux(ReadLRU, NextLRU, ForwardLRU, BypassedLRU);
flop #(NUMWAYS-1) CurrLRUReg(clk, BypassedLRU, CurrLRU);
endmodule

6
src/cache/cachefsm.sv vendored
View file

@ -28,8 +28,7 @@
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module cachefsm import cvw::*; #(parameter cvw_t P,
parameter READ_ONLY_CACHE = 0) (
module cachefsm #(parameter READ_ONLY_CACHE = 0) (
input logic clk,
input logic reset,
// hazard and privilege unit
@ -155,7 +154,8 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
assign SetValid = CurrState == STATE_WRITE_LINE |
(CurrState == STATE_ACCESS & CMOZeroNoEviction) |
(CurrState == STATE_WRITEBACK & CacheBusAck & CMOpM[3]);
assign ClearValid = (CurrState == STATE_ACCESS & CMOpM[0]) |
assign ClearValid = (CurrState == STATE_ACCESS & (CMOpM[0] | (CMOpM[2] & ~HitLineDirty))) |
//assign ClearValid = (CurrState == STATE_ACCESS & (CMOpM[0])) |
(CurrState == STATE_WRITEBACK & CMOpM[2] & CacheBusAck);
assign LRUWriteEn = (((CurrState == STATE_ACCESS & (AnyHit | CMOZeroNoEviction)) |
(CurrState == STATE_WRITE_LINE)) & ~FlushStage) |

15
src/cache/cacheway.sv vendored
View file

@ -29,7 +29,7 @@
////////////////////////////////////////////////////////////////////////////////////////////////
module cacheway import cvw::*; #(parameter cvw_t P,
parameter PA_BITS, XLEN, NUMSETS=512, LINELEN = 256, TAGLEN = 26,
parameter PA_BITS, NUMSETS=512, LINELEN = 256, TAGLEN = 26,
OFFSETLEN = 5, INDEXLEN = 9, READ_ONLY_CACHE = 0) (
input logic clk,
input logic reset,
@ -57,12 +57,6 @@ module cacheway import cvw::*; #(parameter cvw_t P,
output logic DirtyWay , // The selected way is dirty
output logic [TAGLEN-1:0] TagWay); // This way's tag if valid
localparam WORDSPERLINE = LINELEN/XLEN;
localparam BYTESPERLINE = LINELEN/8;
localparam LOGWPL = $clog2(WORDSPERLINE);
localparam LOGXLENBYTES = $clog2(XLEN/8);
localparam BYTESPERWORD = XLEN/8;
logic [NUMSETS-1:0] ValidBits;
logic [NUMSETS-1:0] DirtyBits;
logic [LINELEN-1:0] ReadDataLine;
@ -131,7 +125,6 @@ module cacheway import cvw::*; #(parameter cvw_t P,
localparam NUMSRAM = LINELEN/P.CACHE_SRAMLEN;
localparam SRAMLENINBYTES = P.CACHE_SRAMLEN/8;
localparam LOGNUMSRAM = $clog2(NUMSRAM);
for(words = 0; words < NUMSRAM; words++) begin: word
if (READ_ONLY_CACHE) begin:wordram // no byte-enable needed for i$.
@ -175,7 +168,11 @@ module cacheway import cvw::*; #(parameter cvw_t P,
//if (reset) DirtyBits <= {NUMSETS{1'b0}};
if(CacheEn) begin
Dirty <= DirtyBits[CacheSetTag];
if((SetDirtyWay | ClearDirtyWay) & ~FlushStage) DirtyBits[CacheSetData] <= SetDirtyWay; // exclusion-tag: cache UpdateDirty
if((SetDirtyWay | ClearDirtyWay) & ~FlushStage) begin
DirtyBits[CacheSetData] <= SetDirtyWay; // exclusion-tag: cache UpdateDirty
if (CacheSetData == CacheSetTag) Dirty <= SetDirtyWay;
else Dirty <= DirtyBits[CacheSetTag];
end
end
end
end else assign Dirty = 1'b0;

1
src/fpu/fcmp.sv
View file

@ -75,6 +75,7 @@ module fcmp import cvw::*; #(parameter cvw_t P) (
3'b0?1: if (P.ZFA_SUPPORTED)
CmpNV = Zfa ? EitherSNaN : EitherNaN; // fltq,fleq / flt,fle perform CompareQuietLess / CompareSignalingLess differing on when to set invalid
else CmpNV = EitherNaN; // flt, fle
3'b100: CmpNV = 1'b0;
default: CmpNV = 1'bx;
endcase
end

50
src/fpu/fctrl.sv
View file

@ -153,18 +153,20 @@ module fctrl import cvw::*; #(parameter cvw_t P) (
endcase
7'b11100??: if (Funct3D == 3'b001 & Rs2D == 5'b00000)
ControlsD = `FCTRLW'b0_1_10_00_000_0_0_0_0_0; // fclass
else if (Funct3D == 3'b000 & Rs2D == 5'b00000)
ControlsD = `FCTRLW'b0_1_11_00_000_0_0_0_0_0; // fmv.x.w/d/h/q fp to int register
else if (P.ZFA_SUPPORTED & P.XLEN == 32 & P.D_SUPPORTED & Funct7D[1:0] == 2'b01 & Funct3D == 3'b000 & Rs2D == 5'b00001)
ControlsD = `FCTRLW'b0_1_11_00_000_0_0_0_1_0; // fmvh.x.d (Zfa)
else if (Funct3D == 3'b000 & Rs2D == 5'b00000) begin
if (Fmt[1:0] == 2'b00 | Fmt[1:0] == 2'b10 | (P.XLEN == 64 & Fmt[1:0] == 2'b01))
ControlsD = `FCTRLW'b0_1_11_00_000_0_0_0_0_0; // fmv.x.w/d/h fp to int register (double only in RV64)
end else if (P.ZFA_SUPPORTED & P.XLEN == 32 & P.D_SUPPORTED & Funct7D[1:0] == 2'b01 & Funct3D == 3'b000 & Rs2D == 5'b00001)
ControlsD = `FCTRLW'b0_1_11_00_000_0_0_0_1_0; // fmvh.x.d (Zfa)
// Q not supported in RV64GC
// coverage off
else if (P.ZFA_SUPPORTED & P.XLEN == 64 & P.Q_SUPPORTED & Funct7D[1:0] == 2'b11 & Funct3D == 3'b000 & Rs2D == 5'b00001)
ControlsD = `FCTRLW'b0_1_11_00_000_0_0_0_1_0; // fmvh.x.q (Zfa)
ControlsD = `FCTRLW'b0_1_11_00_000_0_0_0_1_0; // fmvh.x.q (Zfa)
// coverage on
7'b11110??: if (Funct3D == 3'b000 & Rs2D == 5'b00000)
ControlsD = `FCTRLW'b1_0_00_00_011_0_0_0_0_0; // fmv.w/d/h/q.x int to fp reg
else if (P.ZFA_SUPPORTED & Funct3D == 3'b000 & Rs2D == 5'b00001)
7'b11110??: if (Funct3D == 3'b000 & Rs2D == 5'b00000) begin
if (Fmt[1:0] == 2'b00 | Fmt[1:0] == 2'b10 | (P.XLEN == 64 & Fmt[1:0] == 2'b01))
ControlsD = `FCTRLW'b1_0_00_00_011_0_0_0_0_0; // fmv.w/d/h.x int to fp reg (double only in RV64)
end else if (P.ZFA_SUPPORTED & Funct3D == 3'b000 & Rs2D == 5'b00001)
ControlsD = `FCTRLW'b1_0_00_00_111_0_0_0_1_0; // fli (Zfa)
7'b0100000: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b00)
ControlsD = `FCTRLW'b1_0_01_00_000_0_0_0_0_0; // fcvt.s.(d/q/h)
@ -196,54 +198,54 @@ module fctrl import cvw::*; #(parameter cvw_t P) (
7'b1101000: case(Rs2D)
5'b00000: ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0_0_0; // fcvt.s.w w->s
5'b00001: ControlsD = `FCTRLW'b1_0_01_00_100_0_0_0_0_0; // fcvt.s.wu wu->s
5'b00010: ControlsD = `FCTRLW'b1_0_01_00_111_0_0_0_0_0; // fcvt.s.l l->s
5'b00011: ControlsD = `FCTRLW'b1_0_01_00_110_0_0_0_0_0; // fcvt.s.lu lu->s
5'b00010: if (P.XLEN == 64) ControlsD = `FCTRLW'b1_0_01_00_111_0_0_0_0_0; // fcvt.s.l l->s
5'b00011: if (P.XLEN == 64) ControlsD = `FCTRLW'b1_0_01_00_110_0_0_0_0_0; // fcvt.s.lu lu->s
endcase
7'b1100000: case(Rs2D)
5'b00000: ControlsD = `FCTRLW'b0_1_01_00_001_0_0_1_0_0; // fcvt.w.s s->w
5'b00001: ControlsD = `FCTRLW'b0_1_01_00_000_0_0_1_0_0; // fcvt.wu.s s->wu
5'b00010: ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1_0_0; // fcvt.l.s s->l
5'b00011: ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1_0_0; // fcvt.lu.s s->lu
5'b00010: if (P.XLEN == 64) ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1_0_0; // fcvt.l.s s->l
5'b00011: if (P.XLEN == 64) ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1_0_0; // fcvt.lu.s s->lu
endcase
7'b1101001: case(Rs2D)
5'b00000: ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0_0_0; // fcvt.d.w w->d
5'b00001: ControlsD = `FCTRLW'b1_0_01_00_100_0_0_0_0_0; // fcvt.d.wu wu->d
5'b00010: ControlsD = `FCTRLW'b1_0_01_00_111_0_0_0_0_0; // fcvt.d.l l->d
5'b00011: ControlsD = `FCTRLW'b1_0_01_00_110_0_0_0_0_0; // fcvt.d.lu lu->d
5'b00010: if (P.XLEN == 64) ControlsD = `FCTRLW'b1_0_01_00_111_0_0_0_0_0; // fcvt.d.l l->d
5'b00011: if (P.XLEN == 64) ControlsD = `FCTRLW'b1_0_01_00_110_0_0_0_0_0; // fcvt.d.lu lu->d
endcase
7'b1100001: case(Rs2D)
5'b00000: ControlsD = `FCTRLW'b0_1_01_00_001_0_0_1_0_0; // fcvt.w.d d->w
5'b00001: ControlsD = `FCTRLW'b0_1_01_00_000_0_0_1_0_0; // fcvt.wu.d d->wu
5'b00010: ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1_0_0; // fcvt.l.d d->l
5'b00011: ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1_0_0; // fcvt.lu.d d->lu
5'b00010: if (P.XLEN == 64) ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1_0_0; // fcvt.l.d d->l
5'b00011: if (P.XLEN == 64) ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1_0_0; // fcvt.lu.d d->lu
5'b01000: if (P.ZFA_SUPPORTED & P.D_SUPPORTED & Funct3D == 3'b001)
ControlsD = `FCTRLW'b0_1_01_00_001_0_0_1_1_0; // fcvtmod.w.d (Zfa)
endcase
7'b1101010: case(Rs2D)
5'b00000: ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0_0_0; // fcvt.h.w w->h
5'b00001: ControlsD = `FCTRLW'b1_0_01_00_100_0_0_0_0_0; // fcvt.h.wu wu->h
5'b00010: ControlsD = `FCTRLW'b1_0_01_00_111_0_0_0_0_0; // fcvt.h.l l->h
5'b00011: ControlsD = `FCTRLW'b1_0_01_00_110_0_0_0_0_0; // fcvt.h.lu lu->h
5'b00010: if (P.XLEN == 64) ControlsD = `FCTRLW'b1_0_01_00_111_0_0_0_0_0; // fcvt.h.l l->h
5'b00011: if (P.XLEN == 64) ControlsD = `FCTRLW'b1_0_01_00_110_0_0_0_0_0; // fcvt.h.lu lu->h
endcase
7'b1100010: case(Rs2D)
5'b00000: ControlsD = `FCTRLW'b0_1_01_00_001_0_0_1_0_0; // fcvt.w.h h->w
5'b00001: ControlsD = `FCTRLW'b0_1_01_00_000_0_0_1_0_0; // fcvt.wu.h h->wu
5'b00010: ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1_0_0; // fcvt.l.h h->l
5'b00011: ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1_0_0; // fcvt.lu.h h->lu
5'b00010: if (P.XLEN == 64) ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1_0_0; // fcvt.l.h h->l
5'b00011: if (P.XLEN == 64) ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1_0_0; // fcvt.lu.h h->lu
endcase
// Not covered in testing because rv64gc does not support quad precision
// coverage off
7'b1101011: case(Rs2D)
5'b00000: ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0_0_0; // fcvt.q.w w->q
5'b00001: ControlsD = `FCTRLW'b1_0_01_00_100_0_0_0_0_0; // fcvt.q.wu wu->q
5'b00010: ControlsD = `FCTRLW'b1_0_01_00_111_0_0_0_0_0; // fcvt.q.l l->q
5'b00011: ControlsD = `FCTRLW'b1_0_01_00_110_0_0_0_0_0; // fcvt.q.lu lu->q
5'b00010: if (P.XLEN == 64) ControlsD = `FCTRLW'b1_0_01_00_111_0_0_0_0_0; // fcvt.q.l l->q
5'b00011: if (P.XLEN == 64) ControlsD = `FCTRLW'b1_0_01_00_110_0_0_0_0_0; // fcvt.q.lu lu->q
endcase
7'b1100011: case(Rs2D)
5'b00000: ControlsD = `FCTRLW'b0_1_01_00_001_0_0_1_0_0; // fcvt.w.q q->w
5'b00001: ControlsD = `FCTRLW'b0_1_01_00_000_0_0_1_0_0; // fcvt.wu.q q->wu
5'b00010: ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1_0_0; // fcvt.l.q q->l
5'b00011: ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1_0_0; // fcvt.lu.q q->lu
5'b00010: if (P.XLEN == 64) ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1_0_0; // fcvt.l.q q->l
5'b00011: if (P.XLEN == 64) ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1_0_0; // fcvt.lu.q q->lu
endcase
// coverage off
// Not covered in testing because rv64gc is not RV64Q or RV32D

2
src/fpu/fdivsqrt/fdivsqrtiter.sv
View file

@ -38,7 +38,6 @@ module fdivsqrtiter import cvw::*; #(parameter cvw_t P) (
output logic [P.DIVb+3:0] FirstWS, FirstWC // Q4.DIVb
);
/* verilator lint_off UNOPTFLAT */
logic [P.DIVb+3:0] WSNext[P.DIVCOPIES-1:0]; // Q4.DIVb
logic [P.DIVb+3:0] WCNext[P.DIVCOPIES-1:0]; // Q4.DIVb
logic [P.DIVb+3:0] WS[P.DIVCOPIES:0]; // Q4.DIVb
@ -56,7 +55,6 @@ module fdivsqrtiter import cvw::*; #(parameter cvw_t P) (
logic [P.DIVb+1:0] NextC; // Q2.DIVb
logic [P.DIVb:0] UMux, UMMux; // U1.DIVb
logic [P.DIVb:0] initU, initUM; // U1.DIVb
/* verilator lint_on UNOPTFLAT */
// Top Muxes and Registers
// When start is asserted, the inputs are loaded into the divider.

2
src/fpu/fdivsqrt/fdivsqrtpreproc.sv
View file

@ -136,7 +136,7 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) (
// calculate right shift amount RightShiftX to complete in discrete number of steps
if (P.RK > 1) begin // more than 1 bit per cycle
logic [$clog2(P.RK)-1:0] RightShiftX;
/* verilator lint_offf WIDTH */
/* verilator lint_off WIDTH */
assign RightShiftX = P.RK - 1 - ((IntResultBitsE - 1) % P.RK); // Right shift amount
assign DivXShifted = DivX >> RightShiftX; // shift X by up to R*K-1 to complete in n steps
/* verilator lint_on WIDTH */

2
src/fpu/fdivsqrt/fdivsqrtstage2.sv
View file

@ -28,7 +28,6 @@
////////////////////////////////////////////////////////////////////////////////////////////////
/* verilator lint_off UNOPTFLAT */
module fdivsqrtstage2 import cvw::*; #(parameter cvw_t P) (
input logic [P.DIVb+3:0] D, DBar, // Q4.DIVb
input logic [P.DIVb:0] U, UM, // U1.DIVb
@ -40,7 +39,6 @@ module fdivsqrtstage2 import cvw::*; #(parameter cvw_t P) (
output logic [P.DIVb:0] UNext, UMNext, // U1.DIVb
output logic [P.DIVb+3:0] WSNext, WCNext // Q4.DIVb
);
/* verilator lint_on UNOPTFLAT */
logic [P.DIVb+3:0] Dsel; // Q4.DIVb
logic up, uz;

9
src/fpu/fround.sv
View file

@ -115,9 +115,9 @@ module fround import cvw::*; #(parameter cvw_t P) (
///////////////////////////
// Exact logic
// verilator lint_off WIDTHEXPAND
/* verilator lint_off WIDTHEXPAND */
assign EgeNf = (E >= Nf) & Xe[P.NE-1]; // Check if E >= Nf. Also check that Xe is positive to avoid wraparound problems
// verilator lint_on WIDTHEXPAND
/* verilator lint_on WIDTHEXPAND */
// Rounding logic: determine whether to round up in magnitude
always_comb begin
@ -146,7 +146,8 @@ module fround import cvw::*; #(parameter cvw_t P) (
packoutput #(P) packoutput(W, Fmt, FRound); // pack and NaN-box based on selected format.
// Flags
assign FRoundNV = XSNaN; // invalid if input is signaling NaN
assign FRoundNX = ZfaFRoundNX & ~EgeNf & (Rp | Tp); // Inexact if Round or Sticky bit set for FRoundNX instruction
assign FRoundNV = XSNaN; // invalid if input is signaling NaN
assign FRoundNX = ZfaFRoundNX & ~EgeNf & (Rp | Tp) & ~XNaN; // Inexact if Round or Sticky bit set for FRoundNX instruction
// Note: NX must not be raised if input is invalid
endmodule

2
src/generic/prioritythermometer.sv
View file

@ -39,11 +39,9 @@ module prioritythermometer #(parameter N = 8) (
// Rather than linear.
// create thermometer code mask
/* verilator lint_off UNOPTFLAT */
genvar i;
assign y[0] = ~a[0];
for (i=1; i<N; i++) begin:therm
assign y[i] = y[i-1] & ~a[i];
end
/* verilator lint_on UNOPTFLAT */
endmodule

2
src/hazard/hazard.sv
View file

@ -27,7 +27,7 @@
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module hazard import cvw::*; #(parameter cvw_t P) (
module hazard (
input logic BPWrongE, CSRWriteFenceM, RetM, TrapM,
input logic StructuralStallD,
input logic LSUStallM, IFUStallF, FetchBufferStallF,

21
src/ieu/bmu/bmuctrl.sv
View file

@ -119,13 +119,11 @@ module bmuctrl import cvw::*; #(parameter cvw_t P) (
if (P.ZBC_SUPPORTED)
casez({OpD, Funct7D, Funct3D})
17'b0110011_0000101_010: BMUControlsD = `BMUCTRLW'b000_0011_0001_1_0_0_0_1_0_0_0_0_0; // clmulr
17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_0011_0000_1_0_0_0_1_0_0_0_0_0; // clmul/clmulh
17'b0110011_0000101_0?1: BMUControlsD = `BMUCTRLW'b000_0011_0000_1_0_0_0_1_0_0_0_0_0; // clmul/clmulh
endcase
if (P.ZBKC_SUPPORTED) begin
casez({OpD, Funct7D, Funct3D})
17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_0011_0000_1_0_0_0_1_0_0_0_0_0; // clmul/clmulh
// 17'b0110011_0000101_001: BMUControlsD = `BMUCTRLW'b000_0011_0000_1_0_0_0_1_0_0_0_0_0; // clmul
// 17'b0110011_0000101_011: BMUControlsD = `BMUCTRLW'b000_0011_0001_1_0_0_0_1_0_0_0_0_0; // clmulh
17'b0110011_0000101_0?1: BMUControlsD = `BMUCTRLW'b000_0011_0000_1_0_0_0_1_0_0_0_0_0; // clmul/clmulh
endcase
end
@ -153,10 +151,17 @@ module bmuctrl import cvw::*; #(parameter cvw_t P) (
end
if (P.ZBB_SUPPORTED | P.ZBS_SUPPORTED) // rv32i/64i shift instructions need BMU ALUSelect when BMU shifter is used
casez({OpD, Funct7D, Funct3D})
17'b0110011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_0000_1_0_0_0_1_0_0_0_0_0; // sra, srl, sll
17'b0010011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_0000_1_1_0_0_1_0_0_0_0_0; // srai, srli, slli
17'b0111011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_0000_1_0_1_0_1_0_0_0_0_0; // sraw, srlw, sllw
17'b0011011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_0000_1_1_1_0_1_0_0_0_0_0; // sraiw, srliw, slliw
// variable shifts don't encode shift amount in funct7
17'b0110011_0000000_001: BMUControlsD = `BMUCTRLW'b001_0000_0000_1_0_0_0_1_0_0_0_0_0; // sll
17'b0110011_0?00000_101: BMUControlsD = `BMUCTRLW'b001_0000_0000_1_0_0_0_1_0_0_0_0_0; // sra, srl
// Immediate Shifts by more than 32 (Funct7[0]) are only supported in RV64
17'b0010011_000000?_001: if (P.XLEN == 64 | !Funct7D[0]) BMUControlsD = `BMUCTRLW'b001_0000_0000_1_1_0_0_1_0_0_0_0_0; // slli
17'b0010011_0?0000?_101: if (P.XLEN == 64 | !Funct7D[0]) BMUControlsD = `BMUCTRLW'b001_0000_0000_1_1_0_0_1_0_0_0_0_0; // srai, srli
// w-type shifts only supported in RV64 and must have Funct7[0] = 0 because the shift amount is < 32
17'b0111011_0000000_001: if (P.XLEN == 64) BMUControlsD = `BMUCTRLW'b001_0000_0000_1_0_1_0_1_0_0_0_0_0; // sllw
17'b0111011_0?00000_101: if (P.XLEN == 64) BMUControlsD = `BMUCTRLW'b001_0000_0000_1_0_1_0_1_0_0_0_0_0; // sraw, srlw
17'b0011011_0000000_001: if (P.XLEN == 64) BMUControlsD = `BMUCTRLW'b001_0000_0000_1_1_1_0_1_0_0_0_0_0; // slliw
17'b0011011_0?00000_101: if (P.XLEN == 64) BMUControlsD = `BMUCTRLW'b001_0000_0000_1_1_1_0_1_0_0_0_0_0; // sraiw, srliw
endcase
if (P.ZBKB_SUPPORTED) begin // ZBKB Bitmanip

5
src/ieu/controller.sv
View file

@ -181,8 +181,8 @@ module controller import cvw::*; #(parameter cvw_t P) (
assign Funct7ZeroD = (Funct7D == 7'b0000000); // most R-type instructions
assign Funct7b5D = (Funct7D == 7'b0100000); // srai, sub
assign FunctCZeroD = (Funct3D == 3'b101 | Funct3D == 3'b111) & (Funct7D == 7'b0000111) & P.ZICOND_SUPPORTED; // czero.eqz or czero.nez
assign Funct7ShiftZeroD = (P.XLEN==64) ? (Funct7D[6:1] == 6'b000000) : Funct7ZeroD;
assign Funct7Shiftb5D = (P.XLEN==64) ? (Funct7D[6:1] == 6'b010000) : Funct7b5D;
assign Funct7ShiftZeroD = (P.XLEN==64 & ~OpD[3]) ? (Funct7D[6:1] == 6'b000000) : Funct7ZeroD; // 64-bit logical shifts allowed on XLEN=64, non-W
assign Funct7Shiftb5D = (P.XLEN==64 & ~OpD[3]) ? (Funct7D[6:1] == 6'b010000) : Funct7b5D; // 64-bit arithmetic shifts allowed on XLEN=64, non-W
assign IShiftD = (Funct3D == 3'b001 & Funct7ShiftZeroD) | (Funct3D == 3'b101 & (Funct7ShiftZeroD | Funct7Shiftb5D)); // slli, srli, srai, or w forms
assign INoShiftD = ((Funct3D != 3'b001) & (Funct3D != 3'b101));
assign IFunctD = IShiftD | INoShiftD;
@ -300,7 +300,6 @@ module controller import cvw::*; #(parameter cvw_t P) (
// Squash control signals if coming from an illegal compressed instruction
// On RV32E, can't write to upper 16 registers. Checking reads to upper 16 is more costly so disregard them.
assign IllegalERegAdrD = P.E_SUPPORTED & P.ZICSR_SUPPORTED & ControlsD[`CTRLW-1] & InstrD[11];
//assign IllegalBaseInstrD = 1'b0;
assign {BaseRegWriteD, PreImmSrcD, ALUSrcAD, BaseALUSrcBD, MemRWD,
ResultSrcD, BranchD, ALUOpD, JumpD, ALUResultSrcD, BaseW64D, CSRReadD,
PrivilegedD, FenceXD, MDUD, AtomicD, CMOD, unused} = IllegalIEUFPUInstrD ? `CTRLW'b0 : ControlsD;

2
src/ifu/ifu.sv
View file

@ -238,7 +238,7 @@ module ifu import cvw::*; #(parameter cvw_t P) (
assign BusRW = ~ITLBMissF & ~CacheableF & ~SelIROM ? IFURWF : '0;
assign CacheRWF = ~ITLBMissF & CacheableF & ~SelIROM ? IFURWF : '0;
cache #(.P(P), .PA_BITS(P.PA_BITS), .XLEN(P.XLEN), .LINELEN(P.ICACHE_LINELENINBITS),
cache #(.P(P), .PA_BITS(P.PA_BITS), .LINELEN(P.ICACHE_LINELENINBITS),
.NUMSETS(P.ICACHE_WAYSIZEINBYTES*8/P.ICACHE_LINELENINBITS),
.NUMWAYS(P.ICACHE_NUMWAYS), .LOGBWPL(AHBWLOGBWPL), .WORDLEN(32), .MUXINTERVAL(16), .READ_ONLY_CACHE(1))
icache(.clk, .reset, .FlushStage(FlushD), .Stall(GatedStallD),

4
src/lsu/lsu.sv
View file

@ -121,11 +121,9 @@ module lsu import cvw::*; #(parameter cvw_t P) (
logic DCacheCommittedM; // D$ memory operation started, delay interrupts
logic [P.LLEN-1:0] DTIMReadDataWordM; // DTIM read data
/* verilator lint_off WIDTHEXPAND */
logic [MLEN-1:0] DCacheReadDataWordM; // D$ read data
logic [MLEN-1:0] LSUWriteDataSpillM; // Final write data
logic [MLEN/8-1:0] ByteMaskSpillM; // Selects which bytes within a word to write
/* verilator lint_on WIDTHEXPAND */
logic [P.LLEN-1:0] DCacheReadDataWordSpillM; // D$ read data
logic [P.LLEN-1:0] ReadDataWordMuxM; // DTIM or D$ read data
logic [P.LLEN-1:0] LittleEndianReadDataWordM; // Endian-swapped read data
@ -326,7 +324,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
assign CacheRWM = (CacheableM & ~SelDTIM) ? LSURWM : '0;
assign FlushDCache = FlushDCacheM & ~(SelHPTW);
cache #(.P(P), .PA_BITS(P.PA_BITS), .XLEN(P.XLEN), .LINELEN(P.DCACHE_LINELENINBITS), .NUMSETS(P.DCACHE_WAYSIZEINBYTES*8/LINELEN),
cache #(.P(P), .PA_BITS(P.PA_BITS), .LINELEN(P.DCACHE_LINELENINBITS), .NUMSETS(P.DCACHE_WAYSIZEINBYTES*8/LINELEN),
.NUMWAYS(P.DCACHE_NUMWAYS), .LOGBWPL(LLENLOGBWPL), .WORDLEN(CACHEWORDLEN), .MUXINTERVAL(P.LLEN), .READ_ONLY_CACHE(0)) dcache(
.clk, .reset, .Stall(GatedStallW & ~SelSpillE), .SelBusBeat, .FlushStage(LSUFlushW),
.CacheRW(CacheRWM),

4
src/mdu/divstep.sv
View file

@ -27,8 +27,6 @@
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
/* verilator lint_off UNOPTFLAT */
module divstep #(parameter XLEN) (
input logic [XLEN-1:0] W, // Residual in
input logic [XLEN-1:0] XQ, // bits of dividend X and quotient Q in
@ -46,5 +44,3 @@ module divstep #(parameter XLEN) (
assign qi = ~qib;
mux2 #(XLEN) wrestoremux(WShift, WPrime, qi, WOut); // if quotient is zero, restore W
endmodule
/* verilator lint_on UNOPTFLAT */

7
src/mmu/tlb/tlbcontrol.sv
View file

@ -61,6 +61,7 @@ module tlbcontrol import cvw::*; #(parameter cvw_t P, ITLB = 0) (
logic TLBAccess;
logic ImproperPrivilege;
logic BadPBMT, BadNAPOT, BadReserved;
logic ReservedEncoding;
logic InvalidAccess;
logic PreUpdateDA, PrePageFault;
@ -88,6 +89,7 @@ module tlbcontrol import cvw::*; #(parameter cvw_t P, ITLB = 0) (
assign BadPBMT = ((PTE_PBMT != 0) & ~(P.SVPBMT_SUPPORTED & ENVCFG_PBMTE)) | PTE_PBMT == 3; // PBMT must be zero if not supported; value of 3 is reserved
assign BadNAPOT = PTE_N & (~P.SVNAPOT_SUPPORTED | ~NAPOT4); // N must be be 0 if CVNAPOT is not supported or not 64 KiB contiguous region
assign BadReserved = PTE_RESERVED; // Reserved bits must be zero
assign ReservedEncoding = PTE_W & ~PTE_R; // fault on reserved encoding with R=0, W=1 to match ImperasDV behavior
// Check whether the access is allowed, page faulting if not.
if (ITLB == 1) begin:itlb // Instruction TLB fault checking
@ -95,9 +97,9 @@ module tlbcontrol import cvw::*; #(parameter cvw_t P, ITLB = 0) (
// only execute non-user mode pages.
assign ImproperPrivilege = ((PrivilegeModeW == P.U_MODE) & ~PTE_U) | ((PrivilegeModeW == P.S_MODE) & PTE_U);
assign PreUpdateDA = ~PTE_A;
assign InvalidAccess = ~PTE_X;
assign InvalidAccess = ~PTE_X | ReservedEncoding;
end else begin:dtlb // Data TLB fault checking
logic InvalidRead, InvalidWrite, ReservedEncoding;
logic InvalidRead, InvalidWrite;
logic InvalidCBOM, InvalidCBOZ;
// User mode may only load/store from user mode pages, and supervisor mode
@ -112,7 +114,6 @@ module tlbcontrol import cvw::*; #(parameter cvw_t P, ITLB = 0) (
assign InvalidWrite = WriteAccess & ~PTE_W;
assign InvalidCBOM = (|CMOpM[2:0]) & (~PTE_R & (~STATUS_MXR | ~PTE_X));
assign InvalidCBOZ = CMOpM[3] & ~PTE_W;
assign ReservedEncoding = PTE_W & ~PTE_R; // fault on reserved encoding with R=0, W=1 to match ImperasDV behavior
assign InvalidAccess = InvalidRead | InvalidWrite | InvalidCBOM | InvalidCBOZ | ReservedEncoding;
assign PreUpdateDA = ~PTE_A | WriteAccess & ~PTE_D;
end

2
src/mmu/tlb/tlbram.sv
View file

@ -51,6 +51,6 @@ module tlbram import cvw::*; #(parameter cvw_t P,
or_rows #(TLB_ENTRIES, P.XLEN) PTEOr(RamRead, PageTableEntry);
// Rename the bits read from the TLB RAM
assign PTEAccessBits = {PageTableEntry[P.XLEN-1:P.XLEN-4] & {4{P.XLEN == 64}}, PageTableEntry[7:0]}; // for RV64 include N and PBMT bits and OR of reserved bitss
assign PTEAccessBits = {PageTableEntry[P.XLEN-1:P.XLEN-4] & {4{P.XLEN == 64}}, PageTableEntry[7:0]}; // for RV64 include N and PBMT bits and OR of reserved bits
assign PPN = PageTableEntry[P.PPN_BITS+9:10];
endmodule

2
src/privileged/csrm.sv
View file

@ -88,6 +88,7 @@ module csrm import cvw::*; #(parameter cvw_t P) (
// .. up to 15 more at consecutive addresses
localparam PMPADDR0 = 12'h3B0;
// ... up to 63 more at consecutive addresses
/* verilator lint_off UNUSEDPARAM */
localparam TSELECT = 12'h7A0;
localparam TDATA1 = 12'h7A1;
localparam TDATA2 = 12'h7A2;
@ -96,6 +97,7 @@ module csrm import cvw::*; #(parameter cvw_t P) (
localparam DPC = 12'h7B1;
localparam DSCRATCH0 = 12'h7B2;
localparam DSCRATCH1 = 12'h7B3;
/* verilator lint_off UNUSEDPARAM */
// Constants
localparam ZERO = {(P.XLEN){1'b0}};
// when compressed instructions are supported, there can't be misaligned instructions

2
src/privileged/csrs.sv
View file

@ -67,8 +67,6 @@ module csrs import cvw::*; #(parameter cvw_t P) (
localparam STIMECMPH = 12'h15D;
localparam SATP = 12'h180;
// Constants
localparam ZERO = {(P.XLEN){1'b0}};
localparam SEDELEG_MASK = ~(ZERO | {{P.XLEN-3{1'b0}}, 3'b111} << 9);
logic WriteSTVECM;
logic WriteSSCRATCHM, WriteSEPCM;

2
src/privileged/privdec.sv
View file

@ -59,7 +59,7 @@ module privdec import cvw::*; #(parameter cvw_t P) (
// svinval instructions
// any svinval instruction is treated as sfence.vma on Wally
assign sinvalvmaM = (InstrM[31:25] == 7'b0001001);
assign sinvalvmaM = (InstrM[31:25] == 7'b0001011);
assign sfencewinvalM = (InstrM[31:20] == 12'b000110000000) & rs1zeroM;
assign sfenceinvalirM = (InstrM[31:20] == 12'b000110000001) & rs1zeroM;
assign invalM = P.SVINVAL_SUPPORTED & (sinvalvmaM | sfencewinvalM | sfenceinvalirM);

2
src/uncore/clint_apb.sv
View file

@ -115,7 +115,7 @@ module clint_apb import cvw::*; #(parameter cvw_t P) (
always_ff @(posedge PCLK)
if (~PRESETn) begin
MSIP <= 1'b0;
MTIMECMP <= '0;
MTIMECMP <= 64'hFFFFFFFFFFFFFFFF; // Spec says MTIMECMP is not reset, but we reset to maximum value to prevent spurious timer interrupts
end else if (memwrite) begin
if (entry == 16'h0000) MSIP <= PWDATA[0];
if (entry == 16'h4000)

2
src/uncore/ram_ahb.sv
View file

@ -28,7 +28,7 @@
////////////////////////////////////////////////////////////////////////////////////////////////
module ram_ahb import cvw::*; #(parameter cvw_t P,
parameter BASE=0, RANGE = 65535, PRELOAD = 0) (
parameter RANGE = 65535, PRELOAD = 0) (
input logic HCLK, HRESETn,
input logic HSELRam,
input logic [P.PA_BITS-1:0] HADDR,

2
src/uncore/rom_ahb.sv
View file

@ -28,7 +28,7 @@
////////////////////////////////////////////////////////////////////////////////////////////////
module rom_ahb import cvw::*; #(parameter cvw_t P,
parameter BASE=0, RANGE = 65535, PRELOAD = 0) (
parameter RANGE = 65535, PRELOAD = 0) (
input logic HCLK, HRESETn,
input logic HSELRom,
input logic [P.PA_BITS-1:0] HADDR,

12
src/uncore/spi_apb.sv
View file

@ -114,7 +114,7 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
/* verilator lint_off UNDRIVEN */
logic [2:0] TransmitWriteWatermarkLevel, ReceiveReadWatermarkLevel; // unused generic FIFO outputs
/* verilator lint_off UNDRIVEN */
/* verilator lint_on UNDRIVEN */
logic [7:0] ReceiveShiftRegEndian; // Reverses ReceiveShiftReg if Format[2] set (little endian transmission)
// Shift reg signals
@ -174,17 +174,13 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
SPI_CSMODE: ChipSelectMode <= Din[1:0];
SPI_DELAY0: Delay0 <= {Din[23:16], Din[7:0]};
SPI_DELAY1: Delay1 <= {Din[23:16], Din[7:0]};
SPI_FMT: Format <= {Din[19:16], Din[2]};
SPI_FMT: Format <= {Din[19:16], Din[2]};
SPI_TXDATA: if (~TransmitFIFOFull) TransmitData[7:0] <= Din[7:0];
SPI_TXMARK: TransmitWatermark <= Din[2:0];
SPI_RXMARK: ReceiveWatermark <= Din[2:0];
SPI_IE: InterruptEnable <= Din[1:0];
endcase
if (Memwrite)
case(Entry)
SPI_TXDATA: if (~TransmitFIFOFull) TransmitData[7:0] <= Din[7:0];
endcase
/* verilator lint_off CASEINCOMPLETE */
/* verilator lint_on CASEINCOMPLETE */
// According to FU540 spec: Once interrupt is pending, it will remain set until number
// of entries in tx/rx fifo is strictly more/less than tx/rxmark

41
src/uncore/spi_controller.sv
View file

@ -75,6 +75,7 @@ module spi_controller (
logic ShiftEdgePulse;
logic SampleEdgePulse;
logic EndOfFramePulse;
logic InvertClock;
// Frame stuff
logic [3:0] BitNum;
@ -107,8 +108,8 @@ module spi_controller (
logic [7:0] DelayCounter;
logic DelayIsNext;
logic DelayState;
logic DelayState;
// Convenient Delay Reg Names
assign cssck = Delay0[7:0];
assign sckcs = Delay0[15:8];
@ -130,10 +131,6 @@ module spi_controller (
assign EndOfDelay = EndOfCSSCK | EndOfSCKCS | EndOfINTERCS | EndOfINTERXFR;
// Clock Signal Stuff -----------------------------------------------
// I'm going to handle all clock stuff here, including ShiftEdge and
// SampleEdge. This makes sure that SPICLK is an output of a register
// and it properly synchronizes signals.
// SPI enable generation, where SCLK = PCLK/(2*(SckDiv + 1))
// Asserts SCLKenable at the rising and falling edge of SCLK by counting from 0 to SckDiv
// Active at 2x SCLK frequency to account for implicit half cycle delays and actions on both clock edges depending on phase
@ -166,12 +163,14 @@ module spi_controller (
end
// SPICLK Logic
// We only want to trigger the clock during Transmission.
// If Phase == 1, then we want to trigger as soon as NextState == TRANSMIT
// Otherwise, only trigger the clock when the CurrState is TRANSMIT.
// We never want to trigger the clock if the NextState is NOT TRANSMIT
if (TransmitStart & ~DelayState) begin
SPICLK <= SckMode[1];
end else if (SCLKenable) begin
if (Phase & (NextState == TRANSMIT)) SPICLK <= (~EndTransmission & ~DelayIsNext) ? ~SPICLK : SckMode[1];
else if (Transmitting) SPICLK <= (~EndTransmission & ~DelayIsNext) ? ~SPICLK : SckMode[1];
end else if (SCLKenable) begin
SPICLK <= (NextState == TRANSMIT) & (~Phase & Transmitting | Phase) ? ~SPICLK : SckMode[1];
end
// Reset divider
@ -201,32 +200,25 @@ module spi_controller (
// Possible pulses for all edge types. Combined with SPICLK to get
// edges for different phase and polarity modes.
assign ShiftEdgePulse = EdgePulse & ~LastBit;
assign SampleEdgePulse = EdgePulse & ~DelayIsNext;
assign SampleEdgePulse = EdgePulse & (NextState == TRANSMIT);
assign EndOfFramePulse = EdgePulse & LastBit;
// Delay ShiftEdge and SampleEdge by a half PCLK period
// Aligned EXACTLY ON THE MIDDLE of the leading and trailing edges.
// Sweeeeeeeeeet...
assign InvertClock = ^SckMode;
always_ff @(posedge ~PCLK) begin
if (~PRESETn | TransmitStart) begin
ShiftEdge <= 0;
SampleEdge <= 0;
EndOfFrame <= 0;
end else if (^SckMode) begin
ShiftEdge <= ~SPICLK & ShiftEdgePulse;
SampleEdge <= SPICLK & SampleEdgePulse;
EndOfFrame <= ~SPICLK & EndOfFramePulse;
end else begin
ShiftEdge <= SPICLK & ShiftEdgePulse;
SampleEdge <= ~SPICLK & SampleEdgePulse;
EndOfFrame <= SPICLK & EndOfFramePulse;
end
end else begin
ShiftEdge <= (InvertClock ^ SPICLK) & ShiftEdgePulse;
SampleEdge <= (InvertClock ^ ~SPICLK) & SampleEdgePulse;
EndOfFrame <= (InvertClock ^ SPICLK) & EndOfFramePulse;
end
end
// Logic for continuing to transmit through Delay states after end of frame
assign NextEndDelay = NextState == SCKCS | NextState == INTERCS | NextState == INTERXFR;
assign CurrentEndDelay = CurrState == SCKCS | CurrState == INTERCS | CurrState == INTERXFR;
always_ff @(posedge PCLK) begin
if (~PRESETn) begin
CurrState <= INACTIVE;
@ -305,7 +297,6 @@ module spi_controller (
end
assign Transmitting = CurrState == TRANSMIT;
assign DelayIsNext = (NextState == CSSCK | NextState == SCKCS | NextState == INTERCS | NextState == INTERXFR);
assign DelayState = (CurrState == CSSCK | CurrState == SCKCS | CurrState == INTERCS | CurrState == INTERXFR);
assign InactiveState = CurrState == INACTIVE | CurrState == INTERCS;

2
src/uncore/spi_fifo.sv
View file

@ -26,7 +26,7 @@ module spi_fifo #(parameter M=3, N=8)( // 2^M entries of N bits
assign rdata = mem[raddr];
always_ff @(posedge PCLK)
if (winc & ~wfull) mem[waddr] <= wdata;
if (winc & wen & ~wfull) mem[waddr] <= wdata;
// write and read are enabled
always_ff @(posedge PCLK)

4
src/uncore/uartPC16550D.sv
View file

@ -335,10 +335,10 @@ module uartPC16550D #(parameter UART_PRESCALE) (
end
assign rxfifoempty = (rxfifohead == rxfifotail);
// verilator lint_off WIDTH
/* verilator lint_off WIDTH */
assign rxfifoentries = (rxfifohead >= rxfifotail) ? (rxfifohead-rxfifotail) :
(rxfifohead + 16 - rxfifotail);
// verilator lint_on WIDTH
/* verilator lint_on WIDTH */
assign rxfifotriggered = rxfifoentries >= rxfifotriggerlevel;
assign rxfifotimeout = rxtimeoutcnt == {rxbitsexpected, 6'b0}; // time out after 4 character periods; probably not right yet
//assign rxfifotimeout = 0; // disabled pending fix

4
src/uncore/uncore.sv
View file

@ -109,13 +109,13 @@ module uncore import cvw::*; #(parameter cvw_t P)(
// on-chip RAM
if (P.UNCORE_RAM_SUPPORTED) begin : ram
ram_ahb #(.P(P), .BASE(P.UNCORE_RAM_BASE), .RANGE(P.UNCORE_RAM_RANGE), .PRELOAD(P.UNCORE_RAM_PRELOAD)) ram (
ram_ahb #(.P(P), .RANGE(P.UNCORE_RAM_RANGE), .PRELOAD(P.UNCORE_RAM_PRELOAD)) ram (
.HCLK, .HRESETn, .HSELRam, .HADDR, .HWRITE, .HREADY,
.HTRANS, .HWDATA, .HWSTRB, .HREADRam, .HRESPRam, .HREADYRam);
end else assign {HREADRam, HRESPRam, HREADYRam} = '0;
if (P.BOOTROM_SUPPORTED) begin : bootrom
rom_ahb #(.P(P), .BASE(P.BOOTROM_BASE), .RANGE(P.BOOTROM_RANGE), .PRELOAD(P.BOOTROM_PRELOAD))
rom_ahb #(.P(P), .RANGE(P.BOOTROM_RANGE), .PRELOAD(P.BOOTROM_PRELOAD))
bootrom(.HCLK, .HRESETn, .HSELRom(HSELBootRom), .HADDR, .HREADY, .HTRANS,
.HREADRom(HREADBootRom), .HRESPRom(HRESPBootRom), .HREADYRom(HREADYBootRom));
end else assign {HREADBootRom, HRESPBootRom, HREADYBootRom} = '0;

2
src/wally/wallypipelinedcore.sv
View file

@ -274,7 +274,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
end
// global stall and flush control
hazard #(P) hzu(
hazard hzu(
.BPWrongE, .CSRWriteFenceM, .RetM, .TrapM,
.StructuralStallD,
.LSUStallM, .IFUStallF, .FetchBufferStallF,

8
testbench/Makefile
View file

@ -2,11 +2,11 @@
# David_Harris@hmc.edu 3 July 2024
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
%.elf.memfile: %.elf
%.memfile: %
riscv64-unknown-elf-elf2hex --bit-width $(if $(findstring rv32,$*),32,64) --input $< --output $@
%.elf.objdump.addr: %.elf.objdump
%.objdump.addr: %.objdump
extractFunctionRadix.sh $<
%.elf.objdump: %.elf
riscv64-unknown-elf-objdump -S -D $< > $@
%.objdump: %
riscv64-unknown-elf-objdump -S -D $< > $@

2
testbench/common/functionName.sv
View file

@ -70,7 +70,7 @@ module FunctionName import cvw::*; #(parameter cvw_t P) (
begin
if ( pc == 0 ) begin
// *** want to keep the old value for mid and minval
// want to keep the old value for mid and minval
mid = 0;
return;
end

4
testbench/common/instrNameDecTB.sv
View file

@ -219,6 +219,10 @@ module instrNameDecTB(
else if (imm == 258) name = "SRET";
else if (imm == 770) name = "MRET";
else if (funct7 == 9) name = "SFENCE.VMA";
else if (funct7 == 11) name = "SINVAL.VMA";
else if (funct7 == 12 & rs2 == 0) name = "SFENCE.W.INVAL";
else if (funct7 == 12 & rs2 == 1) name = "SFENCE.INVAL.IR";
else if (imm == 259) name = "WFI";
else if (imm == 261) name = "WFI";
else name = "ILLEGAL";
10'b1110011_001: name = "CSRRW";

24
testbench/common/loggers.sv
View file

@ -50,8 +50,9 @@ module loggers import cvw::*; #(parameter cvw_t P,
integer HPMCindex;
logic StartSampleFirst;
logic StartSampleDelayed, BeginDelayed;
logic EndSampleFirst, EndSampleDelayed;
logic EndSampleFirst;
logic [P.XLEN-1:0] InitialHPMCOUNTERH[P.COUNTERS-1:0];
logic EndSampleDelayed;
string HPMCnames[] = '{"Mcycle",
"------",
@ -80,6 +81,7 @@ module loggers import cvw::*; #(parameter cvw_t P,
"Divide Cycles"
};
always_comb
if (TEST == "embench") begin
StartSampleFirst = FunctionName.FunctionName.FunctionName == "start_trigger";
@ -89,9 +91,17 @@ module loggers import cvw::*; #(parameter cvw_t P,
EndSampleFirst = FunctionName.FunctionName.FunctionName == "stop_time";
end else begin
StartSampleFirst = reset;
EndSample = DCacheFlushStart & ~DCacheFlushDone;
EndSampleFirst = '0;
end
flopr #(1) EndSampleReg(clk, reset, EndSampleFirst, EndSampleDelayed);
always_comb
if (TEST == "embench" | TEST == "coremark") begin
EndSample = EndSampleFirst & ~ EndSampleDelayed;
end else begin
EndSample = DCacheFlushStart & ~DCacheFlushDone;
end
/*
if(TEST == "embench") begin
// embench runs warmup then runs start_trigger
@ -132,8 +142,6 @@ module loggers import cvw::*; #(parameter cvw_t P,
flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed);
assign StartSample = StartSampleFirst & ~StartSampleDelayed;
flopr #(1) EndSampleReg(clk, reset, EndSampleFirst, EndSampleDelayed);
assign EndSample = EndSampleFirst & ~ EndSampleDelayed;
flop #(1) BeginReg(clk, StartSampleFirst, BeginDelayed); // ** is this redundant with StartSampleReg?
assign BeginSample = StartSampleFirst & ~BeginDelayed;
@ -210,10 +218,16 @@ module loggers import cvw::*; #(parameter cvw_t P,
dut.core.lsu.LSUAtomicM[1] ? "A" :
dut.core.lsu.bus.dcache.CacheRWM == 2'b10 ? "R" :
dut.core.lsu.bus.dcache.CacheRWM == 2'b01 ? "W" :
dut.core.lsu.bus.dcache.dcache.CMOpM == 4'b1000 ? "Z" : // cbo.zero
dut.core.lsu.bus.dcache.dcache.CMOpM == 4'b0001 ? "V" : // cbo.inval should just clear the valid and dirty bits
dut.core.lsu.bus.dcache.dcache.CMOpM == 4'b0010 ? "C" : // cbo.clean should act like a read in terms of the lru, but clears the dirty bit
dut.core.lsu.bus.dcache.dcache.CMOpM == 4'b0100 ? "L" : // cbo.flush should just clear and the valid and drity bits
"NULL";
end
assign Enabled = dut.core.lsu.bus.dcache.dcache.cachefsm.LRUWriteEn &
assign Enabled = (dut.core.lsu.bus.dcache.dcache.cachefsm.LRUWriteEn |
// don't include cbo.zero as it uses LRUWriteEn to update the LRU and would be double counted.
((AccessTypeString == "C" | AccessTypeString == "L" | AccessTypeString == "V") & ~dut.core.lsu.bus.dcache.dcache.cachefsm.CacheStall)) &
~dut.core.lsu.bus.dcache.dcache.cachefsm.FlushStage &
dut.core.lsu.dmmu.dmmu.pmachecker.Cacheable &
dut.core.lsu.bus.dcache.dcache.cachefsm.CacheEn &

2
testbench/common/ramxdetector.sv
View file

@ -39,7 +39,7 @@ module ramxdetector #(parameter XLEN, LLEN) (
/* verilator lint_off WIDTHXZEXPAND */
if (MemReadM & ~LSULoadAccessFaultM & (ReadDataM === 'bx)) begin
/* verilator lint_on WIDTHXZEXPAND */
$display("WARNING: Attempting to read from unitialized RAM. Processor may go haywire if it uses x value. But this is normal in WALLY-mmu tests.");
$display("WARNING: Attempting to read from unitialized RAM. Processor may go haywire if it uses x value. But this is normal in WALLY-mmu and ExceptionInstr tests.");
$display(" PCM = %x InstrM = %x (%s), IEUAdrM = %x", PCM, InstrM, InstrMName, IEUAdrM);
//$stop;
end

938
testbench/common/wallyTracer.sv
View file

File diff suppressed because it is too large Load diff

58
testbench/testbench.sv
View file

@ -33,12 +33,6 @@
`include "idv/idv.svh"
`endif
`ifdef RVVI_COVERAGE
`include "RISCV_trace_data.svh"
`include "rvvicov.svh"
`include "wrapper.sv"
`endif
import cvw::*;
module testbench;
@ -50,6 +44,15 @@ module testbench;
parameter I_CACHE_ADDR_LOGGER=0;
parameter D_CACHE_ADDR_LOGGER=0;
parameter RVVI_SYNTH_SUPPORTED=0;
parameter MAKE_VCD=0;
// TREK Requires a license for the Breker tool. See tests/breker/README.md for details
`ifdef USE_TREK_DV
event trek_start;
always @(testbench.trek_start) begin
trek_uvm_pkg::trek_uvm_events::do_backdoor_init();
end
`endif
`ifdef USE_IMPERAS_DV
import idvPkg::*;
@ -181,6 +184,7 @@ module testbench;
"arch64zknd": if (P.ZKND_SUPPORTED) tests = arch64zknd;
"arch64zkne": if (P.ZKNE_SUPPORTED) tests = arch64zkne;
"arch64zknh": if (P.ZKNH_SUPPORTED) tests = arch64zknh;
"arch64pmp": if (P.PMP_ENTRIES > 0) tests = arch64pmp;
endcase
end else begin // RV32
case (TEST)
@ -223,6 +227,8 @@ module testbench;
"arch32zknd": if (P.ZKND_SUPPORTED) tests = arch32zknd;
"arch32zkne": if (P.ZKNE_SUPPORTED) tests = arch32zkne;
"arch32zknh": if (P.ZKNH_SUPPORTED) tests = arch32zknh;
"arch32pmp": if (P.PMP_ENTRIES > 0) tests = arch32pmp;
"arch32vm_sv32": if (P.VIRTMEM_SUPPORTED) tests = arch32vm_sv32;
endcase
end
if (tests.size() == 0 & ElfFile == "none") begin
@ -233,10 +239,10 @@ module testbench;
end
$finish;
end
`ifdef MAKEVCD
$dumpfile("testbench.vcd");
$dumpvars;
`endif
if (MAKE_VCD) begin
$dumpfile("testbench.vcd");
$dumpvars;
end
end // initial begin
// Model the testbench as an fsm.
@ -414,7 +420,11 @@ module testbench;
end else if (TEST == "coverage64gc") begin
$display("%s ran. Coverage tests don't get checked", tests[test]);
end else if (ElfFile != "none") begin
$display("Single Elf file tests are not signatured verified.");
`ifdef USE_TREK_DV
$display("Breker test is done.");
`else
$display("Single Elf file tests are not signatured verified.");
`endif
`ifdef QUESTA
$stop; // if this is changed to $finish for Questa, wally-batch.do does not go to the next step to run coverage, and wally.do terminates without allowing GUI debug
`else
@ -521,6 +531,10 @@ module testbench;
end else begin
$fclose(uncoreMemFile);
$readmemh(memfilename, dut.uncoregen.uncore.ram.ram.memory.ram.RAM);
`ifdef USE_TREK_DV
-> trek_start;
$display("starting Trek....");
`endif
end
end
if (TEST == "embench") $display("Read memfile %s", memfilename);
@ -570,7 +584,7 @@ module testbench;
assign SPIIn = 1'b0;
if(P.EXT_MEM_SUPPORTED) begin
ram_ahb #(.P(P), .BASE(P.EXT_MEM_BASE), .RANGE(P.EXT_MEM_RANGE))
ram_ahb #(.P(P), .RANGE(P.EXT_MEM_RANGE))
ram (.HCLK, .HRESETn, .HADDR, .HWRITE, .HTRANS, .HWDATA, .HSELRam(HSELEXT),
.HREADRam(HRDATAEXT), .HREADYRam(HREADYEXT), .HRESPRam(HRESPEXT), .HREADY, .HWSTRB);
end else begin
@ -869,12 +883,14 @@ end
end
always @(dut.core.priv.priv.csr.csri.MIP_REGW[7]) void'(rvvi.net_push("MTimerInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[7]));
always @(dut.core.priv.priv.csr.csri.MIP_REGW[11]) void'(rvvi.net_push("MExternalInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[11]));
always @(dut.core.priv.priv.csr.csri.MIP_REGW[9]) void'(rvvi.net_push("SExternalInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[9]));
always @(dut.core.priv.priv.csr.csri.MIP_REGW[3]) void'(rvvi.net_push("MSWInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[3]));
always @(dut.core.priv.priv.csr.csri.MIP_REGW[1]) void'(rvvi.net_push("SSWInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[1]));
always @(dut.core.priv.priv.csr.csri.MIP_REGW[5]) void'(rvvi.net_push("STimerInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[5]));
if (P.ZICSR_SUPPORTED) begin
always @(dut.core.priv.priv.csr.csri.MIP_REGW[7]) void'(rvvi.net_push("MTimerInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[7]));
always @(dut.core.priv.priv.csr.csri.MIP_REGW[11]) void'(rvvi.net_push("MExternalInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[11]));
always @(dut.core.priv.priv.csr.csri.MIP_REGW[9]) void'(rvvi.net_push("SExternalInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[9]));
always @(dut.core.priv.priv.csr.csri.MIP_REGW[3]) void'(rvvi.net_push("MSWInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[3]));
always @(dut.core.priv.priv.csr.csri.MIP_REGW[1]) void'(rvvi.net_push("SSWInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[1]));
always @(dut.core.priv.priv.csr.csri.MIP_REGW[5]) void'(rvvi.net_push("STimerInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[5]));
end
final begin
void'(rvviRefShutdown());
@ -973,12 +989,6 @@ test_pmp_coverage #(P) pmp_inst(clk);
/* verilator lint_on WIDTHTRUNC */
/* verilator lint_on WIDTHEXPAND */
`ifdef RVVI_COVERAGE
rvviTrace #(.XLEN(P.XLEN), .FLEN(P.FLEN)) rvvi();
wallyTracer #(P) wallyTracer(rvvi);
wrapper #(P) wrap(clk);
`endif
endmodule
/* verilator lint_on STMTDLY */

115
testbench/tests.vh
View file

@ -149,6 +149,121 @@ string wally32a_lrsc[] = '{
"rv32i_m/privilege/src/WALLY-lrsc-01.S"
};
string arch32pmp[] = '{
`RISCVARCHTEST,
"rv32i_m/pmp32/src/pmp-CFG-reg.S",
"rv32i_m/pmp32/src/pmp-CSR-access.S",
"rv32i_m/pmp32/src/pmp-NA4-R-priority-level-2.S",
"rv32i_m/pmp32/src/pmp-NA4-R-priority.S",
"rv32i_m/pmp32/src/pmp-NA4-R.S",
"rv32i_m/pmp32/src/pmp-NA4-RW-priority-level-2.S",
"rv32i_m/pmp32/src/pmp-NA4-RW-priority.S",
"rv32i_m/pmp32/src/pmp-NA4-RW.S",
"rv32i_m/pmp32/src/pmp-NA4-RWX.S",
"rv32i_m/pmp32/src/pmp-NA4-RX-priority-level-2.S",
"rv32i_m/pmp32/src/pmp-NA4-RX-priority.S",
"rv32i_m/pmp32/src/pmp-NA4-RX.S",
"rv32i_m/pmp32/src/pmp-NA4-X-priority-level-2.S",
"rv32i_m/pmp32/src/pmp-NA4-X-priority.S",
"rv32i_m/pmp32/src/pmp-NA4-X.S",
"rv32i_m/pmp32/src/pmp-NAPOT-R-priority-level-2.S",
"rv32i_m/pmp32/src/pmp-NAPOT-R-priority.S",
"rv32i_m/pmp32/src/pmp-NAPOT-R.S",
"rv32i_m/pmp32/src/pmp-NAPOT-RW-priority-level-2.S",
"rv32i_m/pmp32/src/pmp-NAPOT-RW-priority.S",
"rv32i_m/pmp32/src/pmp-NAPOT-RW.S",
"rv32i_m/pmp32/src/pmp-NAPOT-RWX.S",
"rv32i_m/pmp32/src/pmp-NAPOT-RX-priority-level-2.S",
"rv32i_m/pmp32/src/pmp-NAPOT-RX-priority.S",
"rv32i_m/pmp32/src/pmp-NAPOT-RX.S",
"rv32i_m/pmp32/src/pmp-NAPOT-X-priority-level-2.S",
"rv32i_m/pmp32/src/pmp-NAPOT-X-priority.S",
"rv32i_m/pmp32/src/pmp-NAPOT-X.S",
"rv32i_m/pmp32/src/pmp-TOR-R-priority-level-2.S",
"rv32i_m/pmp32/src/pmp-TOR-R-priority.S",
"rv32i_m/pmp32/src/pmp-TOR-R.S",
"rv32i_m/pmp32/src/pmp-TOR-RW-priority-level-2..S",
"rv32i_m/pmp32/src/pmp-TOR-RW-priority.S",
"rv32i_m/pmp32/src/pmp-TOR-RW.S",
"rv32i_m/pmp32/src/pmp-TOR-RWX.S",
"rv32i_m/pmp32/src/pmp-TOR-RX-priority-level-2.S",
"rv32i_m/pmp32/src/pmp-TOR-RX-priority.S",
"rv32i_m/pmp32/src/pmp-TOR-RX.S",
"rv32i_m/pmp32/src/pmp-TOR-X-priority-level-2.S",
"rv32i_m/pmp32/src/pmp-TOR-X-priority.S",
"rv32i_m/pmp32/src/pmp-TOR-X.S"
};
string arch64pmp[] = '{
`RISCVARCHTEST,
"rv64i_m/pmp64/pmp64-CFG-reg.S",
"rv64i_m/pmp64/pmp64-CSR-access.S",
"rv64i_m/pmp64/pmp64-NA4-R-priority-level-2.S",
"rv64i_m/pmp64/pmp64-NA4-R-priority.S",
"rv64i_m/pmp64/pmp64-NA4-R.S",
"rv64i_m/pmp64/pmp64-NA4-RW-priority-level-2.S",
"rv64i_m/pmp64/pmp64-NA4-RW-priority.S",
"rv64i_m/pmp64/pmp64-NA4-RW.S",
"rv64i_m/pmp64/pmp64-NA4-RWX.S",
"rv64i_m/pmp64/pmp64-NA4-RX-priority-level-2.S",
"rv64i_m/pmp64/pmp64-NA4-RX-priority.S",
"rv64i_m/pmp64/pmp64-NA4-RX.S",
"rv64i_m/pmp64/pmp64-NA4-X-priority-level-2.S",
"rv64i_m/pmp64/pmp64-NA4-X-priority.S",
"rv64i_m/pmp64/pmp64-NA4-X.S",
"rv64i_m/pmp64/pmp64-NAPOT-R-priority-level-2.S",
"rv64i_m/pmp64/pmp64-NAPOT-R-priority.S",
"rv64i_m/pmp64/pmp64-NAPOT-R.S",
"rv64i_m/pmp64/pmp64-NAPOT-RW-priority-level-2.S",
"rv64i_m/pmp64/pmp64-NAPOT-RW-priority.S",
"rv64i_m/pmp64/pmp64-NAPOT-RW.S",
"rv64i_m/pmp64/pmp64-NAPOT-RWX.S",
"rv64i_m/pmp64/pmp64-NAPOT-RX-priority-level-2.S",
"rv64i_m/pmp64/pmp64-NAPOT-RX-priority.S",
"rv64i_m/pmp64/pmp64-NAPOT-RX.S",
"rv64i_m/pmp64/pmp64-NAPOT-X-priority-level-2.S",
"rv64i_m/pmp64/pmp64-NAPOT-X-priority.S",
"rv64i_m/pmp64/pmp64-NAPOT-X.S",
"rv64i_m/pmp64/pmp64-TOR-R-priority-level-2.S",
"rv64i_m/pmp64/pmp64-TOR-R-priority.S",
"rv64i_m/pmp64/pmp64-TOR-R.S",
"rv64i_m/pmp64/pmp64-TOR-RW-priority-level-2..S",
"rv64i_m/pmp64/pmp64-TOR-RW-priority.S",
"rv64i_m/pmp64/pmp64-TOR-RW.S",
"rv64i_m/pmp64/pmp64-TOR-RWX.S",
"rv64i_m/pmp64/pmp64-TOR-RX-priority-level-2.S",
"rv64i_m/pmp64/pmp64-TOR-RX-priority.S",
"rv64i_m/pmp64/pmp64-TOR-RX.S",
"rv64i_m/pmp64/pmp64-TOR-X-priority-level-2.S",
"rv64i_m/pmp64/pmp64-TOR-X-priority.S",
"rv64i_m/pmp64/pmp64-TOR-X.S"
};
string arch32vm_sv32[] = '{
`RISCVARCHTEST,
"rv32i_m/vm_sv32/src/pmp_check_on_pa_S_mode.S",
"rv32i_m/vm_sv32/src/pmp_check_on_pa_U_mode.S",
"rv32i_m/vm_sv32/src/pmp_check_on_pte_S_mode.S",
"rv32i_m/vm_sv32/src/pmp_check_on_pte_U_mode.S",
"rv32i_m/vm_sv32/src/vm_A_and_D_S_mode.S",
"rv32i_m/vm_sv32/src/vm_A_and_D_U_mode.S",
"rv32i_m/vm_sv32/src/vm_invalid_pte_S_mode.S",
"rv32i_m/vm_sv32/src/vm_invalid_pte_U_mode.S",
"rv32i_m/vm_sv32/src/vm_misaligned_S_mode.S",
"rv32i_m/vm_sv32/src/vm_misaligned_U_mode.S",
"rv32i_m/vm_sv32/src/vm_mxr_S_mode.S",
"rv32i_m/vm_sv32/src/vm_mxr_U_mode.S",
"rv32i_m/vm_sv32/src/vm_nleaf_pte_level0_S_mode.S",
"rv32i_m/vm_sv32/src/vm_nleaf_pte_level0_U_mode.S",
"rv32i_m/vm_sv32/src/vm_reserved_pte_S_mode.S",
"rv32i_m/vm_sv32/src/vm_reserved_pte_U_mode.S",
"rv32i_m/vm_sv32/src/vm_sum_set_S_mode.S",
"rv32i_m/vm_sv32/src/vm_sum_unset_S_mode.S",
"rv32i_m/vm_sv32/src/vm_U_Bit_set_U_mode.S",
"rv32i_m/vm_sv32/src/vm_U_Bit_unset_S_mode.S",
"rv32i_m/vm_sv32/src/vm_U_Bit_unset_U_mode.S"
};
string arch64priv[] = '{
`RISCVARCHTEST,
"rv64i_m/privilege/src/ebreak.S",

14
testbench/trek_files/Makefile Normal file
View file

@ -0,0 +1,14 @@
SHELL := /bin/bash
TREKFILES := $(WALLY)/testbench/trek_files
PLATFORM_YAML := $(TREKFILES)/platform.yaml
TREKSVIP_YAML := $(BREKER_HOME)/examples/tutorials/svip/treksvip/yaml/treksvip.yaml
TREKEXE_FLAGS += --seed 0x # free (0x) or lock (0x1) the seed used for test generation
TREKSVIP = source $(TREKFILES)/breker-setup.sh && treksvip -p $(PLATFORM_YAML) -p $(TREKSVIP_YAML) $(TREKEXE_FLAGS)
uvm_output: uvm_output/trek_uvm.sv
uvm_output/trek_uvm.sv: $(PLATFORM_YAML) $(TREKSVIP_YAML)
$(TREKSVIP) -p $(PLATFORM_YAML) -p $(TREKSVIP_YAML) --uvm_output=uvm_output
clean:
rm -rf uvm_output

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