github-mirrors/cvw
1
0
Fork 0
mirror of https://github.com/openhwgroup/cvw.git synced 2025-04-24 13:57:07 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

Improved critical path.

Browse source
This commit is contained in:
Ross Thompson 2023-07-19 14:59:37 -05:00
parent 538efaf771
commit c0966c32e5
1 changed files with 4 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

6
src/mmu/hptw.sv
View file

@ -142,7 +142,7 @@ module hptw import cvw::*; #(parameter cvw_t P) (
if(P.SVADU_SUPPORTED) begin : hptwwrites
logic ReadAccess, WriteAccess;
logic InvalidRead, InvalidWrite, InvalidOp;
logic UpperBitsUnequal;
logic UpperBitsUnequal, UpperBitsUnequalD;
logic OtherPageFault;
logic [1:0] EffectivePrivilegeMode;
logic ImproperPrivilege;
@ -172,10 +172,12 @@ module hptw import cvw::*; #(parameter cvw_t P) (
// Check for page faults
vm64check #(P) vm64check(.SATP_MODE(SATP_REGW[P.XLEN-1:P.XLEN-P.SVMODE_BITS]), .VAdr(TranslationVAdr),
.SV39Mode(), .UpperBitsUnequal);
// This register is not functionally necessary, but improves the critical path.
flopr #(1) upperbitsunequalreg(clk, reset, UpperBitsUnequal, UpperBitsUnequalD);
assign InvalidRead = ReadAccess & ~Readable & (~STATUS_MXR | ~Executable);
assign InvalidWrite = WriteAccess & ~Writable;
assign InvalidOp = DTLBWalk ? (InvalidRead | InvalidWrite) : ~Executable;
assign OtherPageFault = ImproperPrivilege | InvalidOp | UpperBitsUnequal | Misaligned | ~Valid;
assign OtherPageFault = ImproperPrivilege | InvalidOp | UpperBitsUnequalD | Misaligned | ~Valid;
// hptw needs to know if there is a Dirty or Access fault occuring on this
// memory access. If there is the PTE needs to be updated seting Access