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Merge PC and instr FBs

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This commit is contained in:
Corey Hickson 2025-02-25 09:47:19 -08:00
parent f0e6d2bc41
commit c3351c85be
2 changed files with 21 additions and 41 deletions
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57
src/ifu/fetchbuffer.sv
View file

@ -26,25 +26,17 @@
// and limitations under the License. // and limitations under the License.
//////////////////////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////////////////////
module fetchbuffer module fetchbuffer import cvw::*; #(parameter cvw_t P, parameter WIDTH = 32) (
import cvw::*; input logic clk, reset,
#( input logic StallF, StallD, FlushD,
parameter cvw_t P, input logic [WIDTH-1:0] nop,
parameter WIDTH = 32 input logic [P.XLEN + WIDTH-1:0] WriteData,
) ( output logic [P.XLEN + WIDTH-1:0] ReadData,
input logic clk, output logic FetchBufferStallF,
reset, output logic RisingFBStallF
input logic StallF,
StallD,
FlushD,
input logic [WIDTH-1:0] nop,
input logic [WIDTH-1:0] WriteData,
output logic [WIDTH-1:0] ReadData,
output logic FetchBufferStallF,
output logic RisingFBStallF
); );
logic [WIDTH-1:0] ReadReg [P.FETCHBUFFER_ENTRIES-1:0]; logic [P.XLEN + WIDTH-1:0] ReadReg [P.FETCHBUFFER_ENTRIES-1:0];
logic [WIDTH-1:0] ReadFetchBuffer; logic [P.XLEN + WIDTH-1:0] ReadFetchBuffer;
logic [P.FETCHBUFFER_ENTRIES-1:0] ReadPtr, WritePtr; logic [P.FETCHBUFFER_ENTRIES-1:0] ReadPtr, WritePtr;
logic Empty, Full; logic Empty, Full;
@ -52,37 +44,24 @@ module fetchbuffer
assign Full = |({WritePtr[P.FETCHBUFFER_ENTRIES-2:0], WritePtr[P.FETCHBUFFER_ENTRIES-1]} & ReadPtr); // Same as above but left rotate WritePtr to "add 1" assign Full = |({WritePtr[P.FETCHBUFFER_ENTRIES-2:0], WritePtr[P.FETCHBUFFER_ENTRIES-1]} & ReadPtr); // Same as above but left rotate WritePtr to "add 1"
assign FetchBufferStallF = Full; assign FetchBufferStallF = Full;
logic [2:0] fbEnable; logic [P.FETCHBUFFER_ENTRIES-1:0] fbEnable;
logic fbEnable;
logic FetchBufferStallFDelay; logic FetchBufferStallFDelay;
assign RisingFBStallF = ~FetchBufferStallFDelay & FetchBufferStallF; assign RisingFBStallF = ~FetchBufferStallFDelay & FetchBufferStallF;
flop #(1) flop1 ( flop #(1) flop1 (clk, FetchBufferStallF, FetchBufferStallFDelay);
clk, assign fbEnable = WritePtr & {P.FETCHBUFFER_ENTRIES{(~Full | RisingFBStallF)}};
FetchBufferStallF, flopenl #(P.XLEN + WIDTH) fbEntries[P.FETCHBUFFER_ENTRIES-1:0] (.clk, .load(reset | FlushD), .en(fbEnable), .d(WriteData), .val({{P.XLEN{1'b0}}, nop}), .q(ReadReg));
FetchBufferStallFDelay
); logic [P.XLEN + WIDTH-1:0] DaoArr [P.FETCHBUFFER_ENTRIES - 1:0];
assign fbEnable = WritePtr & {3{(~Full | RisingFBStallF)}};
flopenl #(WIDTH) fbEntries[P.FETCHBUFFER_ENTRIES-1:0] (
.clk,
.load(reset | FlushD),
.en(fbEnable),
.d(WriteData),
.val(nop),
.q(ReadReg)
);
for (genvar i = 0; i < P.FETCHBUFFER_ENTRIES; i++) begin for (genvar i = 0; i < P.FETCHBUFFER_ENTRIES; i++) begin
assign DaoArr[i] = ReadPtr[i] ? ReadReg[i] : '0; assign DaoArr[i] = ReadPtr[i] ? ReadReg[i] : '0;
end end
or_rows #(P.FETCHBUFFER_ENTRIES, WIDTH) ReadFBAOMux ( or_rows #(P.FETCHBUFFER_ENTRIES, P.XLEN + WIDTH) ReadFBAOMux (.a(DaoArr), .y(ReadFetchBuffer));
.a(DaoArr),
.y(ReadFetchBuffer)
);
assign ReadData = Empty ? nop : ReadFetchBuffer; assign ReadData = Empty ? {{P.XLEN{1'b0}}, nop} : ReadFetchBuffer;
always_ff @(posedge clk) begin : shiftRegister always_ff @(posedge clk) begin : shiftRegister
if (reset) begin if (reset) begin

5
src/ifu/ifu.sv
View file

@ -305,15 +305,16 @@ module ifu import cvw::*; #(parameter cvw_t P) (
logic NoStallPCF; logic NoStallPCF;
if (P.FETCHBUFFER_ENTRIES != 0) begin : fetchbuffer if (P.FETCHBUFFER_ENTRIES != 0) begin : fetchbuffer
fetchbuffer #(P) fetchbuff(.clk, .reset, .StallF, .StallD, .FlushD, .nop, .WriteData(PostSpillInstrRawF), .ReadData(InstrRawD), .FetchBufferStallF, .RisingFBStallF()); fetchbuffer #(P) fetchbuff(.clk, .reset, .StallF, .StallD, .FlushD, .nop, .WriteData({PCF, PostSpillInstrRawF}), .ReadData({PCD, InstrRawD}), .FetchBufferStallF, .RisingFBStallF());
logic PCFetchBufferStallD, FetchBufferStallFDelay; logic PCFetchBufferStallD, FetchBufferStallFDelay;
flop #(1) flop1 (clk, FetchBufferStallF, FetchBufferStallFDelay); flop #(1) flop1 (clk, FetchBufferStallF, FetchBufferStallFDelay);
assign NoStallPCF = ~FetchBufferStallFDelay & FetchBufferStallF; assign NoStallPCF = ~FetchBufferStallFDelay & FetchBufferStallF;
fetchbuffer #(P, P.XLEN) PCFetchBuffer(.clk, .reset, .StallF, .StallD, .FlushD, .nop({{1'b1},{(P.XLEN-1){1'b0}}}), .WriteData(PCF), .ReadData(PCD), .FetchBufferStallF(PCFetchBufferStallD), .RisingFBStallF()); // fetchbuffer #(P, P.XLEN) PCFetchBuffer(.clk, .reset, .StallF, .StallD, .FlushD, .nop({{1'b1},{(P.XLEN-1){1'b0}}}), .WriteData(PCF), .ReadData(PCD), .FetchBufferStallF(PCFetchBufferStallD), .RisingFBStallF());
end else begin end else begin
flopenl #(32) AlignedInstrRawDFlop(clk, reset | FlushD, ~StallD, PostSpillInstrRawF, nop, InstrRawD); flopenl #(32) AlignedInstrRawDFlop(clk, reset | FlushD, ~StallD, PostSpillInstrRawF, nop, InstrRawD);
assign FetchBufferStallF = '0; assign FetchBufferStallF = '0;
flopenrc #(P.XLEN) PCDReg(clk, reset, FlushD, ~StallD, PCF, PCD); flopenrc #(P.XLEN) PCDReg(clk, reset, FlushD, ~StallD, PCF, PCD);
assign NoStallPCF = '0;
end end
//////////////////////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////////////////////