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Fix reverted submodules

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Jordan Carlin 2024-11-02 16:09:14 -07:00
parent 95fc05654b
commit c64c6c4cf1
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3 changed files with 4 additions and 3 deletions
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3
.gitmodules vendored
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@ -25,9 +25,10 @@
sparseCheckout = true
path = addins/verilog-ethernet
url = https://github.com/rosethompson/verilog-ethernet.git
[submodule "cvw-arch-verif"]
[submodule "addins/cvw-arch-verif"]
path = addins/cvw-arch-verif
url = https://github.com/openhwgroup/cvw-arch-verif
ignore = dirty
[submodule "addins/riscvISACOV"]
path = addins/riscvISACOV
url = https://github.com/riscv-verification/riscvISACOV.git