github-mirrors/cvw
1
0
Fork 0
mirror of https://github.com/openhwgroup/cvw.git synced 2025-06-28 09:36:01 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

Fix reverted submodules

Browse source
This commit is contained in:
Jordan Carlin 2024-11-02 16:09:14 -07:00
parent 95fc05654b
commit c64c6c4cf1
No known key found for this signature in database
3 changed files with 4 additions and 3 deletions
Download patch file Download diff file Expand all files Collapse all files

3
.gitmodules vendored
View file

@ -25,9 +25,10 @@
sparseCheckout = true
path = addins/verilog-ethernet
url = https://github.com/rosethompson/verilog-ethernet.git
[submodule "cvw-arch-verif"]
[submodule "addins/cvw-arch-verif"]
path = addins/cvw-arch-verif
url = https://github.com/openhwgroup/cvw-arch-verif
ignore = dirty
[submodule "addins/riscvISACOV"]
path = addins/riscvISACOV
url = https://github.com/riscv-verification/riscvISACOV.git

2
addins/cvw-arch-verif

@ -1 +1 @@
Subproject commit 189974e497d7b8d2c08bb1d151b1ccdeaf3a64c9
Subproject commit 6d658b7b42c83fd584008d72964cc75d0876b769

2
addins/riscv-arch-test

@ -1 +1 @@
Subproject commit 7152865aca51062c87ff2cbb014e199a24bdc874
Subproject commit 3843c736e427a2b52a0d06e6220b073afa4be401