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Merge pull request #319 from davidharrishmc/dev

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Renamed Performance Counter extension
This commit is contained in:
Ross Thompson 2023-06-09 21:21:45 -04:00 • committed by GitHub
commit c7536663c0
29 changed files with 297 additions and 92 deletions
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36
Makefile
View file

@ -4,7 +4,11 @@
all:
make install
make regression
make testfloat
make riscof
make verify
make coverage
make benchmarks
# install copies over the Makefile.include from riscv-isa-sim
# And corrects the TARGETDIR path and the RISCV_PREFIX
@ -18,9 +22,37 @@ install:
##rm tests/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe
##ln -s ${RISCV}/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe tests/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe
regression:
riscof:
make -C sim
testfloat:
cd ${WALLY}/addins/SoftFloat-3e/build/Linux-x86_64-GCC; make
cd ${WALLY}/addins/TestFloat-3e/build/Linux-x86_64-GCC; make
cd ${WALLY}/tests/fp; ./create_all_vectors.sh
verify:
cd ${WALLY}/sim; ./regression-wally
cd ${WALLY}/sim; ./sim-testfloat-batch all
make imperasdv
imperasdv:
iter-elf.bash --search ${WALLY}/tests/riscof/work/wally-riscv-arch-test/rv64i_m
iter-elf.bash --search ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m
coverage:
cd ${WALLY}/sim; ./regresssion-wally -coverage -fp
benchmarks:
make coremark
make embench
coremark:
cd ${WALLY}/benchmarks/coremark; make; make run
embench:
cd ${WALLY}/benchmarks/embench; make; make run
clean:
make clean -C sim

6
benchmarks/coremark/Makefile
View file

@ -11,7 +11,11 @@ sources=$(cmbase)/core_main.c $(cmbase)/core_list_join.c $(cmbase)/coremark.h \
$(PORT_DIR)/core_portme.h $(PORT_DIR)/core_portme.c $(PORT_DIR)/core_portme.mak \
$(PORT_DIR)/crt.S $(PORT_DIR)/encoding.h $(PORT_DIR)/util.h $(PORT_DIR)/syscalls.c
ABI := $(if $(findstring "64","$(XLEN)"),lp64,ilp32)
ARCH := rv$(XLEN)gc
#ARCH := rv$(XLEN)gc_zba_zbb_zbc_zbs
#ARCH := rv$(XLEN)gc
ARCH := rv$(XLEN)imc_zicsr
#ARCH := rv$(XLEN)im_zicsr
#ARCH := rv$(XLEN)i_zicsr
PORT_CFLAGS = -g -mabi=$(ABI) -march=$(ARCH) -static -falign-functions=16 \
-mbranch-cost=1 -DSKIP_DEFAULT_MEMSET -mtune=sifive-3-series -O3 -finline-functions -falign-jumps=4 \
-fno-delete-null-pointer-checks -fno-rename-registers --param=loop-max-datarefs-for-datadeps=0 \

19
bin/wally-tool-chain-install.sh
View file

@ -45,7 +45,7 @@ sudo mkdir -p $RISCV
# Update and Upgrade tools (see https://itsfoss.com/apt-update-vs-upgrade/)
sudo apt update -y
sudo apt upgrade -y
sudo apt install -y git gawk make texinfo bison flex build-essential python3 libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp-dev libglib2.0-dev python3-pip pkg-config opam z3 zlib1g-dev verilator automake autotools-dev libmpc-dev libmpfr-dev gperf libtool patchutils bc
sudo apt install -y git gawk make texinfo bison flex build-essential python3 libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp-dev libglib2.0-dev python3-pip pkg-config opam z3 zlib1g-dev automake autotools-dev libmpc-dev libmpfr-dev gperf libtool patchutils bc
# Other python libraries used through the book.
sudo pip3 install matplotlib scipy scikit-learn adjustText lief
@ -113,6 +113,23 @@ cd ../arch_test_target/spike/device
sed -i 's/--isa=rv32ic/--isa=rv32iac/' rv32i_m/privilege/Makefile.include
sed -i 's/--isa=rv64ic/--isa=rv64iac/' rv64i_m/privilege/Makefile.include
# Wally needs Verilator 5.0 or later.
# Verilator needs to be built from scratch to get the latest version
# apt-get install verilator installs version 4.028 as of 6/8/23
sudo apt-get install -y perl g++ ccache help2man libgoogle-perftools-dev numactl perl-doc zlibc zlib1g
sudo apt-get install -y libfl2 libfl-dev # Ubuntu only (ignore if gives error)
cd $RISCV
git clone https://github.com/verilator/verilator # Only first time
unsetenv VERILATOR_ROOT # For csh; ignore error if on bash
unset VERILATOR_ROOT # For bash
cd verilator
git pull # Make sure git repository is up-to-date
git checkout master # Use development branch (e.g. recent bug fixes)
autoconf # Create ./configure script
./configure # Configure and create Makefile
make -j NUM_THREADS # Build Verilator itself (if error, try just 'make')
sudo make install
# Sail (https://github.com/riscv/sail-riscv)
# Sail is the new golden reference model for RISC-V. Sail is written in OCaml, which
# is an object-oriented extension of ML, which in turn is a functional programming

8
config/buildroot/config.vh
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@ -40,10 +40,16 @@ localparam IEEE754 = 0;
localparam MISA = (32'h0014112D);
localparam ZICSR_SUPPORTED = 1;
localparam ZIFENCEI_SUPPORTED = 1;
localparam ZICOUNTERS_SUPPORTED = 1;
localparam ZICNTR_SUPPORTED = 1;
localparam ZIHPM_SUPPORTED = 1;
localparam COUNTERS = 12'd32;
localparam ZFH_SUPPORTED = 0;
localparam SSTC_SUPPORTED = 0;
localparam ZICBOM_SUPPORTED = 0;
localparam ZICBOZ_SUPPORTED = 0;
localparam ZICBOP_SUPPORTED = 0;
localparam SVPBMT_SUPPORTED = 0;
// LSU microarchitectural Features
localparam BUS_SUPPORTED = 1;

7
config/rv32e/config.vh
View file

@ -41,9 +41,14 @@ localparam MISA = (32'h00000010);
localparam ZICSR_SUPPORTED = 0;
localparam ZIFENCEI_SUPPORTED = 0;
localparam COUNTERS = 12'd0;
localparam ZICOUNTERS_SUPPORTED = 0;
localparam ZICNTR_SUPPORTED = 0;
localparam ZIHPM_SUPPORTED = 0;
localparam ZFH_SUPPORTED = 0;
localparam SSTC_SUPPORTED = 0;
localparam ZICBOM_SUPPORTED = 0;
localparam ZICBOZ_SUPPORTED = 0;
localparam ZICBOP_SUPPORTED = 0;
localparam SVPBMT_SUPPORTED = 0;
// LSU microarchitectural Features
localparam BUS_SUPPORTED = 1;

7
config/rv32gc/config.vh
View file

@ -42,9 +42,14 @@ localparam MISA = (32'h00000104 | 1 << 20 | 1 << 18 | 1 << 12 | 1 << 0 | 1 <<3 |
localparam ZICSR_SUPPORTED = 1;
localparam ZIFENCEI_SUPPORTED = 1;
localparam COUNTERS = 12'd32;
localparam ZICOUNTERS_SUPPORTED = 1;
localparam ZICNTR_SUPPORTED = 1;
localparam ZIHPM_SUPPORTED = 1;
localparam ZFH_SUPPORTED = 0;
localparam SSTC_SUPPORTED = 1;
localparam ZICBOM_SUPPORTED = 0;
localparam ZICBOZ_SUPPORTED = 0;
localparam ZICBOP_SUPPORTED = 0;
localparam SVPBMT_SUPPORTED = 0;
// LSU microarchitectural Features
localparam BUS_SUPPORTED = 1;

9
config/rv32i/config.vh
View file

@ -40,10 +40,15 @@ localparam IEEE754 = 0;
localparam MISA = (32'h00000104);
localparam ZICSR_SUPPORTED = 0;
localparam ZIFENCEI_SUPPORTED = 0;
localparam COUNTERS = 12'd32;
localparam ZICOUNTERS_SUPPORTED = 0;
localparam COUNTERS = 0;
localparam ZICNTR_SUPPORTED = 0;
localparam ZIHPM_SUPPORTED = 0;
localparam ZFH_SUPPORTED = 0;
localparam SSTC_SUPPORTED = 0;
localparam ZICBOM_SUPPORTED = 0;
localparam ZICBOZ_SUPPORTED = 0;
localparam ZICBOP_SUPPORTED = 0;
localparam SVPBMT_SUPPORTED = 0;
// LSU microarchitectural Features
localparam BUS_SUPPORTED = 0;

7
config/rv32imc/config.vh
View file

@ -40,9 +40,14 @@ localparam MISA = (32'h00000104 | 1 << 20 | 1 << 18 | 1 << 12);
localparam ZICSR_SUPPORTED = 1;
localparam ZIFENCEI_SUPPORTED = 1;
localparam COUNTERS = 12'd32;
localparam ZICOUNTERS_SUPPORTED = 1;
localparam ZICNTR_SUPPORTED = 1;
localparam ZIHPM_SUPPORTED = 1;
localparam ZFH_SUPPORTED = 0;
localparam SSTC_SUPPORTED = 0;
localparam ZICBOM_SUPPORTED = 0;
localparam ZICBOZ_SUPPORTED = 0;
localparam ZICBOP_SUPPORTED = 0;
localparam SVPBMT_SUPPORTED = 0;
// LSU microarchitectural Features
localparam BUS_SUPPORTED = 1;

7
config/rv64fpquad/config.vh
View file

@ -41,9 +41,14 @@ localparam MISA = (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20
localparam ZICSR_SUPPORTED = 1;
localparam ZIFENCEI_SUPPORTED = 1;
localparam COUNTERS = 12'd32;
localparam ZICOUNTERS_SUPPORTED = 1;
localparam ZICNTR_SUPPORTED = 1;
localparam ZIHPM_SUPPORTED = 1;
localparam ZFH_SUPPORTED = 1;
localparam SSTC_SUPPORTED = 0;
localparam ZICBOM_SUPPORTED = 0;
localparam ZICBOZ_SUPPORTED = 0;
localparam ZICBOP_SUPPORTED = 0;
localparam SVPBMT_SUPPORTED = 0;
// LSU microarchitectural Features
localparam BUS_SUPPORTED = 1;

7
config/rv64gc/config.vh
View file

@ -44,9 +44,14 @@ localparam MISA = (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12
localparam ZICSR_SUPPORTED = 1;
localparam ZIFENCEI_SUPPORTED = 1;
localparam COUNTERS = 12'd32;
localparam ZICOUNTERS_SUPPORTED = 1;
localparam ZICNTR_SUPPORTED = 1;
localparam ZIHPM_SUPPORTED = 1;
localparam ZFH_SUPPORTED = 0;
localparam SSTC_SUPPORTED = 1;
localparam ZICBOM_SUPPORTED = 0;
localparam ZICBOZ_SUPPORTED = 0;
localparam ZICBOP_SUPPORTED = 0;
localparam SVPBMT_SUPPORTED = 0;
// LSU microarchitectural Features
localparam BUS_SUPPORTED = 1;

9
config/rv64i/config.vh
View file

@ -40,10 +40,15 @@ localparam IEEE754 = 0;
localparam MISA = (32'h00000104);
localparam ZICSR_SUPPORTED = 0;
localparam ZIFENCEI_SUPPORTED = 0;
localparam COUNTERS = 12'd32;
localparam ZICOUNTERS_SUPPORTED = 0;
localparam COUNTERS = 0;
localparam ZICNTR_SUPPORTED = 0;
localparam ZIHPM_SUPPORTED = 0;
localparam ZFH_SUPPORTED = 0;
localparam SSTC_SUPPORTED = 0;
localparam ZICBOM_SUPPORTED = 0;
localparam ZICBOZ_SUPPORTED = 0;
localparam ZICBOP_SUPPORTED = 0;
localparam SVPBMT_SUPPORTED = 0;
// LSU microarchitectural Features
localparam BUS_SUPPORTED = 0;

27
config/shared/parameter-defs.vh
View file

@ -11,20 +11,25 @@ parameter cvw_t P = '{
ZICSR_SUPPORTED : ZICSR_SUPPORTED,
ZIFENCEI_SUPPORTED : ZIFENCEI_SUPPORTED,
COUNTERS : COUNTERS,
ZICOUNTERS_SUPPORTED : ZICOUNTERS_SUPPORTED,
ZICNTR_SUPPORTED : ZICNTR_SUPPORTED,
ZIHPM_SUPPORTED : ZIHPM_SUPPORTED,
ZFH_SUPPORTED : ZFH_SUPPORTED,
SSTC_SUPPORTED : SSTC_SUPPORTED,
VIRTMEM_SUPPORTED : VIRTMEM_SUPPORTED,
VECTORED_INTERRUPTS_SUPPORTED : VECTORED_INTERRUPTS_SUPPORTED,
BIGENDIAN_SUPPORTED : BIGENDIAN_SUPPORTED,
SVADU_SUPPORTED : SVADU_SUPPORTED,
ZMMUL_SUPPORTED : ZMMUL_SUPPORTED,
VIRTMEM_SUPPORTED : VIRTMEM_SUPPORTED,
VECTORED_INTERRUPTS_SUPPORTED : VECTORED_INTERRUPTS_SUPPORTED,
BIGENDIAN_SUPPORTED : BIGENDIAN_SUPPORTED,
SVADU_SUPPORTED : SVADU_SUPPORTED,
ZMMUL_SUPPORTED : ZMMUL_SUPPORTED,
ZICBOM_SUPPORTED : ZICBOM_SUPPORTED,
ZICBOZ_SUPPORTED : ZICBOZ_SUPPORTED,
ZICBOP_SUPPORTED : ZICBOP_SUPPORTED,
SVPBMT_SUPPORTED : SVPBMT_SUPPORTED,
BUS_SUPPORTED : BUS_SUPPORTED,
DCACHE_SUPPORTED : DCACHE_SUPPORTED,
ICACHE_SUPPORTED : ICACHE_SUPPORTED,
ITLB_ENTRIES : ITLB_ENTRIES,
DTLB_ENTRIES : DTLB_ENTRIES,
DCACHE_NUMWAYS : DCACHE_NUMWAYS,
DCACHE_SUPPORTED : DCACHE_SUPPORTED,
ICACHE_SUPPORTED : ICACHE_SUPPORTED,
ITLB_ENTRIES : ITLB_ENTRIES,
DTLB_ENTRIES : DTLB_ENTRIES,
DCACHE_NUMWAYS : DCACHE_NUMWAYS,
DCACHE_WAYSIZEINBYTES : DCACHE_WAYSIZEINBYTES,
DCACHE_LINELENINBITS : DCACHE_LINELENINBITS,
ICACHE_NUMWAYS : ICACHE_NUMWAYS,

2
src/ifu/bpred/bpred.sv
View file

@ -191,7 +191,7 @@ module bpred import cvw::*; #(parameter cvw_t P) (
if(`INSTR_CLASS_PRED) mux2 #(P.XLEN) pcmuxBPWrongInvalidateFlush(PCE, PCF, BPWrongM, NextValidPCE);
else assign NextValidPCE = PCE;
if(P.ZICOUNTERS_SUPPORTED) begin
if(P.ZIHPM_SUPPORTED) begin
logic [P.XLEN-1:0] RASPCD, RASPCE;
logic BTAWrongE, RASPredPCWrongE;
// performance counters

36
src/privileged/csr.sv
View file

@ -94,35 +94,36 @@ module csr import cvw::*; #(parameter cvw_t P) (
localparam MIP = 12'h344;
localparam SIP = 12'h144;
logic [P.XLEN-1:0] CSRMReadValM, CSRSReadValM, CSRUReadValM, CSRCReadValM;
logic [P.XLEN-1:0] CSRReadValM;
logic [P.XLEN-1:0] CSRSrcM;
logic [P.XLEN-1:0] CSRRWM, CSRRSM, CSRRCM;
logic [P.XLEN-1:0] CSRWriteValM;
logic [P.XLEN-1:0] MSTATUS_REGW, SSTATUS_REGW, MSTATUSH_REGW;
logic [P.XLEN-1:0] STVEC_REGW, MTVEC_REGW;
logic [P.XLEN-1:0] MEPC_REGW, SEPC_REGW;
logic [P.XLEN-1:0] CSRMReadValM, CSRSReadValM, CSRUReadValM, CSRCReadValM;
logic [P.XLEN-1:0] CSRReadValM;
logic [P.XLEN-1:0] CSRSrcM;
logic [P.XLEN-1:0] CSRRWM, CSRRSM, CSRRCM;
logic [P.XLEN-1:0] CSRWriteValM;
logic [P.XLEN-1:0] MSTATUS_REGW, SSTATUS_REGW, MSTATUSH_REGW;
logic [P.XLEN-1:0] STVEC_REGW, MTVEC_REGW;
logic [P.XLEN-1:0] MEPC_REGW, SEPC_REGW;
logic [31:0] MCOUNTINHIBIT_REGW, MCOUNTEREN_REGW, SCOUNTEREN_REGW;
logic WriteMSTATUSM, WriteMSTATUSHM, WriteSSTATUSM;
logic CSRMWriteM, CSRSWriteM, CSRUWriteM;
logic UngatedCSRMWriteM;
logic WriteFRMM, WriteFFLAGSM;
logic [P.XLEN-1:0] UnalignedNextEPCM, NextEPCM, NextMtvalM;
logic [P.XLEN-1:0] UnalignedNextEPCM, NextEPCM, NextMtvalM;
logic [4:0] NextCauseM;
logic [11:0] CSRAdrM;
logic IllegalCSRCAccessM, IllegalCSRMAccessM, IllegalCSRSAccessM, IllegalCSRUAccessM;
logic InsufficientCSRPrivilegeM;
logic IllegalCSRMWriteReadonlyM;
logic [P.XLEN-1:0] CSRReadVal2M;
logic [P.XLEN-1:0] CSRReadVal2M;
logic [11:0] MIP_REGW_writeable;
logic [P.XLEN-1:0] TVecM, TrapVectorM, NextFaultMtvalM;
logic [P.XLEN-1:0] TVecM, TrapVectorM, NextFaultMtvalM;
logic MTrapM, STrapM;
logic [P.XLEN-1:0] EPC;
logic [P.XLEN-1:0] EPC;
logic RetM;
logic SelMtvecM;
logic [P.XLEN-1:0] TVecAlignedM;
logic [P.XLEN-1:0] TVecAlignedM;
logic InstrValidNotFlushedM;
logic STimerInt;
logic MENVCFG_STCE;
// only valid unflushed instructions can access CSRs
assign InstrValidNotFlushedM = InstrValidM & ~StallW & ~FlushW;
@ -213,7 +214,7 @@ module csr import cvw::*; #(parameter cvw_t P) (
csri #(P) csri(.clk, .reset,
.CSRMWriteM, .CSRSWriteM, .CSRWriteValM, .CSRAdrM,
.MExtInt, .SExtInt, .MTimerInt, .STimerInt, .MSwInt,
.MIDELEG_REGW, .MIP_REGW, .MIE_REGW, .MIP_REGW_writeable);
.MIDELEG_REGW, .MENVCFG_STCE, .MIP_REGW, .MIE_REGW, .MIP_REGW_writeable);
csrsr #(P) csrsr(.clk, .reset, .StallW,
.WriteMSTATUSM, .WriteMSTATUSHM, .WriteSSTATUSM,
@ -231,7 +232,8 @@ module csr import cvw::*; #(parameter cvw_t P) (
.MEPC_REGW, .MCOUNTEREN_REGW, .MCOUNTINHIBIT_REGW,
.MEDELEG_REGW, .MIDELEG_REGW,.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
.MIP_REGW, .MIE_REGW, .WriteMSTATUSM, .WriteMSTATUSHM,
.IllegalCSRMAccessM, .IllegalCSRMWriteReadonlyM);
.IllegalCSRMAccessM, .IllegalCSRMWriteReadonlyM,
.MENVCFG_STCE);
if (P.S_SUPPORTED) begin:csrs
@ -242,7 +244,7 @@ module csr import cvw::*; #(parameter cvw_t P) (
.CSRWriteValM, .PrivilegeModeW,
.CSRSReadValM, .STVEC_REGW, .SEPC_REGW,
.SCOUNTEREN_REGW,
.SATP_REGW, .MIP_REGW, .MIE_REGW, .MIDELEG_REGW, .MTIME_CLINT,
.SATP_REGW, .MIP_REGW, .MIE_REGW, .MIDELEG_REGW, .MTIME_CLINT, .MENVCFG_STCE,
.WriteSSTATUSM, .IllegalCSRSAccessM, .STimerInt);
end else begin
assign WriteSSTATUSM = 0;
@ -266,7 +268,7 @@ module csr import cvw::*; #(parameter cvw_t P) (
assign IllegalCSRUAccessM = 1;
end
if (P.ZICOUNTERS_SUPPORTED) begin:counters
if (P.ZICNTR_SUPPORTED) begin:counters
csrc #(P) counters(.clk, .reset, .StallE, .StallM, .FlushM,
.InstrValidNotFlushedM, .LoadStallD, .StoreStallD, .CSRWriteM, .CSRMWriteM,
.BPDirPredWrongM, .BTAWrongM, .RASPredPCWrongM, .IClassWrongM, .BPWrongM,

8
src/privileged/csrc.sv
View file

@ -92,9 +92,7 @@ module csrc import cvw::*; #(parameter cvw_t P) (
assign CounterEvent[0] = 1'b1; // MCYCLE always increments
assign CounterEvent[1] = 1'b0; // Counter 1 doesn't exist
assign CounterEvent[2] = InstrValidNotFlushedM; // MINSTRET instructions retired
if(P.QEMU) begin: cevent // No other performance counters in QEMU
assign CounterEvent[P.COUNTERS-1:3] = 0;
end else begin: cevent // User-defined counters
if (P.ZIHPM_SUPPORTED) begin: cevent // User-defined counters
assign CounterEvent[3] = InstrClassM[0] & InstrValidNotFlushedM; // branch instruction
assign CounterEvent[4] = InstrClassM[1] & ~InstrClassM[2] & InstrValidNotFlushedM; // jump and not return instructions
assign CounterEvent[5] = InstrClassM[2] & InstrValidNotFlushedM; // return instructions
@ -121,6 +119,8 @@ module csrc import cvw::*; #(parameter cvw_t P) (
assign CounterEvent[24] = DivBusyE | FDivBusyE; // division cycles *** RT: might need to be delay until the next cycle
// coverage on
assign CounterEvent[P.COUNTERS-1:25] = 0; // eventually give these sources, including FP instructions, I$/D$ misses, branches and mispredictions
end else begin: cevent
assign CounterEvent[P.COUNTERS-1:3] = 0;
end
// Counter update and write logic
@ -165,7 +165,7 @@ module csrc import cvw::*; #(parameter cvw_t P) (
IllegalCSRCAccessM = 1; // requested CSR doesn't exist
end
end else begin // 32-bit counter reads
// Veri lator doesn't realize this only occurs for XLEN=32
// Veril ator doesn't realize this only occurs for XLEN=32
/* verilator lint_off WIDTH */
if (CSRAdrM == TIME) CSRCReadValM = MTIME_CLINT[31:0];// TIME register is a shadow of the memory-mapped MTIME from the CLINT
else if (CSRAdrM == TIMEH) CSRCReadValM = MTIME_CLINT[63:32];

5
src/privileged/csri.sv
View file

@ -30,10 +30,11 @@
module csri import cvw::*; #(parameter cvw_t P) (
input logic clk, reset,
input logic CSRMWriteM, CSRSWriteM,
input logic [P.XLEN-1:0] CSRWriteValM,
input logic [P.XLEN-1:0] CSRWriteValM,
input logic [11:0] CSRAdrM,
input logic MExtInt, SExtInt, MTimerInt, STimerInt, MSwInt,
input logic [11:0] MIDELEG_REGW,
input logic MENVCFG_STCE,
output logic [11:0] MIP_REGW, MIE_REGW,
output logic [11:0] MIP_REGW_writeable // only SEIP, STIP, SSIP are actually writeable; the rest are hardwired to 0
);
@ -60,7 +61,7 @@ module csri import cvw::*; #(parameter cvw_t P) (
if (P.S_SUPPORTED) begin:mask
if (P.SSTC_SUPPORTED) begin
assign MIP_WRITE_MASK = 12'h202; // SEIP and SSIP are writable, but STIP is not writable when STIMECMP is implemented (see SSTC spec)
assign STIP = STimerInt;
assign STIP = MENVCFG_STCE ? STimerInt : MIP_REGW_writeable[5];
end else begin
assign MIP_WRITE_MASK = 12'h222; // SEIP, STIP, SSIP are writeable in MIP (20210108-draft 3.1.9)
assign STIP = MIP_REGW_writeable[5];

73
src/privileged/csrm.sv
View file

@ -32,29 +32,34 @@
////////////////////////////////////////////////////////////////////////////////////////////////
module csrm import cvw::*; #(parameter cvw_t P) (
input logic clk, reset,
input logic UngatedCSRMWriteM, CSRMWriteM, MTrapM,
input logic [11:0] CSRAdrM,
input logic clk, reset,
input logic UngatedCSRMWriteM, CSRMWriteM, MTrapM,
input logic [11:0] CSRAdrM,
input logic [P.XLEN-1:0] NextEPCM, NextMtvalM, MSTATUS_REGW, MSTATUSH_REGW,
input logic [4:0] NextCauseM,
input logic [4:0] NextCauseM,
input logic [P.XLEN-1:0] CSRWriteValM,
input logic [11:0] MIP_REGW, MIE_REGW,
input logic [11:0] MIP_REGW, MIE_REGW,
output logic [P.XLEN-1:0] CSRMReadValM, MTVEC_REGW,
output logic [P.XLEN-1:0] MEPC_REGW,
output logic [31:0] MCOUNTEREN_REGW, MCOUNTINHIBIT_REGW,
output logic [15:0] MEDELEG_REGW,
output logic [11:0] MIDELEG_REGW,
output var logic [7:0] PMPCFG_ARRAY_REGW[P.PMP_ENTRIES-1:0],
output logic [31:0] MCOUNTEREN_REGW, MCOUNTINHIBIT_REGW,
output logic [15:0] MEDELEG_REGW,
output logic [11:0] MIDELEG_REGW,
output var logic [7:0] PMPCFG_ARRAY_REGW[P.PMP_ENTRIES-1:0],
output var logic [P.PA_BITS-3:0] PMPADDR_ARRAY_REGW [P.PMP_ENTRIES-1:0],
output logic WriteMSTATUSM, WriteMSTATUSHM,
output logic IllegalCSRMAccessM, IllegalCSRMWriteReadonlyM
output logic WriteMSTATUSM, WriteMSTATUSHM,
output logic IllegalCSRMAccessM, IllegalCSRMWriteReadonlyM,
output logic MENVCFG_STCE
);
logic [P.XLEN-1:0] MISA_REGW, MHARTID_REGW;
logic [P.XLEN-1:0] MSCRATCH_REGW, MTVAL_REGW, MCAUSE_REGW;
logic WriteMTVECM, WriteMEDELEGM, WriteMIDELEGM;
logic WriteMSCRATCHM, WriteMEPCM, WriteMCAUSEM, WriteMTVALM;
logic WriteMCOUNTERENM, WriteMCOUNTINHIBITM;
logic [63:0] MENVCFG_REGW;
logic [P.XLEN-1:0] MENVCFGH_REGW;
logic [63:0] MENVCFG_PreWriteValM, MENVCFG_WriteValM;
logic WriteMTVECM, WriteMEDELEGM, WriteMIDELEGM;
logic WriteMSCRATCHM, WriteMEPCM, WriteMCAUSEM, WriteMTVALM;
logic WriteMCOUNTERENM, WriteMCOUNTINHIBITM;
logic WriteMENVCFGM;
// Machine CSRs
localparam MVENDORID = 12'hF11;
@ -69,7 +74,9 @@ module csrm import cvw::*; #(parameter cvw_t P) (
localparam MIE = 12'h304;
localparam MTVEC = 12'h305;
localparam MCOUNTEREN = 12'h306;
localparam MENVCFG = 12'h30A;
localparam MSTATUSH = 12'h310;
localparam MENVCFGH = 12'h31A;
localparam MCOUNTINHIBIT = 12'h320;
localparam MSCRATCH = 12'h340;
localparam MEPC = 12'h341;
@ -131,7 +138,7 @@ module csrm import cvw::*; #(parameter cvw_t P) (
// Write machine Mode CSRs
assign WriteMSTATUSM = CSRMWriteM & (CSRAdrM == MSTATUS);
assign WriteMSTATUSHM = CSRMWriteM & (CSRAdrM == MSTATUSH)& (P.XLEN==32);
assign WriteMSTATUSHM = CSRMWriteM & (CSRAdrM == MSTATUSH) & (P.XLEN==32);
assign WriteMTVECM = CSRMWriteM & (CSRAdrM == MTVEC);
assign WriteMEDELEGM = CSRMWriteM & (CSRAdrM == MEDELEG);
assign WriteMIDELEGM = CSRMWriteM & (CSRAdrM == MIDELEG);
@ -140,6 +147,7 @@ module csrm import cvw::*; #(parameter cvw_t P) (
assign WriteMCAUSEM = MTrapM | (CSRMWriteM & (CSRAdrM == MCAUSE));
assign WriteMTVALM = MTrapM | (CSRMWriteM & (CSRAdrM == MTVAL));
assign WriteMCOUNTERENM = CSRMWriteM & (CSRAdrM == MCOUNTEREN);
assign WriteMENVCFGM = CSRMWriteM & (CSRAdrM == MENVCFG);
assign WriteMCOUNTINHIBITM = CSRMWriteM & (CSRAdrM == MCOUNTINHIBIT);
assign IllegalCSRMWriteReadonlyM = UngatedCSRMWriteM & (CSRAdrM == MVENDORID | CSRAdrM == MARCHID | CSRAdrM == MIMPID | CSRAdrM == MHARTID);
@ -161,6 +169,39 @@ module csrm import cvw::*; #(parameter cvw_t P) (
flopenr #(32) MCOUNTERENreg(clk, reset, WriteMCOUNTERENM, CSRWriteValM[31:0], MCOUNTEREN_REGW);
end else assign MCOUNTEREN_REGW = '0;
// MENVCFG is always 64 bits even for RV32
assign MENVCFG_WriteValM = {
MENVCFG_PreWriteValM[63] & P.SSTC_SUPPORTED,
MENVCFG_PreWriteValM[62] & P.SVPBMT_SUPPORTED,
54'b0,
MENVCFG_PreWriteValM[7] & P.ZICBOZ_SUPPORTED,
MENVCFG_PreWriteValM[6:4] & {3{P.ZICBOM_SUPPORTED}},
3'b0,
MENVCFG_PreWriteValM[0] & P.S_SUPPORTED & P.VIRTMEM_SUPPORTED
};
if (P.XLEN == 64) begin
assign MENVCFG_PreWriteValM = CSRWriteValM;
flopenr #(P.XLEN) MENVCFGreg(clk, reset, WriteMENVCFGM, MENVCFG_WriteValM, MENVCFG_REGW);
assign MENVCFGH_REGW = 0;
end else begin
logic WriteMENVCFGHM;
assign MENVCFG_PreWriteValM = {CSRWriteValM, CSRWriteValM};
assign WriteMENVCFGHM = CSRMWriteM & (CSRAdrM == MENVCFGH) & (P.XLEN==32);
flopenr #(P.XLEN) MENVCFGreg(clk, reset, WriteMENVCFGM, MENVCFG_WriteValM[31:0], MENVCFG_REGW[31:0]);
flopenr #(P.XLEN) MENVCFGHreg(clk, reset, WriteMENVCFGHM, MENVCFG_WriteValM[63:32], MENVCFG_REGW[63:32]);
assign MENVCFGH_REGW = MENVCFG_REGW[63:32];
end
// Extract bit fields
assign MENVCFG_STCE = MENVCFG_REGW[63];
// Uncomment these other fields when they are defined
// assign MENVCFG_PBMTE = MENVCFG_REGW[62];
// assign MENVCFG_CBZE = MENVCFG_REGW[7];
// assign MENVCFG_CBCFE = MENVCFG_REGW[6];
// assign MENVCFG_CBIE = MENVCFG_REGW[5:4];
// assign MENVCFG_FIOM = MENVCFG_REGW[0];
// Read machine mode CSRs
// verilator lint_off WIDTH
logic [5:0] entry;
@ -200,6 +241,8 @@ module csrm import cvw::*; #(parameter cvw_t P) (
MTVAL: CSRMReadValM = MTVAL_REGW;
MTINST: CSRMReadValM = 0; // implemented as trivial zero
MCOUNTEREN:CSRMReadValM = {{(P.XLEN-32){1'b0}}, MCOUNTEREN_REGW};
MENVCFG: CSRMReadValM = MENVCFG_REGW[P.XLEN-1:0];
MENVCFGH: CSRMReadValM = MENVCFGH_REGW;
MCOUNTINHIBIT:CSRMReadValM = {{(P.XLEN-32){1'b0}}, MCOUNTINHIBIT_REGW};
default: begin

65
src/privileged/csrs.sv
View file

@ -29,24 +29,25 @@
////////////////////////////////////////////////////////////////////////////////////////////////
module csrs import cvw::*; #(parameter cvw_t P) (
input logic clk, reset,
input logic CSRSWriteM, STrapM,
input logic [11:0] CSRAdrM,
input logic clk, reset,
input logic CSRSWriteM, STrapM,
input logic [11:0] CSRAdrM,
input logic [P.XLEN-1:0] NextEPCM, NextMtvalM, SSTATUS_REGW,
input logic [4:0] NextCauseM,
input logic STATUS_TVM,
input logic MCOUNTEREN_TM, // TM bit (1) of MCOUNTEREN; cause illegal instruction when trying to access STIMECMP if clear
input logic [4:0] NextCauseM,
input logic STATUS_TVM,
input logic MCOUNTEREN_TM, // TM bit (1) of MCOUNTEREN; cause illegal instruction when trying to access STIMECMP if clear
input logic [P.XLEN-1:0] CSRWriteValM,
input logic [1:0] PrivilegeModeW,
input logic [1:0] PrivilegeModeW,
output logic [P.XLEN-1:0] CSRSReadValM, STVEC_REGW,
output logic [P.XLEN-1:0] SEPC_REGW,
output logic [31:0] SCOUNTEREN_REGW,
output logic [31:0] SCOUNTEREN_REGW,
output logic [P.XLEN-1:0] SATP_REGW,
input logic [11:0] MIP_REGW, MIE_REGW, MIDELEG_REGW,
input logic [63:0] MTIME_CLINT,
output logic WriteSSTATUSM,
output logic IllegalCSRSAccessM,
output logic STimerInt
input logic [11:0] MIP_REGW, MIE_REGW, MIDELEG_REGW,
input logic [63:0] MTIME_CLINT,
input logic MENVCFG_STCE,
output logic WriteSSTATUSM,
output logic IllegalCSRSAccessM,
output logic STimerInt
);
// Supervisor CSRs
@ -54,6 +55,7 @@ module csrs import cvw::*; #(parameter cvw_t P) (
localparam SIE = 12'h104;
localparam STVEC = 12'h105;
localparam SCOUNTEREN = 12'h106;
localparam SENVCFG = 12'h10A;
localparam SSCRATCH = 12'h140;
localparam SEPC = 12'h141;
localparam SCAUSE = 12'h142;
@ -70,7 +72,12 @@ module csrs import cvw::*; #(parameter cvw_t P) (
logic WriteSSCRATCHM, WriteSEPCM;
logic WriteSCAUSEM, WriteSTVALM, WriteSATPM, WriteSCOUNTERENM;
logic WriteSTIMECMPM, WriteSTIMECMPHM;
logic [P.XLEN-1:0] SSCRATCH_REGW, STVAL_REGW, SCAUSE_REGW;
logic WriteSENVCFGM;
logic [P.XLEN-1:0] SSCRATCH_REGW, STVAL_REGW, SCAUSE_REGW;
logic [P.XLEN-1:0] SENVCFG_REGW;
logic [P.XLEN-1:0] SENVCFG_WriteValM;
logic [63:0] STIMECMP_REGW;
// write enables
@ -82,8 +89,9 @@ module csrs import cvw::*; #(parameter cvw_t P) (
assign WriteSTVALM = STrapM | (CSRSWriteM & (CSRAdrM == STVAL));
assign WriteSATPM = CSRSWriteM & (CSRAdrM == SATP) & (PrivilegeModeW == P.M_MODE | ~STATUS_TVM);
assign WriteSCOUNTERENM = CSRSWriteM & (CSRAdrM == SCOUNTEREN);
assign WriteSTIMECMPM = CSRSWriteM & (CSRAdrM == STIMECMP) & (PrivilegeModeW == P.M_MODE | MCOUNTEREN_TM);
assign WriteSTIMECMPHM = CSRSWriteM & (CSRAdrM == STIMECMPH) & (PrivilegeModeW == P.M_MODE | MCOUNTEREN_TM) & (P.XLEN == 32);
assign WriteSENVCFGM = CSRSWriteM & (CSRAdrM == SENVCFG);
assign WriteSTIMECMPM = CSRSWriteM & (CSRAdrM == STIMECMP) & (PrivilegeModeW == P.M_MODE | (MCOUNTEREN_TM & MENVCFG_STCE));
assign WriteSTIMECMPHM = CSRSWriteM & (CSRAdrM == STIMECMPH) & (PrivilegeModeW == P.M_MODE | (MCOUNTEREN_TM & MENVCFG_STCE)) & (P.XLEN == 32);
// CSRs
flopenr #(P.XLEN) STVECreg(clk, reset, WriteSTVECM, {CSRWriteValM[P.XLEN-1:2], 1'b0, CSRWriteValM[0]}, STVEC_REGW);
@ -111,6 +119,24 @@ module csrs import cvw::*; #(parameter cvw_t P) (
assign STimerInt = ({1'b0, MTIME_CLINT} >= {1'b0, STIMECMP_REGW}); // unsigned comparison
else
assign STimerInt = 0;
assign SENVCFG_WriteValM = {
{(P.XLEN-8){1'b0}},
CSRWriteValM[7] & P.ZICBOZ_SUPPORTED,
CSRWriteValM[6:4] & {3{P.ZICBOM_SUPPORTED}},
3'b0,
CSRWriteValM[0] & P.S_SUPPORTED & P.VIRTMEM_SUPPORTED
};
flopenr #(P.XLEN) SENVCFGreg(clk, reset, WriteSENVCFGM, SENVCFG_WriteValM, SENVCFG_REGW);
// Extract bit fields
// Uncomment these other fields when they are defined
// assign SENVCFG_PBMTE = SENVCFG_REGW[62];
// assign SENVCFG_CBZE = SENVCFG_REGW[7];
// assign SENVCFG_CBCFE = SENVCFG_REGW[6];
// assign SENVCFG_CBIE = SENVCFG_REGW[5:4];
// assign SENVCFG_FIOM = SENVCFG_REGW[0];
// CSR Reads
always_comb begin:csrr
@ -130,12 +156,15 @@ module csrs import cvw::*; #(parameter cvw_t P) (
IllegalCSRSAccessM = 1;
end
SCOUNTEREN:CSRSReadValM = {{(P.XLEN-32){1'b0}}, SCOUNTEREN_REGW};
STIMECMP: if (P.SSTC_SUPPORTED & (PrivilegeModeW == P.M_MODE | MCOUNTEREN_TM)) CSRSReadValM = STIMECMP_REGW[P.XLEN-1:0];
SENVCFG: CSRSReadValM = SENVCFG_REGW;
STIMECMP: if (P.SSTC_SUPPORTED & (PrivilegeModeW == P.M_MODE | (MCOUNTEREN_TM && MENVCFG_STCE)))
CSRSReadValM = STIMECMP_REGW[P.XLEN-1:0];
else begin
CSRSReadValM = 0;
IllegalCSRSAccessM = 1;
end
STIMECMPH: if (P.SSTC_SUPPORTED & (P.XLEN == 32) & (PrivilegeModeW == P.M_MODE | MCOUNTEREN_TM)) CSRSReadValM[31:0] = STIMECMP_REGW[63:32];
STIMECMPH: if (P.SSTC_SUPPORTED & (P.XLEN == 32) & (PrivilegeModeW == P.M_MODE | (MCOUNTEREN_TM && MENVCFG_STCE)))
CSRSReadValM[31:0] = STIMECMP_REGW[63:32];
else begin // not supported for RV64
CSRSReadValM = 0;
IllegalCSRSAccessM = 1;

2
src/privileged/csrsr.sv
View file

@ -4,7 +4,7 @@
// Written: David_Harris@hmc.edu 9 January 2021
// Modified:
//
// Purpose: Status register
// Purpose: Status register (and environment configuration register and others shared across modes)
// See RISC-V Privileged Mode Specification 20190608
//
// Documentation: RISC-V System on Chip Design Chapter 5

9
src/wally/cvw.sv
View file

@ -47,8 +47,9 @@ typedef struct packed {
// RISC-V Features
logic ZICSR_SUPPORTED;
logic ZIFENCEI_SUPPORTED;
logic [11:0] COUNTERS;
logic ZICOUNTERS_SUPPORTED;
logic [11:0] COUNTERS;
logic ZICNTR_SUPPORTED;
logic ZIHPM_SUPPORTED;
logic ZFH_SUPPORTED;
logic SSTC_SUPPORTED;
logic VIRTMEM_SUPPORTED;
@ -56,6 +57,10 @@ typedef struct packed {
logic BIGENDIAN_SUPPORTED;
logic SVADU_SUPPORTED;
logic ZMMUL_SUPPORTED;
logic ZICBOM_SUPPORTED;
logic ZICBOZ_SUPPORTED;
logic ZICBOP_SUPPORTED;
logic SVPBMT_SUPPORTED;
// Microarchitectural Features
logic BUS_SUPPORTED;

12
testbench/common/wallyTracer.sv
View file

@ -139,6 +139,7 @@ module wallyTracer(rvviTrace rvvi);
CSRArray[12'h344] = testbench.dut.core.priv.priv.csr.csrm.MIP_REGW;
CSRArray[12'h304] = testbench.dut.core.priv.priv.csr.csrm.MIE_REGW;
CSRArray[12'h301] = testbench.dut.core.priv.priv.csr.csrm.MISA_REGW;
CSRArray[12'h30A] = testbench.dut.core.priv.priv.csr.csrm.MENVCFG_REGW;
CSRArray[12'hF14] = testbench.dut.core.priv.priv.csr.csrm.MHARTID_REGW;
CSRArray[12'h340] = testbench.dut.core.priv.priv.csr.csrm.MSCRATCH_REGW;
CSRArray[12'h342] = testbench.dut.core.priv.priv.csr.csrm.MCAUSE_REGW;
@ -157,6 +158,7 @@ module wallyTracer(rvviTrace rvvi);
CSRArray[12'h105] = testbench.dut.core.priv.priv.csr.csrs.csrs.STVEC_REGW;
CSRArray[12'h141] = testbench.dut.core.priv.priv.csr.csrs.csrs.SEPC_REGW;
CSRArray[12'h106] = testbench.dut.core.priv.priv.csr.csrs.csrs.SCOUNTEREN_REGW;
CSRArray[12'h10A] = testbench.dut.core.priv.priv.csr.csrs.csrs.SENVCFG_REGW;
CSRArray[12'h180] = testbench.dut.core.priv.priv.csr.csrs.csrs.SATP_REGW;
CSRArray[12'h140] = testbench.dut.core.priv.priv.csr.csrs.csrs.SSCRATCH_REGW;
CSRArray[12'h143] = testbench.dut.core.priv.priv.csr.csrs.csrs.STVAL_REGW;
@ -189,6 +191,7 @@ module wallyTracer(rvviTrace rvvi);
CSRArray[12'h344] = CSRArrayOld[12'h344];
CSRArray[12'h304] = CSRArrayOld[12'h304];
CSRArray[12'h301] = CSRArrayOld[12'h301];
CSRArray[12'h30A] = CSRArrayOld[12'h30A];
CSRArray[12'hF14] = CSRArrayOld[12'hF14];
CSRArray[12'h340] = CSRArrayOld[12'h340];
CSRArray[12'h342] = CSRArrayOld[12'h342];
@ -207,6 +210,7 @@ module wallyTracer(rvviTrace rvvi);
CSRArray[12'h105] = CSRArrayOld[12'h105];
CSRArray[12'h141] = CSRArrayOld[12'h141];
CSRArray[12'h106] = CSRArrayOld[12'h106];
CSRArray[12'h10A] = CSRArrayOld[12'h10A];
CSRArray[12'h180] = CSRArrayOld[12'h180];
CSRArray[12'h140] = CSRArrayOld[12'h140];
CSRArray[12'h143] = CSRArrayOld[12'h143];
@ -308,6 +312,7 @@ module wallyTracer(rvviTrace rvvi);
CSRArrayOld[12'h344] = CSRArray[12'h344];
CSRArrayOld[12'h304] = CSRArray[12'h304];
CSRArrayOld[12'h301] = CSRArray[12'h301];
CSRArrayOld[12'h30A] = CSRArray[12'h30A];
CSRArrayOld[12'hF14] = CSRArray[12'hF14];
CSRArrayOld[12'h340] = CSRArray[12'h340];
CSRArrayOld[12'h342] = CSRArray[12'h342];
@ -326,6 +331,7 @@ module wallyTracer(rvviTrace rvvi);
CSRArrayOld[12'h105] = CSRArray[12'h105];
CSRArrayOld[12'h141] = CSRArray[12'h141];
CSRArrayOld[12'h106] = CSRArray[12'h106];
CSRArrayOld[12'h10A] = CSRArray[12'h10A];
CSRArrayOld[12'h180] = CSRArray[12'h180];
CSRArrayOld[12'h140] = CSRArray[12'h140];
CSRArrayOld[12'h143] = CSRArray[12'h143];
@ -352,6 +358,7 @@ module wallyTracer(rvviTrace rvvi);
assign #2 CSR_W[12'h305] = (CSRArrayOld[12'h305] != CSRArray[12'h305]) ? 1 : 0;
assign #2 CSR_W[12'h341] = (CSRArrayOld[12'h341] != CSRArray[12'h341]) ? 1 : 0;
assign #2 CSR_W[12'h306] = (CSRArrayOld[12'h306] != CSRArray[12'h306]) ? 1 : 0;
assign #2 CSR_W[12'h30A] = (CSRArrayOld[12'h30A] != CSRArray[12'h30A]) ? 1 : 0;
assign #2 CSR_W[12'h320] = (CSRArrayOld[12'h320] != CSRArray[12'h320]) ? 1 : 0;
assign #2 CSR_W[12'h302] = (CSRArrayOld[12'h302] != CSRArray[12'h302]) ? 1 : 0;
assign #2 CSR_W[12'h303] = (CSRArrayOld[12'h303] != CSRArray[12'h303]) ? 1 : 0;
@ -374,6 +381,7 @@ module wallyTracer(rvviTrace rvvi);
assign #2 CSR_W[12'h105] = (CSRArrayOld[12'h105] != CSRArray[12'h105]) ? 1 : 0;
assign #2 CSR_W[12'h141] = (CSRArrayOld[12'h141] != CSRArray[12'h141]) ? 1 : 0;
assign #2 CSR_W[12'h106] = (CSRArrayOld[12'h106] != CSRArray[12'h106]) ? 1 : 0;
assign #2 CSR_W[12'h10A] = (CSRArrayOld[12'h10A] != CSRArray[12'h10A]) ? 1 : 0;
assign #2 CSR_W[12'h180] = (CSRArrayOld[12'h180] != CSRArray[12'h180]) ? 1 : 0;
assign #2 CSR_W[12'h140] = (CSRArrayOld[12'h140] != CSRArray[12'h140]) ? 1 : 0;
assign #2 CSR_W[12'h143] = (CSRArrayOld[12'h143] != CSRArray[12'h143]) ? 1 : 0;
@ -394,6 +402,7 @@ module wallyTracer(rvviTrace rvvi);
assign rvvi.csr_wb[0][0][12'h303] = CSR_W[12'h303];
assign rvvi.csr_wb[0][0][12'h344] = CSR_W[12'h344];
assign rvvi.csr_wb[0][0][12'h304] = CSR_W[12'h304];
assign rvvi.csr_wb[0][0][12'h30A] = CSR_W[12'h30A];
assign rvvi.csr_wb[0][0][12'h301] = CSR_W[12'h301];
assign rvvi.csr_wb[0][0][12'hF14] = CSR_W[12'hF14];
assign rvvi.csr_wb[0][0][12'h340] = CSR_W[12'h340];
@ -411,6 +420,7 @@ module wallyTracer(rvviTrace rvvi);
assign rvvi.csr_wb[0][0][12'h105] = CSR_W[12'h105];
assign rvvi.csr_wb[0][0][12'h141] = CSR_W[12'h141];
assign rvvi.csr_wb[0][0][12'h106] = CSR_W[12'h106];
assign rvvi.csr_wb[0][0][12'h10A] = CSR_W[12'h10A];
assign rvvi.csr_wb[0][0][12'h180] = CSR_W[12'h180];
assign rvvi.csr_wb[0][0][12'h140] = CSR_W[12'h140];
assign rvvi.csr_wb[0][0][12'h143] = CSR_W[12'h143];
@ -431,6 +441,7 @@ module wallyTracer(rvviTrace rvvi);
assign rvvi.csr[0][0][12'h303] = CSRArray[12'h303];
assign rvvi.csr[0][0][12'h344] = CSRArray[12'h344];
assign rvvi.csr[0][0][12'h304] = CSRArray[12'h304];
assign rvvi.csr[0][0][12'h30A] = CSRArray[12'h30A];
assign rvvi.csr[0][0][12'h301] = CSRArray[12'h301];
assign rvvi.csr[0][0][12'hF14] = CSRArray[12'hF14];
assign rvvi.csr[0][0][12'h340] = CSRArray[12'h340];
@ -448,6 +459,7 @@ module wallyTracer(rvviTrace rvvi);
assign rvvi.csr[0][0][12'h105] = CSRArray[12'h105];
assign rvvi.csr[0][0][12'h141] = CSRArray[12'h141];
assign rvvi.csr[0][0][12'h106] = CSRArray[12'h106];
assign rvvi.csr[0][0][12'h10A] = CSRArray[12'h10A];
assign rvvi.csr[0][0][12'h180] = CSRArray[12'h180];
assign rvvi.csr[0][0][12'h140] = CSRArray[12'h140];
assign rvvi.csr[0][0][12'h143] = CSRArray[12'h143];

2
testbench/testbench-linux-imperas.sv
View file

@ -866,10 +866,12 @@ module testbench;
"medeleg": `checkCSR(`CSR_BASE.csrm.MEDELEG_REGW)
"mepc": `checkCSR(`CSR_BASE.csrm.MEPC_REGW)
"mtval": `checkCSR(`CSR_BASE.csrm.MTVAL_REGW)
"menvcfg": `checkCSR(`CSR_BASE.csrm.MENVCFG_REGW)
"sepc": `checkCSR(`CSR_BASE.csrs.csrs.SEPC_REGW)
"scause": `checkCSR(`CSR_BASE.csrs.csrs.SCAUSE_REGW)
"stvec": `checkCSR(`CSR_BASE.csrs.csrs.STVEC_REGW)
"stval": `checkCSR(`CSR_BASE.csrs.csrs.STVAL_REGW)
"senvcfg": `checkCSR(`CSR_BASE.csrs.SENVCFG_REGW)
"mip": begin
`checkCSR(`CSR_BASE.csrm.MIP_REGW)
if(!NO_SPOOFING) begin

3
tests/coverage/csrwrites.S
View file

@ -33,5 +33,8 @@ main:
csrrw t0, satp, zero
csrrw t0, stvec, zero
csrrw t0, sscratch, zero
li t0, -2
csrrw t1, menvcfg, t0
csrrw t2, senvcfg, t0
j done

2
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-01.reference_output
View file

@ -1,3 +1,5 @@
FFFFFFFF # stimecmp readback
80000000 # menvcfg readback
00000aaa # Test 5.3.1.4: readback value from writing mie to enable interrupts # skipping instruction address fault since they're impossible with compressed instrs enabled
00000001 # mcause from an instruction access fault
00000000 # mtval of faulting instruction address (0x0)

2
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h
View file

@ -280,7 +280,7 @@ end_trap_triggers:
la t4, 0x02004000 // MTIMECMP register in CLINT
li t5, 0xFFFFFFFF
sw t5, 0(t4) // set mtimecmp to 0xFFFFFFFF to really make sure time interrupts don't go off immediately after being enabled
j trap_handler_end_\MODE\() // skip the trap handler when it is being defined.
// ---------------------------------------------------------------------------------------------

7
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-01.S
View file

@ -23,7 +23,7 @@
#include "WALLY-TEST-LIB-32.h"
RVTEST_ISA("RV32I_Zicsr")
RVTEST_ISA("RV32I_Sstc_Zicsr")
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",trap)
INIT_TESTS
@ -34,8 +34,9 @@ TRAP_HANDLER m, EXT_SIGNATURE=1 // turn on recording mtval and status bits on tr
li x28, 0x8
csrs mstatus, x28 // set mstatus.MIE bit to 1
WRITE_READ_CSR mie, 0xFFF // Enable interrupts from all sources // *** commented out until I can get the trap handler (and spike for time interrupts) to work correctly with interrupts
WRITE_READ_CSR stimecmp, 0xFFFFFFFF // set timer to high value so it doesn't go off immediately
WRITE_READ_CSR menvcfgh, 0x80000000 // Enable menvcfg.STCE
WRITE_READ_CSR mie, 0xFFF // Enable interrupts from all sources
// test 5.3.1.4 Basic trap tests
// instr address misaligned instructions are excluded from this test since they are impossible to cause when compressed instructions are enabled.

4
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output
View file

@ -1,3 +1,7 @@
FFFFFFFF # stimecmp low bits
00000000 # stimecmp high bits
00000000 # menvcfg low bits
80000000 # menvcfg high bits
00000aaa # Test 5.3.1.4: readback value from writing mie to enable interrupts
00000000 # skipping instruction address fault since they're impossible with compressed instrs enabled
00000001 # mcause from an instruction access fault

2
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h
View file

@ -274,7 +274,7 @@ end_trap_triggers:
la t4, 0x02004000 // MTIMECMP register in CLINT
li t5, 0xFFFFFFFF
sd t5, 0(t4) // set mtimecmp to 0xFFFFFFFF to really make sure time interrupts don't go off immediately after being enabled
j trap_handler_end_\MODE\() // skip the trap handler when it is being defined.
// ---------------------------------------------------------------------------------------------

6
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-01.S
View file

@ -22,7 +22,7 @@
///////////////////////////////////////////
#include "WALLY-TEST-LIB-64.h"
RVTEST_ISA("RV64I_Zicsr")
RVTEST_ISA("RV64I_Sstc_Zicsr")
RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",trap)
INIT_TESTS
@ -33,7 +33,9 @@ TRAP_HANDLER m, EXT_SIGNATURE=1 // turn on recording mtval and status bits on tr
li x28, 0x8
csrs mstatus, x28 // set mstatus.MIE bit to 1
WRITE_READ_CSR mie, 0xFFF // Enable interrupts from all sources
WRITE_READ_CSR stimecmp, 0xFFFFFFFF // set timer to high value so it doesn't go off immediately
WRITE_READ_CSR menvcfg, 0x8000000000000000 // Enable menvcfg.STCE
WRITE_READ_CSR mie, 0xFFF // Enable interrupts from all sources
// test 5.3.1.4 Basic trap tests