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Merge pull request #1367 from jordancarlin/benchmarking
Branch predictor benchmarking/performance validation updates
This commit is contained in:
Rose Thompson
GitHub
commit
c87fc015ef
11 changed files with 167 additions and 150 deletions
20
Makefile
20
Makefile
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@ -6,9 +6,9 @@ MAKEFLAGS += --output-sync --no-print-directory
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SIM = ${WALLY}/sim
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.PHONY: all riscof testfloat combined_IF_vectors zsbl benchmarks coremark embench coverage cvw-arch-verif clean
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.PHONY: all riscof testfloat combined_IF_vectors zsbl coverage cvw-arch-verif sim_bp clean
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all: riscof testfloat combined_IF_vectors zsbl coverage # cvw-arch-verif benchmarks
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all: riscof testfloat combined_IF_vectors zsbl coverage sim_bp # cvw-arch-verif
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# riscof builds the riscv-arch-test and wally-riscv-arch-test suites
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riscof:
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@ -23,22 +23,17 @@ combined_IF_vectors: testfloat riscof
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zsbl:
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$(MAKE) -C ${WALLY}/fpga/zsbl
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benchmarks:
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$(MAKE) coremark
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$(MAKE) embench
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coremark:
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cd ${WALLY}/benchmarks/coremark; $(MAKE); $(MAKE) run
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embench:
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cd ${WALLY}/benchmarks/embench; $(MAKE); $(MAKE) run
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coverage:
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$(MAKE) -C tests/coverage
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cvw-arch-verif:
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$(MAKE) -C ${WALLY}/addins/cvw-arch-verif
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sim_bp: ${WALLY}/addins/branch-predictor-simulator/src/sim_bp
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${WALLY}/addins/branch-predictor-simulator/src/sim_bp:
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$(MAKE) -C ${WALLY}/addins/branch-predictor-simulator/src
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# Requires a license for the Breker tool. See tests/breker/README.md for details
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breker:
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$(MAKE) -C ${WALLY}/testbench/trek_files
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@ -47,4 +42,5 @@ breker:
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clean:
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$(MAKE) clean -C sim
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$(MAKE) clean -C ${WALLY}/tests/fp
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$(MAKE) clean -C ${WALLY}/tests/coverage
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$(MAKE) clean -C ${WALLY}/addins/cvw-arch-verif
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@ -43,10 +43,7 @@ sim: sim_build_memfile sim_run speed
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# launches sim to simulate tests on wally
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sim_run:
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wsim rv32gc embench
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#mkdir -p ../../sim/wkdir
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#(cd ../../sim/ && wsim rv32gc embench)
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#cd ../../benchmarks/embench/
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wsim rv32gc embench --params "BPRED_LOGGER=1\'b1"
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# builds the objdump based on the compiled c elf files
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objdump:
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@ -3,7 +3,7 @@
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###########################################
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## Written: rose@rosethompson.net
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## Created: 12 March 2023
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## Modified:
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## Modified: 15 April 2025 jcarlin@hmc.edu
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##
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## Purpose: Converts a single branch.log containing multiple benchmark branch outcomes into
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## separate files, one for each program.
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@ -31,27 +31,26 @@
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################################################################################################
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File="$1"
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TrainLineNumbers=`cat $File | grep -n "TRAIN" | awk -NF ':' '{print $1}'`
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BeginLineNumbers=`cat $File | grep -n "BEGIN" | awk -NF ':' '{print $1}'`
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Name=`cat $File | grep -n "BEGIN" | awk -NF '/' '{print $6_$4}'`
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EndLineNumbers=`cat $File | grep -n "END" | awk -NF ':' '{print $1}'`
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echo $Name
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echo $BeginLineNumbers
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echo $EndLineNumbers
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TrainLineNumbers=$(grep -n "TRAIN" "$File" | awk -NF ':' '{print $1}')
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Name=$(grep -n "BEGIN" "$File" | awk -NF '/' '{print $7_$5}')
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EndLineNumbers=$(grep -n "END" "$File" | awk -NF ':' '{print $1}')
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NameArray=($Name)
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TrainLineNumberArray=($TrainLineNumbers)
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BeginLineNumberArray=($BeginLineNumbers)
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EndLineNumberArray=($EndLineNumbers)
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echo Name: "$Name"
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echo TrainLineNumbers: "$TrainLineNumbers"
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echo EndLineNumbers: "$EndLineNumbers"
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mapfile -t NameArray <<< "$Name"
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mapfile -t TrainLineNumberArray <<< "$TrainLineNumbers"
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mapfile -t EndLineNumberArray <<< "$EndLineNumbers"
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OutputPath=${File%%.*}
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mkdir -p $OutputPath
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mkdir -p "$OutputPath"
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Length=${#EndLineNumberArray[@]}
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for i in $(seq 0 1 $((Length-1)))
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do
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CurrName=${NameArray[$i]}
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CurrTrain=$((${TrainLineNumberArray[$i]}+1))
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CurrEnd=$((${EndLineNumberArray[$i]}-1))
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echo $CurrName, $CurrTrain, $CurrEnd
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sed -n "${CurrTrain},${CurrEnd}p" $File > $OutputPath/${CurrName}_${File}
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echo "${CurrName}", "${CurrTrain}", "${CurrEnd}"
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sed -n "${CurrTrain},${CurrEnd}p" "$File" > "${OutputPath}/${CurrName}_${File}"
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done
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@ -34,6 +34,8 @@ import sys
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import matplotlib.pyplot as plt
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import numpy as np
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WALLY = os.environ.get('WALLY')
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RefDataBP = [('twobitCModel6', 'twobitCModel', 64, 128, 10.0060297551637), ('twobitCModel8', 'twobitCModel', 256, 512, 8.4320392215602), ('twobitCModel10', 'twobitCModel', 1024, 2048, 7.29493318805151),
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('twobitCModel12', 'twobitCModel', 4096, 8192, 6.84739616147794), ('twobitCModel14', 'twobitCModel', 16384, 32768, 5.68432926870082), ('twobitCModel16', 'twobitCModel', 65536, 131072, 5.68432926870082),
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('gshareCModel6', 'gshareCModel', 64, 128, 11.4737703417701), ('gshareCModel8', 'gshareCModel', 256, 512, 8.52341470761974), ('gshareCModel10', 'gshareCModel', 1024, 2048, 6.32975690693015),
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@ -49,7 +51,7 @@ def ParseBranchListFile(path):
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with open(path) as BranchList:
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for line in BranchList:
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tokens = line.split()
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predictorLog = os.path.dirname(path) + '/' + tokens[0]
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predictorLog = f"{WALLY}/sim/{args.sim}/logs/{tokens[0]}"
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predictorType = tokens[1]
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predictorParams = tokens[2::]
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lst.append([predictorLog, predictorType, predictorParams])
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@ -64,14 +66,17 @@ def ProcessFile(fileName):
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benchmarks = []
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HPMClist = { }
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testName = ''
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opt = ''
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with open(fileName) as transcript:
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for line in transcript.readlines():
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lineToken = line.split()
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if(len(lineToken) > 3 and lineToken[1] == 'Read' and lineToken[2] == 'memfile'):
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opt = lineToken[3].split('/')[-4]
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testName = lineToken[3].split('/')[-1].split('.')[0]
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if (args.sim == "questa") & (lineToken[0] == "#"):
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lineToken = lineToken[1:] # Questa uses a leading # for each line, other simulators do not
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if(len(lineToken) > 2 and lineToken[0] == 'Read' and lineToken[1] == 'memfile'):
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opt = lineToken[2].split('/')[-4]
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testName = lineToken[2].split('/')[-1].split('.')[0]
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HPMClist = { }
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elif(len(lineToken) > 4 and lineToken[1][0:3] == 'Cnt'):
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elif(len(lineToken) > 3 and lineToken[0][0:3] == 'Cnt'):
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countToken = line.split('=')[1].split()
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value = int(countToken[0]) if countToken[0] != 'x' else 0
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name = ' '.join(countToken[1:])
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@ -440,6 +445,7 @@ displayMode.add_argument('--table', action='store_const', help='Display in text
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displayMode.add_argument('--gui', action='store_const', help='Display in text format only.', default=False, const=True)
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displayMode.add_argument('--debug', action='store_const', help='Display in text format only.', default=False, const=True)
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parser.add_argument('sources', nargs=1, help='File lists the input Questa transcripts to process.')
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parser.add_argument('sim', choices=["questa", "verilator", "vcs"], help='Simulator that was used to generate logs. This is used to find the files specified in the sources file.')
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parser.add_argument('FileName', metavar='FileName', type=str, nargs='?', help='output graph to file <name>.png If not included outputs to screen.', default=None)
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args = parser.parse_args()
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@ -184,52 +184,61 @@ derivconfigtests = [
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]
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bpredtests = [
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["nobpred_rv32gc", ["rv32i"]],
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["bpred_TWOBIT_6_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["bpred_TWOBIT_8_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["bpred_TWOBIT_10_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["bpred_TWOBIT_12_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["bpred_TWOBIT_14_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["bpred_TWOBIT_16_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["bpred_TWOBIT_6_16_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["bpred_TWOBIT_8_16_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["bpred_TWOBIT_10_16_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["bpred_TWOBIT_12_16_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["bpred_TWOBIT_14_16_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["bpred_TWOBIT_16_16_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["nobpred_rv32gc", ["arch32i"], "--params \"PrintHPMCounters=1\\'b1\""],
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["bpred_GSHARE_6_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["bpred_GSHARE_6_16_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["bpred_GSHARE_8_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["bpred_GSHARE_8_16_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["bpred_GSHARE_10_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["bpred_GSHARE_10_16_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["bpred_GSHARE_12_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["bpred_GSHARE_12_16_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["bpred_GSHARE_14_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["bpred_GSHARE_14_16_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["bpred_GSHARE_16_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["bpred_GSHARE_16_16_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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# twobit dirpred
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["bpred_TWOBIT_6_16_10_0_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
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["bpred_TWOBIT_6_16_10_1_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
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["bpred_TWOBIT_8_16_10_0_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
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["bpred_TWOBIT_8_16_10_1_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
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["bpred_TWOBIT_10_16_10_0_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
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["bpred_TWOBIT_10_16_10_1_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
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["bpred_TWOBIT_12_16_10_0_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
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["bpred_TWOBIT_12_16_10_1_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
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["bpred_TWOBIT_14_16_10_0_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
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["bpred_TWOBIT_14_16_10_1_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
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["bpred_TWOBIT_16_16_10_0_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
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["bpred_TWOBIT_16_16_10_1_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
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# gshare dirpred
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["bpred_GSHARE_6_16_10_0_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
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["bpred_GSHARE_6_16_10_1_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
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["bpred_GSHARE_8_16_10_0_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
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["bpred_GSHARE_8_16_10_1_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
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["bpred_GSHARE_10_16_10_0_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
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["bpred_GSHARE_10_16_10_1_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
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["bpred_GSHARE_12_16_10_0_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
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["bpred_GSHARE_12_16_10_1_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
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["bpred_GSHARE_14_16_10_0_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
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["bpred_GSHARE_14_16_10_1_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
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["bpred_GSHARE_16_16_10_0_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
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["bpred_GSHARE_16_16_10_1_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
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# btb
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["bpred_GSHARE_10_16_6_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["bpred_GSHARE_10_16_6_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["bpred_GSHARE_10_16_8_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["bpred_GSHARE_10_16_8_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["bpred_GSHARE_10_16_12_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["bpred_GSHARE_10_16_12_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["bpred_GSHARE_10_16_6_0_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
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["bpred_GSHARE_10_16_6_1_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
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["bpred_GSHARE_10_16_8_0_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
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["bpred_GSHARE_10_16_8_1_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
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# bpred_GSHARE_10_16_10_* tested above
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["bpred_GSHARE_10_16_12_0_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
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["bpred_GSHARE_10_16_12_1_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
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["bpred_GSHARE_10_16_14_0_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
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["bpred_GSHARE_10_16_14_1_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
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["bpred_GSHARE_10_16_16_0_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
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["bpred_GSHARE_10_16_16_1_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
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# ras
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["bpred_GSHARE_10_2_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["bpred_GSHARE_10_2_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["bpred_GSHARE_10_3_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["bpred_GSHARE_10_3_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["bpred_GSHARE_10_4_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["bpred_GSHARE_10_4_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["bpred_GSHARE_10_6_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["bpred_GSHARE_10_6_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["bpred_GSHARE_10_10_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["bpred_GSHARE_10_10_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"]
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["bpred_GSHARE_10_2_10_0_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
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["bpred_GSHARE_10_2_10_1_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
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["bpred_GSHARE_10_3_10_0_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
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["bpred_GSHARE_10_3_10_1_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
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["bpred_GSHARE_10_4_10_0_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
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["bpred_GSHARE_10_4_10_1_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
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["bpred_GSHARE_10_6_10_0_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
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["bpred_GSHARE_10_6_10_1_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
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["bpred_GSHARE_10_10_10_0_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
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["bpred_GSHARE_10_10_10_1_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
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# bpred_GSHARE_10_16_10_* tested above
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]
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testfloatdivconfigs = [
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@ -383,6 +392,7 @@ def parse_args():
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parser.add_argument("--nightly", help="Run large nightly regression", action="store_true")
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parser.add_argument("--buildroot", help="Include Buildroot Linux boot test (takes many hours, done along with --nightly)", action="store_true")
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parser.add_argument("--testfloat", help="Include Testfloat floating-point unit tests", action="store_true")
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parser.add_argument("--branch", help="Run branch predictor accuracy tests", action="store_true")
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parser.add_argument("--fp", help="Include floating-point tests in coverage (slower runtime)", action="store_true") # Currently not used
|
||||
parser.add_argument("--breker", help="Run Breker tests", action="store_true") # Requires a license for the breker tool. See tests/breker/README.md for details
|
||||
parser.add_argument("--dryrun", help="Print commands invoked to console without running regression", action="store_true")
|
||||
|
|
@ -411,6 +421,8 @@ def process_args(args):
|
|||
elif args.testfloat:
|
||||
sims = [testfloatsim]
|
||||
TIMEOUT_DUR = 30*60 # seconds
|
||||
elif args.branch:
|
||||
TIMEOUT_DUR = 120*60 # seconds
|
||||
elif args.nightly:
|
||||
TIMEOUT_DUR = 30*60 # seconds
|
||||
else:
|
||||
|
|
@ -434,8 +446,8 @@ def selectTests(args, sims, coverStr):
|
|||
if args.buildroot:
|
||||
# addTests(tests_buildrootboot, defaultsim) # non-lockstep with Verilator runs in about 2 hours
|
||||
addTests(tests_buildrootbootlockstep, lockstepsim, coverStr, configs) # lockstep with Questa and ImperasDV runs overnight
|
||||
|
||||
if args.ccov: # only run RV64GC tests on Questa in code coverage mode
|
||||
# only run RV64GC tests on in code coverage mode
|
||||
if args.ccov:
|
||||
addTestsByDir(f"{archVerifDir}/tests/rv64/", "rv64gc", coveragesim, coverStr, configs)
|
||||
addTestsByDir(f"{archVerifDir}/tests/priv/rv64/", "rv64gc", coveragesim, coverStr, configs) # doesn't help coverage much dh 4/12/25
|
||||
addTestsByDir(WALLY+"/tests/coverage/", "rv64gc", coveragesim, coverStr, configs)
|
||||
|
|
@ -443,7 +455,8 @@ def selectTests(args, sims, coverStr):
|
|||
addTestsByDir(f"{WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/pmp", "rv64gc", coveragesim, coverStr, configs)
|
||||
addTestsByDir(f"{WALLY}/tests/riscof/work/wally-riscv-arch-test/rv64i_m/privilege", "rv64gc", coveragesim, coverStr, configs)
|
||||
# addTestsByDir(f"{WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/F", "rv64gc", coveragesim, coverStr, configs) # doesn't help fdivsqrt coverage 4/3/2025
|
||||
elif args.fcov: # run tests in lockstep in functional coverage mode
|
||||
# run tests in lockstep in functional coverage mode
|
||||
if args.fcov:
|
||||
addTestsByDir(f"{archVerifDir}/tests/rv32/", "rv32gc", coveragesim, coverStr, configs, lockstepMode=1)
|
||||
addTestsByDir(f"{archVerifDir}/tests/rv64/", "rv64gc", coveragesim, coverStr, configs, lockstepMode=1)
|
||||
addTestsByDir(f"{archVerifDir}/tests/priv/rv32/", "rv32gc", coveragesim, coverStr, configs, lockstepMode=1)
|
||||
|
|
@ -452,17 +465,22 @@ def selectTests(args, sims, coverStr):
|
|||
addTestsByDir(f"{WALLY}/tests/riscof/work/riscv-arch-test/rv32i_m/vm_sv32", "rv32gc", coveragesim, coverStr, configs, lockstepMode=1)
|
||||
# addTestsByDir(f"{WALLY}/tests/riscof/work/riscv-arch-test/rv32i_m/pmp32", "rv32gc", coveragesim, coverStr, configs, lockstepMode=1) TODO: Add when working in lockstep
|
||||
# addTestsByDir(f"{WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/pmp", "rv64gc", coveragesim, coverStr, configs, lockstepMode=1) TODO: Add when working in lockstep
|
||||
elif args.fcov_act:
|
||||
# run riscv-arch-test tests in functional coverage mode
|
||||
if args.fcov_act:
|
||||
addTestsByDir(f"{WALLY}/tests/riscof/work/riscv-arch-test/rv32i_m", "rv32gc", coveragesim, coverStr, configs, lockstepMode=1)
|
||||
addTestsByDir(f"{WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m", "rv64gc", coveragesim, coverStr, configs, lockstepMode=1)
|
||||
elif args.breker:
|
||||
# run branch predictor tests
|
||||
if args.branch:
|
||||
addTests(bpredtests, defaultsim, coverStr, configs)
|
||||
# run Breker tests (requires a license for the breker tool)
|
||||
if args.breker:
|
||||
addTestsByDir(WALLY+"/tests/breker/work", "breker", "questa", coverStr, configs, brekerMode=1)
|
||||
elif not args.testfloat:
|
||||
# standard tests
|
||||
if not (args.testfloat or args.branch):
|
||||
for sim in sims:
|
||||
if not (args.buildroot and sim == lockstepsim): # skip short buildroot sim if running long one
|
||||
addTests(tests_buildrootshort, sim, coverStr, configs)
|
||||
addTests(standard_tests, sim, coverStr, configs)
|
||||
|
||||
# run derivative configurations and lockstep tests in nightly regression
|
||||
if args.nightly:
|
||||
addTestsByDir(WALLY+"/tests/coverage", "rv64gc", lockstepsim, coverStr, configs, lockstepMode=1)
|
||||
|
|
@ -470,7 +488,6 @@ def selectTests(args, sims, coverStr):
|
|||
addTestsByDir(WALLY+"/tests/riscof/work/wally-riscv-arch-test/rv32i_m", "rv32gc", lockstepsim, coverStr, configs, lockstepMode=1)
|
||||
addTests(derivconfigtests, defaultsim, coverStr, configs)
|
||||
# addTests(bpredtests, defaultsim) # This is currently broken in regression due to something related to the new wsim script.
|
||||
|
||||
# testfloat tests
|
||||
if (args.testfloat or args.nightly): # for nightly, run testfloat along with others
|
||||
testfloatconfigs = ["fdqh_rv64gc", "fdq_rv64gc", "fdh_rv64gc", "fd_rv64gc", "fh_rv64gc", "f_rv64gc", "fdqh_rv32gc", "f_rv32gc"]
|
||||
|
|
|
|||
25
sim/bp-results/branch-list-global-local.txt
Normal file
25
sim/bp-results/branch-list-global-local.txt
Normal file
|
|
@ -0,0 +1,25 @@
|
|||
TODO: These names likely need to be updated
|
||||
rv32gc_global6.log global 6
|
||||
rv32gc_global8.log global 8
|
||||
rv32gc_global10.log global 10
|
||||
rv32gc_global12.log global 12
|
||||
rv32gc_global14.log global 14
|
||||
rv32gc_global16.log global 16
|
||||
rv32gc_10local_basic6.log local 10 6
|
||||
rv32gc_10local_basic8.log local 10 8
|
||||
rv32gc_10local_basic10.log local 10 10
|
||||
rv32gc_10local_basic12.log local 10 12
|
||||
rv32gc_10local_basic14.log local 10 14
|
||||
rv32gc_10local_basic16.log local 10 16
|
||||
rv32gc_4local_basic6.log local 4 6
|
||||
rv32gc_4local_basic8.log local 4 8
|
||||
rv32gc_4local_basic10.log local 4 10
|
||||
rv32gc_4local_basic12.log local 4 12
|
||||
rv32gc_4local_basic14.log local 4 14
|
||||
rv32gc_4local_basic16.log local 4 16
|
||||
rv32gc_8local_basic6.log local 8 6
|
||||
rv32gc_8local_basic8.log local 8 8
|
||||
rv32gc_8local_basic10.log local 8 10
|
||||
rv32gc_8local_basic12.log local 8 12
|
||||
rv32gc_8local_basic14.log local 8 14
|
||||
rv32gc_8local_basic16.log local 8 16
|
||||
|
|
@ -1,12 +1,13 @@
|
|||
../logs/rv32gc_gshare6.log gshare 6
|
||||
../logs/rv32gc_gshare8.log gshare 8
|
||||
../logs/rv32gc_gshare10.log gshare 10
|
||||
../logs/rv32gc_gshare12.log gshare 12
|
||||
../logs/rv32gc_gshare14.log gshare 14
|
||||
../logs/rv32gc_gshare16.log gshare 16
|
||||
../logs/rv32gc_8local_basic6.log local 8 6
|
||||
../logs/rv32gc_8local_basic8.log local 8 8
|
||||
../logs/rv32gc_8local_basic10.log local 8 10
|
||||
../logs/rv32gc_8local_basic12.log local 8 12
|
||||
../logs/rv32gc_8local_basic14.log local 8 14
|
||||
../logs/rv32gc_8local_basic16.log local 8 16
|
||||
TODO: These names likely need to be updated
|
||||
rv32gc_gshare6.log gshare 6
|
||||
rv32gc_gshare8.log gshare 8
|
||||
rv32gc_gshare10.log gshare 10
|
||||
rv32gc_gshare12.log gshare 12
|
||||
rv32gc_gshare14.log gshare 14
|
||||
rv32gc_gshare16.log gshare 16
|
||||
rv32gc_8local_basic6.log local 8 6
|
||||
rv32gc_8local_basic8.log local 8 8
|
||||
rv32gc_8local_basic10.log local 8 10
|
||||
rv32gc_8local_basic12.log local 8 12
|
||||
rv32gc_8local_basic14.log local 8 14
|
||||
rv32gc_8local_basic16.log local 8 16
|
||||
|
|
|
|||
|
|
@ -1,36 +1,12 @@
|
|||
../logs/rv32gc_gshare6.log gshare 6
|
||||
../logs/rv32gc_gshare8.log gshare 8
|
||||
../logs/rv32gc_gshare10.log gshare 10
|
||||
../logs/rv32gc_gshare12.log gshare 12
|
||||
../logs/rv32gc_gshare14.log gshare 14
|
||||
../logs/rv32gc_gshare16.log gshare 16
|
||||
../logs/rv32gc_twobit6.log twobit 6
|
||||
../logs/rv32gc_twobit8.log twobit 8
|
||||
../logs/rv32gc_twobit10.log twobit 10
|
||||
../logs/rv32gc_twobit12.log twobit 12
|
||||
../logs/rv32gc_twobit14.log twobit 14
|
||||
../logs/rv32gc_twobit16.log twobit 16
|
||||
../logs/rv32gc_global6.log global 6
|
||||
../logs/rv32gc_global8.log global 8
|
||||
../logs/rv32gc_global10.log global 10
|
||||
../logs/rv32gc_global12.log global 12
|
||||
../logs/rv32gc_global14.log global 14
|
||||
../logs/rv32gc_global16.log global 16
|
||||
../logs/rv32gc_10local_basic6.log local 10 6
|
||||
../logs/rv32gc_10local_basic8.log local 10 8
|
||||
../logs/rv32gc_10local_basic10.log local 10 10
|
||||
../logs/rv32gc_10local_basic12.log local 10 12
|
||||
../logs/rv32gc_10local_basic14.log local 10 14
|
||||
../logs/rv32gc_10local_basic16.log local 10 16
|
||||
../logs/rv32gc_4local_basic6.log local 4 6
|
||||
../logs/rv32gc_4local_basic8.log local 4 8
|
||||
../logs/rv32gc_4local_basic10.log local 4 10
|
||||
../logs/rv32gc_4local_basic12.log local 4 12
|
||||
../logs/rv32gc_4local_basic14.log local 4 14
|
||||
../logs/rv32gc_4local_basic16.log local 4 16
|
||||
../logs/rv32gc_8local_basic6.log local 8 6
|
||||
../logs/rv32gc_8local_basic8.log local 8 8
|
||||
../logs/rv32gc_8local_basic10.log local 8 10
|
||||
../logs/rv32gc_8local_basic12.log local 8 12
|
||||
../logs/rv32gc_8local_basic14.log local 8 14
|
||||
../logs/rv32gc_8local_basic16.log local 8 16
|
||||
bpred_GSHARE_6_16_10_1_rv32gc_embench.log gshare 6
|
||||
bpred_GSHARE_8_16_10_1_rv32gc_embench.log gshare 8
|
||||
bpred_GSHARE_10_16_10_1_rv32gc_embench.log gshare 10
|
||||
bpred_GSHARE_12_16_10_1_rv32gc_embench.log gshare 12
|
||||
bpred_GSHARE_14_16_10_1_rv32gc_embench.log gshare 14
|
||||
bpred_GSHARE_16_16_10_1_rv32gc_embench.log gshare 16
|
||||
bpred_TWOBIT_6_16_10_1_rv32gc_embench.log twobit 6
|
||||
bpred_TWOBIT_8_16_10_1_rv32gc_embench.log twobit 8
|
||||
bpred_TWOBIT_10_16_10_1_rv32gc_embench.log twobit 10
|
||||
bpred_TWOBIT_12_16_10_1_rv32gc_embench.log twobit 12
|
||||
bpred_TWOBIT_14_16_10_1_rv32gc_embench.log twobit 14
|
||||
bpred_TWOBIT_16_16_10_1_rv32gc_embench.log twobit 16
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
../logs/bpred_GSHARE_16_16_6_0_rv32gc_embench.log btb 6
|
||||
../logs/bpred_GSHARE_16_16_8_0_rv32gc_embench.log btb 8
|
||||
../logs/bpred_GSHARE_16_16_10_0_rv32gc_embench.log btb 10
|
||||
../logs/bpred_GSHARE_16_16_12_0_rv32gc_embench.log btb 12
|
||||
../logs/bpred_GSHARE_16_16_14_0_rv32gc_embench.log btb 14
|
||||
../logs/bpred_GSHARE_16_16_16_0_rv32gc_embench.log btb 16
|
||||
bpred_GSHARE_10_16_6_0_rv32gc_embench.log btb 6
|
||||
bpred_GSHARE_10_16_8_0_rv32gc_embench.log btb 8
|
||||
bpred_GSHARE_10_16_10_0_rv32gc_embench.log btb 10
|
||||
bpred_GSHARE_10_16_12_0_rv32gc_embench.log btb 12
|
||||
bpred_GSHARE_10_16_14_0_rv32gc_embench.log btb 14
|
||||
bpred_GSHARE_10_16_16_0_rv32gc_embench.log btb 16
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
../logs/bpred_GSHARE_16_16_6_1_rv32gc_embench.log btb 6
|
||||
../logs/bpred_GSHARE_16_16_8_1_rv32gc_embench.log btb 8
|
||||
../logs/bpred_GSHARE_16_16_10_1_rv32gc_embench.log btb 10
|
||||
../logs/bpred_GSHARE_16_16_12_1_rv32gc_embench.log btb 12
|
||||
../logs/bpred_GSHARE_16_16_14_1_rv32gc_embench.log btb 14
|
||||
../logs/bpred_GSHARE_16_16_16_1_rv32gc_embench.log btb 16
|
||||
bpred_GSHARE_10_16_6_1_rv32gc_embench.log btb 6
|
||||
bpred_GSHARE_10_16_8_1_rv32gc_embench.log btb 8
|
||||
bpred_GSHARE_10_16_10_1_rv32gc_embench.log btb 10
|
||||
bpred_GSHARE_10_16_12_1_rv32gc_embench.log btb 12
|
||||
bpred_GSHARE_10_16_14_1_rv32gc_embench.log btb 14
|
||||
bpred_GSHARE_10_16_16_1_rv32gc_embench.log btb 16
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
../logs/bpred_GSHARE_10_3_10_0_rv32gc_embench.log ras 3
|
||||
../logs/bpred_GSHARE_10_4_10_0_rv32gc_embench.log ras 4
|
||||
../logs/bpred_GSHARE_10_6_10_0_rv32gc_embench.log ras 6
|
||||
../logs/bpred_GSHARE_10_10_10_0_rv32gc_embench.log ras 10
|
||||
../logs/bpred_GSHARE_10_16_10_0_rv32gc_embench.log ras 16
|
||||
bpred_GSHARE_10_3_10_0_rv32gc_embench.log ras 3
|
||||
bpred_GSHARE_10_4_10_0_rv32gc_embench.log ras 4
|
||||
bpred_GSHARE_10_6_10_0_rv32gc_embench.log ras 6
|
||||
bpred_GSHARE_10_10_10_0_rv32gc_embench.log ras 10
|
||||
bpred_GSHARE_10_16_10_0_rv32gc_embench.log ras 16
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue