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Merge pull request #1367 from jordancarlin/benchmarking
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Branch predictor benchmarking/performance validation updates
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Rose Thompson 2025-04-17 17:56:51 -05:00 • committed by GitHub
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11 changed files with 167 additions and 150 deletions
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20
Makefile
View file

@ -6,9 +6,9 @@ MAKEFLAGS += --output-sync --no-print-directory
SIM = ${WALLY}/sim SIM = ${WALLY}/sim
.PHONY: all riscof testfloat combined_IF_vectors zsbl benchmarks coremark embench coverage cvw-arch-verif clean .PHONY: all riscof testfloat combined_IF_vectors zsbl coverage cvw-arch-verif sim_bp clean
all: riscof testfloat combined_IF_vectors zsbl coverage # cvw-arch-verif benchmarks all: riscof testfloat combined_IF_vectors zsbl coverage sim_bp # cvw-arch-verif
# riscof builds the riscv-arch-test and wally-riscv-arch-test suites # riscof builds the riscv-arch-test and wally-riscv-arch-test suites
riscof: riscof:
@ -23,22 +23,17 @@ combined_IF_vectors: testfloat riscof
zsbl: zsbl:
$(MAKE) -C ${WALLY}/fpga/zsbl $(MAKE) -C ${WALLY}/fpga/zsbl
benchmarks:
$(MAKE) coremark
$(MAKE) embench
coremark:
cd ${WALLY}/benchmarks/coremark; $(MAKE); $(MAKE) run
embench:
cd ${WALLY}/benchmarks/embench; $(MAKE); $(MAKE) run
coverage: coverage:
$(MAKE) -C tests/coverage $(MAKE) -C tests/coverage
cvw-arch-verif: cvw-arch-verif:
$(MAKE) -C ${WALLY}/addins/cvw-arch-verif $(MAKE) -C ${WALLY}/addins/cvw-arch-verif
sim_bp: ${WALLY}/addins/branch-predictor-simulator/src/sim_bp
${WALLY}/addins/branch-predictor-simulator/src/sim_bp:
$(MAKE) -C ${WALLY}/addins/branch-predictor-simulator/src
# Requires a license for the Breker tool. See tests/breker/README.md for details # Requires a license for the Breker tool. See tests/breker/README.md for details
breker: breker:
$(MAKE) -C ${WALLY}/testbench/trek_files $(MAKE) -C ${WALLY}/testbench/trek_files
@ -47,4 +42,5 @@ breker:
clean: clean:
$(MAKE) clean -C sim $(MAKE) clean -C sim
$(MAKE) clean -C ${WALLY}/tests/fp $(MAKE) clean -C ${WALLY}/tests/fp
$(MAKE) clean -C ${WALLY}/tests/coverage
$(MAKE) clean -C ${WALLY}/addins/cvw-arch-verif $(MAKE) clean -C ${WALLY}/addins/cvw-arch-verif

5
benchmarks/embench/Makefile
View file

@ -43,10 +43,7 @@ sim: sim_build_memfile sim_run speed
# launches sim to simulate tests on wally # launches sim to simulate tests on wally
sim_run: sim_run:
wsim rv32gc embench wsim rv32gc embench --params "BPRED_LOGGER=1\'b1"
#mkdir -p ../../sim/wkdir
#(cd ../../sim/ && wsim rv32gc embench)
#cd ../../benchmarks/embench/
# builds the objdump based on the compiled c elf files # builds the objdump based on the compiled c elf files
objdump: objdump:

29
bin/SeparateBranch.sh
View file

@ -3,7 +3,7 @@
########################################### ###########################################
## Written: rose@rosethompson.net ## Written: rose@rosethompson.net
## Created: 12 March 2023 ## Created: 12 March 2023
## Modified: ## Modified: 15 April 2025 jcarlin@hmc.edu
## ##
## Purpose: Converts a single branch.log containing multiple benchmark branch outcomes into ## Purpose: Converts a single branch.log containing multiple benchmark branch outcomes into
## separate files, one for each program. ## separate files, one for each program.
@ -31,27 +31,26 @@
################################################################################################ ################################################################################################
File="$1" File="$1"
TrainLineNumbers=`cat $File | grep -n "TRAIN" | awk -NF ':' '{print $1}'` TrainLineNumbers=$(grep -n "TRAIN" "$File" | awk -NF ':' '{print $1}')
BeginLineNumbers=`cat $File | grep -n "BEGIN" | awk -NF ':' '{print $1}'` Name=$(grep -n "BEGIN" "$File" | awk -NF '/' '{print $7_$5}')
Name=`cat $File | grep -n "BEGIN" | awk -NF '/' '{print $6_$4}'` EndLineNumbers=$(grep -n "END" "$File" | awk -NF ':' '{print $1}')
EndLineNumbers=`cat $File | grep -n "END" | awk -NF ':' '{print $1}'`
echo $Name
echo $BeginLineNumbers
echo $EndLineNumbers
NameArray=($Name) echo Name: "$Name"
TrainLineNumberArray=($TrainLineNumbers) echo TrainLineNumbers: "$TrainLineNumbers"
BeginLineNumberArray=($BeginLineNumbers) echo EndLineNumbers: "$EndLineNumbers"
EndLineNumberArray=($EndLineNumbers)
mapfile -t NameArray <<< "$Name"
mapfile -t TrainLineNumberArray <<< "$TrainLineNumbers"
mapfile -t EndLineNumberArray <<< "$EndLineNumbers"
OutputPath=${File%%.*} OutputPath=${File%%.*}
mkdir -p $OutputPath mkdir -p "$OutputPath"
Length=${#EndLineNumberArray[@]} Length=${#EndLineNumberArray[@]}
for i in $(seq 0 1 $((Length-1))) for i in $(seq 0 1 $((Length-1)))
do do
CurrName=${NameArray[$i]} CurrName=${NameArray[$i]}
CurrTrain=$((${TrainLineNumberArray[$i]}+1)) CurrTrain=$((${TrainLineNumberArray[$i]}+1))
CurrEnd=$((${EndLineNumberArray[$i]}-1)) CurrEnd=$((${EndLineNumberArray[$i]}-1))
echo $CurrName, $CurrTrain, $CurrEnd echo "${CurrName}", "${CurrTrain}", "${CurrEnd}"
sed -n "${CurrTrain},${CurrEnd}p" $File > $OutputPath/${CurrName}_${File} sed -n "${CurrTrain},${CurrEnd}p" "$File" > "${OutputPath}/${CurrName}_${File}"
done done

16
bin/parseHPMC.py
View file

@ -34,6 +34,8 @@ import sys
import matplotlib.pyplot as plt import matplotlib.pyplot as plt
import numpy as np import numpy as np
WALLY = os.environ.get('WALLY')
RefDataBP = [('twobitCModel6', 'twobitCModel', 64, 128, 10.0060297551637), ('twobitCModel8', 'twobitCModel', 256, 512, 8.4320392215602), ('twobitCModel10', 'twobitCModel', 1024, 2048, 7.29493318805151), RefDataBP = [('twobitCModel6', 'twobitCModel', 64, 128, 10.0060297551637), ('twobitCModel8', 'twobitCModel', 256, 512, 8.4320392215602), ('twobitCModel10', 'twobitCModel', 1024, 2048, 7.29493318805151),
('twobitCModel12', 'twobitCModel', 4096, 8192, 6.84739616147794), ('twobitCModel14', 'twobitCModel', 16384, 32768, 5.68432926870082), ('twobitCModel16', 'twobitCModel', 65536, 131072, 5.68432926870082), ('twobitCModel12', 'twobitCModel', 4096, 8192, 6.84739616147794), ('twobitCModel14', 'twobitCModel', 16384, 32768, 5.68432926870082), ('twobitCModel16', 'twobitCModel', 65536, 131072, 5.68432926870082),
('gshareCModel6', 'gshareCModel', 64, 128, 11.4737703417701), ('gshareCModel8', 'gshareCModel', 256, 512, 8.52341470761974), ('gshareCModel10', 'gshareCModel', 1024, 2048, 6.32975690693015), ('gshareCModel6', 'gshareCModel', 64, 128, 11.4737703417701), ('gshareCModel8', 'gshareCModel', 256, 512, 8.52341470761974), ('gshareCModel10', 'gshareCModel', 1024, 2048, 6.32975690693015),
@ -49,7 +51,7 @@ def ParseBranchListFile(path):
with open(path) as BranchList: with open(path) as BranchList:
for line in BranchList: for line in BranchList:
tokens = line.split() tokens = line.split()
predictorLog = os.path.dirname(path) + '/' + tokens[0] predictorLog = f"{WALLY}/sim/{args.sim}/logs/{tokens[0]}"
predictorType = tokens[1] predictorType = tokens[1]
predictorParams = tokens[2::] predictorParams = tokens[2::]
lst.append([predictorLog, predictorType, predictorParams]) lst.append([predictorLog, predictorType, predictorParams])
@ -64,14 +66,17 @@ def ProcessFile(fileName):
benchmarks = [] benchmarks = []
HPMClist = { } HPMClist = { }
testName = '' testName = ''
opt = ''
with open(fileName) as transcript: with open(fileName) as transcript:
for line in transcript.readlines(): for line in transcript.readlines():
lineToken = line.split() lineToken = line.split()
if(len(lineToken) > 3 and lineToken[1] == 'Read' and lineToken[2] == 'memfile'): if (args.sim == "questa") & (lineToken[0] == "#"):
opt = lineToken[3].split('/')[-4] lineToken = lineToken[1:] # Questa uses a leading # for each line, other simulators do not
testName = lineToken[3].split('/')[-1].split('.')[0] if(len(lineToken) > 2 and lineToken[0] == 'Read' and lineToken[1] == 'memfile'):
opt = lineToken[2].split('/')[-4]
testName = lineToken[2].split('/')[-1].split('.')[0]
HPMClist = { } HPMClist = { }
elif(len(lineToken) > 4 and lineToken[1][0:3] == 'Cnt'): elif(len(lineToken) > 3 and lineToken[0][0:3] == 'Cnt'):
countToken = line.split('=')[1].split() countToken = line.split('=')[1].split()
value = int(countToken[0]) if countToken[0] != 'x' else 0 value = int(countToken[0]) if countToken[0] != 'x' else 0
name = ' '.join(countToken[1:]) name = ' '.join(countToken[1:])
@ -440,6 +445,7 @@ displayMode.add_argument('--table', action='store_const', help='Display in text
displayMode.add_argument('--gui', action='store_const', help='Display in text format only.', default=False, const=True) displayMode.add_argument('--gui', action='store_const', help='Display in text format only.', default=False, const=True)
displayMode.add_argument('--debug', action='store_const', help='Display in text format only.', default=False, const=True) displayMode.add_argument('--debug', action='store_const', help='Display in text format only.', default=False, const=True)
parser.add_argument('sources', nargs=1, help='File lists the input Questa transcripts to process.') parser.add_argument('sources', nargs=1, help='File lists the input Questa transcripts to process.')
parser.add_argument('sim', choices=["questa", "verilator", "vcs"], help='Simulator that was used to generate logs. This is used to find the files specified in the sources file.')
parser.add_argument('FileName', metavar='FileName', type=str, nargs='?', help='output graph to file <name>.png If not included outputs to screen.', default=None) parser.add_argument('FileName', metavar='FileName', type=str, nargs='?', help='output graph to file <name>.png If not included outputs to screen.', default=None)
args = parser.parse_args() args = parser.parse_args()

115
bin/regression-wally
View file

@ -184,52 +184,61 @@ derivconfigtests = [
] ]
bpredtests = [ bpredtests = [
["nobpred_rv32gc", ["rv32i"]], ["nobpred_rv32gc", ["arch32i"], "--params \"PrintHPMCounters=1\\'b1\""],
["bpred_TWOBIT_6_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
["bpred_TWOBIT_8_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
["bpred_TWOBIT_10_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
["bpred_TWOBIT_12_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
["bpred_TWOBIT_14_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
["bpred_TWOBIT_16_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
["bpred_TWOBIT_6_16_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
["bpred_TWOBIT_8_16_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
["bpred_TWOBIT_10_16_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
["bpred_TWOBIT_12_16_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
["bpred_TWOBIT_14_16_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
["bpred_TWOBIT_16_16_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
["bpred_GSHARE_6_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"], # twobit dirpred
["bpred_GSHARE_6_16_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"], ["bpred_TWOBIT_6_16_10_0_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
["bpred_GSHARE_8_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"], ["bpred_TWOBIT_6_16_10_1_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
["bpred_GSHARE_8_16_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"], ["bpred_TWOBIT_8_16_10_0_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
["bpred_GSHARE_10_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"], ["bpred_TWOBIT_8_16_10_1_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
["bpred_GSHARE_10_16_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"], ["bpred_TWOBIT_10_16_10_0_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
["bpred_GSHARE_12_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"], ["bpred_TWOBIT_10_16_10_1_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
["bpred_GSHARE_12_16_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"], ["bpred_TWOBIT_12_16_10_0_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
["bpred_GSHARE_14_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"], ["bpred_TWOBIT_12_16_10_1_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
["bpred_GSHARE_14_16_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"], ["bpred_TWOBIT_14_16_10_0_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
["bpred_GSHARE_16_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"], ["bpred_TWOBIT_14_16_10_1_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
["bpred_GSHARE_16_16_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"], ["bpred_TWOBIT_16_16_10_0_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
["bpred_TWOBIT_16_16_10_1_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
# gshare dirpred
["bpred_GSHARE_6_16_10_0_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
["bpred_GSHARE_6_16_10_1_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
["bpred_GSHARE_8_16_10_0_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
["bpred_GSHARE_8_16_10_1_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
["bpred_GSHARE_10_16_10_0_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
["bpred_GSHARE_10_16_10_1_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
["bpred_GSHARE_12_16_10_0_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
["bpred_GSHARE_12_16_10_1_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
["bpred_GSHARE_14_16_10_0_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
["bpred_GSHARE_14_16_10_1_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
["bpred_GSHARE_16_16_10_0_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
["bpred_GSHARE_16_16_10_1_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
# btb # btb
["bpred_GSHARE_10_16_6_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"], ["bpred_GSHARE_10_16_6_0_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
["bpred_GSHARE_10_16_6_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"], ["bpred_GSHARE_10_16_6_1_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
["bpred_GSHARE_10_16_8_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"], ["bpred_GSHARE_10_16_8_0_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
["bpred_GSHARE_10_16_8_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"], ["bpred_GSHARE_10_16_8_1_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
["bpred_GSHARE_10_16_12_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"], # bpred_GSHARE_10_16_10_* tested above
["bpred_GSHARE_10_16_12_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"], ["bpred_GSHARE_10_16_12_0_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
["bpred_GSHARE_10_16_12_1_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
["bpred_GSHARE_10_16_14_0_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
["bpred_GSHARE_10_16_14_1_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
["bpred_GSHARE_10_16_16_0_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
["bpred_GSHARE_10_16_16_1_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
# ras # ras
["bpred_GSHARE_10_2_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"], ["bpred_GSHARE_10_2_10_0_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
["bpred_GSHARE_10_2_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"], ["bpred_GSHARE_10_2_10_1_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
["bpred_GSHARE_10_3_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"], ["bpred_GSHARE_10_3_10_0_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
["bpred_GSHARE_10_3_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"], ["bpred_GSHARE_10_3_10_1_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
["bpred_GSHARE_10_4_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"], ["bpred_GSHARE_10_4_10_0_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
["bpred_GSHARE_10_4_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"], ["bpred_GSHARE_10_4_10_1_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
["bpred_GSHARE_10_6_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"], ["bpred_GSHARE_10_6_10_0_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
["bpred_GSHARE_10_6_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"], ["bpred_GSHARE_10_6_10_1_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
["bpred_GSHARE_10_10_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"], ["bpred_GSHARE_10_10_10_0_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
["bpred_GSHARE_10_10_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"] ["bpred_GSHARE_10_10_10_1_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
# bpred_GSHARE_10_16_10_* tested above
] ]
testfloatdivconfigs = [ testfloatdivconfigs = [
@ -383,6 +392,7 @@ def parse_args():
parser.add_argument("--nightly", help="Run large nightly regression", action="store_true") parser.add_argument("--nightly", help="Run large nightly regression", action="store_true")
parser.add_argument("--buildroot", help="Include Buildroot Linux boot test (takes many hours, done along with --nightly)", action="store_true") parser.add_argument("--buildroot", help="Include Buildroot Linux boot test (takes many hours, done along with --nightly)", action="store_true")
parser.add_argument("--testfloat", help="Include Testfloat floating-point unit tests", action="store_true") parser.add_argument("--testfloat", help="Include Testfloat floating-point unit tests", action="store_true")
parser.add_argument("--branch", help="Run branch predictor accuracy tests", action="store_true")
parser.add_argument("--fp", help="Include floating-point tests in coverage (slower runtime)", action="store_true") # Currently not used parser.add_argument("--fp", help="Include floating-point tests in coverage (slower runtime)", action="store_true") # Currently not used
parser.add_argument("--breker", help="Run Breker tests", action="store_true") # Requires a license for the breker tool. See tests/breker/README.md for details parser.add_argument("--breker", help="Run Breker tests", action="store_true") # Requires a license for the breker tool. See tests/breker/README.md for details
parser.add_argument("--dryrun", help="Print commands invoked to console without running regression", action="store_true") parser.add_argument("--dryrun", help="Print commands invoked to console without running regression", action="store_true")
@ -411,6 +421,8 @@ def process_args(args):
elif args.testfloat: elif args.testfloat:
sims = [testfloatsim] sims = [testfloatsim]
TIMEOUT_DUR = 30*60 # seconds TIMEOUT_DUR = 30*60 # seconds
elif args.branch:
TIMEOUT_DUR = 120*60 # seconds
elif args.nightly: elif args.nightly:
TIMEOUT_DUR = 30*60 # seconds TIMEOUT_DUR = 30*60 # seconds
else: else:
@ -434,8 +446,8 @@ def selectTests(args, sims, coverStr):
if args.buildroot: if args.buildroot:
# addTests(tests_buildrootboot, defaultsim) # non-lockstep with Verilator runs in about 2 hours # addTests(tests_buildrootboot, defaultsim) # non-lockstep with Verilator runs in about 2 hours
addTests(tests_buildrootbootlockstep, lockstepsim, coverStr, configs) # lockstep with Questa and ImperasDV runs overnight addTests(tests_buildrootbootlockstep, lockstepsim, coverStr, configs) # lockstep with Questa and ImperasDV runs overnight
# only run RV64GC tests on in code coverage mode
if args.ccov: # only run RV64GC tests on Questa in code coverage mode if args.ccov:
addTestsByDir(f"{archVerifDir}/tests/rv64/", "rv64gc", coveragesim, coverStr, configs) addTestsByDir(f"{archVerifDir}/tests/rv64/", "rv64gc", coveragesim, coverStr, configs)
addTestsByDir(f"{archVerifDir}/tests/priv/rv64/", "rv64gc", coveragesim, coverStr, configs) # doesn't help coverage much dh 4/12/25 addTestsByDir(f"{archVerifDir}/tests/priv/rv64/", "rv64gc", coveragesim, coverStr, configs) # doesn't help coverage much dh 4/12/25
addTestsByDir(WALLY+"/tests/coverage/", "rv64gc", coveragesim, coverStr, configs) addTestsByDir(WALLY+"/tests/coverage/", "rv64gc", coveragesim, coverStr, configs)
@ -443,7 +455,8 @@ def selectTests(args, sims, coverStr):
addTestsByDir(f"{WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/pmp", "rv64gc", coveragesim, coverStr, configs) addTestsByDir(f"{WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/pmp", "rv64gc", coveragesim, coverStr, configs)
addTestsByDir(f"{WALLY}/tests/riscof/work/wally-riscv-arch-test/rv64i_m/privilege", "rv64gc", coveragesim, coverStr, configs) addTestsByDir(f"{WALLY}/tests/riscof/work/wally-riscv-arch-test/rv64i_m/privilege", "rv64gc", coveragesim, coverStr, configs)
# addTestsByDir(f"{WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/F", "rv64gc", coveragesim, coverStr, configs) # doesn't help fdivsqrt coverage 4/3/2025 # addTestsByDir(f"{WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/F", "rv64gc", coveragesim, coverStr, configs) # doesn't help fdivsqrt coverage 4/3/2025
elif args.fcov: # run tests in lockstep in functional coverage mode # run tests in lockstep in functional coverage mode
if args.fcov:
addTestsByDir(f"{archVerifDir}/tests/rv32/", "rv32gc", coveragesim, coverStr, configs, lockstepMode=1) addTestsByDir(f"{archVerifDir}/tests/rv32/", "rv32gc", coveragesim, coverStr, configs, lockstepMode=1)
addTestsByDir(f"{archVerifDir}/tests/rv64/", "rv64gc", coveragesim, coverStr, configs, lockstepMode=1) addTestsByDir(f"{archVerifDir}/tests/rv64/", "rv64gc", coveragesim, coverStr, configs, lockstepMode=1)
addTestsByDir(f"{archVerifDir}/tests/priv/rv32/", "rv32gc", coveragesim, coverStr, configs, lockstepMode=1) addTestsByDir(f"{archVerifDir}/tests/priv/rv32/", "rv32gc", coveragesim, coverStr, configs, lockstepMode=1)
@ -452,17 +465,22 @@ def selectTests(args, sims, coverStr):
addTestsByDir(f"{WALLY}/tests/riscof/work/riscv-arch-test/rv32i_m/vm_sv32", "rv32gc", coveragesim, coverStr, configs, lockstepMode=1) addTestsByDir(f"{WALLY}/tests/riscof/work/riscv-arch-test/rv32i_m/vm_sv32", "rv32gc", coveragesim, coverStr, configs, lockstepMode=1)
# addTestsByDir(f"{WALLY}/tests/riscof/work/riscv-arch-test/rv32i_m/pmp32", "rv32gc", coveragesim, coverStr, configs, lockstepMode=1) TODO: Add when working in lockstep # addTestsByDir(f"{WALLY}/tests/riscof/work/riscv-arch-test/rv32i_m/pmp32", "rv32gc", coveragesim, coverStr, configs, lockstepMode=1) TODO: Add when working in lockstep
# addTestsByDir(f"{WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/pmp", "rv64gc", coveragesim, coverStr, configs, lockstepMode=1) TODO: Add when working in lockstep # addTestsByDir(f"{WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/pmp", "rv64gc", coveragesim, coverStr, configs, lockstepMode=1) TODO: Add when working in lockstep
elif args.fcov_act: # run riscv-arch-test tests in functional coverage mode
if args.fcov_act:
addTestsByDir(f"{WALLY}/tests/riscof/work/riscv-arch-test/rv32i_m", "rv32gc", coveragesim, coverStr, configs, lockstepMode=1) addTestsByDir(f"{WALLY}/tests/riscof/work/riscv-arch-test/rv32i_m", "rv32gc", coveragesim, coverStr, configs, lockstepMode=1)
addTestsByDir(f"{WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m", "rv64gc", coveragesim, coverStr, configs, lockstepMode=1) addTestsByDir(f"{WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m", "rv64gc", coveragesim, coverStr, configs, lockstepMode=1)
elif args.breker: # run branch predictor tests
if args.branch:
addTests(bpredtests, defaultsim, coverStr, configs)
# run Breker tests (requires a license for the breker tool)
if args.breker:
addTestsByDir(WALLY+"/tests/breker/work", "breker", "questa", coverStr, configs, brekerMode=1) addTestsByDir(WALLY+"/tests/breker/work", "breker", "questa", coverStr, configs, brekerMode=1)
elif not args.testfloat: # standard tests
if not (args.testfloat or args.branch):
for sim in sims: for sim in sims:
if not (args.buildroot and sim == lockstepsim): # skip short buildroot sim if running long one if not (args.buildroot and sim == lockstepsim): # skip short buildroot sim if running long one
addTests(tests_buildrootshort, sim, coverStr, configs) addTests(tests_buildrootshort, sim, coverStr, configs)
addTests(standard_tests, sim, coverStr, configs) addTests(standard_tests, sim, coverStr, configs)
# run derivative configurations and lockstep tests in nightly regression # run derivative configurations and lockstep tests in nightly regression
if args.nightly: if args.nightly:
addTestsByDir(WALLY+"/tests/coverage", "rv64gc", lockstepsim, coverStr, configs, lockstepMode=1) addTestsByDir(WALLY+"/tests/coverage", "rv64gc", lockstepsim, coverStr, configs, lockstepMode=1)
@ -470,7 +488,6 @@ def selectTests(args, sims, coverStr):
addTestsByDir(WALLY+"/tests/riscof/work/wally-riscv-arch-test/rv32i_m", "rv32gc", lockstepsim, coverStr, configs, lockstepMode=1) addTestsByDir(WALLY+"/tests/riscof/work/wally-riscv-arch-test/rv32i_m", "rv32gc", lockstepsim, coverStr, configs, lockstepMode=1)
addTests(derivconfigtests, defaultsim, coverStr, configs) addTests(derivconfigtests, defaultsim, coverStr, configs)
# addTests(bpredtests, defaultsim) # This is currently broken in regression due to something related to the new wsim script. # addTests(bpredtests, defaultsim) # This is currently broken in regression due to something related to the new wsim script.
# testfloat tests # testfloat tests
if (args.testfloat or args.nightly): # for nightly, run testfloat along with others if (args.testfloat or args.nightly): # for nightly, run testfloat along with others
testfloatconfigs = ["fdqh_rv64gc", "fdq_rv64gc", "fdh_rv64gc", "fd_rv64gc", "fh_rv64gc", "f_rv64gc", "fdqh_rv32gc", "f_rv32gc"] testfloatconfigs = ["fdqh_rv64gc", "fdq_rv64gc", "fdh_rv64gc", "fd_rv64gc", "fh_rv64gc", "f_rv64gc", "fdqh_rv32gc", "f_rv32gc"]

25
sim/bp-results/branch-list-global-local.txt Normal file
View file

@ -0,0 +1,25 @@
TODO: These names likely need to be updated
rv32gc_global6.log global 6
rv32gc_global8.log global 8
rv32gc_global10.log global 10
rv32gc_global12.log global 12
rv32gc_global14.log global 14
rv32gc_global16.log global 16
rv32gc_10local_basic6.log local 10 6
rv32gc_10local_basic8.log local 10 8
rv32gc_10local_basic10.log local 10 10
rv32gc_10local_basic12.log local 10 12
rv32gc_10local_basic14.log local 10 14
rv32gc_10local_basic16.log local 10 16
rv32gc_4local_basic6.log local 4 6
rv32gc_4local_basic8.log local 4 8
rv32gc_4local_basic10.log local 4 10
rv32gc_4local_basic12.log local 4 12
rv32gc_4local_basic14.log local 4 14
rv32gc_4local_basic16.log local 4 16
rv32gc_8local_basic6.log local 8 6
rv32gc_8local_basic8.log local 8 8
rv32gc_8local_basic10.log local 8 10
rv32gc_8local_basic12.log local 8 12
rv32gc_8local_basic14.log local 8 14
rv32gc_8local_basic16.log local 8 16

25
sim/bp-results/branch-list-gshare-local8.txt
View file

@ -1,12 +1,13 @@
../logs/rv32gc_gshare6.log gshare 6 TODO: These names likely need to be updated
../logs/rv32gc_gshare8.log gshare 8 rv32gc_gshare6.log gshare 6
../logs/rv32gc_gshare10.log gshare 10 rv32gc_gshare8.log gshare 8
../logs/rv32gc_gshare12.log gshare 12 rv32gc_gshare10.log gshare 10
../logs/rv32gc_gshare14.log gshare 14 rv32gc_gshare12.log gshare 12
../logs/rv32gc_gshare16.log gshare 16 rv32gc_gshare14.log gshare 14
../logs/rv32gc_8local_basic6.log local 8 6 rv32gc_gshare16.log gshare 16
../logs/rv32gc_8local_basic8.log local 8 8 rv32gc_8local_basic6.log local 8 6
../logs/rv32gc_8local_basic10.log local 8 10 rv32gc_8local_basic8.log local 8 8
../logs/rv32gc_8local_basic12.log local 8 12 rv32gc_8local_basic10.log local 8 10
../logs/rv32gc_8local_basic14.log local 8 14 rv32gc_8local_basic12.log local 8 12
../logs/rv32gc_8local_basic16.log local 8 16 rv32gc_8local_basic14.log local 8 14
rv32gc_8local_basic16.log local 8 16

48
sim/bp-results/branch-list.txt
View file

@ -1,36 +1,12 @@
../logs/rv32gc_gshare6.log gshare 6 bpred_GSHARE_6_16_10_1_rv32gc_embench.log gshare 6
../logs/rv32gc_gshare8.log gshare 8 bpred_GSHARE_8_16_10_1_rv32gc_embench.log gshare 8
../logs/rv32gc_gshare10.log gshare 10 bpred_GSHARE_10_16_10_1_rv32gc_embench.log gshare 10
../logs/rv32gc_gshare12.log gshare 12 bpred_GSHARE_12_16_10_1_rv32gc_embench.log gshare 12
../logs/rv32gc_gshare14.log gshare 14 bpred_GSHARE_14_16_10_1_rv32gc_embench.log gshare 14
../logs/rv32gc_gshare16.log gshare 16 bpred_GSHARE_16_16_10_1_rv32gc_embench.log gshare 16
../logs/rv32gc_twobit6.log twobit 6 bpred_TWOBIT_6_16_10_1_rv32gc_embench.log twobit 6
../logs/rv32gc_twobit8.log twobit 8 bpred_TWOBIT_8_16_10_1_rv32gc_embench.log twobit 8
../logs/rv32gc_twobit10.log twobit 10 bpred_TWOBIT_10_16_10_1_rv32gc_embench.log twobit 10
../logs/rv32gc_twobit12.log twobit 12 bpred_TWOBIT_12_16_10_1_rv32gc_embench.log twobit 12
../logs/rv32gc_twobit14.log twobit 14 bpred_TWOBIT_14_16_10_1_rv32gc_embench.log twobit 14
../logs/rv32gc_twobit16.log twobit 16 bpred_TWOBIT_16_16_10_1_rv32gc_embench.log twobit 16
../logs/rv32gc_global6.log global 6
../logs/rv32gc_global8.log global 8
../logs/rv32gc_global10.log global 10
../logs/rv32gc_global12.log global 12
../logs/rv32gc_global14.log global 14
../logs/rv32gc_global16.log global 16
../logs/rv32gc_10local_basic6.log local 10 6
../logs/rv32gc_10local_basic8.log local 10 8
../logs/rv32gc_10local_basic10.log local 10 10
../logs/rv32gc_10local_basic12.log local 10 12
../logs/rv32gc_10local_basic14.log local 10 14
../logs/rv32gc_10local_basic16.log local 10 16
../logs/rv32gc_4local_basic6.log local 4 6
../logs/rv32gc_4local_basic8.log local 4 8
../logs/rv32gc_4local_basic10.log local 4 10
../logs/rv32gc_4local_basic12.log local 4 12
../logs/rv32gc_4local_basic14.log local 4 14
../logs/rv32gc_4local_basic16.log local 4 16
../logs/rv32gc_8local_basic6.log local 8 6
../logs/rv32gc_8local_basic8.log local 8 8
../logs/rv32gc_8local_basic10.log local 8 10
../logs/rv32gc_8local_basic12.log local 8 12
../logs/rv32gc_8local_basic14.log local 8 14
../logs/rv32gc_8local_basic16.log local 8 16

12
sim/bp-results/btb-list.txt
View file

@ -1,6 +1,6 @@
../logs/bpred_GSHARE_16_16_6_0_rv32gc_embench.log btb 6 bpred_GSHARE_10_16_6_0_rv32gc_embench.log btb 6
../logs/bpred_GSHARE_16_16_8_0_rv32gc_embench.log btb 8 bpred_GSHARE_10_16_8_0_rv32gc_embench.log btb 8
../logs/bpred_GSHARE_16_16_10_0_rv32gc_embench.log btb 10 bpred_GSHARE_10_16_10_0_rv32gc_embench.log btb 10
../logs/bpred_GSHARE_16_16_12_0_rv32gc_embench.log btb 12 bpred_GSHARE_10_16_12_0_rv32gc_embench.log btb 12
../logs/bpred_GSHARE_16_16_14_0_rv32gc_embench.log btb 14 bpred_GSHARE_10_16_14_0_rv32gc_embench.log btb 14
../logs/bpred_GSHARE_16_16_16_0_rv32gc_embench.log btb 16 bpred_GSHARE_10_16_16_0_rv32gc_embench.log btb 16

12
sim/bp-results/class-list.txt
View file

@ -1,6 +1,6 @@
../logs/bpred_GSHARE_16_16_6_1_rv32gc_embench.log btb 6 bpred_GSHARE_10_16_6_1_rv32gc_embench.log btb 6
../logs/bpred_GSHARE_16_16_8_1_rv32gc_embench.log btb 8 bpred_GSHARE_10_16_8_1_rv32gc_embench.log btb 8
../logs/bpred_GSHARE_16_16_10_1_rv32gc_embench.log btb 10 bpred_GSHARE_10_16_10_1_rv32gc_embench.log btb 10
../logs/bpred_GSHARE_16_16_12_1_rv32gc_embench.log btb 12 bpred_GSHARE_10_16_12_1_rv32gc_embench.log btb 12
../logs/bpred_GSHARE_16_16_14_1_rv32gc_embench.log btb 14 bpred_GSHARE_10_16_14_1_rv32gc_embench.log btb 14
../logs/bpred_GSHARE_16_16_16_1_rv32gc_embench.log btb 16 bpred_GSHARE_10_16_16_1_rv32gc_embench.log btb 16

10
sim/bp-results/ras-list.txt
View file

@ -1,5 +1,5 @@
../logs/bpred_GSHARE_10_3_10_0_rv32gc_embench.log ras 3 bpred_GSHARE_10_3_10_0_rv32gc_embench.log ras 3
../logs/bpred_GSHARE_10_4_10_0_rv32gc_embench.log ras 4 bpred_GSHARE_10_4_10_0_rv32gc_embench.log ras 4
../logs/bpred_GSHARE_10_6_10_0_rv32gc_embench.log ras 6 bpred_GSHARE_10_6_10_0_rv32gc_embench.log ras 6
../logs/bpred_GSHARE_10_10_10_0_rv32gc_embench.log ras 10 bpred_GSHARE_10_10_10_0_rv32gc_embench.log ras 10
../logs/bpred_GSHARE_10_16_10_0_rv32gc_embench.log ras 16 bpred_GSHARE_10_16_10_0_rv32gc_embench.log ras 16