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exclude only impossible scenarios rather than whole line

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Corey Hickson 2025-04-02 18:06:19 -07:00
parent e6b3b3cec5
commit cc8a5b152f
3 changed files with 5 additions and 17 deletions
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3
sim/questa/coverage-exclusions-rv64gc.do
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@ -55,6 +55,9 @@ coverage exclude -scope /dut/core/fpu/fpu/postprocess/flags -linerange [GetLineN
coverage exclude -scope /dut/core/fpu/fpu/postprocess/flags -linerange [GetLineNum ${SRC}/fpu/postproc/flags.sv "assign Underflow"] -item e 1 -fecexprrow 22 coverage exclude -scope /dut/core/fpu/fpu/postprocess/flags -linerange [GetLineNum ${SRC}/fpu/postproc/flags.sv "assign Underflow"] -item e 1 -fecexprrow 22
# Convert int to fp will never underflow # Convert int to fp will never underflow
coverage exclude -scope /dut/core/fpu/fpu/postprocess/cvtshiftcalc -linerange [GetLineNum ${SRC}/fpu/postproc/cvtshiftcalc.sv "assign CvtResUf"] -item e 1 -fecexprrow 4 coverage exclude -scope /dut/core/fpu/fpu/postprocess/cvtshiftcalc -linerange [GetLineNum ${SRC}/fpu/postproc/cvtshiftcalc.sv "assign CvtResUf"] -item e 1 -fecexprrow 4
# without Q support, the FMT field is guaranteed to be 00, 01, or 10
coverage exclude -scope /dut/core/fpu/fpu/fctrl -linerange [GetLineNum ${SRC}/fpu/fctrl.sv "fmv int to fp"] -item 1 3 5
coverage exclude -scope /dut/core/fpu/fpu/fctrl -linerange [GetLineNum ${SRC}/fpu/fctrl.sv "fmv fp to int"] -item 1 3 5
################## ##################
# Cache Exclusions # Cache Exclusions

10
src/fpu/fctrl.sv
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@ -154,11 +154,8 @@ module fctrl import cvw::*; #(parameter cvw_t P) (
7'b11100??: if (Funct3D == 3'b001 & Rs2D == 5'b00000) 7'b11100??: if (Funct3D == 3'b001 & Rs2D == 5'b00000)
ControlsD = `FCTRLW'b0_1_10_00_000_0_0_0_0_0; // fclass ControlsD = `FCTRLW'b0_1_10_00_000_0_0_0_0_0; // fclass
else if (Funct3D == 3'b000 & Rs2D == 5'b00000) begin else if (Funct3D == 3'b000 & Rs2D == 5'b00000) begin
// coverage off if (Fmt[1:0] == 2'b00 | Fmt[1:0] == 2'b10 | (P.XLEN == 64 & Fmt[1:0] == 2'b01)) // coverage-tag: fmv fp to int
// without Q support, the FMT field is guaranteed to match one of these three, so this line cannot be fully covered
if (Fmt[1:0] == 2'b00 | Fmt[1:0] == 2'b10 | (P.XLEN == 64 & Fmt[1:0] == 2'b01))
ControlsD = `FCTRLW'b0_1_11_00_000_0_0_0_0_0; // fmv.x.w/d/h fp to int register (double only in RV64) ControlsD = `FCTRLW'b0_1_11_00_000_0_0_0_0_0; // fmv.x.w/d/h fp to int register (double only in RV64)
// coverage on
end else if (P.ZFA_SUPPORTED & P.XLEN == 32 & P.D_SUPPORTED & Funct7D[1:0] == 2'b01 & Funct3D == 3'b000 & Rs2D == 5'b00001) end else if (P.ZFA_SUPPORTED & P.XLEN == 32 & P.D_SUPPORTED & Funct7D[1:0] == 2'b01 & Funct3D == 3'b000 & Rs2D == 5'b00001)
ControlsD = `FCTRLW'b0_1_11_00_000_0_0_0_1_0; // fmvh.x.d (Zfa) ControlsD = `FCTRLW'b0_1_11_00_000_0_0_0_1_0; // fmvh.x.d (Zfa)
// Q not supported in RV64GC // Q not supported in RV64GC
@ -167,11 +164,8 @@ module fctrl import cvw::*; #(parameter cvw_t P) (
ControlsD = `FCTRLW'b0_1_11_00_000_0_0_0_1_0; // fmvh.x.q (Zfa) ControlsD = `FCTRLW'b0_1_11_00_000_0_0_0_1_0; // fmvh.x.q (Zfa)
// coverage on // coverage on
7'b11110??: if (Funct3D == 3'b000 & Rs2D == 5'b00000) begin 7'b11110??: if (Funct3D == 3'b000 & Rs2D == 5'b00000) begin
// coverage off if (Fmt[1:0] == 2'b00 | Fmt[1:0] == 2'b10 | (P.XLEN == 64 & Fmt[1:0] == 2'b01)) // coverage-tag: fmv int to fp
// without Q support, the FMT field is guaranteed to match one of these three, so this line cannot be fully covered
if (Fmt[1:0] == 2'b00 | Fmt[1:0] == 2'b10 | (P.XLEN == 64 & Fmt[1:0] == 2'b01))
ControlsD = `FCTRLW'b1_0_00_00_011_0_0_0_0_0; // fmv.w/d/h.x int to fp reg (double only in RV64) ControlsD = `FCTRLW'b1_0_00_00_011_0_0_0_0_0; // fmv.w/d/h.x int to fp reg (double only in RV64)
// coverage on
end else if (P.ZFA_SUPPORTED & Funct3D == 3'b000 & Rs2D == 5'b00001) end else if (P.ZFA_SUPPORTED & Funct3D == 3'b000 & Rs2D == 5'b00001)
ControlsD = `FCTRLW'b1_0_00_00_111_0_0_0_1_0; // fli (Zfa) ControlsD = `FCTRLW'b1_0_00_00_111_0_0_0_1_0; // fli (Zfa)
7'b0100000: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b00) 7'b0100000: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b00)

9
tests/coverage/fpu.S
View file

@ -154,15 +154,6 @@ main:
fdiv.s ft2, ft1, ft0 # should get interrupted, triggering a flush fdiv.s ft2, ft1, ft0 # should get interrupted, triggering a flush
csrci mstatus, 0b1000 # disable interrupts with mstatus.MIE csrci mstatus, 0b1000 # disable interrupts with mstatus.MIE
// fcrtl: unsupported rm with dyn rounding
csrrwi t0, frm, 0b111 # save previous rm, set frm csr to 111 (unsupported)
fadd.s f0, f0, f0, dyn # try to use unsupported rounding mode in csr
csrrwi x0, frm, 0b110 # set frm csr to 110 (unsupported)
fadd.s f0, f0, f0, dyn # try to use unsupported rounding mode in csr
csrrwi x0, frm, 0b101 # set frm csr to 101 (unsupported)
fadd.s f0, f0, f0, dyn # try to use unsupported rounding mode in csr
csrrw x0, frm, t0 # restore previous rm
# Completing branch coverage in fctrl.sv # Completing branch coverage in fctrl.sv
.word 0x38007553 // Testing the all False case for 119 - funct7 under, op = 101 0011 .word 0x38007553 // Testing the all False case for 119 - funct7 under, op = 101 0011
.word 0x40000053 // Line 145 All False Test case - illegal instruction? .word 0x40000053 // Line 145 All False Test case - illegal instruction?