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Added rv32 cboz test.
This commit is contained in:
Ross Thompson
parent
914b6f9734
commit
cd3349bd26
4 changed files with 568 additions and 0 deletions
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@ -1936,6 +1936,7 @@ string arch64zbs[] = '{
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string wally64priv[] = '{
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`WALLYTEST,
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"rv64i_m/privilege/src/WALLY-csr-permission-s-01.S",
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"rv64i_m/privilege/src/WALLY-cboz-01.S",
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"rv64i_m/privilege/src/WALLY-cbom-01.S",
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"rv64i_m/privilege/src/WALLY-csr-permission-u-01.S",
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"rv64i_m/privilege/src/WALLY-mie-01.S",
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@ -2030,6 +2031,7 @@ string arch64zbs[] = '{
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"rv32i_m/privilege/src/WALLY-csr-permission-s-01.S",
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"rv32i_m/privilege/src/WALLY-csr-permission-u-01.S",
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"rv32i_m/privilege/src/WALLY-cbom-01.S",
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"rv32i_m/privilege/src/WALLY-cboz-01.S",
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"rv32i_m/privilege/src/WALLY-mie-01.S",
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"rv32i_m/privilege/src/WALLY-minfo-01.S",
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"rv32i_m/privilege/src/WALLY-misa-01.S",
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@ -58,6 +58,7 @@ target_tests_nosim = \
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WALLY-plic-01 \
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WALLY-uart-01 \
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WALLY-cbom-01 \
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WALLY-cboz-01 \
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rv32i_tests = $(addsuffix .elf, $(rv32i_sc_tests))
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@ -0,0 +1,188 @@
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deadbeef # begin_signature
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deadbeef
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00000000 # destination 1
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00000000
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00000000 # destination 2
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ffffffff # signature The test writes -1 for correct answers and the a positive integer for incorrect copies.
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ffffffff
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ffffffff
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ffffffff
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ffffffff
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ffffffff
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ffffffff
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ffffffff
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ffffffff
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ffffffff
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ffffffff
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ffffffff
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ffffffff
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ffffffff
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0bad0bad
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0bad0bad
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@ -0,0 +1,377 @@
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///////////////////////////////////////////
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//
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// WALLY-cache-management-tests
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// invalidate, clean, and flush
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//
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// Author: Rose Thompson <ross1728@gmail.com>
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//
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// Created 22 August 2023
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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# Purpose: Tests the Zicboz cache instruction which all operate on cacheline
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# granularity blocks of memory. The instruction cbo.zero allocates a cacheline
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# and writes 0 to each byte. A dirty cacheline is overwritten, any data in main
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# memory is over written.
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# -----------
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# Copyright (c) 2020. RISC-V International. All rights reserved.
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# SPDX-License-Identifier: BSD-3-Clause
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# -----------
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#
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# This assembly file tests the cbo.inval, cbo.clean, and cbo.flush instructions of the RISC-V Zicbom extension.
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#
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#include "model_test.h"
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#include "arch_test.h"
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RVTEST_ISA("RV32I_Zicboz_Zicbom")
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# Test code region
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.section .text.init
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.globl rvtest_entry_point
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rvtest_entry_point:
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RVMODEL_BOOT
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RVTEST_CODE_BEGIN
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RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",cbo.zero)
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RVMODEL_IO_WRITE_STR(x31, "# Test Begin\n")
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CBOZTest:
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# *** TODO
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# first need to discover the length of the cacheline.
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# for now assume it is 64 bytes
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#addi sp, sp, -16
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#sd s0, 0(sp)
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#sd ra, 8(sp)
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la s0, signature
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################################################################################
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# Zero cache line hit overwrites
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################################################################################
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# theory of operation
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# 1. Read several cachelines of data from memory into the d cache and copy to a second region of memory
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# 2. Then verify the second region has the same data
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# 3. Zero that region of memory
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# 4. Verify the second region is all zero.
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# step 1
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CBOZTest_zero_step1:
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la a0, SourceData
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la a1, Destination1
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li a2, 128
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jal ra, memcpy4
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# step 2
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CBOZTest_zero_step2:
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la a0, SourceData
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la a1, Destination1
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li a2, 128
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jal ra, memcmp4
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sw a0, 0(s0) # should be -1
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addi s0, s0, 4
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# step 3
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CBOZTest_zero_step3:
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la a1, Destination1
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cbo.zero (a1)
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la a1, Destination1+64
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cbo.zero (a1)
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la a1, Destination1+128
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cbo.zero (a1)
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la a1, Destination1+192
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cbo.zero (a1)
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la a1, Destination1+256
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cbo.zero (a1)
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la a1, Destination1+320
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cbo.zero (a1)
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la a1, Destination1+384
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cbo.zero (a1)
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la a1, Destination1+448
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cbo.zero (a1)
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CBOZTest_zero_step4:
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# step 4 (should be zero)
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la a0, ZeroData
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la a1, Destination1
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li a2, 128
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jal ra, memcmp4
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sw a0, 0(s0) # should be -1
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addi s0, s0, 4
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################################################################################
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# Verify cbo.zero miss overwrites
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################################################################################
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# theory of operation
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# 1. Read 1 cacheline of data from memory into the d cache and copy to a second region of memory
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# 2. Then verify the second region has the same data
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# 3. Flush that one line
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# 4. Zero that one line
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# 5. Verify the second region is zero
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# step 1
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CBOZTest_miss_zero_step1:
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la a0, SourceData
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la a1, Destination1
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li a2, 16
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jal ra, memcpy4
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# step 2
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CBOZTest_miss_zero_step2:
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la a0, SourceData
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la a1, Destination1
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li a2, 16
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jal ra, memcmp4
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sw a0, 0(s0) # should be -1
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addi s0, s0, 4
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# step 3
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CBOZTest_miss_zero_step3:
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la a1, Destination1
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cbo.flush (a1)
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cbo.zero (a1)
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CBOZTest_miss_zero_step4:
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# step 4 (should be Invalid)
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la a0, ZeroData
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la a1, Destination1
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li a2, 16
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jal ra, memcmp4
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sw a0, 0(s0) # should be -1
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addi s0, s0, 4
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################################################################################
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# Verify cbo.zero miss with eviction overwrites
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################################################################################
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# theory of operation
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# 1. Read 1 cacheline of data from memory into the d cache and copy to a second region of memory
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# 2. Repeate 1 four times at 4KiB intervals
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# 2. Then verify the second region has the same data
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# 4. Zero each line
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# 5. Verify the second region is zero
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# step 1
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CBOZTest_eviction_zero_step1_0:
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la a0, SourceData
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la a1, Destination2
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li a2, 16
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jal ra, memcpy4
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CBOZTest_eviction_zero_step2_4096:
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la a0, SourceData+8
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la a1, Destination2+4096
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li a2, 16
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jal ra, memcpy4
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CBOZTest_eviction_zero_step2_8192:
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la a0, SourceData+16
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la a1, Destination2+8192
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li a2, 16
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jal ra, memcpy4
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CBOZTest_eviction_zero_step2_12288:
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la a0, SourceData+24
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la a1, Destination2+12288
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li a2, 16
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jal ra, memcpy4
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CBOZTest_eviction_zero_step2_16384:
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la a0, SourceData+32
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la a1, Destination2+16384
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li a2, 16
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jal ra, memcpy4
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# step 3
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CBOZTest_eviction_zero_step3_0:
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la a0, SourceData
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la a1, Destination2
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li a2, 16
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jal ra, memcmp4
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sw a0, 0(s0) # should be -1
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addi s0, s0, 4
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CBOZTest_eviction_zero_step3_4096:
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la a0, SourceData+8
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la a1, Destination2+4096
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li a2, 16
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jal ra, memcmp4
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sw a0, 0(s0) # should be -1
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addi s0, s0, 4
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CBOZTest_eviction_zero_step3_8192:
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la a0, SourceData+16
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la a1, Destination2+8192
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li a2, 16
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jal ra, memcmp4
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sw a0, 0(s0) # should be -1
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addi s0, s0, 4
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CBOZTest_eviction_zero_step3_12288:
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la a0, SourceData+24
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la a1, Destination2+12288
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li a2, 16
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jal ra, memcmp4
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sw a0, 0(s0) # should be -1
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addi s0, s0, 4
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CBOZTest_eviction_zero_step3_16384:
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la a0, SourceData+32
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la a1, Destination2+16384
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li a2, 16
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jal ra, memcmp4
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sw a0, 0(s0) # should be -1
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addi s0, s0, 4
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# step 4
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CBOZTest_eviction_zero_step4:
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la a1, Destination2
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cbo.zero (a1)
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la a1, Destination2+4096
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cbo.zero (a1)
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la a1, Destination2+8192
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cbo.zero (a1)
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la a1, Destination2+12288
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cbo.zero (a1)
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la a1, Destination2+16384
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cbo.zero (a1)
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CBOZTest_eviction_zero_step5_0:
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# step 5 (should be zero)
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la a0, ZeroData
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la a1, Destination2
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li a2, 16
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jal ra, memcmp4
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sw a0, 0(s0) # should be -1
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addi s0, s0, 4
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CBOZTest_eviction_zero_step5_4096:
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# step 5 (should be zero)
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la a0, ZeroData
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la a1, Destination2+4096
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li a2, 16
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jal ra, memcmp4
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sw a0, 0(s0) # should be -1
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addi s0, s0, 4
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CBOZTest_eviction_zero_step5_8192:
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# step 5 (should be zero)
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la a0, ZeroData
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la a1, Destination2+8192
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li a2, 16
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jal ra, memcmp4
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sw a0, 0(s0) # should be -1
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addi s0, s0, 4
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CBOZTest_eviction_zero_step5_12288:
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# step 5 (should be zero)
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la a0, ZeroData
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la a1, Destination2+12288
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li a2, 16
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jal ra, memcmp4
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sw a0, 0(s0) # should be -1
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addi s0, s0, 4
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CBOZTest_eviction_zero_step5_16384:
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# step 5 (should be zero)
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la a0, ZeroData
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la a1, Destination2+16384
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li a2, 16
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jal ra, memcmp4
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sw a0, 0(s0) # should be -1
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addi s0, s0, 4
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#ld s0, 0(sp)
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#ld ra, 8(sp)
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#addi sp, sp, 16
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#ret
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RVMODEL_HALT
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.type memcpy4, @function
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memcpy4:
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# a0 is the source
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# a1 is the dst
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# a2 is the number of 4 byte words
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mv t0, a0
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mv t1, a1
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li t2, 0
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memcpy4_loop:
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lw t3, 0(t0)
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sw t3, 0(t1)
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addi t0, t0, 4
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addi t1, t1, 4
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addi t2, t2, 1
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blt t2, a2, memcpy4_loop
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ret
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.type memcmp4, @function
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# returns which index mismatch, -1 if none
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memcmp4:
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# a0 is the source1
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# a1 is the source2
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# a2 is the number of 4 byte words
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mv t0, a0
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mv t1, a1
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li t2, 0
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memcmp4_loop:
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lw t3, 0(t0)
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lw t4, 0(t1)
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bne t3, t4, memcmp4_ne
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addi t0, t0, 4
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addi t1, t1, 4
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addi t2, t2, 1
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blt t2, a2, memcmp4_loop
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li a0, -1
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ret
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memcmp4_ne:
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mv a0, t2
|
||||
ret
|
||||
|
||||
RVTEST_CODE_END
|
||||
|
||||
|
||||
RVTEST_DATA_BEGIN
|
||||
# Input data section.
|
||||
#.data
|
||||
.align 7
|
||||
|
||||
ZeroData:
|
||||
.fill 128, 4, 0x0
|
||||
SourceData:
|
||||
.int 0, 1, 2, 3, 4, 5, 6, 7
|
||||
.int 8, 9, 10, 11, 12, 13, 14, 15
|
||||
.int 16, 17, 18, 19, 20, 21, 22, 23
|
||||
.int 24, 25, 26, 27, 28, 29, 30, 31
|
||||
.int 32, 33, 34, 35, 36, 37, 38, 39
|
||||
.int 40, 41, 42, 43, 44, 45, 46, 47
|
||||
.int 48, 49, 50, 51, 52, 53, 54, 55
|
||||
.int 56, 57, 58, 59, 60, 61, 62, 63
|
||||
.int 64, 65, 66, 67, 68, 69, 70, 71
|
||||
.int 72, 73, 74, 75, 76, 77, 78, 79
|
||||
.int 80, 81, 82, 83, 84, 85, 86, 87
|
||||
.int 88, 89, 90, 91, 92, 93, 94, 95
|
||||
.int 96, 97, 98, 99, 100, 101, 102, 103
|
||||
.int 104, 105, 106, 107, 108, 109, 110, 111
|
||||
.int 112, 113, 114, 115, 116, 117, 118, 119
|
||||
.int 120, 121, 122, 123, 124, 125, 126, 127
|
||||
|
||||
RVTEST_DATA_END
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
.fill 28, 4, 0xdeadbeef # this is annoying, but RVMODEL_DATA_END and BEGIN insert
|
||||
# 4 bytes. This needs to be aligned to a cacheline
|
||||
|
||||
.align 6
|
||||
Destination1:
|
||||
.fill 128, 4, 0xdeadbeef
|
||||
Destination2:
|
||||
.fill 16, 4, 0xdeadbeef
|
||||
signature:
|
||||
.fill 16, 4, 0x0bad0bad
|
||||
|
||||
RVMODEL_DATA_END
|
||||
|
||||
Loading…
Add table
Add a link
Reference in a new issue