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Merge pull request #1302 from davidharrishmc/dev

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E154 lab 4 script, cleanup, fix ebu.S page tables
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Jordan Carlin 2025-02-26 18:32:09 -08:00 • committed by GitHub
commit d07d7149cf
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13 changed files with 80 additions and 83 deletions
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6
config/rv32gc/imperas.ic
View file

@ -132,9 +132,9 @@
--callcommand refRoot/cpu/setPMA -lo 0x0000012100 -hi 0x000001211F -attributes " rw-aA- --48 " # SDC --callcommand refRoot/cpu/setPMA -lo 0x0000012100 -hi 0x000001211F -attributes " rw-aA- --48 " # SDC
--callcommand refRoot/cpu/setPMA -lo 0x0002000000 -hi 0x000200FFFF -attributes " rw-aA- 1248 " # CLINT --callcommand refRoot/cpu/setPMA -lo 0x0002000000 -hi 0x000200FFFF -attributes " rw-aA- 1248 " # CLINT
--callcommand refRoot/cpu/setPMA -lo 0x000C000000 -hi 0x000FFFFFFF -attributes " rw-aA- --4- " # PLIC --callcommand refRoot/cpu/setPMA -lo 0x000C000000 -hi 0x000FFFFFFF -attributes " rw-aA- --4- " # PLIC
--callcommand refRoot/cpu/setPMA -lo 0x0010000000 -hi 0x0010000007 -attributes " rw-aA- 1--- " # UART0 error - 0x10000000 - 0x100000FF --callcommand refRoot/cpu/setPMA -lo 0x0010000000 -hi 0x0010000007 -attributes " rw-aA- 1--- " # UART0
--callcommand refRoot/cpu/setPMA -lo 0x0010060000 -hi 0x00100600FF -attributes " rw-aA- --4- " # GPIO error - 0x10069000 - 0x100600FF --callcommand refRoot/cpu/setPMA -lo 0x0010060000 -hi 0x00100600FF -attributes " rw-aA- --4- " # GPIO
--callcommand refRoot/cpu/setPMA -lo 0x0010040000 -hi 0x0010040FFF -attributes " rw-aA- --4- " # SPI error - 0x10040000 - 0x10040FFF --callcommand refRoot/cpu/setPMA -lo 0x0010040000 -hi 0x0010040FFF -attributes " rw-aA- --4- " # SPI
--callcommand refRoot/cpu/setPMA -lo 0x0080000000 -hi 0x008FFFFFFF -attributes " rwx--- 1248 " # UNCORE_RAM --callcommand refRoot/cpu/setPMA -lo 0x0080000000 -hi 0x008FFFFFFF -attributes " rwx--- 1248 " # UNCORE_RAM
# Enable the Imperas instruction coverage # Enable the Imperas instruction coverage

6
config/rv64gc/imperas.ic
View file

@ -131,9 +131,9 @@
--callcommand refRoot/cpu/setPMA -lo 0x0000012100 -hi 0x000001211F -attributes " rw-aA- --48 " # SDC --callcommand refRoot/cpu/setPMA -lo 0x0000012100 -hi 0x000001211F -attributes " rw-aA- --48 " # SDC
--callcommand refRoot/cpu/setPMA -lo 0x0002000000 -hi 0x000200FFFF -attributes " rw-aA- 1248 " # CLINT --callcommand refRoot/cpu/setPMA -lo 0x0002000000 -hi 0x000200FFFF -attributes " rw-aA- 1248 " # CLINT
--callcommand refRoot/cpu/setPMA -lo 0x000C000000 -hi 0x000FFFFFFF -attributes " rw-aA- --4- " # PLIC --callcommand refRoot/cpu/setPMA -lo 0x000C000000 -hi 0x000FFFFFFF -attributes " rw-aA- --4- " # PLIC
--callcommand refRoot/cpu/setPMA -lo 0x0010000000 -hi 0x0010000007 -attributes " rw-aA- 1--- " # UART0 error - 0x10000000 - 0x100000FF --callcommand refRoot/cpu/setPMA -lo 0x0010000000 -hi 0x0010000007 -attributes " rw-aA- 1--- " # UART0
--callcommand refRoot/cpu/setPMA -lo 0x0010060000 -hi 0x00100600FF -attributes " rw-aA- --4- " # GPIO error - 0x10069000 - 0x100600FF --callcommand refRoot/cpu/setPMA -lo 0x0010060000 -hi 0x00100600FF -attributes " rw-aA- --4- " # GPIO
--callcommand refRoot/cpu/setPMA -lo 0x0010040000 -hi 0x0010040FFF -attributes " rw-aA- --4- " # SPI error - 0x10040000 - 0x10040FFF --callcommand refRoot/cpu/setPMA -lo 0x0010040000 -hi 0x0010040FFF -attributes " rw-aA- --4- " # SPI
--callcommand refRoot/cpu/setPMA -lo 0x0080000000 -hi 0x008FFFFFFF -attributes " rwx--- 1248 " # UNCORE_RAM --callcommand refRoot/cpu/setPMA -lo 0x0080000000 -hi 0x008FFFFFFF -attributes " rwx--- 1248 " # UNCORE_RAM
# Enable the Imperas instruction coverage # Enable the Imperas instruction coverage

5
examples/exercises/16p1/antimul.sh Executable file
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@ -0,0 +1,5 @@
#!/bin/sh
sed -i 's/assign MFunctD.*/assign MFunctD = 0; \/\/ *** Replace with your logic/' $WALLY/src/ieu/controller.sv
sed -i 's/ControlsD.*Divide/assign ControlsD = 0; \/\/ *** Replace with your logic/' $WALLY/src/ieu/controller.sv
sed -zi 's/\/\/ Number systems.*logic/ logic/' $WALLY/src/mdu/mul.sv
sed -zi 's/assign Aprime.*Memory/\/\/ Memory/' $WALLY/src/mdu/mul.sv

2
examples/exercises/fma16/fma16_testgen.c
View file

@ -77,7 +77,7 @@ void genCase(FILE *fptr, float16_t x, float16_t y, float16_t z, int mul, int add
float16_t resultmag = result; float16_t resultmag = result;
resultmag.v &= 0x7FFF; // take absolute value resultmag.v &= 0x7FFF; // take absolute value
if (f16_lt(resultmag, smallest) && (resultmag.v != 0x0000)) fprintf (fptr, "// skip denorm: "); if (f16_lt(resultmag, smallest) && (resultmag.v != 0x0000)) fprintf (fptr, "// skip denorm: ");
if ((softfloat_exceptionFlags) >> 1 % 2) fprintf(fptr, "// skip underflow: "); if ((softfloat_exceptionFlags >> 1) % 2) fprintf(fptr, "// skip underflow: ");
// skip special cases if requested // skip special cases if requested
if (resultmag.v == 0x0000 && !zeroAllowed) fprintf(fptr, "// skip zero: "); if (resultmag.v == 0x0000 && !zeroAllowed) fprintf(fptr, "// skip zero: ");

8
sim/questa/wave.do
View file

@ -127,7 +127,6 @@ add wave -noupdate -group ifu -expand -group icache -expand -group lru /testbenc
add wave -noupdate -group ifu -expand -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/LRUMemory add wave -noupdate -group ifu -expand -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/LRUMemory
add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/SelAdrTag add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/SelAdrTag
add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/AdrSelMuxSelTag add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/AdrSelMuxSelTag
add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/CacheSetTag
add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/PAdr add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/PAdr
add wave -noupdate -group ifu -expand -group icache -group way3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/SelectedWriteWordEn} add wave -noupdate -group ifu -expand -group icache -group way3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/SelectedWriteWordEn}
add wave -noupdate -group ifu -expand -group icache -group way3 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/CacheTagMem/ram/RAM} add wave -noupdate -group ifu -expand -group icache -group way3 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/CacheTagMem/ram/RAM}
@ -674,15 +673,8 @@ add wave -noupdate -group spi /testbench/dut/uncoregen/uncore/spi/spi/ChipSelect
add wave -noupdate -group spi /testbench/dut/uncoregen/uncore/spi/spi/SckMode add wave -noupdate -group spi /testbench/dut/uncoregen/uncore/spi/spi/SckMode
add wave -noupdate /testbench/dut/uncoregen/uncore/spi/spi/ShiftEdge add wave -noupdate /testbench/dut/uncoregen/uncore/spi/spi/ShiftEdge
add wave -noupdate /testbench/dut/uncoregen/uncore/spi/spi/TransmitData add wave -noupdate /testbench/dut/uncoregen/uncore/spi/spi/TransmitData
add wave -noupdate /testbench/loggers/ICacheLogger/HitMissString
add wave -noupdate /testbench/loggers/ICacheLogger/Enable
add wave -noupdate /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CacheEn add wave -noupdate /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CacheEn
add wave -noupdate /testbench/dut/core/ifu/bus/icache/icache/cachefsm/FlushStage add wave -noupdate /testbench/dut/core/ifu/bus/icache/icache/cachefsm/FlushStage
add wave -noupdate -expand -group {Dcache logger} /testbench/loggers/DCacheLogger/HitMissString
add wave -noupdate -expand -group {Dcache logger} /testbench/loggers/DCacheLogger/AccessTypeString
add wave -noupdate -expand -group {Dcache logger} /testbench/loggers/DCacheLogger/resetD
add wave -noupdate -expand -group {Dcache logger} /testbench/loggers/DCacheLogger/resetEdge
add wave -noupdate -expand -group {Dcache logger} -color Pink /testbench/loggers/DCacheLogger/Enabled
add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn
add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/FlushStage add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/FlushStage
TreeUpdate [SetDefaultTree] TreeUpdate [SetDefaultTree]

4
src/ieu/controller.sv
View file

@ -119,7 +119,7 @@ module controller import cvw::*; #(parameter cvw_t P) (
logic CMOD; // Cache management instruction logic CMOD; // Cache management instruction
logic InvalidateICacheD, FlushDCacheD;// Invalidate I$, flush D$ logic InvalidateICacheD, FlushDCacheD;// Invalidate I$, flush D$
logic MemReadE, CSRReadE; // Instruction reads memory, reads a CSR (needed for Hazard unit) logic MemReadE, CSRReadE; // Instruction reads memory, reads a CSR (needed for Hazard unit)
logic MDUE; // MDU (multiply/divide) operatio logic MDUE; // MDU (multiply/divide) operation
logic SCE; // Store Conditional instruction logic SCE; // Store Conditional instruction
logic CSRWriteD, CSRWriteE; // CSR write logic CSRWriteD, CSRWriteE; // CSR write
logic PrivilegedD, PrivilegedE; // Privileged instruction logic PrivilegedD, PrivilegedE; // Privileged instruction
@ -275,7 +275,7 @@ module controller import cvw::*; #(parameter cvw_t P) (
7'b0110011: if (RFunctD) 7'b0110011: if (RFunctD)
ControlsD = `CTRLW'b1_000_00_00_000_0_1_0_0_0_0_0_0_0_00_0_0; // R-type ControlsD = `CTRLW'b1_000_00_00_000_0_1_0_0_0_0_0_0_0_00_0_0; // R-type
else if (MFunctD) else if (MFunctD)
ControlsD = `CTRLW'b1_000_00_00_011_0_0_0_0_0_0_0_0_1_00_0_0; // Multiply/divide ControlsD = `CTRLW'b1_000_00_00_011_0_0_0_0_0_0_0_0_1_00_0_0; // Multiply/Divide
7'b0110111: ControlsD = `CTRLW'b1_100_01_00_000_0_0_0_1_0_0_0_0_0_00_0_0; // lui 7'b0110111: ControlsD = `CTRLW'b1_100_01_00_000_0_0_0_1_0_0_0_0_0_00_0_0; // lui
7'b0111011: if (RWFunctD) 7'b0111011: if (RWFunctD)
ControlsD = `CTRLW'b1_000_00_00_000_0_1_0_0_1_0_0_0_0_00_0_0; // R-type W instructions for RV64i ControlsD = `CTRLW'b1_000_00_00_000_0_1_0_0_1_0_0_0_0_00_0_0; // R-type W instructions for RV64i

86
tests/coverage/ebu.S
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@ -167,56 +167,56 @@ label1:
.align 16 .align 16
# root Page table situated at 0x80010000 # root Page table situated at 0x80010000
pagetable: pagetable:
.8byte 0x200044C1 # 0x00000000-0x80_00000000: PTE at 0x80011000 C1 dirty, accessed, valid .8byte 0x20004401 # 0x00000000-0x80_00000000: PTE at 0x80011000 01 valid
.8byte 0x00000000000010CF # misaligned terapage at 0x80_00000000 .8byte 0x000000000000100F # misaligned terapage at 0x80_00000000
# next page table at 0x80011000 # next page table at 0x80011000
.align 12 .align 12
.8byte 0x00000000000010CF # misaligned gigapage at 0x00000000 .8byte 0x000000000000100F # misaligned gigapage at 0x00000000
.8byte 0x00000000200058C1 # PTE for pages at 0x40000000 .8byte 0x0000000020005801 # PTE for pages at 0x40000000
.8byte 0x00000000200048C1 # gigapage at 0x80000000 pointing to 0x80120000 .8byte 0x0000000020004801 # gigapage at 0x80000000 pointing to 0x80120000
# Next page table at 0x80012000 for gigapage at 0x80000000 # Next page table at 0x80012000 for gigapage at 0x80000000
.align 12 .align 12
.8byte 0x0000000020004CC1 # for VA starting at 80000000 (pointer to NAPOT 64 KiB pages) .8byte 0x0000000020004C01 # for VA starting at 80000000 (pointer to NAPOT 64 KiB pages)
.8byte 0x0000000020014CCF # for VA starting at 80200000 (misaligned megapage) .8byte 0x0000000020014C0F # for VA starting at 80200000 (misaligned megapage)
.8byte 0x00000000200050C1 # for VA starting at 80400000 (bad PBMT pages) .8byte 0x0000000020005001 # for VA starting at 80400000 (bad PBMT pages)
.8byte 0x4000000020004CC1 # for VA starting at 80600000 (bad entry: nonleaf PTE can't have PBMT != 0) .8byte 0x4000000020004C01 # for VA starting at 80600000 (bad entry: nonleaf PTE can't have PBMT != 0)
.8byte 0x00000000200054C1 # for VA starting at 80800000 (testing rwx permissiosn with cbom/cboz) .8byte 0x0000000020005401 # for VA starting at 80800000 (testing rwx permissiosn with cbom/cboz)
.8byte 0x00000000200058C1 # for VA starting at 80A00000 (pointer to NAPOT 64 KiB pages like at 80000000) .8byte 0x0000000020005801 # for VA starting at 80A00000 (pointer to NAPOT 64 KiB pages like at 80000000)
.8byte 0x0000000020004CC1 .8byte 0x0000000020004C01
.8byte 0x0000000020004CC1 .8byte 0x0000000020004C01
.8byte 0x0000000020004CC1 .8byte 0x0000000020004C01
.8byte 0x0000000020004CC1 .8byte 0x0000000020004C01
.8byte 0x0000000020004CC1 .8byte 0x0000000020004C01
.8byte 0x0000000020004CC1 .8byte 0x0000000020004C01
.8byte 0x0000000020004CC1 .8byte 0x0000000020004C01
.8byte 0x0000000020004CC1 .8byte 0x0000000020004C01
.8byte 0x0000000020004CC1 .8byte 0x0000000020004C01
.8byte 0x0000000020004CC1 .8byte 0x0000000020004C01
.8byte 0x0000000020004CC1 .8byte 0x0000000020004C01
.8byte 0x0000000020004CC1 .8byte 0x0000000020004C01
.8byte 0x0000000020004CC1 .8byte 0x0000000020004C01
.8byte 0x0000000020004CC1 .8byte 0x0000000020004C01
.8byte 0x0000000020004CC1 .8byte 0x0000000020004C01
.8byte 0x0000000020004CC1 .8byte 0x0000000020004C01
.8byte 0x0000000020004CC1 .8byte 0x0000000020004C01
.8byte 0x0000000020004CC1 .8byte 0x0000000020004C01
.8byte 0x0000000020004CC1 .8byte 0x0000000020004C01
.8byte 0x0000000020004CC1 .8byte 0x0000000020004C01
.8byte 0x0000000020004CC1 .8byte 0x0000000020004C01
.8byte 0x0000000020004CC1 .8byte 0x0000000020004C01
.8byte 0x0000000020004CC1 .8byte 0x0000000020004C01
.8byte 0x0000000020004CC1 .8byte 0x0000000020004C01
.8byte 0x0000000020004CC1 .8byte 0x0000000020004C01
.8byte 0x0000000020004CC1 .8byte 0x0000000020004C01
.8byte 0x0000000020004CC1 .8byte 0x0000000020004C01
.8byte 0x0000000020004CC1 .8byte 0x0000000020004C01
.8byte 0x0000000020004CC1 .8byte 0x0000000020004C01
.8byte 0x0000000020004CC1 .8byte 0x0000000020004C01
.8byte 0x0000000020004CC1 .8byte 0x0000000020004C01
.8byte 0x0000000020004CC1 .8byte 0x0000000020004C01
# Leaf page table at 0x80013000 with NAPOT pages # Leaf page table at 0x80013000 with NAPOT pages
.align 12 .align 12

8
tests/coverage/ifuCamlineWrite.S
View file

@ -64,16 +64,16 @@ finished:
.align 16 .align 16
# Page table situated at 0x80010000 # Page table situated at 0x80010000
pagetable: pagetable:
.8byte 0x200044C1 // old page table was 200040 which just pointed to itself! wrong .8byte 0x20004401 // old page table was 200040 which just pointed to itself! wrong
.align 12 .align 12
.8byte 0x0000000000000000 .8byte 0x0000000000000000
.8byte 0x00000000200048C1 .8byte 0x0000000020004801
.8byte 0x00000000200048C1 .8byte 0x0000000020004801
.align 12 .align 12
.8byte 0x0000000020004CC1 .8byte 0x0000000020004C01
//.8byte 0x00000200800CF// ADD IN THE MEGAPAGE should 3 nibbles of zeros be removed? //.8byte 0x00000200800CF// ADD IN THE MEGAPAGE should 3 nibbles of zeros be removed?
.align 12 .align 12

12
tests/coverage/nonleafpbmtfault.S
View file

@ -60,17 +60,17 @@ finished:
.align 16 .align 16
# Page table situated at 0x80010000 # Page table situated at 0x80010000
pagetable: pagetable:
.8byte 0x200044C1 .8byte 0x20004401
.8byte 0x200044C1 .8byte 0x20004401
.align 12 .align 12
.8byte 0x40000040200048C1 .8byte 0x4000004020004801
.8byte 0x00000000200048C1 .8byte 0x0000000020004801
.8byte 0x00000000200048C1 .8byte 0x0000000020004801
.align 12 .align 12
.8byte 0x0000000020004CC1 .8byte 0x0000000020004C01
.align 12 .align 12
#80000000 #80000000

6
tests/coverage/tlbASID.S
View file

@ -73,16 +73,16 @@ finished:
.align 19 .align 19
# level 3 Page table situated at 0x8008 0000, should point to 8008,1000 # level 3 Page table situated at 0x8008 0000, should point to 8008,1000
pagetable: pagetable:
.8byte 0x200204C1 .8byte 0x20020401
.align 12 // level 2 page table, contains direction to a gigapage .align 12 // level 2 page table, contains direction to a gigapage
.8byte 0x0 .8byte 0x0
.8byte 0x0 .8byte 0x0
.8byte 0x200000CF // gigapage that starts at 8000 0000 goes to C000 0000 .8byte 0x200000CF // gigapage that starts at 8000 0000 goes to C000 0000
.8byte 0x200208C1 // pointer to next page table entry at 8008 2000 .8byte 0x20020801 // pointer to next page table entry at 8008 2000
.align 12 // level 1 page table, points to level 0 page table .align 12 // level 1 page table, points to level 0 page table
.8byte 0x20020CC1 .8byte 0x20020C01
.align 12 // level 0 page table, points to address C000 0000 // FOR NOW ALL OF THESE GO TO 8 instead of C cause they start with 2 .align 12 // level 0 page table, points to address C000 0000 // FOR NOW ALL OF THESE GO TO 8 instead of C cause they start with 2
.8byte 0x200000CF // access xC000 0000 .8byte 0x200000CF // access xC000 0000

6
tests/coverage/tlbGLB.S
View file

@ -83,16 +83,16 @@ nASID: #swap to different address space -> jump to each address
.align 19 .align 19
# level 3 Page table situated at 0x8008 0000, should point to 8008,1000 # level 3 Page table situated at 0x8008 0000, should point to 8008,1000
pagetable: pagetable:
.8byte 0x200204C1 .8byte 0x20020401
.align 12 // level 2 page table, contains direction to a gigapageg .align 12 // level 2 page table, contains direction to a gigapageg
.8byte 0x0 .8byte 0x0
.8byte 0x0 .8byte 0x0
.8byte 0x200000EF // gigapage that starts at 8000 0000 goes to C000 0000 .8byte 0x200000EF // gigapage that starts at 8000 0000 goes to C000 0000
.8byte 0x200208E1 // pointer to next page table entry at 8008 2000 .8byte 0x20020821 // pointer to next page table entry at 8008 2000
.align 12 // level 1 page table, points to level 0 page table .align 12 // level 1 page table, points to level 0 page table
.8byte 0x20020CE1 .8byte 0x20020C21
.align 12 // level 0 page table, points to address C000 0000 // FOR NOW ALL OF THESE GO TO 8 instead of C cause they start with 2 .align 12 // level 0 page table, points to address C000 0000 // FOR NOW ALL OF THESE GO TO 8 instead of C cause they start with 2
.8byte 0x200000EF // access xC000 0000 .8byte 0x200000EF // access xC000 0000

2
tests/coverage/tlbGP.S
View file

@ -64,7 +64,7 @@ finished:
.align 16 .align 16
# Page table situated at 0x80010000 # Page table situated at 0x80010000
pagetable: pagetable:
.8byte 0x200044C1 .8byte 0x20004401
.align 12 .align 12
.8byte 0x000000CF //8000 0000 .8byte 0x000000CF //8000 0000

12
tests/coverage/tlbMisaligned.S
View file

@ -69,17 +69,17 @@ finished:
.align 16 .align 16
# Page table situated at 0x80010000 # Page table situated at 0x80010000
pagetable: pagetable:
.8byte 0x200044C1 .8byte 0x20004401
.align 12 .align 12
.8byte 0x00000000200048C1 .8byte 0x0000000020004801
.8byte 0x00000000200048C1 .8byte 0x0000000020004801
.8byte 0x00000000200048C1 .8byte 0x0000000020004801
.align 12 .align 12
.8byte 0x0000000020004CC1 .8byte 0x0000000020004C01
//.8byte 0x00000200800CF// ADD IN THE MEGAPAGE should 3 nibbles of zeros be removed? //.8byte 0x000002008000F// ADD IN THE MEGAPAGE should 3 nibbles of zeros be removed?
.align 12 .align 12
#80000000 #80000000