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Factored out the rvvi testbench code into rvvitbwrapper.

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This commit is contained in:
Rose Thompson 2024-07-24 13:10:57 -05:00
parent b1a711ae0f
commit d0a5b278b7
3 changed files with 174 additions and 124 deletions
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2
fpga/src/fpgaTopArtyA7.sv
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@ -28,7 +28,7 @@
import cvw::*;
module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0)
module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 1)
(input default_100mhz_clk,
(* mark_debug = "true" *) input resetn,
input south_reset,