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Removed ahbsdc submodule since it is no longer used. Updated old

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submodules pointing to ross144 to rosethompson repos.
This commit is contained in:
Rose Thompson 2024-10-15 10:11:12 -05:00
parent fed88f6b17
commit d4fc3245b0
3 changed files with 3 additions and 7 deletions
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7
.gitmodules vendored
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@ -20,14 +20,11 @@
branch = dev
[submodule "addins/branch-predictor-simulator"]
path = addins/branch-predictor-simulator
url = https://github.com/ross144/branch-predictor-simulator
[submodule "addins/ahbsdc"]
path = addins/ahbsdc
url = https://github.com/JacobPease/ahbsdc.git
url = https://github.com/rosethompson/branch-predictor-simulator
[submodule "addins/verilog-ethernet"]
sparseCheckout = true
path = addins/verilog-ethernet
url = https://github.com/ross144/verilog-ethernet.git
url = https://github.com/rosethompson/verilog-ethernet.git
[submodule "cvw-arch-verif"]
path = addins/cvw-arch-verif
url = https://github.com/openhwgroup/cvw-arch-verif

1
addins/ahbsdc

@ -1 +0,0 @@
Subproject commit 33418c8dc11baf63e843b0d35f57d22c1e3182e3

2
fpga/generator/wally.tcl
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@ -47,7 +47,7 @@ if {$board=="ArtyA7"} {
# read in all other rtl
add_files [glob -type f ../src/CopiedFiles_do_not_add_to_repo/*/*.sv ../src/CopiedFiles_do_not_add_to_repo/*/*/*.sv]
set_property include_dirs {../src/CopiedFiles_do_not_add_to_repo/config ../../config/shared ../../addins/ahbsdc/sdc} [current_fileset]
set_property include_dirs {../src/CopiedFiles_do_not_add_to_repo/config ../../config/shared} [current_fileset]
# define top level