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Simplified the fpgatop SDCCLK logic.

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Rose Thompson 2024-11-12 15:29:05 -06:00
parent f7270763a6
commit d5e8ecbed5
1 changed files with 1 additions and 2 deletions
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3
fpga/src/fpgaTop.sv
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@ -182,7 +182,6 @@ module fpgaTop
logic [511 : 0] dbg_bus;
logic CLK208;
logic SDCCLKInternal;
assign GPIOIN = {25'b0, SDCCD, SDCWP, 2'b0, GPI};
assign GPO = GPIOOUT[4:0];
@ -216,7 +215,7 @@ module fpgaTop
.HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
.HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0),
.GPIOIN, .GPIOOUT, .GPIOEN,
.UARTSin, .UARTSout, .SDCIn, .SDCCmd, .SDCCS(SDCCSin), .SDCCLK(SDCCLK), .ExternalStall(RVVIStall));
.UARTSin, .UARTSout, .SDCIn, .SDCCmd, .SDCCS(SDCCSin), .SDCCLK, .ExternalStall(RVVIStall));
// ahb lite to axi bridge