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Fixed bug decoding svinval instructions and checking TVM
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2 changed files with 18 additions and 10 deletions
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@ -31,7 +31,7 @@
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module privdec import cvw::*; #(parameter cvw_t P) (
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input logic clk, reset,
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input logic StallW, FlushW,
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input logic [31:15] InstrM, // privileged instruction function field
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input logic [31:7 ] InstrM, // privileged instruction function field
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input logic PrivilegedM, // is this a privileged instruction (from IEU controller)
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input logic IllegalIEUFPUInstrM, // Not a legal IEU instruction
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input logic IllegalCSRAccessM, // Not a legal CSR access
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@ -43,26 +43,31 @@ module privdec import cvw::*; #(parameter cvw_t P) (
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output logic wfiM, wfiW, sfencevmaM // wfi / sfence.vma / sinval.vma instructions
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);
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logic rs1zeroM; // rs1 field = 0
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logic rs1zeroM, rdzeroM; // rs1 / rd field = 0
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logic IllegalPrivilegedInstrM; // privileged instruction isn't a legal one or in legal mode
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logic WFITimeoutM; // WFI reaches timeout threshold
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logic ebreakM, ecallM; // ebreak / ecall instructions
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logic sinvalvmaM; // sinval.vma
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logic presfencevmaM; // sfence.vma before checking privilege mode
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logic sfencewinvalM, sfenceinvalirM; // sfence.w.inval, sfence.inval.ir
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logic invalM; // any of the svinval instructions
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logic vmaM; // sfence.vma or sinval.vma
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logic fenceinvalM; // sfence.w.inval or sfence.inval.ir
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///////////////////////////////////////////
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// Decode privileged instructions
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///////////////////////////////////////////
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assign rs1zeroM = InstrM[19:15] == 5'b0;
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assign rdzeroM = InstrM[11:7] == 5'b0;
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// svinval instructions
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// any svinval instruction is treated as sfence.vma on Wally
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assign sinvalvmaM = (InstrM[31:25] == 7'b0001011);
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assign sfencewinvalM = (InstrM[31:20] == 12'b000110000000) & rs1zeroM;
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assign sfenceinvalirM = (InstrM[31:20] == 12'b000110000001) & rs1zeroM;
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assign invalM = P.SVINVAL_SUPPORTED & (sinvalvmaM | sfencewinvalM | sfenceinvalirM);
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assign sinvalvmaM = (InstrM[31:25] == 7'b0001011) & rdzeroM;
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assign sfencewinvalM = (InstrM[31:20] == 12'b000110000000) & rs1zeroM & rdzeroM;
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assign sfenceinvalirM = (InstrM[31:20] == 12'b000110000001) & rs1zeroM & rdzeroM;
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assign presfencevmaM = (InstrM[31:25] == 7'b0001001) & rdzeroM;
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assign vmaM = presfencevmaM | (sinvalvmaM & P.SVINVAL_SUPPORTED); // sfence.vma or sinval.vma
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assign fenceinvalM = (sfencewinvalM | sfenceinvalirM) & P.SVINVAL_SUPPORTED; // sfence.w.inval or sfence.inval.ir
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assign sretM = PrivilegedM & (InstrM[31:20] == 12'b000100000010) & rs1zeroM & P.S_SUPPORTED &
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(PrivilegeModeW == P.M_MODE | PrivilegeModeW == P.S_MODE & ~STATUS_TSR);
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@ -71,8 +76,11 @@ module privdec import cvw::*; #(parameter cvw_t P) (
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assign ecallM = PrivilegedM & (InstrM[31:20] == 12'b000000000000) & rs1zeroM;
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assign ebreakM = PrivilegedM & (InstrM[31:20] == 12'b000000000001) & rs1zeroM;
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assign wfiM = PrivilegedM & (InstrM[31:20] == 12'b000100000101) & rs1zeroM;
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assign sfencevmaM = PrivilegedM & (InstrM[31:25] == 7'b0001001 | invalM) &
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(PrivilegeModeW == P.M_MODE | (PrivilegeModeW == P.S_MODE & ~STATUS_TVM)) & P.VIRTMEM_SUPPORTED;
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// all of sinval.vma, sfence.w.inval, sfence.inval.ir are treated as sfence.vma
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assign sfencevmaM = PrivilegedM & P.VIRTMEM_SUPPORTED &
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((PrivilegeModeW == P.M_MODE & (vmaM | fenceinvalM)) |
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(PrivilegeModeW == P.S_MODE & (vmaM & ~STATUS_TVM | fenceinvalM))); // sfence.w.inval & sfence.inval.ir not affected by TVM
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///////////////////////////////////////////
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// WFI timeout Privileged Spec 3.1.6.5
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@ -127,7 +127,7 @@ module privileged import cvw::*; #(parameter cvw_t P) (
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.STATUS_MPP, .STATUS_SPP, .NextPrivilegeModeM, .PrivilegeModeW);
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// decode privileged instructions
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privdec #(P) pmd(.clk, .reset, .StallW, .FlushW, .InstrM(InstrM[31:15]),
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privdec #(P) pmd(.clk, .reset, .StallW, .FlushW, .InstrM(InstrM[31:7]),
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.PrivilegedM, .IllegalIEUFPUInstrM, .IllegalCSRAccessM,
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.PrivilegeModeW, .STATUS_TSR, .STATUS_TVM, .STATUS_TW, .IllegalInstrFaultM,
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.EcallFaultM, .BreakpointFaultM, .sretM, .mretM, .RetM, .wfiM, .wfiW, .sfencevmaM);
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