mirror of
https://github.com/openhwgroup/cvw.git
synced 2025-04-23 13:27:16 -04:00
Fixed Type 5b interaction between dcache and hptw.
This is a load concurrent with ITLBMiss.
This commit is contained in:
Ross Thompson
parent
6aff6b0fa3
commit
d830721a11
3 changed files with 45 additions and 94 deletions
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@ -5,42 +5,26 @@ add wave -noupdate /testbench/reset
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add wave -noupdate /testbench/reset_ext
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add wave -noupdate -radix unsigned /testbench/InstrCountW
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add wave -noupdate /testbench/dut/hart/SATP_REGW
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/EcallFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InterruptM
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add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/PendingIntsM
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add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/CommittedM
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add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/InstrValidM
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM
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add wave -noupdate -expand -group HDU -expand -group hazards -color Pink /testbench/dut/hart/hzu/TrapM
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/StoreStallD
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/LSUStall
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/DivBusyE
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add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
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add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD
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add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE
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add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushM
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add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushW
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add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF
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add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD
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add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE
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add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM
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add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM
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add wave -noupdate -group HDU -expand -group hazards -color Pink /testbench/dut/hart/hzu/TrapM
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/StoreStallD
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LSUStall
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/DivBusyE
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add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
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add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD
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add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE
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add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushM
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add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushW
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW
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add wave -noupdate -group PCS /testbench/dut/hart/ifu/PCNextF
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add wave -noupdate -group PCS /testbench/dut/hart/PCF
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add wave -noupdate -group PCS /testbench/dut/hart/ifu/PCD
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@ -60,16 +44,15 @@ add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/c/RegWriteD
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add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/RdD
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add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs1D
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add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs2D
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add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE
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add wave -noupdate -expand -group {Execution Stage} /testbench/ExpectedPCE
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add wave -noupdate -expand -group {Execution Stage} /testbench/MepcExpected
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add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE
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add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName
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add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ieu/c/InstrValidE
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add wave -noupdate -expand -group {Execution Stage} /testbench/textE
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add wave -noupdate -expand -group {Execution Stage} -color {Cornflower Blue} /testbench/FunctionName/FunctionName
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add wave -noupdate -group {Execution Stage} /testbench/dut/hart/ifu/PCE
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add wave -noupdate -group {Execution Stage} /testbench/ExpectedPCE
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add wave -noupdate -group {Execution Stage} /testbench/MepcExpected
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add wave -noupdate -group {Execution Stage} /testbench/dut/hart/ifu/InstrE
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add wave -noupdate -group {Execution Stage} /testbench/InstrEName
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add wave -noupdate -group {Execution Stage} /testbench/dut/hart/ieu/c/InstrValidE
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add wave -noupdate -group {Execution Stage} /testbench/textE
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add wave -noupdate -group {Execution Stage} -color {Cornflower Blue} /testbench/FunctionName/FunctionName
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add wave -noupdate -expand -group {Memory Stage} /testbench/checkInstrM
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/priv/trap/InstrValidM
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/PCM
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add wave -noupdate -expand -group {Memory Stage} /testbench/ExpectedPCM
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/InstrM
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@ -154,15 +137,7 @@ add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/A
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/B
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/ALUControl
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/result
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/FlagsE
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add wave -noupdate -group alu -divider internals
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/overflow
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/carry
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/zero
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/neg
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/lt
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/ltu
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add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1D
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add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs2D
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add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1E
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@ -180,15 +155,6 @@ add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/Write
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add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/ALUResultE
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add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcAE
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add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcBE
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add wave -noupdate -group muldiv /testbench/dut/hart/mdu/Funct3E
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add wave -noupdate -group muldiv /testbench/dut/hart/mdu/MulDivE
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add wave -noupdate -group muldiv /testbench/dut/hart/mdu/W64E
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add wave -noupdate -group muldiv /testbench/dut/hart/mdu/StallM
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add wave -noupdate -group muldiv /testbench/dut/hart/mdu/StallW
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add wave -noupdate -group muldiv /testbench/dut/hart/mdu/FlushM
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add wave -noupdate -group muldiv /testbench/dut/hart/mdu/FlushW
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add wave -noupdate -group muldiv /testbench/dut/hart/mdu/MulDivResultW
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add wave -noupdate -group muldiv /testbench/dut/hart/mdu/DivBusyE
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add wave -noupdate -group icache -color Gold /testbench/dut/hart/ifu/icache/controller/CurrState
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add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/controller/NextState
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add wave -noupdate -group icache /testbench/dut/hart/ifu/ITLBMissF
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@ -239,9 +205,13 @@ add wave -noupdate -expand -group AMO_ALU /testbench/dut/hart/lsu/dcache/genblk3
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add wave -noupdate -expand -group AMO_ALU /testbench/dut/hart/lsu/dcache/genblk3/amoalu/srca
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add wave -noupdate -expand -group AMO_ALU /testbench/dut/hart/lsu/dcache/genblk3/amoalu/srcb
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add wave -noupdate -expand -group AMO_ALU /testbench/dut/hart/lsu/dcache/genblk3/amoalu/width
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add wave -noupdate -expand -group lsu -group {LSU ARB} /testbench/dut/hart/lsu/arbiter/SelHPTW
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add wave -noupdate -expand -group lsu -color Gold /testbench/dut/hart/lsu/CurrState
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/SelHPTW
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/InterlockStall
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/LSUStall
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/WalkerInstrPageFaultF
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/WalkerInstrPageFaultRaw
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add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/hart/lsu/dcache/dcachefsm/CurrState
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WalkerPageFaultM
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WriteDataM
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWriteEnableM
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableM
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@ -250,6 +220,10 @@ add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWayWriteEnableM
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/ReadDataBlockM
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/SelReplayCPURequest
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/IEUAdrE
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/IEUAdrM
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/RAdr
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add wave -noupdate -expand -group lsu -expand -group dcache -group flush -radix unsigned /testbench/dut/hart/lsu/dcache/FlushAdr
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add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/FlushWay
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add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/VictimDirtyWay
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@ -404,7 +378,6 @@ add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/pm
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add wave -noupdate -expand -group lsu -expand -group ptwalker -color Gold /testbench/dut/hart/lsu/hptw/genblk1/WalkerState
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add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/PCF
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add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/genblk1/TranslationVAdr
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add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/TranslationPAdr
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add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/HPTWReadPTE
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add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/PTE
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add wave -noupdate -expand -group lsu -expand -group ptwalker -group types /testbench/dut/hart/lsu/hptw/ITLBMissF
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@ -414,24 +387,6 @@ add wave -noupdate -expand -group lsu -expand -group ptwalker -group types /test
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add wave -noupdate -expand -group lsu -expand -group ptwalker -group types /testbench/dut/hart/lsu/hptw/WalkerInstrPageFaultF
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add wave -noupdate -expand -group lsu -expand -group ptwalker -group types /testbench/dut/hart/lsu/hptw/WalkerLoadPageFaultM
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add wave -noupdate -expand -group lsu -expand -group ptwalker -group types /testbench/dut/hart/lsu/hptw/WalkerStorePageFaultM
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add wave -noupdate -group csr -color Gray90 -radix unsigned /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/INSTRET_REGW
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add wave -noupdate -group csr /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/HPMCOUNTER_REGW
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add wave -noupdate -group csr -expand -group machine /testbench/dut/hart/priv/csr/genblk1/csrm/MIE_REGW
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add wave -noupdate -group csr -expand -group machine /testbench/dut/hart/priv/csr/MIP_REGW
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add wave -noupdate -group csr -expand -group machine /testbench/dut/hart/priv/csr/genblk1/csrm/MSTATUS_REGW
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add wave -noupdate -group csr -expand -group machine /testbench/dut/hart/priv/csr/genblk1/csrm/MEPC_REGW
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add wave -noupdate -group csr -expand -group machine /testbench/dut/hart/priv/csr/genblk1/csrm/MTVAL_REGW
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add wave -noupdate -group csr -expand -group machine /testbench/dut/hart/priv/csr/MTVEC_REGW
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add wave -noupdate -group csr -expand -group machine /testbench/dut/hart/priv/csr/genblk1/csrm/MCAUSE_REGW
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add wave -noupdate -group csr -expand -group machine /testbench/dut/hart/priv/csr/genblk1/csrm/MEDELEG_REGW
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add wave -noupdate -group csr -expand -group machine /testbench/dut/hart/priv/csr/genblk1/csrm/MIDELEG_REGW
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add wave -noupdate -group csr -expand -group machine -color Brown /testbench/dut/hart/priv/PrivilegeModeW
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add wave -noupdate -group csr -expand -group supervisor /testbench/dut/hart/priv/csr/STVEC_REGW
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add wave -noupdate -group csr -expand -group supervisor /testbench/dut/hart/priv/csr/genblk1/csrs/STVAL
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add wave -noupdate -group csr -expand -group supervisor /testbench/dut/hart/priv/csr/genblk1/csrs/genblk1/SCAUSE_REGW
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add wave -noupdate -group csr -expand -group supervisor /testbench/dut/hart/priv/csr/genblk1/csrs/SIP_REGW
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add wave -noupdate -group csr -expand -group supervisor /testbench/dut/hart/priv/csr/genblk1/csrs/SIE_REGW
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add wave -noupdate -group csr -expand -group supervisor /testbench/dut/hart/priv/csr/genblk1/csrs/SEPC_REGW
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add wave -noupdate -group itlb /testbench/dut/hart/ifu/immu/TLBWrite
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add wave -noupdate -group itlb /testbench/dut/hart/ifu/ITLBMissF
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add wave -noupdate -group itlb /testbench/dut/hart/ifu/immu/PhysicalAddress
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@ -504,7 +459,6 @@ add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HADDR
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add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HWRITE
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add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HWDATA
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add wave -noupdate -group {debug trace} -expand -group mem -color Yellow /testbench/dut/hart/FlushW
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add wave -noupdate -group {debug trace} -expand -group mem /testbench/dut/hart/priv/trap/InstrValidM
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add wave -noupdate -group {debug trace} -expand -group mem /testbench/checkInstrM
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add wave -noupdate -group {debug trace} -expand -group mem /testbench/dut/hart/PCM
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add wave -noupdate -group {debug trace} -expand -group mem /testbench/ExpectedPCM
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@ -518,19 +472,15 @@ add wave -noupdate -group {debug trace} -expand -group wb /testbench/textW
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add wave -noupdate -group {pc selection} /testbench/dut/hart/ifu/PCNext2F
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add wave -noupdate -group {pc selection} /testbench/dut/hart/ifu/PrivilegedNextPCM
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add wave -noupdate -group {pc selection} /testbench/dut/hart/ifu/PrivilegedChangePCM
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add wave -noupdate -group {pc selection} /testbench/dut/hart/priv/PrivilegedNextPCM
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add wave -noupdate -group {pc selection} /testbench/dut/hart/priv/trap/PrivilegedVectoredTrapVector
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add wave -noupdate -group {pc selection} /testbench/dut/hart/priv/trap/PrivilegedTrapVector
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add wave -noupdate /testbench/dut/hart/ifu/PCCorrectE
|
||||
add wave -noupdate /testbench/dut/hart/ifu/PCSrcE
|
||||
add wave -noupdate /testbench/dut/hart/ieu/c/BranchTakenE
|
||||
add wave -noupdate /testbench/dut/hart/ieu/c/BranchE
|
||||
add wave -noupdate /testbench/dut/hart/ifu/PCTargetE
|
||||
add wave -noupdate /testbench/dut/hart/ifu/PCLinkE
|
||||
add wave -noupdate /testbench/dut/hart/lsu/DCtoAHBSizeM
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 23} {14157765 ns} 0} {{Cursor 3} {29725 ns} 1}
|
||||
quietly wave cursor active 1
|
||||
WaveRestoreCursors {{Cursor 23} {14157765 ns} 0} {{Cursor 3} {29725 ns} 1} {{Cursor 5} {163846 ns} 0}
|
||||
quietly wave cursor active 3
|
||||
configure wave -namecolwidth 250
|
||||
configure wave -valuecolwidth 314
|
||||
configure wave -justifyvalue left
|
||||
|
|
@ -545,4 +495,4 @@ configure wave -griddelta 40
|
|||
configure wave -timeline 0
|
||||
configure wave -timelineunits ns
|
||||
update
|
||||
WaveRestoreZoom {14157667 ns} {14157811 ns}
|
||||
WaveRestoreZoom {163681 ns} {164021 ns}
|
||||
|
|
|
|||
|
|
@ -186,7 +186,8 @@ module lsu
|
|||
STATE_T0_READY: if(DTLBMissM | ITLBMissF) InterlockStall = 1'b1;
|
||||
STATE_T3_DTLB_MISS: if (~WalkerPageFaultM) InterlockStall = 1'b1;
|
||||
STATE_T4_ITLB_MISS: if (~WalkerInstrPageFaultRaw) InterlockStall = 1'b1;
|
||||
STATE_T5_ITLB_MISS: if (~WalkerInstrPageFaultRaw) InterlockStall = 1'b1;
|
||||
STATE_T5_ITLB_MISS: InterlockStall = 1'b1;
|
||||
//STATE_T0_FAULT_REPLAY: if (~WalkerInstrPageFaultF) InterlockStall = 1'b1;
|
||||
STATE_T7_DITLB_MISS: if (~WalkerPageFaultM) InterlockStall = 1'b1;
|
||||
default: InterlockStall = 1'b0;
|
||||
endcase
|
||||
|
|
@ -194,7 +195,7 @@ module lsu
|
|||
|
||||
|
||||
// When replaying CPU memory request after PTW select the IEUAdrM for correct address.
|
||||
assign SelReplayCPURequest = NextState == STATE_T0_REPLAY;
|
||||
assign SelReplayCPURequest = (NextState == STATE_T0_REPLAY) | (NextState == STATE_T0_FAULT_REPLAY);
|
||||
assign SelHPTW = (CurrState == STATE_T3_DTLB_MISS) | (CurrState == STATE_T4_ITLB_MISS) |
|
||||
(CurrState == STATE_T5_ITLB_MISS) | (CurrState == STATE_T7_DITLB_MISS);
|
||||
assign IgnoreRequest = CurrState == STATE_T0_READY & (ITLBMissF | DTLBMissM);
|
||||
|
|
|
|||
|
|
@ -199,7 +199,7 @@ module hptw
|
|||
// LEVEL0: if (ValidLeafPTE) NextWalkerState = LEAF;
|
||||
// else NextWalkerState = FAULT;
|
||||
LEAF: NextWalkerState = IDLE; // updates TLB
|
||||
FAULT: if (ITLBMissF & AnyCPUReqM) NextWalkerState = FAULT;
|
||||
FAULT: if (ITLBMissF & AnyCPUReqM) NextWalkerState = FAULT; /// **** BUG: Stays in fault 1 cycle longer than it should.
|
||||
else NextWalkerState = IDLE;
|
||||
default: begin
|
||||
// synthesis translate_off
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue