github-mirrors/cvw
1
0
Fork 0
mirror of https://github.com/openhwgroup/cvw.git synced 2025-04-22 12:57:23 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

whitespace cleanup

Browse source
This commit is contained in:
Jordan Carlin 2025-03-07 12:58:48 -08:00
parent e532f8c023
commit d8523bb8c4
No known key found for this signature in database
1 changed files with 19 additions and 19 deletions
Download patch file Download diff file Expand all files Collapse all files

38
testbench/common/wallyTracer.sv
View file

@ -79,8 +79,8 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
logic [(P.PA_BITS-1):0] IPAF,IPAD,IPAE,IPAM,IPAW,DPAM,DPAW;
logic [(P.PPN_BITS-1):0] IPPNF,IPPND,IPPNE,IPPNM,IPPNW,DPPNM,DPPNW;
logic [1:0] IPageTypeF, IPageTypeD, IPageTypeE, IPageTypeM, IPageTypeW, DPageTypeM, DPageTypeW;
logic ReadAccessM,WriteAccessM,ReadAccessW,WriteAccessW;
logic ExecuteAccessF,ExecuteAccessD,ExecuteAccessE,ExecuteAccessM,ExecuteAccessW;
logic ReadAccessM,WriteAccessM,ReadAccessW,WriteAccessW;
logic ExecuteAccessF,ExecuteAccessD,ExecuteAccessE,ExecuteAccessM,ExecuteAccessW;
assign clk = testbench.dut.clk;
// assign InstrValidF = testbench.dut.core.ieu.InstrValidF; // not needed yet
@ -137,12 +137,12 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
assign ReadAccessM = testbench.dut.core.lsu.dmmu.dmmu.ReadAccessM;
assign WriteAccessM = testbench.dut.core.lsu.dmmu.dmmu.WriteAccessM;
assign ExecuteAccessF = testbench.dut.core.ifu.immu.immu.ExecuteAccessF;
assign IPTEF = testbench.dut.core.ifu.immu.immu.PTE;
assign DPTEM = testbench.dut.core.lsu.dmmu.dmmu.PTE;
assign IPPNF = testbench.dut.core.ifu.immu.immu.tlb.tlb.PPN;
assign DPPNM = testbench.dut.core.lsu.dmmu.dmmu.tlb.tlb.PPN;
assign IPageTypeF = testbench.dut.core.ifu.immu.immu.PageTypeWriteVal;
assign DPageTypeM = testbench.dut.core.lsu.dmmu.dmmu.PageTypeWriteVal;
assign IPTEF = testbench.dut.core.ifu.immu.immu.PTE;
assign DPTEM = testbench.dut.core.lsu.dmmu.dmmu.PTE;
assign IPPNF = testbench.dut.core.ifu.immu.immu.tlb.tlb.PPN;
assign DPPNM = testbench.dut.core.lsu.dmmu.dmmu.tlb.tlb.PPN;
assign IPageTypeF = testbench.dut.core.ifu.immu.immu.PageTypeWriteVal;
assign DPageTypeM = testbench.dut.core.lsu.dmmu.dmmu.PageTypeWriteVal;
// CSR connections
if (P.ZICSR_SUPPORTED) begin
@ -370,10 +370,10 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
`ifdef FCOV
// Interrupts
assign rvvi.m_ext_intr[0][0] = MExtInt;
assign rvvi.s_ext_intr[0][0] = SExtInt;
assign rvvi.m_ext_intr[0][0] = MExtInt;
assign rvvi.s_ext_intr[0][0] = SExtInt;
assign rvvi.m_timer_intr[0][0] = MTimerInt;
assign rvvi.m_soft_intr[0][0] = MSwInt;
assign rvvi.m_soft_intr[0][0] = MSwInt;
`endif
// *** implementation only cancel? so sc does not clear?
@ -381,17 +381,17 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
`ifdef FCOV
// Virtual Memory signals for verification
assign rvvi.virt_adr_i[0][0] = IVAdrW;
assign rvvi.virt_adr_d[0][0] = DVAdrW;
assign rvvi.phys_adr_i[0][0] = IPAW;
assign rvvi.phys_adr_d[0][0] = DPAW;
assign rvvi.virt_adr_i[0][0] = IVAdrW;
assign rvvi.virt_adr_d[0][0] = DVAdrW;
assign rvvi.phys_adr_i[0][0] = IPAW;
assign rvvi.phys_adr_d[0][0] = DPAW;
assign rvvi.read_access[0][0] = ReadAccessW;
assign rvvi.write_access[0][0] = WriteAccessW;
assign rvvi.execute_access[0][0] = ExecuteAccessW;
assign rvvi.pte_i[0][0] = IPTEW;
assign rvvi.pte_d[0][0] = DPTEW;
assign rvvi.ppn_i[0][0] = IPPNW;
assign rvvi.ppn_d[0][0] = DPPNW;
assign rvvi.pte_i[0][0] = IPTEW;
assign rvvi.pte_d[0][0] = DPTEW;
assign rvvi.ppn_i[0][0] = IPPNW;
assign rvvi.ppn_d[0][0] = DPPNW;
assign rvvi.page_type_i[0][0] = IPageTypeW;
assign rvvi.page_type_d[0][0] = DPageTypeW;
`endif