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Merge pull request #1011 from davidharrishmc/dev

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Fixed bug causing Issue 1010 and made some changes to Wally privileged fields to match ImperasDV
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Rose Thompson 2024-10-14 11:10:21 -05:00 • committed by GitHub
commit d8fe68b912
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4 changed files with 19 additions and 3 deletions
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11
config/rv64gc/imperas.ic
View file

@ -57,6 +57,17 @@
#--override cpu/instret_undefined=T
#--override cpu/hpmcounter_undefined=T
--override cpu/scontext_undefined=T
--override cpu/mcontext_undefined=T
--override cpu/mnoise_undefined=T
# *** how to override other undefined registers: seed, mphmevent, mseccfg, debugger registers
#--override cpu/seed_undefined=T
#--override mhpmevent3_undefined=T
#--override cpu/mseccfg_undefined=T
#--override cpu/tselect_undefined=T
#--override cpu/tdata1_undefined=T
--override cpu/reset_address=0x80000000
--override cpu/unaligned=T # Zicclsm (should be true)

5
src/privileged/csrm.sv
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@ -180,7 +180,9 @@ module csrm import cvw::*; #(parameter cvw_t P) (
if (P.U_SUPPORTED) begin // menvcfg only exists if there is a lower privilege to control
logic WriteMENVCFGM;
logic [63:0] MENVCFG_PreWriteValM, MENVCFG_WriteValM;
logic [1:0] LegalizedCBIE;
assign WriteMENVCFGM = CSRMWriteM & (CSRAdrM == MENVCFG);
assign LegalizedCBIE = MENVCFG_PreWriteValM[5:4] == 2'b10 ? MENVCFG_REGW[5:4] : MENVCFG_PreWriteValM[5:4]; // Assume WARL for reserved CBIE = 10, keeps old value
// MENVCFG is always 64 bits even for RV32
assign MENVCFG_WriteValM = {
MENVCFG_PreWriteValM[63] & P.SSTC_SUPPORTED,
@ -188,7 +190,8 @@ module csrm import cvw::*; #(parameter cvw_t P) (
MENVCFG_PreWriteValM[61] & P.SVADU_SUPPORTED,
53'b0,
MENVCFG_PreWriteValM[7] & P.ZICBOZ_SUPPORTED,
MENVCFG_PreWriteValM[6:4] & {3{P.ZICBOM_SUPPORTED}},
MENVCFG_PreWriteValM[6] & P.ZICBOM_SUPPORTED,
LegalizedCBIE & {2{P.ZICBOM_SUPPORTED}},
3'b0,
MENVCFG_PreWriteValM[0] & P.S_SUPPORTED & P.VIRTMEM_SUPPORTED
};

3
src/privileged/csrsr.sv
View file

@ -106,7 +106,8 @@ module csrsr import cvw::*; #(parameter cvw_t P) (
always_comb
if (CSRWriteValM[12:11] == P.U_MODE & P.U_SUPPORTED) STATUS_MPP_NEXT = P.U_MODE;
else if (CSRWriteValM[12:11] == P.S_MODE & P.S_SUPPORTED) STATUS_MPP_NEXT = P.S_MODE;
else STATUS_MPP_NEXT = P.M_MODE;
else if (CSRWriteValM[12:11] == 2'b10) STATUS_MPP_NEXT = STATUS_MPP; // do not change MPP when trying to write reserved 10
else STATUS_MPP_NEXT = P.M_MODE;
///////////////////////////////////////////
// Endianness logic Privileged Spec 3.1.6.4

3
tests/coverage/WALLY-init-lib.h
View file

@ -134,9 +134,10 @@ self_loop:
setmsb:
li a0, 0x80000000 # 1 in bit 31
slli a1, a0, 1 # check if register is wider than 31 bits
beqz a1, 1f # yes, a0 has 1 in bit 31
beqz a1, setmsbdone # yes, a0 has 1 in bit 31
slli a0, a0, 16 # no: shift a0 to have 1 inn bit 63
slli a0, a0, 16 # use two shifts of 16 bits each to be compatible with compiling either RV32 or 64
setmsbdone:
ret # return to calller
.section .tohost