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Fix typo

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Jordan Carlin 2025-01-13 10:50:12 -08:00
parent 8aabf57437
commit da0b65289d
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testbench/common/instrNameDecTB.sv
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@ -35,7 +35,7 @@ module instrNameDecTB #(parameter XLEN) (
logic [11:0] imm;
logic [4:0] rs2, rd, CRrs2;
logic [1:0] compressedOp;
logic [2:0] compressed15_10;
logic [5:0] compressed15_10;
assign op = instr[6:0];