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Memory synthesis updates

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This commit is contained in:
David Harris 2023-02-17 15:33:49 -08:00
parent 3f2f48ddc6
commit daf2f822c2
3 changed files with 2 additions and 4 deletions
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2
src/generic/mem/ram1p1rwbe.sv
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@ -34,7 +34,7 @@
`include "wally-config.vh"
module ram1p1rwbe #(parameter DEPTH=128, WIDTH=256) (
module ram1p1rwbe #(parameter DEPTH=64, WIDTH=128) (
input logic clk,
input logic ce,
input logic [$clog2(DEPTH)-1:0] addr,

2
src/generic/mem/ram1p1rwbe_64x22.sv
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@ -37,6 +37,6 @@ module ram1p1rwbe_64x22(
// replace "generic64x22RAM" with "TS1N..64X22.." module from your memory vendor
// use part of a larger RAM to avoid generating more flavors of RAM
TS1N28HPCPSVTB64X44M4SW sramIP(.CLK, .CEB, .WEB, .A, .D(D[21:0]), .BWEB(BWEB[21:0]), .Q(Q[21:0]));
//generic64x22RAM sramIP (.CLK, .CEB, .WEB, .A, .D, .BWEB, .Q);
// genericRAM #(64, 22) sramIP (.CLK, .CEB, .WEB, .A, .D, .BWEB, .Q);
endmodule

2
src/generic/mem/ram2p1r1wbe_64x32.sv
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@ -44,8 +44,6 @@ module ram2p1r1wbe_64x32(
// replace "generic64x32RAM" with "TSDN..64X32.." module from your memory vendor
//generic64x32RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB,
// .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB);
//generic64x32RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB,
// .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB);
TSDN28HPCPA64X32M4MW sramIP(.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB,
.AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB);
endmodule